DDR Version 1.13 20180801
In
soft reset
SRX
Channel 0: LPDDR4,50MHz
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,50MHz
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
256B stride
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 400MHz 0,1
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x40
ch 1 ddrconfig = 0x101, ddrsize = 0x40
pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
OUT
U-Boot SPL board init

U-Boot SPL 2017.09-armbian (Aug 17 2020 - 08:32:19)
booted from SD
Trying to boot from MMC2
"Synchronous Abort" handler, esr 0x02000000
ELR:     404c8
LR:      1000c
x 0: 0000000000400000 x 1: 0000000000000000
x 2: 0000000000000000 x 3: 0000000000400180
x 4: 0000000000000000 x 5: 0000000000000000
x 6: 0000000000000000 x 7: 0000000000000003
x 8: 00000000000003ec x 9: 0000000000020000
x10: 00000000005ffc1c x11: 00000000001ff8c0
x12: 00000000000003a8 x13: 00000000005ffc6c
x14: 00000000001ff8c0 x15: 000000000000f720
x16: 0000000000010000 x17: 0000000000000000
x18: 00000000005ffea0 x19: 000000000000efa0
x20: 0000000000400000 x21: 0000000000000000
x22: 00000000005ffe58 x23: 0000000000000000
x24: 000000000000d2a3 x25: 000000000000d28b
x26: 00000000deadbeef x27: 000000000000048c
x28: 000000000000048c x29: 00000000005ffdf0

Resetting CPU ...

DDR Version 1.13 20180801
In
soft reset
SRX
Channel 0: LPDDR4,50MHz
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,50MHz
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x4D
MR14=0x4D
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
256B stride
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 400MHz 0,1
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 800MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x40
ch 1 ddrconfig = 0x101, ddrsize = 0x40
pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
OUT
U-Boot SPL board init

U-Boot SPL 2017.09-armbian (Aug 17 2020 - 08:32:19)
booted from SD
Trying to boot from MMC2
"Synchronous Abort" handler, esr 0x02000000
ELR:     404c8
LR:      1000c
x 0: 0000000000400000 x 1: 0000000000000000
x 2: 0000000000000000 x 3: 0000000000400180
x 4: 0000000000000000 x 5: 0000000000000000
x 6: 0000000000000000 x 7: 0000000000000003
x 8: 00000000000003ec x 9: 0000000000020000
x10: 00000000005ffc1c x11: 00000000001ff8c0
x12: 00000000000003a8 x13: 00000000005ffc6c
x14: 00000000001ff8c0 x15: 000000000000f720
x16: 0000000000010000 x17: 0000000000000000
x18: 00000000005ffea0 x19: 000000000000efa0
x20: 0000000000400000 x21: 0000000000000000
x22: 00000000005ffe58 x23: 0000000000000000
x24: 000000000000d2a3 x25: 000000000000d28b
x26: 00000000deadbeef x27: 000000000000048c
x28: 000000000000048c x29: 00000000005ffdf0

Resetting CPU ...