SPI transfer for FBTFT device framebuffer

Marko Buršič


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I have one silly problem developing a FBTFT device driver for SSD1322 display https://github.com/MarkoBursic/fbtft---SSD1322/blob/master/fb_ssd1322.c


The initialisation starts OK, all GPIOs (DC, RESET, CS) follows as they should, since the data is sent through a function write_reg. For example :


write_reg(par, 0xA0, 0x14, 0x11);


It asserts DC low, then sends 0xA0, then asserts DC high and sends 0x14 and 0x11. Within every sent character (8bit bata) the CS toggles. The problem becomes when I want to send video data, I guess a function write_vmem is called. But here the entire tx buffer is filled and then streamed.

for (y = 0; y < bl_height; y++) {

		for (x = 0; x < bl_width / 2; x++) {

			*buf = cpu_to_le16(rgb565_to_y(vmem16[offset++])) >> 8 & 0xF0;

			*buf++ |= cpu_to_le16(rgb565_to_y(vmem16[offset++])) >> 12;



/* Write data */

ret = par->fbtftops.write(par, par->txbuf.buf, bl_width/2*bl_height);


In fact the whole buffer is sent from SPI but the CS doesn't toggle every 8-th clock pulse, it is just asserted low and then streamed out whole 8kB. 


Is there any settings on SPI to tell that it has to toggle, for example the dtb ovelay for FBTFT device has a setting: buswidth=<8>; but it seems that it doesn't take care of it. Any advice?


p.s.: the code was cloned from other sites that have used this device on RPi.





Problem is solved. I had a test example from BuyDisplay.com written for RPi, which sent data with toggling CS for each sent byte. I have patched this example and found out that SSD1322 works even better with a continuous stream without toggling CS when sending VRAM buffer. Later, the problem on my Rockpi4 and linux FBTFT driver was found to be a RES signal, which is active low. Therefore the display was hold in reset every time due to wrong parameter setting in DT overlay. 

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