joek Posted May 8, 2020 Share Posted May 8, 2020 hello, i need help porting Goodix gt911 touch panel into orange pi plus 2E (h3), the reset pin is at PA1 and interrupt pin is at PA0 here is my dts. soc@01c00000 { twi0: twi@0x01c2ac00{ gt911@5d { compatible = "goodix,gt911"; reg = <0x5d>; interrupt-parent = <&pio>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* EINT0 (PA0) */ irq-gpios = <&pio 0 0>; /* INT (PA0) */ reset-gpios = <&pio 0 1>; /* RST (PA1) */ irq-flags = <2>; touchscreen-max-id = <11>; touchscreen-size-x = <1280>; touchscreen-size-y = <720>; touchscreen-max-w = <512>; touchscreen-max-p = <512>; }; }; }; here is my pin-ctl gt911_reset_pin: gt911_reset_pin@1 { allwinner,pins = "PA1"; allwinner,function = "gpio_in"; allwinner,muxsel = <0>; allwinner,drive = <1>; allwinner,pull = <0>; }; gt911_irq_pin: gt911_irq_pin@0 { allwinner,pins = "PA0"; allwinner,function = "gpio_out"; allwinner,muxsel = <1>; allwinner,drive = <1>; allwinner,pull = <0>; }; i am getting Quote Goodix-TS 0-005d: ID 911, version: 1060 [ 25.804843] input: Goodix Capacitive TouchScreen as /devices/platform/soc/twi0/i2c-0/0-005d/input/input3 [ 25.831248] Goodix-TS 0-005d: request IRQ failed: -22 [ 26.012697] Goodix-TS: probe of 0-005d failed with error -22 i am also getting I2c interrupts, which means the i2c successfully reading from the chip. Quote 126: 265 0 0 0 GIC 38 Level twi0 i would like to know what is missing here? Thank you Link to comment Share on other sites More sharing options...
martinayotte Posted May 8, 2020 Share Posted May 8, 2020 29 minutes ago, joek said: i would like to know what is missing here? Are you using UART2 ? Because UART2 also use PA0/PA1 if enabled ... Link to comment Share on other sites More sharing options...
joek Posted May 8, 2020 Author Share Posted May 8, 2020 3 hours ago, martinayotte said: Are you using UART2 ? Because UART2 also use PA0/PA1 if enabled ... no, UART2 is disabled, is there anything wrong with my DTS configuration? or it is just fine? Link to comment Share on other sites More sharing options...
joek Posted May 9, 2020 Author Share Posted May 9, 2020 here is the pinctrl dtsi file /* * Allwinner sun8iw7 pin config info. */ / { soc@01c00000 { r_pio: pinctrl@01f02c00 { compatible = "allwinner,sun8iw7p1-r-pinctrl"; reg = <0x0 0x01f02c00 0x0 0x400>; interrupts = <GIC_SPI 45 4>; clocks = <&clk_cpurpio>; device_type = "r_pio"; gpio-controller; interrupt-controller; #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <6>; s_uart0_pins_a: s_uart0@0 { allwinner,pins = "PL2", "PL3"; allwinner,function = "s_uart0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <1>; }; s_twi0_pins_a: s_twi0@0 { allwinner,pins = "PL0", "PL1"; allwinner,function = "s_twi0"; allwinner,muxsel = <3>; allwinner,drive = <2>; allwinner,pull = <1>; }; s_jtag0_pins_a: s_jtag0@0 { allwinner,pins = "PL4", "PL5", "PL6", "PL7"; allwinner,function = "s_jtag0"; allwinner,muxsel = <2>; allwinner,drive = <2>; allwinner,pull = <1>; }; s_cir0_pins_a: s_cir0@0 { allwinner,pins = "PL11"; allwinner,function = "s_cir0"; allwinner,muxsel = <2>; allwinner,drive = <2>; allwinner,pull = <1>; }; }; pio: pinctrl@01c20800 { compatible = "allwinner,sun8iw7p1-pinctrl"; reg = <0x0 0x01c20800 0x0 0x400>; interrupts = <GIC_SPI 11 4>, <GIC_SPI 17 4>; device_type = "pio"; clocks = <&clk_pio>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <6>; gt911_reset_pin: gt911_reset_pin@1 { allwinner,pins = "PA1"; allwinner,function = "gpio_in"; allwinner,muxsel = <0>; allwinner,drive = <1>; allwinner,pull = <0>; }; gt911_irq_pin: gt911_irq_pin@0 { allwinner,pins = "PA0"; allwinner,function = "gpio_out"; allwinner,muxsel = <1>; allwinner,drive = <1>; allwinner,pull = <0>; }; vdevice_pins_a: vdevice@0 { allwinner,pins = "PA1", "PA2"; allwinner,function = "vdevice"; allwinner,muxsel = <5>; allwinner,drive = <1>; allwinner,pull = <1>; }; uart0_pins_a: uart0@0 { allwinner,pins = "PA4", "PA5"; allwinner,pname = "uart0_tx", "uart0_rx"; allwinner,function = "uart0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <1>; }; uart0_pins_b: uart0@1 { allwinner,pins = "PA4", "PA5"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; uart1_pins_a: uart1@0 { allwinner,pins = "PG6", "PG7", "PG8", "PG9"; allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts"; allwinner,function = "uart1"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <1>; }; uart1_pins_b: uart1@1 { allwinner,pins = "PG6", "PG7", "PG8", "PG9"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; uart2_pins_a: uart2@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3"; allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts"; allwinner,function = "uart2"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <1>; }; uart2_pins_b: uart2@1 { allwinner,pins = "PA0", "PA1", "PA2", "PA3"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; uart3_pins_a: uart3@0 { allwinner,pins = "PA13", "PA14", "PA15", "PA16"; allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts"; allwinner,function = "uart3"; allwinner,muxsel = <3>; allwinner,drive = <1>; allwinner,pull = <1>; }; uart3_pins_b: uart3@1 { allwinner,pins = "PA13", "PA14", "PA15", "PA16"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; twi0_pins_a: twi0@0 { allwinner,pins = "PA11", "PA12"; allwinner,pname = "twi0_scl", "twi0_sda"; allwinner,function = "twi0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <0>; }; twi0_pins_b: twi0@1 { allwinner,pins = "PA11", "PA12"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; twi1_pins_a: twi1@0 { allwinner,pins = "PA18", "PA19"; allwinner,pname = "twi1_scl", "twi1_sda"; allwinner,function = "twi1"; allwinner,muxsel = <3>; allwinner,drive = <1>; allwinner,pull = <0>; }; twi1_pins_b: twi1@1 { allwinner,pins = "PA18", "PA19"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; twi2_pins_a: twi2@0 { allwinner,pins = "PE12", "PE13"; allwinner,pname = "twi2_scl", "twi2_sda"; allwinner,function = "twi2"; allwinner,muxsel = <3>; allwinner,drive = <1>; allwinner,pull = <0>; }; twi2_pins_b: twi2@1 { allwinner,pins = "PE12", "PE13"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; ts0_pins_a: ts0@0 { allwinner,pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7"; allwinner,function = "ts0"; allwinner,muxsel = <3>; allwinner,drive = <1>; allwinner,pull = <0>; }; ts0_pins_b: ts0_sleep@0 { allwinner,pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; spi0_pins_a: spi0@0 { allwinner,pins = "PC0", "PC1", "PC2"; allwinner,pname = "spi0_mosi", "spi0_miso", "spi0_sclk"; allwinner,function = "spi0"; allwinner,muxsel = <3>; allwinner,drive = <1>; allwinner,pull = <0>; }; spi0_pins_b: spi0@1 { allwinner,pins = "PC3"; allwinner,pname = "spi0_cs0"; allwinner,function = "spi0"; allwinner,muxsel = <3>; allwinner,drive = <1>; allwinner,pull = <1>; // only CS should be pulled up }; spi0_pins_c: spi0@2 { allwinner,pins = "PC0", "PC1", "PC2", "PC3"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; spi1_pins_a: spi1@0 { allwinner,pins = "PA15", "PA16", "PA14"; allwinner,pname = "spi1_mosi", "spi1_miso", "spi1_sclk"; allwinner,function = "spi1"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <0>; }; spi1_pins_b: spi1@1 { allwinner,pins = "PA13"; allwinner,pname = "spi1_cs0"; allwinner,function = "spi1"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <1>; // only CS should be pulled up }; spi1_pins_c: spi1@2 { allwinner,pins = "PA13", "PA14", "PA15", "PA16"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; sdc0_pins_a: sdc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,function = "sdc0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <1>; }; sdc0_pins_b: sdc0@1 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <1>; }; sdc1_pins_a: sdc1@0 { allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; allwinner,function = "sdc1"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <1>; }; sdc1_pins_b: sdc1@1 { allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <1>; }; sdc2_pins_a: sdc2@0 { allwinner,pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16"; allwinner,function = "sdc2"; allwinner,muxsel = <3>; allwinner,drive = <2>; allwinner,pull = <1>; }; sdc2_pins_b: sdc2@1 { allwinner,pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <1>; }; daudio0_pins_a: daudio0@0 { allwinner,pins = "PA18", "PA19", "PA20", "PA21"; allwinner,function = "i2s0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <0>; }; daudio0_pins_b: daudio0_sleep@0 { allwinner,pins = "PA18", "PA19", "PA20", "PA21"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; daudio1_pins_a: daudio1@0 { allwinner,pins = "PG10", "PG11", "PG12", "PG13"; allwinner,function = "i2s1"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <0>; }; daudio1_pins_b: daudio1_sleep@0 { allwinner,pins = "PG10", "PG11", "PG12", "PG13"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; spdif_pins_a: spdif@0 { allwinner,pins = "PA17"; allwinner,function = "spdif0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <0>; }; spdif_pins_b: spdif_sleep@0 { allwinner,pins = "PA17"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; csi0_pins_a: csi0@0 { allwinner,pins = "PE0","PE1","PE2","PE3","PE4", "PE5", "PE6","PE7","PE8","PE9", "PE10","PE11", "PE12","PE13"; allwinner,pname = "csi0_pck","csi0_mck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7","csi0_sck", "csi0_sda"; allwinner,function = "csi0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <0>; allwinner,data = <0>; }; csi0_pins_b: csi0@1 { allwinner,pins = "PE0","PE1","PE2","PE3", "PE4","PE5","PE6","PE7", "PE8","PE9","PE10","PE11", "PE12","PE13"; allwinner,pname = "csi0_pck","csi0_mck", "csi0_hsync","csi0_vsync", "csi0_d0","csi0_d1", "csi0_d2","csi0_d3", "csi0_d4","csi0_d5", "csi0_d6","csi0_d7", "csi0_sck","csi0_sda"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; allwinner,data = <0>; }; scr0_pins_a: smartcard@0 { allwinner,pins = "PA6", "PA7", "PA8", "PA9", "PA10"; allwinner,pname = "scr0_vccen", "scr0_sck", "scr0_sda", "scr0_rst", "scr0_det"; allwinner,function = "sim0"; allwinner,muxsel = <2>; allwinner,drive = <0>; allwinner,pull = <1>; }; scr0_pins_b: smartcard@1 { allwinner,pins = "PA20", "PA21"; allwinner,pname = "scr0_vppen", "scr0_vppp"; allwinner,function = "sim0"; allwinner,muxsel = <3>; allwinner,drive = <0>; allwinner,pull = <1>; }; scr0_pins_c: smartcard@2 { allwinner,pins = "PA6", "PA7", "PA8", "PA9", "PA10", "PA20", "PA21"; allwinner,pname = "scr0_rst", "scr0_vppen", "scr0_vppp", "scr0_det", "scr0_vccen", "scr0_sck", "scr0_sda"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <0>; allwinner,pull = <0>; }; nand0_pins_a: nand0@0 { allwinner,pins = "PC0", "PC1", "PC2", "PC4", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14"; allwinner,pname= "nand0_we", "nand0_ale", "nand0_cle", "nand0_nre", "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3", "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7", "nand0_ndqs"; allwinner,function = "nand0"; allwinner,muxsel = <2>; allwinner,drive = <1>; allwinner,pull = <0>; }; nand0_pins_b: nand0@1 { allwinner,pins = "PC3", "PC5", "PC15", "PC16"; allwinner,pname= "nand0_ce0", "nand0_rb0", "nand0_ce1", "nand0_rb1"; allwinner,function = "nand0"; allwinner,muxsel = <2>; allwinner,drive = <1>; //only RB&CE should be pulled up allwinner,pull = <1>; }; nand0_pins_c: nand0@2 { allwinner,pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16"; allwinner,function = "io_disabled"; allwinner,muxsel = <7>; allwinner,drive = <1>; allwinner,pull = <0>; }; }; }; }; here is the main dtsi file /* * Allwinner Technology CO., Ltd. sun8iw7p1 platform */ /* kernel used */ /*/memreserve/ 0x43000000 0x00000800; /* super standby range : [0x43000000~0x43000800], size = 2K */ /* tf used */ /memreserve/ 0x43080000 0x00010000; /* arisc dram code space range */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/ion/ion_sunxi.h> #include "sun8iw7p1-clk.dtsi" #include "sun8iw7p1-pinctrl.dtsi" / { model = "sun8iw7p1"; compatible = "allwinner,sun8iw7p1", "allwinner,,sun8iw7p1"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; twi0 = &twi0; twi1 = &twi1; twi2 = &twi2; spi0 = &spi0; spi1 = &spi1; scr0 = &scr0; gmac0 = &gmac0; global_timer0 = &soc_timer0; cci0 = &csi_cci0; csi_res0 = &csi_res0; vfe0 = &csi0; mmc0 = &sdc0; mmc2 = &sdc2; nand0 =&nand0; disp = &disp; pwm = &pwm; pwm0 = &pwm0; pwm1 = &pwm1; tv0 = &tv0; hdmi = &hdmi; boot_disp = &boot_disp; }; chosen { bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init"; linux,initrd-start = <0x0 0x0>; linux,initrd-end = <0x0 0x0>; }; cpus { enable-method = "allwinner,sun8iw7p1"; #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; regulators = "vdd-cpua"; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x1>; regulators = "vdd-cpua"; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x2>; regulators = "vdd-cpua"; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x3>; regulators = "vdd-cpua"; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; }; opp_dvfs_table:opp_dvfs_table { cluster_num = <1>; opp_table_count = <1>; cpu_opp_l_table0: opp_l_table0 { /* compatible = "operating-points-v2"; */ compatible = "allwinner,opp_l_table0"; opp-shared; opp00 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp01 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp02 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp03 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp04 { opp-hz = /bits/ 64 <912000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp05 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; }; }; n_brom { compatible = "allwinner,n-brom"; reg = <0x0 0x0 0x0 0xc000>; }; s_brom { compatible = "allwinner,s-brom"; reg = <0x0 0x0 0x0 0x10000>; }; prcm { compatible = "allwinner,prcm"; reg = <0x0 0x01f01400 0x0 0x400>; }; cpuscfg { compatible = "allwinner,cpuscfg"; reg = <0x0 0x01f01c00 0x0 0x400>; }; ion { compatible = "allwinner,sunxi-ion"; system { type = <ION_HEAP_TYPE_SYSTEM>; name = "system"; }; system_contig { type = <ION_HEAP_TYPE_SYSTEM_CONTIG>; name = "system_contig"; }; cma { type = <ION_HEAP_TYPE_DMA>; name = "cma"; }; }; dram: dram { compatible = "allwinner,dram"; clocks = <&clk_pll_ddr>; clock-names = "pll_ddr"; dram_clk = <672>; dram_type = <3>; dram_zq = <0x003F3FDD>; dram_odt_en = <1>; dram_para1 = <0x10f41000>; dram_para2 = <0x00001200>; dram_mr0 = <0x1A50>; dram_mr1 = <0x40>; dram_mr2 = <0x10>; dram_mr3 = <0>; dram_tpr0 = <0x04E214EA>; dram_tpr1 = <0x004214AD>; dram_tpr2 = <0x10A75030>; dram_tpr3 = <0>; dram_tpr4 = <0>; dram_tpr5 = <0>; dram_tpr6 = <0>; dram_tpr7 = <0>; dram_tpr8 = <0>; dram_tpr9 = <0>; dram_tpr10 = <0>; dram_tpr11 = <0>; dram_tpr12 = <168>; dram_tpr13 = <0x823>; }; memory@40000000 { device_type = "memory"; reg = <0x00000000 0x40000000 0x00000000 0x40000000>; }; gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; device_type = "gic"; interrupt-controller; reg = <0x0 0x01c81000 0 0x1000>, /* GIC Dist */ <0x0 0x01c82000 0 0x2000>, /* GIC CPU */ <0x0 0x01c84000 0 0x2000>, /* GIC VCPU Control */ <0x0 0x01c86000 0 0x2000>; /* GIC VCPU */ interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */ }; sid: sunxi-sid@01c14000 { compatible = "allwinner,sunxi-sid"; device_type = "sid"; reg = <0x0 0x01c14000 0 0x0200>; }; chipid: sunxi-chipid@01c14200 { compatible = "allwinner,sunxi-chipid"; device_type = "chipid"; reg = <0x0 0x01c14200 0 0x0200>; }; timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 0xff01>, /* Secure Phys IRQ */ <GIC_PPI 14 0xff01>; /* Non-secure Phys IRQ */ clock-frequency = <24000000>; arm,cpu-registers-not-fw-configured; }; wdt: watchdog@01c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x0 0x01c20ca0 0 0x18>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_SPI 120 4>, <GIC_SPI 121 4>, <GIC_SPI 122 4>, <GIC_SPI 123 4>; }; dvfs_table: dvfs_table { compatible = "allwinner,dvfs_table"; max_freq = <1200000000>; min_freq = <480000000>; lv_count = <8>; lv1_freq = <1200000000>; lv1_volt = <1300>; lv2_freq = <1104000000>; lv2_volt = <1240>; lv3_freq = <1008000000>; lv3_volt = <1160>; lv4_freq = <912000000>; lv4_volt = <1100>; lv5_freq = <720000000>; lv5_volt = <1000>; lv6_freq = <0>; lv6_volt = <1000>; lv7_freq = <0>; lv7_volt = <1000>; lv8_freq = <0>; lv8_volt = <1000>; }; dramfreq { compatible = "allwinner,sunxi-dramfreq"; reg = <0x0 0x01c62000 0x0 0x1000>, <0x0 0x01c63000 0x0 0x1000>, <0x0 0x01c20000 0x0 0x800>; interrupts = <GIC_SPI 66 0x4>; clocks = <&clk_pll_ddr>, <&clk_ahb1>; status = "okay"; }; uboot: uboot { }; gpu: gpu@0x01c40000 { compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0x01c40000 0x0 0x10000>; interrupts = <GIC_SPI 97 4>, <GIC_SPI 98 4>, <GIC_SPI 99 4>, <GIC_SPI 100 4>, <GIC_SPI 102 4>, <GIC_SPI 103 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clocks = <&clk_pll_gpu>, <&clk_gpu>; }; soc: soc@01c00000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; device_type = "soc"; sram-controller@01c00000 { device_type = "sram-controller"; compatible = "allwinner,sram_ctrl"; reg = <0x0 0x01c00000 0x0 0x24>; #address-cells = <1>; #size-cells = <1>; sram_a: sram@00000000 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00000000 0xc000>; emac_sram: sram-section@8000 { compatible = "allwinner,sun4i-a10-sram-a3-a4"; #size-cells = <1>; reg = <0x8000 0x4000>; status = "okay"; }; }; sram_d: sram@00010000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0000 { compatible = "allwinner,sun4i-a10-sram-d"; #size-cells = <1>; reg = <0x0000 0x1000>; status = "disabled"; }; }; }; dma0:dma-controller@01c02000 { compatible = "allwinner,sun8i-dma"; reg = <0x0 0x01c02000 0x0 0x1000>; interrupts = <GIC_SPI 50 4>; clocks = <&clk_dma>; #dma-cells = <1>; }; mbus0:mbus-controller@01c62000 { compatible = "allwinner,sun8i-mbus"; reg = <0x0 0x01c62000 0x0 0x110>; #mbus-cells = <1>; }; arisc { compatible = "allwinner,sunxi-arisc"; #address-cells = <2>; #size-cells = <2>; clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>; clock-names = "losc", "iosc", "hosc", "pll_periph0"; powchk_used = <0x0>; power_reg = <0x02309621>; system_power = <50>; }; arisc_space { compatible = "allwinner,arisc_space"; /* num dst offset size */ space1 = <0x00040000 0x00000000 0x0000c000>; /*srama2*/ space2 = <0x43080000 0x00000000 0x00010000>; /*dram*/ space3 = <0x00000000 0x00000000 0x00000000>; /*para*/ space4 = <0x0004b800 0x00000000 0x00000800>; /*msgpool*/ }; standby_space { compatible = "allwinner,standby_space"; /* num dst offset size */ space1 = <0x43000000 0x00000000 0x00000800>; }; msgbox: msgbox@1c17000 { compatible = "allwinner,msgbox"; clocks = <&clk_msgbox>; clock-names = "clk_msgbox"; reg = <0x0 0x01c17000 0x0 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>; status = "okay"; }; hwspinlock: hwspinlock@1c18000 { compatible = "allwinner,sunxi-hwspinlock"; clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>; clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus"; reg = <0x0 0x01c18000 0x0 0x1000>; num-locks = <8>; /* the number hwspinlock */ status = "okay"; }; s_cir0: s_cir@0x01f02000 { compatible = "allwinner,s_cir"; reg = <0x0 0x01f02000 0x0 0x400>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&s_cir0_pins_a>; clocks = <&clk_hosc>,<&clk_cpurcir>; ir_power_key_code = <0x1a>; ir_addr_code = <0xfb04>; supply = ""; supply_vol = ""; status = "okay"; }; s_uart0: s_uart@0x01f02800 { compatible = "allwinner,s_uart"; reg = <0x0 0x01f02800 0x0 0x400>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&s_uart0_pins_a>; status = "okay"; }; s_twi0: s_twi@0x01f02400 { compatible = "allwinner,s_twi"; reg = <0x0 0x01f02400 0x0 0x400>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&s_twi0_pins_a>; status = "okay"; }; s_cpuscfg: s_cpuscfg@0x01f01c00 { compatible = "allwinner,s_cpuscfg"; reg = <0x0 0x01f01c00 0x0 0x400>; status = "okay"; }; box_start_os: box_start_os0 { compatible = "allwinner,box_start_os"; start_type = <0x0>; irkey_used = <0x0>; pmukey_used = <0x0>; pmukey_num = <0x0>; led_power = <0x0>; led_state = <0x0>; status = "disable"; }; soc_timer0: timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; device_type = "soc_timer"; reg = <0x0 0x01c20c00 0x0 0x90>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; /* On FPGA, timer can only use the losc. * On IC, timer should use the hosc. */ clocks = <&clk_hosc>, <&clk_losc>; }; rtc: rtc@01f000000 { compatible = "allwinner,sun8i-rtc"; device_type = "rtc"; reg = <0x0 0x01f00000 0x0 0x1FC>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; gpr_offset = <0x100>; gpr_len = <4>; }; ve: ve@01c0e000 { compatible = "allwinner,sunxi-cedar-ve"; reg = <0x0 0x01c0e000 0x0 0x1000>, <0x0 0x01c00000 0x0 0x10>, <0x0 0x01c20000 0x0 0x800>; interrupts = <GIC_SPI 58 4>; clocks = <&clk_pll_ve>, <&clk_ve>; }; uart0: uart@01c28000 { compatible = "allwinner,sun8i-uart"; device_type = "uart0"; reg = <0x0 0x01c28000 0x0 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_uart0>; pinctrl-0 = <&uart0_pins_a>; pinctrl-1 = <&uart0_pins_b>; pinctrl-names = "default", "sleep"; uart0_port = <0>; uart0_type = <2>; status = "okay"; }; uart1: uart@01c28400 { compatible = "allwinner,sun8i-uart"; device_type = "uart1"; reg = <0x0 0x01c28400 0x0 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_uart1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pins_a>; pinctrl-1 = <&uart1_pins_b>; uart1_port = <1>; uart1_type = <8>; status = "okay"; }; uart2: uart@01c28800 { compatible = "allwinner,sun8i-uart"; device_type = "uart2"; reg = <0x0 0x01c28800 0x0 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_uart2>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart2_pins_a>; pinctrl-1 = <&uart2_pins_b>; uart2_port = <2>; uart2_type = <4>; status = "disabled"; }; uart3: uart@01c28c00 { compatible = "allwinner,sun8i-uart"; device_type = "uart3"; reg = <0x0 0x01c28c00 0x0 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_uart3>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pins_a>; pinctrl-1 = <&uart3_pins_b>; uart3_port = <3>; uart3_type = <4>; status = "disabled"; }; twi0: twi@0x01c2ac00{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi0"; reg = <0x0 0x01c2ac00 0x0 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_twi0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi0_pins_a>; pinctrl-1 = <&twi0_pins_b>; status = "okay"; }; twi1: twi@0x01c2b000{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi1"; reg = <0x0 0x01c2b000 0x0 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_twi1>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi1_pins_a>; pinctrl-1 = <&twi1_pins_b>; status = "okay"; }; twi2: twi@0x01c2b400{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi2"; reg = <0x0 0x01c2b400 0x0 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_twi2>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi2_pins_a>; pinctrl-1 = <&twi2_pins_b>; status = "disabled"; }; spi0: spi@01c68000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-spi"; device_type = "spi0"; reg = <0x0 0x01c68000 0x0 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_pll_periph0>, <&clk_spi0>; clock-frequency = <100000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_pins_a &spi0_pins_b>; pinctrl-1 = <&spi0_pins_c>; spi0_cs_number = <2>; spi0_cs_bitmap = <3>; status = "okay"; }; spi1: spi@01c69000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-spi"; device_type = "spi1"; reg = <0x0 0x01c69000 0x0 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_pll_periph0>, <&clk_spi1>; clock-frequency = <100000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_a &spi1_pins_b>; pinctrl-1 = <&spi1_pins_c>; spi1_cs_number = <2>; spi1_cs_bitmap = <3>; status = "disabled"; }; usbc0:usbc0@0 { device_type = "usbc0"; compatible = "allwinner,sunxi-otg-manager"; usb_port_type = <2>; usb_detect_type = <1>; usb_detect_mode = <0>; usb_id_gpio; usb_det_vbus_gpio; usb_drv_vbus_gpio; usb_host_init_state = <0>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; usb_luns = <3>; usb_serial_unique = <0>; usb_serial_number = "20080411"; rndis_wceis = <1>; status = "okay"; }; udc:udc-controller@0x01c19000 { compatible = "allwinner,sunxi-udc"; reg = <0x0 0x01c19000 0x0 0x1000>, /*udc base*/ <0x0 0x01c00000 0x0 0x100>; /*sram base*/ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy0>, <&clk_usbotg>; status = "okay"; }; ehci0:ehci0-controller@0x01c1a000 { compatible = "allwinner,sunxi-ehci0"; reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy0>, <&clk_usbehci0>; hci_ctrl_no = <0>; status = "okay"; }; ohci0:ohci0-controller@0x01c1a400 { compatible = "allwinner,sunxi-ohci0"; reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy0>, <&clk_usbohci0>; hci_ctrl_no = <0>; status = "okay"; }; usbc1:usbc1@0 { device_type = "usbc1"; usb_drv_vbus_gpio; usb_host_init_state = <1>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "okay"; }; ehci1:ehci1-controller@0x01c1b000 { compatible = "allwinner,sunxi-ehci1"; reg = <0x0 0x01c1b000 0x0 0xFFF>, /*hci1 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy1>, <&clk_usbehci1>; hci_ctrl_no = <1>; status = "okay"; }; ohci1:ohci1-controller@0x01c1b400 { compatible = "allwinner,sunxi-ohci1"; reg = <0x0 0x01c1b000 0x0 0xFFF>, /*hci1 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy1>, <&clk_usbohci1>; hci_ctrl_no = <1>; status = "okay"; }; usbc2:usbc2@0 { device_type = "usbc2"; usb_drv_vbus_gpio; usb_host_init_state = <1>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "okay"; }; ehci2:ehci2-controller@0x01c1c000 { compatible = "allwinner,sunxi-ehci2"; reg = <0x0 0x01c1c000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy2>, <&clk_usbehci2>; hci_ctrl_no = <2>; status = "okay"; }; ohci2:ohci2-controller@0x01c1c400 { compatible = "allwinner,sunxi-ohci2"; reg = <0x0 0x01c1c000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy2>, <&clk_usbohci2>; hci_ctrl_no = <2>; status = "okay"; }; usbc3:usbc3@0 { device_type = "usbc3"; usb_drv_vbus_gpio; usb_host_init_state = <1>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "okay"; }; ehci3:ehci3-controller@0x01c1d000 { compatible = "allwinner,sunxi-ehci3"; reg = <0x0 0x01c1d000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy3>, <&clk_usbehci3>; hci_ctrl_no = <3>; status = "okay"; }; ohci3:ohci3-controller@0x01c1d400 { compatible = "allwinner,sunxi-ohci3"; reg = <0x0 0x01c1d000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_usbphy3>, <&clk_usbohci3>; hci_ctrl_no = <3>; status = "okay"; }; codec:codec@0x01c22c00 { compatible = "allwinner,sunxi-internal-codec"; reg = <0x0 0x01c22c00 0x0 0x2bc>,/*digital baseadress*/ <0x0 0x01f015c0 0x0 0x4>;/*analog baseadress*/ clocks = <&clk_pll_audio>,<&clk_adda>; headphonevol = <0x3b>; spkervol = <0x1b>; maingain = <0x4>; hp_dirused = <0x0>; pa_sleep_time = <0x15e>; status = "okay"; }; cpudai:cpudai0-controller@0x01c22c00 { compatible = "allwinner,sunxi-internal-cpudai"; reg = <0x0 0x01c22c00 0x0 0x2bc>;/*digital baseadress*/ status = "okay"; }; daudio0:daudio@0x01c22000 { compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x01c22000 0x0 0x70>; clocks = <&clk_pll_audio>,<&clk_i2s0>; pinctrl-names = "default","sleep"; pinctrl-0 = <&daudio0_pins_a>; pinctrl-1 = <&daudio0_pins_b>; pcm_lrck_period = <0x20>; slot_width_select = <0x20>; daudio_master = <0x04>; audio_format = <0x01>; signal_inversion = <0x01>; frametype = <0x0>; tdm_config = <0x01>; mclk_div = <0x0>; tdm_num = <0x0>; status = "disabled"; }; daudio1:daudio@0x01c22400 { compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x01c22400 0x0 0x70>; pinctrl-names = "default","sleep"; pinctrl-0 = <&daudio1_pins_a>; pinctrl-1 = <&daudio1_pins_b>; clocks = <&clk_pll_audio>,<&clk_i2s1>; pcm_lrck_period = <0x20>; slot_width_select = <0x20>; daudio_master = <0x04>; audio_format = <0x01>; signal_inversion = <0x01>; frametype = <0x0>; tdm_config = <0x01>; mclk_div = <0x0>; tdm_num = <0x1>; status = "disabled"; }; audiohdmi:daudio@0x01c22800{ compatible = "allwinner,sunxi-tdmhdmi"; reg = <0x0 0x01c22800 0x0 0x58>; clocks = <&clk_pll_audio>,<&clk_i2s2>; status = "okay"; }; spdif:spdif-controller@0x01c21000{ compatible = "allwinner,sunxi-spdif"; reg = <0x0 0x01c21000 0x0 0x38>; clocks = <&clk_pll_audio>,<&clk_owa>; pinctrl-names = "default","sleep"; pinctrl-0 = <&spdif_pins_a>; pinctrl-1 = <&spdif_pins_b>; status = "okay"; }; sndcodec:sound@0 { compatible = "allwinner,sunxi-codec-machine"; interrupts = <GIC_SPI 29 4>; sunxi,cpudai-controller = <&cpudai>; sunxi,audio-codec = <&codec>; hp_detect_case = <0x00>; /* jack_det_gpio = <&pio PH 12 1 0 1 0>; */ /* invert: 0->high is plug_in, 1->high is plug_out */ jack_invert = <1>; status = "okay"; }; snddaudio0:sound@1{ compatible = "allwinner,sunxi-daudio0-machine"; sunxi,daudio0-controller = <&daudio0>; status = "okay"; }; snddaudio1:sound@2{ compatible = "allwinner,sunxi-daudio1-machine"; sunxi,daudio1-controller = <&daudio1>; status = "okay"; }; sndhdmi:sound@3{ compatible = "allwinner,sunxi-hdmi-machine"; sunxi,hdmi-controller = <&audiohdmi>; status = "okay"; }; sndspdif:sound@4{ compatible = "allwinner,sunxi-spdif-machine"; sunxi,spdif-controller = <&spdif>; status = "disabled"; }; sdc2: sdmmc@01C11000 { compatible = "allwinner,sunxi-mmc-v4p10x"; device_type = "sdc2"; reg = <0x0 0x01C11000 0x0 0x1000>; interrupts = <GIC_SPI 62 0x0104>; /* */ clocks = <&clk_hosc>,<&clk_pll_periph0>, <&clk_sdmmc2_module>,<&clk_sdmmc2_mode>, <&clk_sdmmc2_bus>,<&clk_sdmmc2_rst>; clock-names = "osc24m","pll_periph","mmc", "sdmmc2mod","ahb","rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc2_pins_a>; pinctrl-1 = <&sdc2_pins_b>; bus-width = <8>; cap-mmc-highspeed; cap-sd-highspeed; mmc-ddr-1_8v; /*mmc-hs200-1_8v;*/ /*mmc-hs400-1_8v;*/ non-removable; /*max-frequency = <200000000>;*/ max-frequency = <50000000>; cap-erase; mmc-high-capacity-erase-size; /*-- speed mode --*/ /*sm0: DS26_SDR12*/ /*sm1: HSSDR52_SDR25*/ /*sm2: HSDDR52_DDR50*/ /*sm3: HS200_SDR104*/ /*sm4: HS400*/ /*-- frequency point -- /*f0: CLK_400K*/ /*f1: CLK_25M*/ /*f2: CLK_50M*/ /*f3: CLK_100M*/ /*f4: CLK_150M*/ /*f5: CLK_200M*/ sdc_tm4_sm0_freq0 = <0>; sdc_tm4_sm0_freq1 = <0>; sdc_tm4_sm1_freq0 = <0x00000000>; sdc_tm4_sm1_freq1 = <0>; sdc_tm4_sm2_freq0 = <0x00000000>; sdc_tm4_sm2_freq1 = <0>; sdc_tm4_sm3_freq0 = <0x05000000>; sdc_tm4_sm3_freq1 = <0x00000005>; sdc_tm4_sm4_freq0 = <0x00050000>; sdc_tm4_sm4_freq1 = <0x00000004>; /*vmmc-supply = <®_3p3v>;*/ /*vqmc-supply = <®_3p3v>;*/ /*vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ /*sunxi-power-save-mode;*/ /*status = "disabled";*/ status = "okay"; }; sdc0: sdmmc@01c0f000 { compatible = "allwinner,sunxi-mmc-v4p00x"; device_type = "sdc0"; reg = <0x0 0x01c0f000 0x0 0x1000>; /* only sdmmc0 */ interrupts = <GIC_SPI 60 0x0104>; /* */ clocks = <&clk_hosc>,<&clk_pll_periph0>, <&clk_sdmmc0_mod>,<&clk_sdmmc0_bus>, <&clk_sdmmc0_rst>; clock-names = "osc24m","pll_periph","mmc","ahb","rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc0_pins_a>; pinctrl-1 = <&sdc0_pins_b>; max-frequency = <50000000>; bus-width = <4>; /*broken-cd;*/ /*non-removable;*/ /*cd-inverted*/ cd-gpios = <&pio PF 6 0 1 2 1>; /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ cap-sd-highspeed; cap-mmc-highspeed; cap-wait-while-busy; /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*cap-sdio-irq;*/ /*keep-power-in-suspend;*/ /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/ /*sunxi-dly-104M = <1 0 0 0>;*/ /*sunxi-dly-208M = <1 0 0 0>;*/ /*sunxi-dly-104M-ddr = <1 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0>;*/ status = "okay"; /*status = "disabled";*/ }; sdc1: sdmmc@1C10000 { compatible = "allwinner,sunxi-mmc-v4p10x"; device_type = "sdc1"; reg = <0x0 0x1C10000 0x0 0x1000>; interrupts = <GIC_SPI 61 0x0104>; /* */ clocks = <&clk_hosc>,<&clk_pll_periph0>, <&clk_sdmmc1_module>,<&clk_sdmmc1_mode>, <&clk_sdmmc1_bus>,<&clk_sdmmc1_rst>; clock-names = "osc24m","pll_periph","mmc", "sdmmc2mod","ahb","rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc1_pins_a>; pinctrl-1 = <&sdc1_pins_b>; max-frequency = <50000000>; bus-width = <4>; /*broken-cd;*/ /*cd-inverted*/ /*cd-gpios = <&pio PG 6 6 1 2 0>;*/ /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ cap-sd-highspeed; cap-mmc-highspeed; /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*sd-uhs-sdr104;*/ /*cap-sdio-irq;*/ /*keep-power-in-suspend;*/ /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0 0>;*/ /*sunxi-dly-52M-ddr4 = <1 0 0 0 2>;*/ /*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/ /*sunxi-dly-104M = <1 0 0 0 1>;*/ /*sunxi-dly-208M = <1 1 0 0 0>;*/ /*sunxi-dly-208M = <1 0 0 0 1>;*/ /*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/ status = "okay"; }; disp: disp@01000000 { compatible = "allwinner,sunxi-disp"; reg = <0x0 0x01000000 0x0 0x00300000>,/*de*/ <0x0 0x01c0c000 0x0 0xfff>,/*tcon0*/ <0x0 0x01c0d000 0x0 0xfff>;/*tcon1*/ interrupts = <GIC_SPI 86 0x0104>, <GIC_SPI 87 0x0104>; clocks = <&clk_de>,<&clk_tcon0>,<&clk_tcon1>; boot_disp = <0>; fb_base = <0>; status = "okay"; }; hdmi: hdmi@01ee0000 { compatible = "allwinner,sunxi-hdmi"; reg = <0x0 0x01ee0000 0x0 0x20000>; clocks = <&clk_hdmi>,<&clk_hdmi_slow>; status = "okay"; }; tv0: tv0@01c94000 { compatible = "allwinner,sunxi-tv"; reg = <0x0 0x01e00000 0x0 0x100>; clocks = <&clk_tve>; device_type = "tv0"; pinctrl-names = "active","sleep"; status = "disabled"; }; soc_tr: tr@01000000 { compatible = "allwinner,sun8iw11-tr"; reg = <0x0 0x01000000 0x0 0x000200bc>; interrupts = <GIC_SPI 96 0x0104>; clocks = <&clk_de>; status = "disabled"; }; g2d: g2d@01e80000 { compatible = "allwinner,sunxi-g2d"; reg = <0x0 0x01e80000 0x0 0x800>; interrupts = <GIC_SPI 46 0x0104>; status = "disabled"; }; pwm: pwm@01c21400 { compatible = "allwinner,sunxi-pwm"; reg = <0x0 0x01c21400 0x0 0x154>; pwm-number = <1>; pwm-base = <0x1>; pwms = <&pwm0>, <&pwm1>; }; pwm0: pwm0@01c21400 { compatible = "allwinner,sunxi-pwm0"; pinctrl-names = "active", "sleep"; reg_base = <0x01c21400>; reg_busy_offset = <0x00>; reg_busy_shift = <28>; reg_polarity_offset = <0x00>; reg_polarity_shift = <5>; reg_peci_offset = <0x00>; reg_peci_shift = <0x00>; reg_peci_width = <0x01>; reg_pis_offset = <0x04>; reg_pis_shift = <0x00>; reg_pis_width = <0x01>; reg_crie_offset = <0x10>; reg_crie_shift = <0x00>; reg_crie_width = <0x01>; reg_cfie_offset = <0x10>; reg_cfie_shift = <0x01>; reg_cfie_width = <0x01>; reg_cris_offset = <0x14>; reg_cris_shift = <0x00>; reg_cris_width = <0x01>; reg_cfis_offset = <0x14>; reg_cfis_shift = <0x01>; reg_cfis_width = <0x01>; reg_clk_src_offset = <0x20>; reg_clk_src_shift = <0x07>; reg_clk_src_width = <0x02>; reg_bypass_offset = <0x20>; reg_bypass_shift = <0x05>; reg_bypass_width = <0x01>; reg_clk_gating_offset = <0x20>; reg_clk_gating_shift = <0x04>; reg_clk_gating_width = <0x01>; reg_clk_div_m_offset = <0x20>; reg_clk_div_m_shift = <0x00>; reg_clk_div_m_width = <0x04>; reg_pdzintv_offset = <0x30>; reg_pdzintv_shift = <0x08>; reg_pdzintv_width = <0x08>; reg_dz_en_offset = <0x30>; reg_dz_en_shift = <0x00>; reg_dz_en_width = <0x01>; reg_enable_offset = <0x40>; reg_enable_shift = <0x00>; reg_enable_width = <0x01>; reg_cap_en_offset = <0x44>; reg_cap_en_shift = <0x00>; reg_cap_en_width = <0x01>; reg_period_rdy_offset = <0x60>; reg_period_rdy_shift = <0x0b>; reg_period_rdy_width = <0x01>; reg_pul_start_offset = <0x60>; reg_pul_start_shift = <0x0a>; reg_pul_start_width = <0x01>; reg_mode_offset = <0x60>; reg_mode_shift = <0x09>; reg_mode_width = <0x01>; reg_act_sta_offset = <0x60>; reg_act_sta_shift = <0x08>; reg_act_sta_width = <0x01>; reg_prescal_offset = <0x60>; reg_prescal_shift = <0x00>; reg_prescal_width = <0x08>; reg_entire_offset = <0x64>; reg_entire_shift = <0x10>; reg_entire_width = <0x10>; reg_active_offset = <0x64>; reg_active_shift = <0x00>; reg_active_width = <0x10>; }; pwm1: pwm1@01c21400 { compatible = "allwinner,sunxi-pwm1"; pinctrl-names = "active", "sleep"; reg_base = <0x01c21400>; reg_busy_offset = <0x00>; reg_busy_shift = <28>; reg_polarity_offset = <0x00>; reg_polarity_shift = <5>; reg_peci_offset = <0x00>; reg_peci_shift = <0x01>; reg_peci_width = <0x01>; reg_pis_offset = <0x04>; reg_pis_shift = <0x01>; reg_pis_width = <0x01>; reg_crie_offset = <0x10>; reg_crie_shift = <0x00>; reg_crie_width = <0x01>; reg_cfie_offset = <0x10>; reg_cfie_shift = <0x01>; reg_cfie_width = <0x01>; reg_cris_offset = <0x14>; reg_cris_shift = <0x01>; reg_cris_width = <0x01>; reg_cfis_offset = <0x14>; reg_cfis_shift = <0x01>; reg_cfis_width = <0x01>; reg_clk_src_offset = <0x20>; reg_clk_src_shift = <0x07>; reg_clk_src_width = <0x02>; reg_bypass_offset = <0x20>; reg_bypass_shift = <0x06>; reg_bypass_width = <0x01>; reg_clk_gating_offset = <0x20>; reg_clk_gating_shift = <0x04>; reg_clk_gating_width = <0x01>; reg_clk_div_m_offset = <0x20>; reg_clk_div_m_shift = <0x00>; reg_clk_div_m_width = <0x04>; reg_pdzintv_offset = <0x30>; reg_pdzintv_shift = <0x08>; reg_pdzintv_width = <0x08>; reg_dz_en_offset = <0x30>; reg_dz_en_shift = <0x00>; reg_dz_en_width = <0x01>; reg_enable_offset = <0x40>; reg_enable_shift = <0x01>; reg_enable_width = <0x01>; reg_cap_en_offset = <0x44>; reg_cap_en_shift = <0x01>; reg_cap_en_width = <0x01>; reg_period_rdy_offset = <0x80>; reg_period_rdy_shift = <0x0b>; reg_period_rdy_width = <0x01>; reg_pul_start_offset = <0x80>; reg_pul_start_shift = <0x0a>; reg_pul_start_width = <0x01>; reg_mode_offset = <0x80>; reg_mode_shift = <0x09>; reg_mode_width = <0x01>; reg_act_sta_offset = <0x80>; reg_act_sta_shift = <0x08>; reg_act_sta_width = <0x01>; reg_prescal_offset = <0x80>; reg_prescal_shift = <0x00>; reg_prescal_width = <0x08>; reg_entire_offset = <0x84>; reg_entire_shift = <0x10>; reg_entire_width = <0x10>; reg_active_offset = <0x84>; reg_active_shift = <0x00>; reg_active_width = <0x10>; }; boot_disp: boot_disp { compatible = "allwinner,boot_disp"; }; csi_cci0:cci@0x01cb3000 { compatible = "allwinner,sunxi-csi_cci"; reg = <0x0 0x01cb3000 0x0 0x1000>; /*0x01cb3000--0x01cb4000*/ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;/*SUNXI_IRQ_CSI0_CCI (SUNXI_GIC_START + 85) = 117*/ status = "disabled"; }; csi_res0:csi_res@0x01cb0000 { compatible = "allwinner,sunxi-csi"; reg = <0x0 0x01cb0000 0x0 0x1000>;/*0x01cb0000--0x01cb1000*/ clocks = <&clk_csi_s>, <&clk_csi_m>, <&clk_csi_misc>, <&clk_pll_periph0>, <&clk_hosc>,<&clk_pll_periph1>; clocks-index = <0 1 2 3 4 5>; status = "disabled"; }; csi0:vfe@0 { device_type= "csi0"; compatible = "allwinner,sunxi-vfe"; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;/*SUNXI_IRQ_CSI0 (SUNXI_GIC_START + 84 ) = 116*/ pinctrl-names = "default","sleep"; pinctrl-0 = <&csi0_pins_a>; pinctrl-1 = <&csi0_pins_b>; cci_sel = <0>; csi_sel = <0>; mipi_sel = <0>; isp_sel = <0>; csi0_sensor_list = <0>; csi0_mck = <&pio PE 1 2 0 1 0>; /*PD9 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/ status = "disabled"; csi0_dev0:dev@0{ csi0_dev0_mname = "ov5640"; csi0_dev0_twi_addr = <0x78>; csi0_dev0_pos = "rear"; csi0_dev0_isp_used = <0>; csi0_dev0_fmt = <0>; csi0_dev0_stby_mode = <0>; csi0_dev0_vflip = <0>; csi0_dev0_hflip = <0>; csi0_dev0_iovdd = "iovdd-csi"; csi0_dev0_iovdd_vol = <2800000>; csi0_dev0_avdd = "avdd-csi"; csi0_dev0_avdd_vol = <2800000>; csi0_dev0_dvdd = "dvdd-csi-18"; csi0_dev0_dvdd_vol = <1500000>; csi0_dev0_afvdd = "afvcc-csi"; csi0_dev0_afvdd_vol = <2800000>; csi0_dev0_power_en = <>; csi0_dev0_reset = <&pio PE 14 1 0 1 0>; /*PB03 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/ csi0_dev0_pwdn = <&pio PE 15 1 0 1 0>; /*PB10 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/ csi0_dev0_flash_en = <>; csi0_dev0_flash_mode = <>; csi0_dev0_af_pwdn = <>; csi0_dev0_act_used = <0>; csi0_dev0_act_name = "ad5820_act"; csi0_dev0_act_slave = <0x18>; status = "disabled"; }; csi0_dev1:dev@1{ csi0_dev1_mname = ""; csi0_dev1_twi_addr = <0x78>; csi0_dev1_pos = "rear"; csi0_dev1_isp_used = <1>; csi0_dev1_fmt = <0>; csi0_dev1_stby_mode = <0>; csi0_dev1_vflip = <0>; csi0_dev1_hflip = <0>; csi0_dev1_iovdd = "iovdd-csi"; csi0_dev1_iovdd_vol = <2800000>; csi0_dev1_avdd = "avdd-csi"; csi0_dev1_avdd_vol = <2800000>; csi0_dev1_dvdd = "dvdd-csi-18"; csi0_dev1_dvdd_vol = <1500000>; csi0_dev1_afvdd = "afvcc-csi"; csi0_dev1_afvdd_vol = <2800000>; csi0_dev1_power_en = <>; csi0_dev1_reset = <>; csi0_dev1_pwdn = <>; csi0_dev1_flash_en = <>; csi0_dev1_flash_mode = <>; csi0_dev1_af_pwdn = <>; csi0_dev1_act_used = <0>; csi0_dev1_act_name = "ad5820_act"; csi0_dev1_act_slave = <0x18>; status = "disabled"; }; }; Vdevice: vdevice@0{ compatible = "allwinner,sun8i-vdevice"; device_type = "Vdevice"; pinctrl-names = "default"; pinctrl-0 = <&vdevice_pins_a>; test-gpios = <&pio PG 10 1 2 2 1>; status = "disabled"; }; cryptoengine: ce@1c15000 { compatible = "allwinner,sunxi-ce"; device_name = "ce"; reg = <0x0 0x01c15000 0x0 0x80>, <0x0 0x01c15800 0x0 0x80>; /* Unused */ interrupts = <GIC_SPI 94 0xff01>, <GIC_SPI 80 0xff01>; /* Unused */ clock-frequency = <300000000 200000000>; /* 300MHz */ clocks = <&clk_ss>, <&clk_pll_periph0>; }; di:deinterlace@0x01400000{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sunxi-deinterlace"; reg = <0x0 0x01400000 0x0 0x77c>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_deinterlace> ,<&clk_pll_periph0>; status = "okay"; }; scr0:smartcard@0x01c2c400{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sunxi-scr"; reg = <0x0 0x01c2c400 0x0 0x400>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_scr>, <&clk_apb2>; clock-frequency = <24000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&scr0_pins_a &scr0_pins_b>; pinctrl-1 = <&scr0_pins_c>; status = "disabled"; }; nmi:nmi@0{ compatible = "allwinner,sunxi-nmi"; reg = <0x0 0x01c00030 0x0 0x0c>; nmi_irq_ctrl = <0x00>; nmi_irq_en = <0x08>; nmi_irq_status = <0x04>; status = "disabled"; }; nand0:nand0@01c03000 { compatible = "allwinner,sun8iw7-nand"; device_type = "nand0"; reg = <0x0 0x01c03000 0x0 0x1000>; /* nand0 */ interrupts = <GIC_SPI 70 0x04>; clocks = <&clk_pll_periph0>,<&clk_nand>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&nand0_pins_a &nand0_pins_b>; pinctrl-1 = <&nand0_pins_c>; nand0_regulator1 = "vcc-nand"; nand0_regulator2 = "none"; nand0_cache_level = <0x55aaaa55>; nand0_flush_cache_num = <0x55aaaa55>; nand0_capacity_level = <0x55aaaa55>; nand0_id_number_ctl = <0x55aaaa55>; nand0_print_level = <0x55aaaa55>; nand0_p0 = <0x55aaaa55>; nand0_p1 = <0x55aaaa55>; nand0_p2 = <0x55aaaa55>; nand0_p3 = <0x55aaaa55>; status = "okay"; }; sunxi_thermal_sensor:thermal_sensor{ compatible = "allwinner,thermal_sensor"; reg = <0x0 0x01c25000 0x0 0x84>, <0x0 0x01c14040 0x0 0x4>; interrupts = <GIC_SPI 31 IRQ_TYPE_NONE>; clocks = <&clk_hosc>,<&clk_ths>; clock-frequency = <6000000>; combine_num = <1>; sensor_num = <1>; shut_temp= <115>; status = "okay"; ths_combine0:ths_combine0{ compatible = "allwinner,ths_combine0"; #thermal-sensor-cells = <1>; combine_sensor_num = <1>; combine_sensor_type = "CPU"; combine_sensor_temp_type = "max"; combine_sensor_id = <0>; }; }; cpu_budget_cooling:cpu_budget_cool{ compatible = "allwinner,budget_cooling"; device_type = "cpu_budget_cooling"; #cooling-cells = <2>; status = "okay"; state_cnt = <5>; cluster_num = <1>; state0 = <1200000 4>; state1 = <1200000 3>; state2 = <1200000 2>; state3 = <1200000 1>; state4 = <504000 1>; }; gpu_cooling:gpu_cooling{ compatible = "allwinner,gpu_cooling"; device_type = "gpu_cooling"; reg = <0x0 0x0 0x0 0x0>; #cooling-cells = <2>; status = "okay"; state_cnt = <4>; state0 = <4>; state1 = <3>; state2 = <2>; state3 = <1>; }; thermal-zones{ soc_thermal{ polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&ths_combine0 0>; trips{ cpu_trip0:t0{ temperature = <85>; type = "passive"; hysteresis = <0>; }; cpu_trip1:t1{ temperature = <95>; type = "passive"; hysteresis = <0>; }; cpu_trip2:t2{ temperature = <105>; type = "passive"; hysteresis = <0>; }; gpu_trip0:t3{ temperature = <90>; type = "passive"; hysteresis = <0>; }; gpu_trip1:t4{ temperature = <100>; type = "passive"; hysteresis = <0>; }; gpu_trip2:t5{ temperature = <110>; type = "passive"; hysteresis = <0>; }; crt_trip:t6{ temperature = <115>; type = "critical"; hysteresis = <0>; }; }; cooling-maps{ bind0{ contribution = <0>; trip = <&cpu_trip0>; cooling-device = <&cpu_budget_cooling 1 1>; }; bind1{ contribution = <0>; trip = <&cpu_trip1>; cooling-device = <&cpu_budget_cooling 2 2>; }; bind2{ contribution = <0>; trip = <&cpu_trip2>; cooling-device = <&cpu_budget_cooling 3 4>; }; bind3{ contribution = <0>; trip = <&gpu_trip0>; cooling-device = <&gpu_cooling 1 1>; }; bind4{ contribution = <0>; trip = <&gpu_trip1>; cooling-device = <&gpu_cooling 2 2>; }; bind5{ contribution = <0>; trip = <&gpu_trip2>; cooling-device = <&gpu_cooling 3 3>; }; }; }; }; keyboard0:keyboard{ compatible = "allwinner,keyboard_2000mv"; reg = <0x0 0x01c21800 0x0 0x400>; interrupts = <GIC_SPI 30 IRQ_TYPE_NONE>; status = "disabled"; key_cnt = <5>; key0 = <190 115>; key1 = <390 114>; key2 = <600 139>; key3 = <800 28>; key4 = <980 102>; }; gmac0: eth@01c30000 { compatible = "allwinner,sunxi-gmac"; reg = <0x0 0x01c30000 0x0 0x40000>, <0x0 0x01c00030 0x0 0x04>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gmacirq"; clocks = <&clk_gmac>, <&clk_ephy>; clock-names = "gmac", "ephy"; phy-mode = "mii"; tx-delay = <7>; rx-delay = <31>; phy-rst; gmac-power0 = ""; gmac-power1 = ""; gmac-power2 = ""; status = "disabled"; }; emac0: eth@01c0B000 { compatible = "allwinner,sun4i-emac"; reg = <0x0 0x01c0b000 0x0 0x0c000>; pinctrl-names = "default"; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "emacirq"; clock-names = "emac"; phy = <&phy1>; phy-rst; allwinner,sram = <&emac_sram 1>; emac_power1 = ""; emac_power2 = ""; emac_power3 = ""; status = "disabled"; }; mdio: mdio@01c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x0 0x01c0b080 0x0 0x14>; #address-cells = <1>; #size-cells = <0>; status = "okay"; phy1: ethernet-phy@1 { reg = <1>; }; }; cpucfg@01c25c00 { compatible = "allwinner,sunxi-cpucfg"; reg = <0x0 0x01c25c00 0x0 0x288>; }; sysctl@01c00000 { /** *sun8iw7 use the region of cpus to bring up cpu1~3, *in order to compatible with current framework, use *this node to transmit the parameters of cpus. */ compatible = "allwinner,sunxi-sysctl"; reg = <0x0 0x01f01c00 0x0 0x288>; cpu-soft-entry; }; }; }; Link to comment Share on other sites More sharing options...
martinayotte Posted May 9, 2020 Share Posted May 9, 2020 Sorry, I don't see any things which could be obviously wrong ... Link to comment Share on other sites More sharing options...
joek Posted May 9, 2020 Author Share Posted May 9, 2020 44 minutes ago, martinayotte said: Sorry, I don't see any things which could be obviously wrong ... here is the goodix driver, as you can see at line 400, it fails on irq request, maybe the implementation has to be different? i mean is there other way of requesting IRQ? goodix.c Link to comment Share on other sites More sharing options...
joek Posted May 9, 2020 Author Share Posted May 9, 2020 here is the pinctrl debug info Quote [ 0.265668] sun8iw7p1-r-pinctrl r_pio: try to register 12 pins ... [ 0.265688] pinctrl core: registered pin 352 (PL0) on r_pio [ 0.265699] pinctrl core: registered pin 353 (PL1) on r_pio [ 0.265708] pinctrl core: registered pin 354 (PL2) on r_pio [ 0.265718] pinctrl core: registered pin 355 (PL3) on r_pio [ 0.265727] pinctrl core: registered pin 356 (PL4) on r_pio [ 0.265736] pinctrl core: registered pin 357 (PL5) on r_pio [ 0.265753] pinctrl core: registered pin 358 (PL6) on r_pio [ 0.265762] pinctrl core: registered pin 359 (PL7) on r_pio [ 0.265771] pinctrl core: registered pin 360 (PL8) on r_pio [ 0.265780] pinctrl core: registered pin 361 (PL9) on r_pio [ 0.265789] pinctrl core: registered pin 362 (PL10) on r_pio [ 0.265798] pinctrl core: registered pin 363 (PL11) on r_pio [ 0.265817] sun8iw7p1-r-pinctrl r_pio: failed to lookup the default state [ 0.265829] sun8iw7p1-r-pinctrl r_pio: failed to lookup the sleep state [ 0.266463] sun8iw7p1-r-pinctrl r_pio: initialized sunXi PIO driver [ 0.267417] sun8iw7p1-pinctrl pio: try to register 96 pins ... [ 0.267430] pinctrl core: registered pin 0 (PA0) on pio [ 0.267440] pinctrl core: registered pin 1 (PA1) on pio [ 0.267449] pinctrl core: registered pin 2 (PA2) on pio [ 0.267458] pinctrl core: registered pin 3 (PA3) on pio [ 0.267467] pinctrl core: registered pin 4 (PA4) on pio [ 0.267476] pinctrl core: registered pin 5 (PA5) on pio [ 0.267498] pinctrl core: registered pin 6 (PA6) on pio [ 0.267507] pinctrl core: registered pin 7 (PA7) on pio [ 0.267516] pinctrl core: registered pin 8 (PA8) on pio [ 0.267524] pinctrl core: registered pin 9 (PA9) on pio [ 0.267533] pinctrl core: registered pin 10 (PA10) on pio [ 0.267542] pinctrl core: registered pin 11 (PA11) on pio [ 0.267551] pinctrl core: registered pin 12 (PA12) on pio [ 0.267559] pinctrl core: registered pin 13 (PA13) on pio [ 0.267568] pinctrl core: registered pin 14 (PA14) on pio [ 0.267577] pinctrl core: registered pin 15 (PA15) on pio [ 0.267586] pinctrl core: registered pin 16 (PA16) on pio [ 0.267595] pinctrl core: registered pin 17 (PA17) on pio [ 0.267603] pinctrl core: registered pin 18 (PA18) on pio [ 0.267612] pinctrl core: registered pin 19 (PA19) on pio [ 0.267621] pinctrl core: registered pin 20 (PA20) on pio [ 0.267630] pinctrl core: registered pin 21 (PA21) on pio [ 0.267639] pinctrl core: registered pin 64 (PC0) on pio [ 0.267648] pinctrl core: registered pin 65 (PC1) on pio [ 0.267657] pinctrl core: registered pin 66 (PC2) on pio [ 0.267666] pinctrl core: registered pin 67 (PC3) on pio [ 0.267674] pinctrl core: registered pin 68 (PC4) on pio [ 0.267683] pinctrl core: registered pin 69 (PC5) on pio [ 0.267692] pinctrl core: registered pin 70 (PC6) on pio [ 0.267701] pinctrl core: registered pin 71 (PC7) on pio [ 0.267709] pinctrl core: registered pin 72 (PC8) on pio [ 0.267718] pinctrl core: registered pin 73 (PC9) on pio [ 0.267727] pinctrl core: registered pin 74 (PC10) on pio [ 0.267736] pinctrl core: registered pin 75 (PC11) on pio [ 0.267744] pinctrl core: registered pin 76 (PC12) on pio [ 0.267753] pinctrl core: registered pin 77 (PC13) on pio [ 0.267762] pinctrl core: registered pin 78 (PC14) on pio [ 0.267771] pinctrl core: registered pin 79 (PC15) on pio [ 0.267779] pinctrl core: registered pin 80 (PC16) on pio [ 0.267788] pinctrl core: registered pin 81 (PC17) on pio [ 0.267797] pinctrl core: registered pin 82 (PC18) on pio [ 0.267806] pinctrl core: registered pin 96 (PD0) on pio [ 0.267815] pinctrl core: registered pin 97 (PD1) on pio [ 0.267823] pinctrl core: registered pin 98 (PD2) on pio [ 0.267832] pinctrl core: registered pin 99 (PD3) on pio [ 0.267841] pinctrl core: registered pin 100 (PD4) on pio [ 0.267850] pinctrl core: registered pin 101 (PD5) on pio [ 0.267858] pinctrl core: registered pin 102 (PD6) on pio [ 0.267867] pinctrl core: registered pin 103 (PD7) on pio [ 0.267876] pinctrl core: registered pin 104 (PD8) on pio [ 0.267885] pinctrl core: registered pin 105 (PD9) on pio [ 0.267894] pinctrl core: registered pin 106 (PD10) on pio [ 0.267903] pinctrl core: registered pin 107 (PD11) on pio [ 0.267911] pinctrl core: registered pin 108 (PD12) on pio [ 0.267920] pinctrl core: registered pin 109 (PD13) on pio [ 0.267929] pinctrl core: registered pin 110 (PD14) on pio [ 0.267938] pinctrl core: registered pin 111 (PD15) on pio [ 0.267946] pinctrl core: registered pin 112 (PD16) on pio [ 0.267955] pinctrl core: registered pin 113 (PD17) on pio [ 0.267965] pinctrl core: registered pin 128 (PE0) on pio [ 0.267973] pinctrl core: registered pin 129 (PE1) on pio [ 0.267982] pinctrl core: registered pin 130 (PE2) on pio [ 0.267991] pinctrl core: registered pin 131 (PE3) on pio [ 0.268000] pinctrl core: registered pin 132 (PE4) on pio [ 0.268009] pinctrl core: registered pin 133 (PE5) on pio [ 0.268017] pinctrl core: registered pin 134 (PE6) on pio [ 0.268027] pinctrl core: registered pin 135 (PE7) on pio [ 0.268035] pinctrl core: registered pin 136 (PE8) on pio [ 0.268044] pinctrl core: registered pin 137 (PE9) on pio [ 0.268059] pinctrl core: registered pin 138 (PE10) on pio [ 0.268068] pinctrl core: registered pin 139 (PE11) on pio [ 0.268077] pinctrl core: registered pin 140 (PE12) on pio [ 0.268086] pinctrl core: registered pin 141 (PE13) on pio [ 0.268094] pinctrl core: registered pin 142 (PE14) on pio [ 0.268103] pinctrl core: registered pin 143 (PE15) on pio [ 0.268112] pinctrl core: registered pin 160 (PF0) on pio [ 0.268121] pinctrl core: registered pin 161 (PF1) on pio [ 0.268130] pinctrl core: registered pin 162 (PF2) on pio [ 0.268139] pinctrl core: registered pin 163 (PF3) on pio [ 0.268148] pinctrl core: registered pin 164 (PF4) on pio [ 0.268156] pinctrl core: registered pin 165 (PF5) on pio [ 0.268165] pinctrl core: registered pin 166 (PF6) on pio [ 0.268175] pinctrl core: registered pin 192 (PG0) on pio [ 0.268183] pinctrl core: registered pin 193 (PG1) on pio [ 0.268192] pinctrl core: registered pin 194 (PG2) on pio [ 0.268201] pinctrl core: registered pin 195 (PG3) on pio [ 0.268210] pinctrl core: registered pin 196 (PG4) on pio [ 0.268219] pinctrl core: registered pin 197 (PG5) on pio [ 0.268228] pinctrl core: registered pin 198 (PG6) on pio [ 0.268236] pinctrl core: registered pin 199 (PG7) on pio [ 0.268245] pinctrl core: registered pin 200 (PG8) on pio [ 0.268254] pinctrl core: registered pin 201 (PG9) on pio [ 0.268263] pinctrl core: registered pin 202 (PG10) on pio [ 0.268271] pinctrl core: registered pin 203 (PG11) on pio [ 0.268280] pinctrl core: registered pin 204 (PG12) on pio [ 0.268289] pinctrl core: registered pin 205 (PG13) on pio [ 0.268309] sun8iw7p1-pinctrl pio: failed to lookup the default state [ 0.268319] sun8iw7p1-pinctrl pio: failed to lookup the sleep state [ 0.269420] failed to create debugfs directory [ 0.269436] sun8iw7p1-pinctrl pio: initialized sunXi PIO driver Link to comment Share on other sites More sharing options...
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