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Orange Pi One strange/inaccurate behavior with SPI Clk (SPI0_CLK)


sunzone

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I came across a spi clk  problem with my Orange Pi One. 

A similar unanswered question has  previously been asked for Orange Pi Zero, but I started a new topic because of the new board.

I am  using  ARMBIAN 5.32.170913 nightly Ubuntu 16.04.3 LTS 4.11.12-sun8i

Everything is set up properly and spidev0.0 is created  and working.

 

Following is my /boot/armbianEnv.txt

verbosity=1
logo=disabled
console=both
disp_mode=1920x1080p60
fdtfile=sun8i-h3-orangepi-one.dtb
overlay_prefix=sun8i-h3
rootdev=UUID=a2df1e68-90c9-46a0-ab26-169cb43e35c8
rootfstype=ext4
overlays=spi-spidev i2c0 uart1 uart2 uart3
param_spidev_spi_bus=0
param_spidev_spi_cs=0

verbosity=1 logo=disabled console=both disp_mode=1920x1080p60 fdtfile=sun8i-h3-orangepi-one.dtb overlay_prefix=sun8i-h3 rootdev=UUID=a2df1e68-90c9-46a0-ab26-169cb43e35c8 rootfstype=ext4 overlays=spi-spidev i2c0 uart1 uart2 uart3 param_spidev_spi_bus=0 param_spidev_spi_cs=0

to test the spi, I created a small C program to send one signal of 0x11 every second.

SPI_MOSI works fine, but there is a problem with SPI_SCLK. If you see the following picture the first signal marked by an arrow should not exist,but some how it appears.

Yellow- SPI_CLK

Blue- SPI_MOSI

 

KakaoTalk_20170929_114853585.thumb.jpg.33fae81ed7f66210e96119947b4047df.jpg

 

CLK behavior is obviously weird.

Can someone please explain why this unwanted signal(marked with a red arrow) is passed ? And how can I get rid of it?

 

Because of this ADS131E04 chip is not working.

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12 minutes ago, sunzone said:

Can someone please explain why this unwanted signal(marked with a red arrow) is passed ? And how can I get rid of it?

 

 

Check latest kernel 4.13.4 if this is solved, otherwise, it is yet another issue to be dealt with. We currently don't provide new beta builds for this board, so you need to build it on your own (make sure to use switch EXPERT=yes) and chose NEXT branch. If you are not in a position to build on your own, we can enable auto building.

 

Edit: deleted duplicate post at other location.

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Hi,

exactly the same issue on an OPi2+ here, same Kernel. However, this extra clock pulse does not have any effect on the operation of my SPI slaves. I have connected an SPI TFT display and a PIC microcontroller on the same SPI bus but different chip selects.

If you monitor chip select and spi clock simultaneously on the scope, you will see that the extra clock cycle occurs around the falling edge of the cs signal, so the SPI slave "sees" only the falling edge of this clock pulse, and data is sampled on the rising edge in my case. I dont know the reason for the extra pulse, but as far I can say, it does not cause any problem.

 

Are you sure that the extra clock pulse is really the problem why your slave refuses working? Perhaps you can alter the sampling clock edge of the slave and play with the CPOL/CPHA settings.

 

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On 9/29/2017 at 1:47 PM, Igor said:

 

Check latest kernel 4.13.4 if this is solved, otherwise, it is yet another issue to be dealt with. We currently don't provide new beta builds for this board, so you need to build it on your own (make sure to use switch EXPERT=yes) and chose NEXT branch. If you are not in a position to build on your own, we can enable auto building.

 

Edit: deleted duplicate post at other location.

Latest kernal seems to have solved the problem. I checked with 4.13.10. and CLK behavior was similar but Chip Select works properly.

But I encountered with another SPI problem.

 

When I use SPI, most of the times SPI is stable. But some times it becomes unstable. Does anyone encounter with unstable SPI? 

Stable/Unstable  SPI status continues to last from from the boot to the next boot. In other words if SPI is unstable, by booting/restarting again SPI can be turned to stable sometimes; vise versa. After boot, if SPI is stable it continues to be stable till next boot ; vise versa.

armbianEnv.txt is almost same as mentioned above. I am using OPi One, 4.13.10 mainline kernal

 

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