Update
i created a patch to add +CONFIG_PHY_MOTORCOMM=y to the uboot defconfig since the chip is a Motorcomm YT8512C. Changed things up a little.
[ 0.000000] psci: probing for conduit method from DT.
[ 2.670967] rk_gmac-dwmac fe010000.ethernet: IRQ eth_lpi not found
[ 2.671508] rk_gmac-dwmac fe010000.ethernet: clock input or output? (input).
[ 2.671532] rk_gmac-dwmac fe010000.ethernet: TX delay(0x30).
[ 2.671546] rk_gmac-dwmac fe010000.ethernet: RX delay(0x10).
[ 2.671566] rk_gmac-dwmac fe010000.ethernet: integrated PHY? (no).
[ 2.671622] rk_gmac-dwmac fe010000.ethernet: clock input from PHY
[ 2.676655] rk_gmac-dwmac fe010000.ethernet: init for RGMII
[ 2.677175] rk_gmac-dwmac fe010000.ethernet: User ID: 0x30, Synopsys ID: 0x51
[ 2.677214] rk_gmac-dwmac fe010000.ethernet: DWMAC4/5
[ 2.677230] rk_gmac-dwmac fe010000.ethernet: DMA HW capability register supported
[ 2.677240] rk_gmac-dwmac fe010000.ethernet: RX Checksum Offload Engine supported
[ 2.677249] rk_gmac-dwmac fe010000.ethernet: TX Checksum insertion supported
[ 2.677258] rk_gmac-dwmac fe010000.ethernet: Wake-Up On Lan supported
[ 2.677395] rk_gmac-dwmac fe010000.ethernet: TSO supported
[ 2.677410] rk_gmac-dwmac fe010000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[ 2.677424] rk_gmac-dwmac fe010000.ethernet: Enabled RFS Flow TC (entries=10)
[ 2.677439] rk_gmac-dwmac fe010000.ethernet: TSO feature enabled
[ 2.677450] rk_gmac-dwmac fe010000.ethernet: Using 32/32 bits DMA host/device width
[ 13.145407] rk_gmac-dwmac fe010000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[ 13.147665] rk_gmac-dwmac fe010000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211E Gigabit Ethernet] (irq=POLL)
[ 14.151864] rk_gmac-dwmac fe010000.ethernet: Failed to reset the dma
[ 14.151894] rk_gmac-dwmac fe010000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 14.151904] rk_gmac-dwmac fe010000.ethernet eth0: __stmmac_open: Hw setup failed
Here is current dts
ethernet@fe010000 {
compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a";
reg = <0x00 0xfe010000 0x00 0x10000>;
interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>;
interrupt-names = "macirq\0eth_wake_irq";
clocks = <0x0e 0x186 0x0e 0x189 0x0e 0x189 0x0e 0xc7 0x0e 0xc3 0x0e 0xc4 0x0e 0x189 0x0e 0xc8>;
clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref";
resets = <0x0e 0xec>;
reset-names = "stmmaceth";
rockchip,grf = <0x1d>;
snps,axi-config = <0x43>;
snps,mixed-burst;
snps,mtl-rx-config = <0x44>;
snps,mtl-tx-config = <0x45>;
snps,tso;
status = "okay";
assigned-clocks = <0x0e 0x189 0x0e 0x187 0x0e 0x186>;
assigned-clock-parents = <0x0e 0x187 0x0e 0x186 0x46>;
clock_in_out = "input";
phy-supply = <0x18>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <0x47 0x48 0x49 0x4a 0x4b 0x4c>;
snps,reset-gpio = <0x4d 0x01 0x01>;
snps,reset-active-low;
snps,reset-delays-us = <0x00 0x4e20 0x186a0>;
tx_delay = <0x30>;
rx_delay = <0x10>;
phy-handle = <0x4e>;
phandle = <0xe5>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0xe6>;
ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c915\0ethernet-phy-ieee802.3-c22";
reg = <0x00>;
status = "okay";
phandle = <0x4e>;
};
};
Will continue to work on, although any insight would be great. could use a nudge