Hi, I have tried that and the burn tool errors out
Uboot/Get Result/ Disk initial error
And this is the serial output
Attempt 1:
ATA transfer complete...
PIEI prepare done
DDR4 probe
ddr clke
DATA transfer complete...
AML DDR FW load done
DATA transfeone
DATA transfer complete...
AML DDR FW load done
DATA transization
INFO : End of write delay center optimization
INFO : Elly!
1D init succeed
DATA transfer complete...
Check phy resu 00000019 00000019 0000001a 00000017 00000019 00000017 00000018 00000018 00000019 dram_vref_reg_value 0x 0000006 1024MB
DMC_DDR_CTRL: 00e0001bDDR size: 2048MB
cs0 DataBus tesspi_post_bind(spifc): req_seq = 0
[MSG]MMC init in usb
aml_priSM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:800;NAND:82;SD?:20000;USB:8; cfg
ddr probe id done
DATA transfer complete...
fw parse donCheck phy result
INFO : End of initialization
INFO : ERROR : Tlt
INFO : End of initialization
0.0;C
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02
L0:00000000
L1:00000703
L2:00008067
L3:15000020
S1:00000000
B2:20282000
B1:a0f83180
TE: 2781386
BL2 Built : 20:29:41, Jun 18 2019. g12a ga659aac - luan.yuan@droid15-sz
Board ID = 12
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
DDR driver_vesion: LPDDR4_PHY_V_0_1_15 build time: Junfg
ddr probe id done
DATA transfer complete...
fw parse done
DATA transfer complete...
PIEI prepare done
DDR3 probe
ddr
DATA transfer complete...
dmc_version 0001
2MHz
DATA transfer complete...
dmc_version 0001
Check phy rnd of read delay center optimization
INFO : End of max read latINFO : End of 2D read delay Voltage center optimization
018 00000019 00000019 00000018 00000017 00000019 00000016 000000t
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 201-2: Chip: SM1 Rev: C (2B:C - 10:2)
INFO: BL3-2: crypto enginv->desc_buf = 0x0000000073e40a70
aml_priv->desc_buf = 0x0000000[MSG]sof
Set Addr 10
Get DT cfg
Get DT cfg
Get DT cfg
set CFG
b 3 soc: sm1 plat: ac213 vari: 4g
Find match dtb: 2
clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
found!!!
nand init failed: -6
get_sys_clk_rate_mtd() 290, clocg
cmd [store init 3] init failed
[info]failed:
001000000, sz=0x14552
[MSG]Burn complete
BULKcmd[download get_BULKcmd[disk_initial 1]
Amlogic multi-dtb tool
GZI0
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0,, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, statuscess
BULKcmd[ low_power]
[info]success
ID[16]
tplcmd[ P format, decompress...
Multi dtb detected
Multi d
emmc/sd response timeout, cmd55, status=0x1ff2800
co-phase 0x3k setting 200!
NAND device id: 0 ff ff ff ff ff
No NAND devicSM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:800;NAND:82;SD?:20000;USB:8;55. Force loop cfg
DATA transfer complete...
fw parse done
DAining
INFO : End of MPR read delay center optimization
INFO : INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
channel==0
RxClkDly_Margin_A0==149 ps 11
TxDqDly_Margin_A0==149 ps 11
RxClkDly_Margin_A1==rainedVREFDQ_A1==74
VrefDac_Margin_A0==29
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==28
DeviceVref_Margin_A1==40
channel==1
RxClkDly_Margin_A0==135 ps 10
TxDqDly_Margin_A0==149 ps fDac_Margin_A0==27
DeviceVref_Margin_A0==40
VrefDac_Margin_A1=t
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2012241b5 2019-07-02 17:22:49 luan.yuan@droid15-sz]
OPS=0x10
ri073e42db0
SDIO Port B: 0, SDIO Port C: 1
Cfg max: 5, cur: 2. Board id: 255. Force loop cfg
ddr probe idid done
DATA transfer complete...
fw parse done
DATA transfere id done
DATA transfer complete...
fw parse done
DATA transftage center optimization
=28
DeviceVref_Margin_A1==40
dwc_ddrphy_apb_wr((0<<20)|(2<<4
2D init succeed
ddr init done, boot next stage
result reporng efuse init
2b 0c 10 00 01 19 15 00 00 18 37 31 56 52 52 50 iver_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019 20:29:37
board id: 12
Cfg max: 5, cur: 1. Board id: 2er complete...
AML DDR FW load done
DATA transfer complete...
INFO : End of initialization
INFO : End of read dq deskew traINFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
149 ps 11
TxDqDly_Margin_A1==135 ps 10
TrainedVREFDQ_A0==74
T11
RxClkDly_Margin_A1==135 ps 10
TxDqDly_Margin_A1==149 ps 11
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==74
Vre16)|(0<<12)|(0xb0):0004
soc_vref_reg_value 0x 0000001a 00000 00000018 00000019 00000019 00000016 00000018 00000017 00000018 00000017 00000018 dram_vref_reg_value 0x 0000006t pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBu
[0.017355 Inits done]
secure task start!
high task start!
001000000, sz=0x14552
[MSG]Burn complete
BULKcmd[download get_ 0000000000200000 1
10: tee 0000000002000e 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400[info]success
[MSG]Burn Start...
[MSG]load dt.img to 0x000000000800000 1
01: recovery 0000000001800000 1
02: misc 0000, clock 400000
emmc/sd response timeout, cmd8, response timeout, cmd8, status=0x1ff2800
co-phase 0x3, tx-dly 0
ID[16]
tplcmd[ echo 12345]
12345
[MSG]ret = 0
[info]sucstatus]
[info]success
oot 0000000001000000 1
set has_boot_slot = 0
07: rsv 000esponse timeout, cmd55, status=0x1ff2800
co-phase 0x3, tx-dly 0
nand init failed: -6
NAND init failed
deviceINFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO :149 ps 11
TxDqDly_Margin_A1==135 ps 10
TrainedVREFDQ_A0==74
TDac_Margin_A0==28
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 18 2019c40b1
NOTICE: BL31: Built : 15:57:33, May 22 2019
NOTICE: BLEVICE_SECURE 0xb200000e
U-Boot 2015.01-g32cc24e (Aug 26 202SM1: transfer complete...
dmc_version 0001
Check phy result
INFd done
DATA transfer complete...
fw parse done
DATA transfer d!
Cfg max: 5, cur: 4. Board id: 255. Force loop cfg
ddr probend of initialization
INFO : End of read enable training
INFO : initialization
Training has run successfully!
channel==0
RxClkDly_Margin_A27
DeviceVref_Margin_A1==40
dwc_ddrphy_apb_wr((0<<20)|(2<<1 pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fSet Addr 14
Get DT cfg
82000
B1:a0f83180
TE: 2727178
BL2 Built : 20:29:41, Jun 1lete...
PIEI prepare done
DDR4 probe
ddr clk to 1152MHz
DATATA transfer complete...
dmc_version 0001
Check phy result
IPIEI prepare done
LPDDR4 probe
ddr clk to 1152MHz
DATA transf End of fine write leveling
INFO : End of Write leveling coarse 00000018 00000019 0000001a 00000016 00000017 00000016 00000019 00018 00000018 00000019 00000019 dram_vref_reg_value 0x 00000063 test pass
DATA transfer complete...
..
RUN bl2 usb boot
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12a_v1.1.3389-9Get DT cfg
Get DT cfg
set CFG
001000000, sz=0x14552
[MSG]Burn complete
BULKcmd[download get_ 4g
dtb 2 soc: sm1 plat: ac213 vari: 2g
dto 0000000000800000 1
01: recovery 0000000001800000 1
02: clock 400000
emmc/sd response timeout, cmd8, status=0x1ff2800
setting 200!
NAND device id: 0 ff ff ff ff ff
No NAND device 14552) fmt(normal)
[MSG]totalSlotNum = 0, nextWriteBackSlot 2
: sm1 platform: ac213 variant: 2g
dtb 0 soc: g12a plalti-dtb tool
Single dtb detected
parts: 17
00: log 0000000008000000 1
13: system 0000000080000000 1
14: proe found!!!
nand init failed: -6
NAND init fail
ID[16]
tplcmd[ echo 12345]
12345
[MSG]ret = 0
[info]success
BULKcmd[ low_power]
[info]success
ID[16]
tplcmd[ status]
[info]success
b 3 soc: sm1 plat: ac213 vari: 4g
Find match dtb: 2
rsv 0000000001000000 1
08: metadata 0000000001000000 1
09:0
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0,ut, cmd8, status=0x1ff2800
co-phase 0x3, tx-dly 0, clock 400000, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, statusþðüÿ<ø~
Attempt 2:
0.0;C
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 -plete...
PIEI prepare done
DDR4 probe
ddr clk to 1152MHz
DAT!
Cfg max: 5, cur: 3. Board id: 255. Force loop cfg
ddr probe
PIEI prepare done
LPDDR4 probe
ddr clk to 1152MHz
DATA transINFO : Training has run successfully!
Check phy result
INFO : f initialization
c40b1
NOTICE: BL31: Built : 15:57:33, May 22 2019
NOTICE: BL-13-gc341bc0 #1 Thu Jun 27 19:33:34 2019 +0800 arm
INFO: BL3spi_post_bind(spifc): req_seq = 0
[MSG]MMC init in usb
aml_priInUsbBurn
[MSG]sof
download mem dtb normal 83282]
[MSG]Down(mem) part(dtb) sz(0x000000800000 1
03: dtbo 0000000000800000 1
04: cri_data nand init failed: -6
get_sys_clk_rate_mtd() 290, clock setting BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;8 2019. g12a ga659aac - luan.yuan@droid15-sz
Board ID = 12
SCfg max: 5, cur: 2. Board id: 255. Force loop cfg
ddr probe id complete...
AML DDR FW load done
DATA transfer complete...
PIDATA transfer complete...
dmc_version 0001
Check phy result
of CA training
INFO : End of initialization
I delay
INFO : Training has run successfully!
Check phy result
el==1
RxClkDly_Margin_A0==149 ps 11
TxDqDly_Margin_A0==149 ps _A1==149 ps 11
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==74
Vrefa 00000018 00000016 00000018 00000016 0000001b 00000017 00000016 20:29:43
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 31: G12A normal boot!
0 - 10:58:36)
DRAM: 2 GiB
Relocation Offset is: 76e50000
InUsbBurn
tb tool version: v2 .
Support 4 dtbs.
aml_dt soc cri_data 0000000000800000 2
05: param 0000000001000000 2
emmc/sd response timeout, cmd55, status=0x1ff2800
co-phase 0x3k setting 200!
NAND device id: 0 ff ff ff ff ff
No NAND devic