Just look at this from datasheet and schematic perspective - ASM1164 needs SSC if SRIS is enabled, but according to datasheet of clock generator there is no SSC, so the original schem is not correct. There are three solutions:
1) place somehow clock with SSC or the best one is adding the independent clock for ASM1164
2) unsolder R29 to disable SRIS
3) disable SRIS by software
At this moment I choose number two, but if you find the third one I will stand on your side
Actually, SRIS means that RC and EP are clocked by different sources (I think it is like SSC where some jitter always exists), but in Radxa 5 ITX all the clocks are produced by one oscillator, so, SRIS is not right mode for this board. According to PCIe architecture the board uses Common REFCLK, not SRIS. Due to Common Clock the PLL of ASM1164 can't sync in SRIS mode because it needs a little deviation to be locked