@jock The schematic is maybe was a wrong example (I just search for rk3399 schematic, and take the first) in this case Leez P710,
but I also look at the RK3399_Design_Guide and find a interesting point, UART2 based on the sd card pins!!!
I already read a bit regarding the ddrbin_tool.py (which is part of the rkbin), which one could be used to manipulate the rockchip boot loader,
but until now I not really understood how this work, then I find this in the Rockpi4 schematic
I became enlightened.
In the ddrbin_tool_user_guide is the following:
* UART info
uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart.
uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2),
or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c).
uart baudrate: uart baudrate should be 115200 or 1500000.
I still don't understanding what the iomux (io multiplexing) is, but in theory if I change the uart iomux parameter to 1 then this should means that UART2A is used, which is SD card D0,D1 pins.
(Similar concept I see in Amlogic SoCs. )
So I read out the ddrbin parameters from rk3399_ddr_800MHz_v1.27.bin
./tools/ddrbin_tool.py RK3399 -g ddrbin_param.txt ./bin/rk33/rk3399_ddr_800MHz_v1.27.bin
then I change the UART parameters in the file ddrbin_param.txt like this:
uart id=2
uart iomux=1
uart baudrate=115200
then I write the parameters back
./tools/ddrbin_tool.py RK3399 ddrbin_param.txt ./bin/rk33/rk3399_ddr_800MHz_v1.27.bin
Then I build a new loader based on the rk3399_ddr_800MHz_v1.27.bin
./tools/boot_merger ./RKBOOT/RK3399MINIALL_1.27.ini
Content of the ./RKBOOT/RK3399MINIALL_1.27.ini
[CHIP_NAME]
NAME=RK330C
[VERSION]
MAJOR=1
MINOR=30
[CODE471_OPTION]
NUM=1
Path1=bin/rk33/rk3399_ddr_800MHz_v1.27.bin
Sleep=1
[CODE472_OPTION]
NUM=1
Path1=bin/rk33/rk3399_usbplug_v1.26.bin
[LOADER_OPTION]
NUM=2
LOADER1=FlashData
LOADER2=FlashBoot
FlashData=bin/rk33/rk3399_ddr_800MHz_v1.27.bin
FlashBoot=bin/rk33/rk3399_miniloader_v1.26.bin
[OUTPUT]
PATH=rk3399_loader_v1.27.126.bin
The result was uploaded in the emmc
rkdeveloptool db rk3399_loader_v1.27.126.bin
rkdeveloptool ul rk3399_loader_v1.27.126.bin
the I connected my microsd sniffer and after some praying I reset the device ...
Then the magic is happened 🤩
DDR Version 1.27 20211018
In
channel 0
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
256B stride
channel 0
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x18
MR4=0x1
MR5=0x1
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
channel 1, cs 0, advanced training done
change freq to 856MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x40
ch 1 ddrconfig = 0x101, ddrsize = 0x40
pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
ddr_set_rate to 328MHZ
ddr_set_rate to 666MHZ
ddr_set_rate to 416MHZ, ctl_index 0
ddr_set_rate to 856MHZ, ctl_index 1
support 416 856 328 666 MHz, current 856MHz
OUT
Boot1 Release Time: May 29 2020 17:36:36, version: 1.26
CPUId = 0x0
ChipType = 0x10, 645
SdmmcInit=2 0
BootCa
Yes, is working, I have debug output 😁 this is maybe not the best solution but I could start working running Armbian on this device.
The key point was:
So thanks again the advise.