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[Armbian build PR] - H3 ddr dynamic freq (experimental)


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Description

This is experimental support for DDR dynamic frequency changing for Allwinner H3.

It based on:

Due to H3 hardware bugs (see listing) it implemented by software "emulation" of MDFS:

  • It uses a special helper in the u-boot PSCI code. This is needed, because changing DDR freq is possible only in the SRAM.
  • Before freq changing all secondary CPU's put in the while(true) on PSCI handler (in SRAM). This is needed, because after DDR RAM enters self-refresh mode any RAM access leads to a complete freeze. We must suspend all execution on any secondary cores to prevent this.
  • And, finally, call PSCI callback SUNXI_PSCI_DRAM_DVFS_REQ on CPU0 for changing frequency.

Not great, but works.

Similar way implemented in the original legacy sunxi kernels: https://github.com/Tina-Linux/tina-v83x-linux-4.9/blob/master/drivers/devfreq/dramfreq/sunxi-ddrfreq.c#L1373 But instead of PSCI in u-boot it uses a dirty hack by writing code from kernel to the SRAM.

P.S.II'm not sure if this module should be enabled by default. Most of users want performance instead of power saving. Maybe better and safer to disable this in DT (by status = "disabled"). And who needs it can enable using DT overlay.

How Has This Been Tested?

Tested:

  • [x] h3 (orangepilite)

Not tested:

  • [ ] a33 (support added by this patches)
  • [ ] a83t (support added by this patches)
  • [ ] a64
  • [ ] h5

Checklist:

  • [x] My code follows the style guidelines of this project
  • [x] I have performed a self-review of my own code
  • [x] I have commented my code, particularly in hard-to-understand areas
  • [ ] I have made corresponding changes to the documentation
  • [x] My changes generate no new warnings
  • [x] Any dependent changes have been merged and published in downstream modules

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