God bless YOU!!!
According to this portion of a code [arch/arm64/kernel/cpuinfo.c: 384] (and other one):
if (IS_ENABLED(CONFIG_ARM64_SVE) &&
id_aa64pfr0_sve(info->reg_id_aa64pfr0))
info->reg_zcr = read_zcr_features();
Of course, I double-check this [if] statement and {IS_ENABLED(CONFIG_ARM64_SVE)} part gives [1] but other one not (this is obvious to us because the already present in our defconfig) ;(
And if WE all try to read this feature register [res_from_aa64pfr0_el1 (64-bit width)] WE will get (if I am right) some unpleasantness results ;( :
register uint64_t res_from_aa64pfr0_el1;
__asm__ __volatile__("mrs %[res_from_aa64pfr0_el1], id_aa64pfr0_el1 \n\t"
::[res_from_aa64pfr0_el1]"r"(res_from_aa64pfr0_el1)
:"memory", "cc");
printf("ID_AA64PFR0_EL1[0] 0x%" PRIX64 "\n", res_from_aa64pfr0_el1);
printf("ID_AA64PFR0_EL1[1] 0x%" PRIX64 "\n", res_from_aa64pfr0_el1 >> 32);
printf("ID_AA64PFR0_EL1.SVE 0x%" PRIX64 "\n", (res_from_aa64pfr0_el1 >> 32) & 0xF);
Our [CPU] doesn't have [SVE]. Please somebody proves me wrong!
