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  1. Something like that: add that to sources\linux-pine64-dev\sunxi64-next-20170125\arch\arm64\boot\dts\allwinner\sun50i-a64-pine64.dts make sure you have FORCE_CHECKOUT = "no" in &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; gt911@5d { compatibile = "goodix,gt911"; reg = <0x5d>; pinctrl-names = "default"; pinctrl-0 = <&gt911_irq_pin>, <&gt911_reset_pin>; interrput-parent = <&pio>; interrputs = <7 4 IRQ_TYPE_EDGE_RISING>; irq-gpios = <&pio 7 4>; reset-gpios = <&pio 7 11>; }; }; &pio { i2c0_pins: i2c0_pins { pins = "PH0", "PH1"; function = "i2c0"; }; gt911_irq_pin: gt911_irq_pin { pins = "PH4"; function = "irq"; }; gt911_reset_pin: gt911_reset_pin { pins = "PH11"; function = "gpio_out"; }; }; Note that i don't have pine64 and this is untested. After boot do: ls -lah /dev/input/by-path and try with evtest
  2. Look at the datasheet and schematics of pine64 and your screen. its looks that screen uses GT911 and on pine64 its connected by TWI0 with address 0x5d. PH4 as Interrupt pin, and PH11 as Reset pin.
  3. With legacy kernel there was different way to enable gt9xx touchscreen. With dev kernel you need to compile kernel drivers module (now it's called "goodix" ) in menuconfig it is in Drivers -> Input Devices -> Touchscreens -> "Goodix". But i think this drivers is compiled by default. After that you need to modify Device Tree, compile it, and boot board with it. Some info what add to Device Tree are in kernel source Documentation/devicetree/bindings/input/touchscreen/goodix.txt
  4. They included AXP803 without Lipo circuit. What a waste
  5. bomber

    H3 SPI

    For compiling my dtbo i used dtc located in /usr/src/linux-headers-4.6.7-sun8i/scripts/dtc , not system one located at /usr/bin/dtc Version: DTC 1.4.1-g4273dca2 it has -@ param
  6. Seams like NanoPi's microusb don't have direct connection to 5v rail, there is p-mosfet on the way, probably to eliminate short when connecting to PC with nanoPi powered from external source. So otg port can't provide power to external device.