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  1. ChrisK

    Tips on speeding up boot process M1/Neo

    That's just way too overgeneralized. Of course it is possible to speed up boot time, use a custom kernel and custom u-boot, while staying compatible to the "distro", which is merely the whole userspace stuff. Customizing a u-boot build, with ethernet and USB disabled will save the init tme for that. Removing the wait-time for user input gives another few seconds to save. Just because a system has some init system installed by default doesn't mean one has to use it. One can always tell the kernel what to use as init (PID 1). That can be the required app, or a shell, or some rudimentary script to start some networking, damons and then an app. One just has to be mindfull of what stuff needs to be started/required. Simply saying that nothing is compatible is rather silly and counterproductive. Greeting, Chris
  2. The isolcpus belongs into the bootargs in boot.cmd. For example, this will reserve core number 4: setenv bootargs console=ttyS0,115200 noinitrd root=/dev/mmcblk0p2 rootfstype=ext4 rootwait isolcpus=3 This will reserve cores 3 and 4: setenv bootargs console=ttyS0,115200 noinitrd root=/dev/mmcblk0p2 rootfstype=ext4 rootwait isolcpus=2,3 This will reserve cores 2 to 4: setenv bootargs console=ttyS0,115200 noinitrd root=/dev/mmcblk0p2 rootfstype=ext4 rootwait isolcpus=1-3 The isolcpus argument starts counting cores at 0. Keep in mind that the above are just examples, you may have the root file system elsewhere, for example. It is also possible to assign IRQ's to specific cores using the /proc/irq/... stuff, but i haven't tried that on the H3 yet, since in my own code i set the cpu affinity directly. That _may_ help a bit with latency for the audio i/o through the underlying driver stack, by assigning the irq of the audio hardware to a specific core as well. However, i don't know much about the way audio hardware is handled on the H3. If you want to get really nasty, i made a patch to the sunxi legacy kernel a while back, that allows a specific IRQ to be handled as fast as possibly, by bypassing a bunch of code in the Linux IRQ handler code. But that isn't for the faint of heart and may cause nasty side-effects. Greetings, Chris
  3. ChrisK

    Linksprite pcDuino4 Nano

    Funny, it looks exactly like the FriendlyArm NanoPi M1. Down to the silkscreen, even! The only change seems to be the removal of the FA label, and placing the pcDuino label there instead on the silkscreen.
  4. You can try to reserve one of the cores to the audio process(es). First you isolate a core by using the kernel parameter (boot argument) "isolcpus=...", and then you can use taskset to place threads/threads onto that core. In addition you should then also set a higher priority for those processes/threads. That way you have a complete core only for the audio processing, which should help a bit. Greetings, Chris
  5. ChrisK

    NanoPi Neo OTG power

    It can, it uses GPIOG12 as the OTG-ID input. That is true for the NanoPi Neo as well as the NanoPi M1. It's right there in the schematic... Greetings, Chris
  6. What does the syslog/dmesg say? Does the ethernet disconnect and reconnect often? Here's the thing with chinese vendors: They like to cut corners wherever they can. This doesn't mean that the OPi folks want it that way, it could easily be their own supplier. Cheap chinese power supplies are known for being of lousy quality (frankly, i personally wouldn't leave them plugged in unattended). Those QC stickers, if there are any, are just decoration. I think it would be at least worth try, don't you think? Use the charger plug from your phone, assuming that is of a decent quality, and see what happens then. Greetings, Chris
  7. Ha, it seems that the BananaPI M2+ _does_ have the SPDIF output. I just checked the datasheet: I was checking it because i was wondering why the heck they would use a PA pin on the cam header, whereas the NanoPI's just use all the PE signals, since PE has everything that is needed for the camera (it's the cam interface, after all). Turns out they made a a rather nasty typo. Check page 2, upper-left. In the chip symbol itself you see PA17/SPDIF_OUT/PA_EINT17, over the signal line they put the label "SPDIF_OUT", but they named the signal itself "PA16", probably by mistake. On page 9 then you see that signal PA16 ends up on pin 37 of the expansion header. So, according to the schematic the SPDIF output on the BananaPi M2+ is on pin 37 of that header, mislabelled as PA16. Greetings, Chris
  8. That's not possible. The OWA interface (which is what they call SPDIF in the Allwinner datasheet) can only use PA17, there is no other routing/multiplexing option. The same holds true for any other hardware peripherial of the chip. Check chapter 3.7 of the datasheet, "GPIO Multiplexing Functions". And if you do direct register access to set up pin functions, check chapter 4.22/4.23 to see what register settings are required to chose what pin is selected for which function/peripherial. The case of 1-Wire sensors etc. is different, since that is implemented in software (the H3 does not have a 1-Wire peripherial), and thus can be placed on any generic GPIO pin. Greetings, Chris
  9. Check the output of dmesg repeatedly. If you see a lot of ETH disconnects/connects, it is possible that your power supply is the issue. I had such an effect on a NanoPI M1, getting a lot of dis-/reconnects (and sometimes just settling at 10MBit after a while). The problem was the power supply, which simply wasn't stable enough. Used a different one (the charger of my Samsung phone), and the problem went away instantly. BTW, power supply quality also plays a big role in the stability in general. With a bad supply i can freeze my boards reliably when starting "stress -c 4 -i 4". Sometimes almost immediately, sometimes after a few seconds, but it always happens. Especially those cheap chinese supplies and cables are usually of really bad quality, causing all sorts of problems. Greetings, Chris
  10. ChrisK

    RT patches for sun8i kernel?

    Hi Igor, what exactly is the issue with the 39-112 patch? The overlay-patch (02-0003-linux-sunxi-3.4.108-overlayfs.patch) is included in that one. I have tested it here, and so far it works. Let me know what the issue is, the i can re-crete it and possibly fix the large patch. Greetings, Chris
  11. Hi, my current project is about using a NanoPI M1 as a controller for a 3D printer. As such, one wants to have very tight timing on the GPIO output, with as little jitter as possible, to get smooth motion of the stepper motors. However, it is common belief that getting a fast timing with little jitter is virtually impossible to do under linux, without the help of a dedicated chip just for the IO. While that is true in general on stock kernels, it's possible to vastly improve on that front by spending a little effort. One way on ARM chips is to use the FIQ. That is an interrupt that has the highest priority, which can interrupt all other, regular interrupts. However, modern chips use a GIC for interrupt control instead of a VIC, so adding a FIQ is not that easy. There are patches out there to do just that, but then, those are for newer kernels, and not the old, which is somewhat of the standard kernel for the time beeing. So, what to do? Well, diving into the kernel sources and do some nasty hacking, of course! To give a quick overview of how an interrupt is usually handled on our ARM platform: 1: IRQ happens, the IRQ controller notifies the CPU about that 2: A small assembly stub is invoked, which then jumps into a small routine, asm_do_IRQ() 3: That small routine calls another routine, handle_IRQ() 4: That in turn calls generic_handle_irq() 5: Which then calls handle_fasteoi_irq(), by using a pointer to that in the IRQ descriptor 6: Subsequently, handle_irq_event() is called 7: And since we are on a SMP machine, that in turn calls handle_irq_event_percpu() 8: And finally, that calls action->handler(), the _actual_ interrupt routine! Now, not only is that a long way to go, but in many of those functions a lot of other functions are called, many of which are by themselves interruptible/preemptible. No surprise then that there is little chance to get a tight timing... Now, this is where my nasty hack come in. Step 2 of the above list is preserved as it is, but in step 3, that is, in handle_IRQ(), i added some code. That code checks if the requested IRQ is one to quickly handle, and if it is, basically calls the real IRQ handler directly. This leads to _great_ improvements, as you can see in the following images. All scope images are with 10 second persistency turned on, so that glitches become visible. First, this is how it would normally look, without any patches at all. It is supposed to be a ~40kHz square wave: Basically just a blur. OK, most of that is because the interrupt runs on core 0, which is used by other stuff as well. I made a patch to have an IRQ attached to a specific core or cores (see this thread: Once the kernel has that patch applied, and the boot-arg isolcpus=3 is given, only the first 3 cores are used by the kernel, leaving the fourth one free. Attaching the used timer-IRQ to that core gives this result: Much better, but still a lot of jitter. Now, this is where the quickirq patch comes in. Applying that patch results in this: Now, that is already a _lot_ better. Is there still room for improvement? Yes, by applying the RT patch. Which gives the final result: In all the scope shots the board was running at 624MHz RAM, 1200MHz core, while in the background "stress -c 4 -i 4" was active, resulting in a cpu load of roundabout 9 according to top. Now, let's be clear: Using the quickirq patch is not for the faint of heart. One has to know exactly what she/he is doing, otherwise the kernel will very likely lock up. There are noc checks, no nothing, it assumes that the handler itself is set up and registered correctly. And that no other interrupt handler wants to attach itself (or is already attached) to that interrupt number. Also, it is no hard realtime. While the outcome is vastly improved, there still is the occasional jitter. However, it is quite good enough to control stepper motors within reasonable limits. Since my aim is tu use the nanoPI M1 to directly control stepper motors, it should be noted that a frequency of 40kHz would, if we assume 100 steps/mm, result in a speed of 400mm/s, or 40cm/s! More reasonable speeds of 200 or 300mm/s mean that any jitter that happens is less pronounced, relative to the pulse width itself. The patch also include a sample driver which will output a square wave on PA0. In the kernel menuconfig, under Device Drivers -> quickirq you can enable/disable the quickirq handling, define up to 3 interrupt numbers to handle through that patch, as well as enable the sample driver. The sample driver uses TMR1 of the H3, which is otherwise completely unused. TMR1 has interrupt number 51. The driver uses PA0, but it accesses the port registers directly. So if you have any other stuff that toggles GPIO pins on PORTA, that will interfere with the output of the sample driver. So, if you want to test it and look at the output on a scope, it's best to disable anything else on PORTA (like the heartbeat LED, for example). If the sample driver is loaded (either directly compiled into the kernel, or as a module and the "modprobe -i quickirq"), it creates a device node at /dev/quickirq. You can echo characters into that to control it: echo 0 > /dev/quickirq -> disable the timer echo 1 > /dev/quickirq -> enable the timer (squarewave appears on PA0) Sending it the numbers 2, 3, 4, 5, 6 and 7 changes the output frequency to (about) 10Hz, 100Hz, 1kHz, 10kHz, 20kHz and 40kHz repsectively. Sending it + or - will adjust the raw timer reload value in 1-increments, q and w in 10-increments, e and r in 100 increments. The shorter the intervall time gets (the higher the frequency), you will notice that there is a base overhead that can't be avoided. Like, the timer reload value for the 40kHz setting is half of that for the 20kHz setting, but the output is slightly less than double. It's just a crude example, after all. All that said, here is the patch: 0000-add-quickirq.patch.gz Have fun with it, hopefully it is useful for others as well. But keep in mind that this is a rather rude brute-force method. You _really_ have to know what you are doing! Greetings, Chris EDIT: Re-uploaded the patch
  12. ChrisK

    RT patches for sun8i kernel?

    Just to make sure the edit isn't overlooked: There was a bug in the full RT patch in the post above. Fixed it, and replaced the file in the previous post. Greetings, Chris
  13. ChrisK

    RT patches for sun8i kernel?

    Hi, Igor asked me if i could consolidate the RT patches into a single one, and only doing the extra patches seperately, so here they are. First, i added the fix for firmware_class.c in the 02-0005-backport-firmware-loader.patch, because that is what introduces the issue in the first place. So, that patch can be replaced by this file: 02-0005-backport-firmware-loader.patch.gz Then i took the liberty to consolidate all the patches that brings the kernel from 2.4.39 to 2.4.112 into a single one. I did so by first disabling all the patches from 02-0001-patch... down to z-0003... (leaving those before 02-0001 enabled), having the compile script apply the patches. Then i saved the kernel source tree, enabled these 39-112 patches: and ran again to have all those applied. Then i saved that source tree, and made single patch file. This one brings the kernel from 2.4.39 up to 2.4.112 in one patch: 02-0001-patch-3.4.39-112.patch.gz That means that in the lib/patch/kernel/sun8i-default directory all the patches in the above list can be removed and the single patch file be used instead. Here is the consolidated RT patch, which now includes the RT itself plus the fixes for it: 0000-rt143-full-plus-rt-fixes.patch.gz So all that is left is the patch for those who want to have irq_set_affinity_hin() work properly. I leave that one extra, because for one it doesn't change anything to the way the kernel operates and sets up IRQ's by default, and it also doesn't have anything to do with the RT patches as such. So, this applies opnly for those who write their own drivers (or want to modify existing ones) that use interrupts, and want to tie said IRQ's to a specific core (or cores): 0001-make-irq-set-affinity-hint-work-properly.patch.gz Greetings, Chris EDIT: There was a bug in the full RT patch. Fixed it, and replaced the file in this post!
  14. ChrisK

    RT patches for sun8i kernel?

    Hi, and here is another patch that should be added if the RT patch is applied. This one fixes BUG's that are triggered when using the interactive cpufreq governor. The probelm is that spin_lock_irqsave and spin_lock_irqrestore are used there, which leads to: BUG: scheduling while atomic: swapper/0/0/0x00000002 This patch makes it use the raw_ versions of those in case the PREEMPT_RT_FULL patch is applied. I wasn't aware of the issue until now, since i usually use the "userpsace" governor. Greetings, Chris 0006-cpufreq_interactive-spin_lock_for_rt.patch.gz
  15. Hi, attached is a patch for U-Boot (should work on 2016.09-rc1 and 2016-09-rc2-dirty, will probably work on older ones as well) that makes it use the plain text file uEnv.txt instead of boot.scr, which has to be translated to a binary file first. This way changing the environment means only editing a text file, instead of editing a file, converting it to binary, and copying it over to the /boot partition on the SD. This becomes active if the U-Boot config has the option OLD_SUNXI_COMPAT disabled (in the menuconfig this is under ARM architecture -> Enable workarounds for booting old kernels). It also adds a small patch to board/sunxi/board.c to skip the setting of the MAC address if the option CONFIG_CMD_NET is disabled. That way it is possible to leave out networking stuff and save some time at boot because it doesn't init the networking stuff. Personally i prefer a boot that is as quick as possible, because i just hate it to wait for no useful reason On my board it basically just falls through to immediately boot the kernel after power-up, because i have the wait time for user-input disabled as well in the config. As an example, this is what my uEnv.txt looks like, i have reserved a core and incresed the loglevel: machid=1029 bootm_boot_mode=sec bootargs=console=ttyS0,115200 noinitrd root=/dev/mmcblk0p2 rootfstype=ext4 rootwait loglevel=7 isolcpus=3 bootcmd=load mmc 0 0x43000000 script.bin; load mmc 0 0x40008000 uImage; bootm 0x40008000 Greetings, Chris 0000-use-uEnv.txt-by-default-on-sunxi.patch.gz