Follow-up: Given the fact that Linux was able to detect the presence of the eMMC chip at all, and that it was able to correctly identify the capacity, I figured that it was at least able to get rudimentary communication up and running. Since every MMC always starts up in SDR 1-bit mode by default, and then the host has the option to interrogate the chip for the possibility to negotiate a higher bus width and/or clock mode, I figured I'd try carefully re-introducing the interface with more limited capabilities.
My board has a Samsung KLM8G1GETF eMMC chip, and that part supports single-data-rate 26 MHz at all possible I/O voltages, single-data-rate 52 MHz at all possible I/O voltages, double-data-rate 52 MHz at all possible I/O voltages, HS200 (single-data-rate 200 Mhz at 1.8V only). and HS400 (double-data-rate 200 Mhz at 1.8V only).
Looking at the voltage rail fan-out in the schematic, it's pretty clear that it's physically impossible to power the eMMC's I/O bus at anything other than 3.3V, and so HS200 and HS400 are definitively off the table.
But the device tree bindings for sunxi-mmc don't seem to provide very much configuration to take away modes which I know cannot be supported. Really just the bus width. So, since it was apparent that Linux must have successfully connected to the eMMC in a 1-bit mode before, I tried re-enabling the eMMC interface, but limiting its bus width to 1 bit. At least that would eliminate the unsupportable HS200 and HS400 as possibilities; they cannot operate on a data bus narrower than 4 bits.
It worked, Armbian booted successfully, and I am able to see the eMMC and manipulate its partitions. It also seems to have detected the device as high-speed (and presumably single-data-rate):
[ 2.481613] mmc2: new high speed MMC card at address 0001
[ 2.483323] mmcblk2: mmc2:0001 8GTF4R 7.28 GiB
[ 2.488509] mmcblk2boot0: mmc2:0001 8GTF4R 4.00 MiB
[ 2.492442] mmcblk2boot1: mmc2:0001 8GTF4R 4.00 MiB
This is a reasonable milestone, I suppose -- the chip works and (not pictured) I can create and format partitions.
But it's still not ideal. It is supposed to be possible to operate with:
- SDR 4-bit and 8-bit data bus
- DDR at 52 MHz with 1-bit, 4-bit, and 8-bit data bus.
Ideally, I would like to try out each of these combinations in isolation so I can figure out where things are breaking. But it looks like this might be the sort of thing that I will not be able to configure using a patched dts alone - I might need to actually dig into the kernel sources themselves.
I still would appreciate pointers about where to go next.