stepw

So I've fiddled around with EMAC IC and its RGMII interface to PHY IC.
 
Some findings:
1. MII RXERC = 0 in mii-tool reg dump, supposedly that indicates PHY is not receiving erroneous frames
#mii-tool -vvv registers for MII PHY 0: 1140 796d 001c c915 01e1 cde1 000d 2001 6801 0300 7800 0000 0000 0000 0000 3000 016e acc2 9f01 0000 8040 1006 4100 2100 0000 8c00 0040 0106 21fc 8038 0123 0000  2. EMAC reports RGMII speed/duplex and clock is consistent with PHY link type
 
1Gbps/full: EMAC BASIC_CTL_0:  #devmem2 0x1c30000 w 0x1 = 1Gbps/full EMAC RGMII_STA:
#devmem2 0x1c300d0 w 0xD = 0b1101 - 1Gbps, 125MHz clock MII PHY:
#mii-tool -vvv   registers for MII PHY 0:     1140 796d 001c c915 0001 cde1 000f 2001     6801 0200 7800 0000 0000 0000 0000 3000     016e acc2 9f01 6c52 8040 1006 4100 2100     0000 8c00 0040 0106 21fc 8038 0123 0000 100Mbps/full: EMAC BASIC_CTL_0:  #devmem2 0x1c30000 w 0xD = 100Mbps/full EMAC RGMII_STA:
#devmem2 0x1c300d0 w 0xB = 0b1011 - 100Mbps, 25MHz clock MII PHY:
#mii-tool -vvv   registers for MII PHY 0:     1140 796d 001c c915 01e1 cde1 000d 2001     6801 0300 7800 0000 0000 0000 0000 3000     016e acc2 9f01 0000 8040 1006 4100 2100     0000 8c00 0040 0106 21fc 8038 0123 0000  
3. EMAC is using internal clock for 1Gbps/125MHz
A64 EMAC_CLK_REG:
#devmem2 0x1c00030 w clock 0b01 = GMII/RGMII external clock 0b10 = GMII/RGMII internal (default)  This said, there could be a problem with 125MHz clock sync, required for proper RGMII communication between EMAC and PHY at 1Gbps rate. Judging by latest PCB diagrams, PHY CLK125 is attached to EMAC, presumably to supply 125MHz clock to EMAC, however EMAC's internal clock is enabled (by the EMAC driver?), so EMAC and PHY clocks are not synchronized. However, switching to external clock (supplied by PHY?) results in even higher packet loss, upwards of 80%   I was trying to dump EMAC DMA TX/RX descriptors and buffers to get an idea of whether frames received by PHY make it to EMAC over RGMII and vice versa, but so far didn't manage to access them from userland. I guess it would take to debug EMAC driver to monitor them and accumulate TX/RX frames and errors statistics.