kostap

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  1. I have updated the 18.12 branch with patches from current development stream. Please check if it improves the stability. https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell/commits/A3700_utils-armada-18.12
  2. These boards are using MAC addresses defined in u-boot environment. They are usually not updated by the manufacturer of the evaluation platform. You can replace them by defining the following variables and issuing "saveenv" afterwards: ethaddr=00:51:82:11:22:00 eth1addr=00:51:82:11:22:01 eth2addr=00:51:82:11:22:02 eth3addr=00:51:82:11:22:03 ...etc.
  3. Hello, @FlashBurn, FYI, the XTAL clock readout was fixed by Marvall LSP, but not yet taken into the mainline sources. The fix is available here: https://github.com/MarvellEmbeddedProcessors/linux-marvell/commit/80d4cec4cef8282e5ac3aaf98ce3e68fb299a134 For reviewing the clock setup it is better to look though the a3700_utils sources. There is a big text table here describing the divider values: https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell/blob/A3700_utils-armada-18.12/wtmi/sys_init/clock.c
  4. @ebin-dev - tested your last flash image and it was working on my board: TIM-1.0 WTMI-devel-18.12.0-a0a1cb8 WTMI: system early-init SVC REV: 4, CPU VDD voltage: 1.108V NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.5(release):1f8ca7e (Marvell-devel-18.12.2) NOTICE: BL1: Built : 09:50:21, Feb 20 2019 NOTICE: BL1: Booting BL2 NOTICE: BL2: v1.5(release):1f8ca7e (Marvell-devel-18.12.2) NOTICE: BL2: Built : 09:50:23, Feb 20 2019 NOTICE: BL1: Booting BL31 NOTICE: BL31: v1.5(release):1f8ca7e (Marvell-devel-18.12.2) NOTICE: BL31: Built : 09:5 U-Boot 2018.03-devel-18.12.3-gc9aa92c-armbian (Feb 20 2019 - 09:45:04 +0100) Model: Marvell Armada 3720 Community Board ESPRESSOBin CPU 1000 [MHz] L2 800 [MHz] TClock 200 [MHz] DDR 800 [MHz] DRAM: 1 GiB Comphy chip #0: Comphy-0: USB3 5 Gbps Comphy-1: PEX0 2.5 Gbps Comphy-2: SATA0 6 Gbps SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: ncq led only pmp fbss pio slum part sxs PCIE-0: Link down MMC: sdhci@d0000: 0, sdhci@d8000: 1 Loading Environment from SPI Flash... SF: Detected w25q32dw with page size 256 Bytes, erase size 4 KiB, total 4 MiB OK Model: Marvell Armada 3720 Community Board ESPRESSOBin Net: eth0: neta@30000 [PRIME] Hit any key to stop autoboot: 0 Marvell>> mmcinfo Card did not respond to voltage select! Marvell>> mmc dev 1 switch to partitions #0, OK mmc1(part 0) is current device Marvell>> mmcinfo Device: sdhci@d8000 Manufacturer ID: 45 OEM: 100 Name: SEM08 Bus Speed: 52000000 Mode : MMC High Speed (52MHz) Rd Block Len: 512 MMC version 4.5 High Capacity: Yes Capacity: 7.3 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 16 MiB User Capacity: 7.3 GiB WRREL Boot Capacity: 2 MiB RPMB Capacity: 2 MiB Marvell>>
  5. You cannot download it :-) This is my private build and I even do not remember saving it somewhere after burning to the board eMMC. This is not even "boot from SPI" case. I sent the DTS content required for enabling eMMC in u-boot to ebin-dev. If he decide, you may have such build in the official Armbian set. As an option, you may build the flash image by yourself enabling second SDHCI controller in DTS.
  6. Your u-boot DTB file does not have second controller enabled. Once both controllers are enabled in this DTB file, you will see them during uboot init phase TIM-1.0 WTMI-devel-18.12.0-a0a1cb8 WTMI: system early-init SVC REV: 4, CPU VDD voltage: 1.108V NOTICE: Booting Trusted Firmware NOTICE: BL1: v2.0(release):v2.0-313-gea14b3d53 (Marvell-devel-18.12.0) NOTICE: BL1: Built : 18:37:55, Nov 29 2018 NOTICE: BL1: Booting BL2 NOTICE: BL2: v2.0(release):v2.0-313-gea14b3d53 (Marvell-devel-18.12.0) NOTICE: BL2: Built : 18:37:56, Nov 29 2018 NOTICE: BL1: Booting BL31 NOTICE: BL31: v2.0(release):v2.0-313-gea14b3d53 (Marvell-devel-18.12.0) NOTICE: BL31: Built : 18:3 U-Boot 2018.03-devel-18.12.2-00315-g1d4ab62367 (Nov 29 2018 - 18:34:51 +0200) Model: Marvell Armada 3720 Community Board ESPRESSOBin (eMMC) CPU @ 1000 [MHz] L2 @ 800 [MHz] TClock @ 200 [MHz] DDR @ 800 [MHz] DRAM: 1 GiB Comphy chip #0: Comphy-0: USB3 5 Gbps Comphy-1: PEX0 2.5 Gbps Comphy-2: SATA0 6 Gbps SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: ncq led only pmp fbss pio slum part sxs PCIE-0: Link down MMC: sdhci@d0000: 0, sdhci@d8000: 1 Loading Environment from MMC... OK Model: Marvell Armada 3720 Community Board ESPRESSOBin (eMMC) Net: eth0: neta@30000 [PRIME] Hit any key to stop autoboot: 0 Marvell>>
  7. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commits/u-boot-2018.03-armada-18.12 https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell/commits/A3700_utils-armada-18.12 https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/commits/mv_ddr-armada-18.12 https://github.com/MarvellEmbeddedProcessors/atf-marvell/commits/atf-v1.5-armada-18.12 https://github.com/MarvellEmbeddedProcessors/uefi-marvell/commits/uefi-2.7-armada-18.12 https://github.com/MarvellEmbeddedProcessors/linux-marvell/commits/linux-4.14.76-armada-18.12 This release is based on ATF v1.5, but is also compatible with mainline ATF v2.0 sources. The the flash image could be build with both mainline and LSP ATF sources
  8. I would never TRY to use trusted boot on a single board without BGA socket. You may end up with SoC that does not boot and needs replacement. Have you burned your trusted image after burning efuses but before you reset the board? It is true, that on Marvell A8K platform you can test most of efuse operations without entering the trust boot mode. The only trigger is the single efuse "security enable". This is not a case with A3700. I think A3700 BootROM assumes that the SoC is in trusted boot mode even this DEV_DEPLOY fuse is not burned, but the KAK/CSK values already programmed. In any case you have to exactly follow the instructions for the trusted boot enablement. Trusted boot is always tricky and people who test it for the first time, trash few SoCs before they get it working as expected.
  9. There are some nice upgrades in this v7 board design, like the new SATA connector. However the FW image is based on old Marvell 17.10 LSP. Since the new DDR4 layout is only included in Globalscale in-house FW images, the official Marvell LSP has no support for the new DDDR4 layouts yet. Marvell asked Globalscale team to upgrade their base to 18.09. If it happens, it will be much easier to add these new layouts to the official LSP and to the mainline sources. FYI - the A3700 support pull request is under review @ TF-A right now. Once it gets merged, you will be able to try the new TF-A v2.0. Unfortunately this PR code supports only DDR3-based EspressoBin for now.
  10. Just remember that Marvell release 18.09 contains both u-boot 2017.03 and 2018.03. It turns out that A3700 support in the new 2018 u-boot is not yet mature. So I would recommend to take all the component of 18.09 release (ATF, DDR code, A3700 utilities) and build the image with u-boot 2017.03-18.09 (the last one after applying Macronix patch on top). So you will benefit from all extensions and fixes in the boot loader code up to current date.
  11. U-boot-2017 18.09 is still good. I tried it and it seems to boot normally: IM-1.0 WTMI-devel-18.07.0-6050fd5 WTMI: system early-init CPU VDD voltage default value: 1.108V NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.5(release):v1.5-221-g9e22043 (Marvell-devel-18.09.0) NOTICE: BL1: Built : 16:51:14, Sep 5 2018 NOTICE: BL1: Booting BL2 NOTICE: BL2: v1.5(release):v1.5-221-g9e22043 (Marvell-devel-18.09.0) NOTICE: BL2: Built : 16:51:15, Sep 5 2018 WARNING: Failed to obtain reference to image id=4 (-2) WARNING: Failed to load BL32 (-2) NOTICE: BL1: Booting BL31 NOTICE: BL31: v1.5(release):v1.5-221-g9e22043 (Marvell-devel-18.09.0) NOTICE: BL31: Built : 16:51:18 U-Boot 2017.03-devel-18.09.0-00814-g09e03ea-dirty (Sep 05 2018 - 16:45:31 +0300) Model: Marvell Armada 3720 Community Board ESPRESSOBin CPU 800 [MHz] L2 800 [MHz] NB AXI 200 [MHz] SB AXI 250 [MHz] DDR 800 [MHz] DRAM: 1 GiB U-Boot DT blob at : 000000003f7142d8 Comphy chip #0: Comphy-0: USB3 5 Gbps Comphy-1: PEX0 2.5 Gbps Comphy-2: SATA0 6 Gbps SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: ncq led only pmp fbss pio slum part sxs PCIE-0: Link down MMC: sdhci@d0000: 0 SF: Detected w25q32dw with page size 256 Bytes, erase size 4 KiB, total 4 MiB Net: eth0: neta@30000 [PRIME] Hit any key to stop autoboot: 0 Marvell>> Marvell>> version U-Boot 2017.03-devel-18.09.0-00814-g09e03ea-dirty (Sep 05 2018 - 16:45:31 +0300) aarch64-linux-gnu-gcc (Linaro GCC 7.3-2018.05) 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] GNU ld (Linaro_Binutils-2018.05) 2.28.2.20170706 0001-drivers-spi-Add-support-for-Macronix-mx25u3235f-devi.patch
  12. Do not copy your boot image to offset 0 of SATA device. The BootROM will look for the boot image on LBA1 and then on LBA34. This is done for keeping the MBR and/or GPT intact, so besides booting from disk you can use it as a root FS.