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  1. From your description it seems that the function dma_set_mask_and_coherent() which used to work for kernel version 4.13.3 and no longer for newer kernel versions? That's a shame, Have you checked the release notes of newer kernel versions with sunxi modifications or maybe some of the experts on this forum can react?
  2. When i read the PA_EINT_DEB_REG using devmem2 i get the following: sudo devmem2 0x01c20a18 /dev/mem opened. Memory mapped at address 0xb6fa5000. Value at address 0x1C20A18 (0xb6fa5a18): 0x51 Does this mean that the te debounce register is set to the correct oscilator 24MHZ but somthing else has written to the DEB_CLK_PRE_SCALE?
  3. I have tried the to place input-debounce = <1 0>; In multiple places in the device tree, as i do not understand exactly were to place it. I just can not get it to work like this what am i doing wrong? /dts-v1/; / { ... counters { compatible = "allwinner,sun8i-h3-pinctrl", "gpio-pulse-counter"; pi_irq_counter@0 { label = "sst_PA19_pulse_counter"; pinctrl-names = "default"; pinctrl-0 = <&ext_counter_PA19>; /* CON3, pin 12: PH2
  4. Gentlemen Thank you very much. Both solutions work in a similar way by getting the base address from /dev/mem. By writing 1 to the PA_EINT_DEB_REG which sets HSOSC24MHz on for the debounce filter i managed to get PA19 interrupts working. # Read PA_EINT_CTL_REG sudo devmem2 0x01c20a10 /dev/mem opened. Memory mapped at address 0xb6f87000. Value at address 0x1C20A10 (0xb6f87a10): 0x80000 #which indicates that PA19 is set to external interrupts (OK) # Enable HSOSC by writing a 1 to PA_EINT_DEB_REG sudo devmem2 0x01c20a18 w 1 /dev/mem opened. Memory mapped at address 0xb6f38000. Val
  5. Thanks for the help i will give it a try and report back
  6. Thanks for the link. But when i try to do low level programming of the registers on mainline kernel, using the code presented in my first post, I get a segmentation fault. Do you know how to obtain the base address of the registers on mainline kernel? For legacy kernel 3.4 it is IO_ADDRESS(x) ((x) + 0xf0000000).
  7. Yes the interrupts are short if the processor is polling, but this is quite normal for hardware trigger circuits. I looked up the datasheets and it seems that there are 2 frequency modes for input debounce but i have no idea how to set them. I have tried input-debounce = <1>; in the device tree but it makes no difference. Further i see no reference to a higher precision clock. It seems that the H3 is not suitable for this kind of design???
  8. Here is a follow up on the latest changes: cat /proc/interrupts shows 0 at pi_irq_counter, irq 64 CPU0 CPU1 CPU2 CPU3 ... 64: 0 0 0 0 sunxi_pio_edge 19 Edge pi_irq_counter ... sudo cat /sys/kernel/debug/gpio shows: gpiochip0: GPIOs 0-223, parent: platform/1c20800.pinctrl, 1c20800.pinctrl: gpio-3 ( |sst:red:led ) out lo gpio-9 ( |reset ) out hi gpio-17 ( |orangepi:red:status ) out lo gpio-19
  9. Ok i will give it a try an report back. Thanks for the tip.
  10. Recently i have been experimenting with interrupts on orange pi zero plus2-H3 trying to capture data-ready pulses from an external adc on gpio PA19. The aim is to synchronize spi-read-data transactions with the incoming adc data-ready signal. First I tried to get it to work on legacy kernel 3.4 by adding the following section in to /boot/script.fex and compile the .fex file to .bin file using fex2bin: [gpio_para] gpio_used = 1 gpio_num = 6 .... gpio_pin_6 = port:PA19<0><default><default><1> This configured the pin properly as i had tested on other pins with