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dotbg

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  1. @hexdump There are mem=2048 limitation in kernel cmdline. I remove it and now have a box working with 3GB of RAM. Pretty good for now. Is there any way to to boot directly from USB in case of NAND flash on board?
  2. I know about 3GB limitation. Tnx, And also, I didn't notice kernel cmdline mem limit!
  3. Hello, Can someone to explain me this one U-Boot SPL 2021.10-armbian (Dec 02 2021 - 17:00:41 +0300) DRAM: 4096 MiB Trying to boot from MMC1 .....cut.... U-Boot 2021.10-armbian (Dec 02 2021 - 17:00:41 +0300) Allwinner Technology CPU: Allwinner H6 (SUN50I) Model: Tanix TX6 DRAM: 3 GiB MMC: mmc@4020000: 0, mmc@4022000: 1 .....cut..... Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 5.10.82-station (root@vbox) (aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0, GNU ld (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 2.32.0.20190321) #trunk SMP PREEMPT Wed Dec 1 09:44:49 MSK 2021 [ 0.000000] Machine model: Tanix TX6 [ 0.000000] Memory limited to 2048MB Why memory is limited to 2048MB? DTB file is sun50i-h6-tanix-tx6 And one more thing. nand-sata-install do not change boot=UUID in /boot/extlinux/extlinux.conf. Any ideas why?
  4. Nope! There are some kind of boxes claiming 8GB of RAM for example!
  5. Is there any limits to the maximum usable size of RAM?
  6. It's possible to install u-boot only ( rkdeveloptool method ) and boot from External USB drive?
  7. Any chance to boot from USB on eMCP board?
  8. Hello, Can some one to explain me, how exactly armbian set face RTC clock on interface up? I need to synchronize clock on tx3 mini with local NTP server, but no success at this moment. There are no chrony or ntp running... tx3mini@aml:~$ cat /etc/network/if-up.d/chrony #!/bin/sh set -e [ -x /usr/sbin/chronyd ] || exit 0 if [ -e /run/chronyd.pid ] && ip r list dev $IFACE 2> /dev/null | grep -q '^default'; then chronyc online > /dev/null 2>&1 fi exit 0 tx3mini@aml:~$ ls /usr/sbin/ch chgpasswd chmem chpasswd chroot tx3mini@aml:~$ ls /etc/chrony/chrony. chrony.conf chrony.keys
  9. Because fail of one device drops down the whole bus. p.s. 10x for answer. Anyway, I manage to bring up 3 pins. Kernel driver fully support more than one bus.
  10. Board OPi Zero 512, NEXT kernel 4.13.7, last Sunday compiled. I'm trying do start more than one Dallas 1 wire interface. My primary idea was to add second w1-gpio overlay but no success. The next one is to edit device tree for w1-gpio to add another pin, and then to edit fixup script. And need some help to understand this ( copied from sun8i-h3-w1-gpio.dts ) fragment@0 { target = <&pio>; __overlay__ { w1_pins: w1_pins { pins = "PD14"; function = "gpio_in"; }; }; }; fragment@1 { target-path = "/"; __overlay__ { onewire@0 { compatible = "w1-gpio"; pinctrl-names = "default"; pinctrl-0 = <&w1_pins>; gpios = <&pio 3 14 0>; /* PD14 */ status = "okay"; }; }; }; What exactly w1_pins: w1_pins mean? w1_pins{} is some kind of definition? Any driver limitations for pins count? btw: I be grateful for any other ideas how to enable second 1 Wire pin.
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