vobo70

Members
  • Content Count

    8
  • Joined

  • Last visited

About vobo70

  • Rank
    Newbie

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Thank you. But my Sata SSD drives connected through sata data and power cable; It's not USB drive. Should I power whole Banana Pi Pro from USB powered HUB? (I think hub gives me less power than genuine 2,4A charger ...)
  2. Banana Pi Pro are both same: powered by microUSB cable and dual 2,4A charger (aukey), both SATA cables are genuine (sinovoip - manufacturer of Banana Pi R2) and both SSD's are quite low power. Both SSD's works on same setup (except power supply) on Banana Pi R2. Here are results of armbianmonitor -u for both SBC's: http://ix.io/2eI7 http://ix.io/2eI8
  3. Hello, I have two Banana Pi Pro boards with current Armbian 20.02.1_Bananapipro_buster_current_5.4.20_minimal, kernel 5.4.20-sunxi and both have small SSD connected (WD 120GB and Goodram 120GB). fdisk -l doesn't show any drive's except sdcard (and ram drives). Is there any way I can get it working?
  4. last build: Armbian_20.02.2_Bananapir2_******_legacy_4.19.105_minimal works perfectly (both debian and ubuntu based)
  5. checked all builds: up to 5.75 works perfectly; after no one boot; all stuck on same message; any help will appreciated.
  6. Hello, I try to run this image: Armbian_20.02.0-rc0_Bananapir2_buster_legacy_4.19.97_minimal.img on Sinovoip Banana PI R2 (from SD card) and on 1-st boot i'm stuck: Tx DQM dly bit4 = 0x0 DRAMC_DQODLY1=79A98889h DRAMC_DQODLY2=8988B99Ah DRAMC_DQODLY3=2203123h DRAMC_DQODLY4=31103014h Tx DQ dly bit4 = 0x0 Tx DQS dly = 0x8949 Tx DQS dly bit4 = 0x0 TX Byte0: DQ - 16, DQS - 17. win_sum= 32 TX Byte1: DQ - 21, DQS - 13. win_sum= 33 TX Byte2: DQ - 8, DQS - 22. win_sum= 29 TX Byte3: DQ - 8, DQS - 22. win_sum= 29 DRAMC calibration takes 651397386 CPU cycles [EMI] DRAMC calibration passed [MEM] complex R/W mem test pass 0:dram_rank_size:80000000 [Dram_Buffer] dram size:-2147483648 [Dram_Buffer] structure size: 1725560 [Dram_Buffer] MAX_TEE_DRAM_SIZE: 0 Boot from SD Card!! [PLFM] Init Boot Device: OK(0) [PART] blksz: 512B [PART] [0x0000000000000000-0x000000000003FFFF] "PRELOADER" (512 blocks) [PART] [0x0000000000000000-0x000000000003FFFF] " B[TOOL] <UART> listen ended, receive size:3! [TOOL] <UART> wait sync time 150ms->5ms [TOOL] <UART> receieved data: () Device APC domain init setup: bootloader load uboot ,the address of uboot is 81E00000 [PART]partition name UBOOT [PART]partition start block 0x200 [PART]partition size 0x80000 [PART]partition blks 0x400 [PART]partition flags 0x0 [PART]partition name 0x8 [bean] part->startblk(0x200) bdev->blksz(0x200) part->part_id(8) hdr(0xFFB50000) [BlkDev.c 101 ]partition block size 0x200 ,blks:0xECE000 [BlkDev.c 101 ]partition block erase size 0x200 [PART] load "UBOOT" from 0x0000000000050000 (dev) to 0x81E00000 (mem) [SUCCESS] [PART] load speed: 5978KB/s, 300000 bytes, 49ms [BT_SD_PG] device info 0x8590 0x8A00 0xCB01 0x102 0:dram_rank_size:80000000 [PLFM] md_type[0] = 255 [PLFM] md_type[1] = 255 [PLFM] boot reason: 0 [PLFM] boot mode: 0 [PLFM] META COM0: 0 [PLFM] <0xFFB7CC10>: 0x0 [PLFM] boot time: 1906ms [PLFM] DDR reserve mode: enable = 0, success = 0 [BLDR] jump to 0x81E00000 [BLDR] <0x81E00000>=0xEA0000B8 [BLDR] <0x81E00004>=0xE59FF014 [USBD] USB PRB0 LineState: 0 [USBD] USB cable/ No Cable inserted! [PLFM] Keep stay in USB Mode Platform initialization is ok wait for frequency meter finish, CLK26CALI = 0x81 mt_pll_post_init: mt_get_cpu_freq = 1040000Khz wait for frequency meter finish, CLK26CALI = 0x90 mt_pll_post_init: mt_get_bus_freq = 273000Khz wait for frequency meter finish, CLK26CALI = 0x81 mt_pll_post_init: mt_get_mem_freq = 133250Khz [PWRAP] pwrap_init_preloader [PWRAP] pwrap_init [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=0,rdata=2D52 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=1,rdata=2D52 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=2,rdata=2D52 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=3,rdata=800 [PWRAP] _pwrap_init_sistrobe [Read Test] pass,index=4 rdata=5AA5 [PWRAP] _pwrap_init_sistrobe [Read Test] pass,index=5 rdata=5AA5 [PWRAP] _pwrap_init_sistrobe [Read Test] pass,index=6 rdata=5AA5 [PWRAP] _pwrap_init_sistrobe [Read Test] pass,index=7 rdata=5AA5 [PWRAP] _pwrap_init_sistrobe [Read Test] pass,index=8 rdata=5AA5 [PWRAP] _pwrap_init_sistrobe [Read Test] pass,index=9 rdata=5AA5 [PWRAP] _pwrap_init_sistrobe [Read Test] pass,index=10 rdata=5AA5 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=11,rdata=1001 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=12,rdata=B54B [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=13,rdata=B54B [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=14,rdata=B54B [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=15,rdata=B54B [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=16,rdata=B54B [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=17,rdata=B54B [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=18,rdata=B54B [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=19,rdata=2003 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=20,rdata=6A97 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=21,rdata=6A97 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=22,rdata=6A97 [PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=23,rdata=6A97 [PWRAP] _pwrap_init_reg_clock [PMIC_WRAP]wrap_init pass,the return value=0. [pmic6323_init] Preloader Start.................. [pmic6323_init] PMIC CHIP Code = 0x2023 INT_MISC_CON: 1 TOP_RST_MISC: 1 pl pmic powerkey Release [pmic6323_init] powerKey = 0 [pmic6323_init] is USB in = 0xB004 [pmic6323_init] Reg[0x11A]=0x1B pmic setup LED [pmic6323_init] Done................... mt7623 disable long press reset ->>>>> mt7623 disable long press reset <<<<<- mt7623 VPA supplied by 1.0V to MT7530 -> mt7623 VPA supplied by 1.0V to MT7530 <- mt7623 enables RG_VGP1_EN for LCM -> mt7623 enables RG_VGP1_EN for LCM <- MT7623 E2 setting => MT7623 E2 setting <= [PLFM] Init I2C: OK(0) [PLFM] Init PWRAP: OK(0) [PLFM] Init PMIC: OK(0) [PLFM] chip[CA00] [BLDR] [Support SD/eMMC] Build Time: 20170114-170026 ==== Dump RGU Reg ======== RGU MODE: 4D RGU LENGTH: FFE0 RGU STA: 0 RGU INTERVAL: FFF RGU SWSYSRST: 0 ==== Dump RGU Reg End ==== RGU: g_rgu_satus:0 mtk_wdt_mode_config mode value=10, tmp:22000010 PL P ON WDT does not trigger reboot RGU mtk_wdt_init:MTK_WDT_DEBUG_CTL(590200F3) kpd read addr: 0x0040: data:0x4001 Enter mtk_kpd_gpio_set! kpd debug column : 0, 0, 0, 0, 0, 0, 0, 0 kpd debug row : 0, 0, 0, 0, 0, 0, 0, 0 after set KP enable: KP_SEL = 0x0 ! MTK_PMIC_RST_KEY is used for this project! [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=3967 [RTC] get_frequency_meter: input=0x0, ouput=5 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] get_frequency_meter: input=0x0, ouput=0 [RTC] bbpu = 0xD, con = 0x426 [RTC] powerkey1 = 0xA357, powerkey2 = 0x67D2 Writeif_unlock [RTC] RTC_SPAR0=0x40 rtc_2sec_reboot_check cali=1792 rtc_2sec_stat_clear [RTC] irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0x40, spar1 = 0x800 [RTC] new_spare0 = 0x0, new_spare1 = 0x1, new_spare2 = 0x1, new_spare3 = 0x1 [RTC] bbpu = 0xD, con = 0x426, cali = 0x700 pl pmic powerkey Release [PLFM] Power key boot! [RTC] rtc_bbpu_power_on done [EMI] mcp_dram_num:0,discrete_dram_num:1,enable_combo_dis:0 [EMI] PCDDR3 [Check]mt_get_mdl_number 0x0 [EMI] eMMC/NAND ID = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 [EMI] MDL number = 0 [EMI] emi_set eMMC/NAND ID = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 [EMI][Vcore]0x21E=0x48,0x220=0x48 [EMI][Vmem]0x554=0x0 wait for frequency meter finish, CLK26CALI = 0x81 [EMI] PCDDR3 DRAM Clock = 1600012 KHz, MEMPLL MODE = 2 [EMI] PCDDR3 RXTDN Calibration: Start REXTDN SW calibration... drvp=0xB,drvn=0x9 [EMI] pinmux = 4 =============================================================================== dramc_write_leveling_swcal =============================================================================== delay byte0 byte1 byte2 byte3 ----------------------------- 0 0 0 0 1 1 0 0 0 1 2 0 0 1 1 3 0 0 1 1 4 0 1 1 1 5 0 1 1 1 6 0 1 1 1 7 0 1 1 1 8 0 1 1 1 9 1 1 1 1 10 1 1 1 1 11 1 1 1 1 12 1 1 1 1 13 1 1 1 1 14 1 1 1 1 15 1 1 1 1 pass bytecount = 4 byte_i status best delay 0 2 9 1 2 4 2 2 2 3 2 0 ======================================== [write leveling]DQS: 0x249, DQM: 0x249 [write leveling after remap]DQ byte0 reg: 0x200 val: 0x99994444 [write leveling after remap]DQ byte1 reg: 0x204 val: 0x44449999 [write leveling after remap]DQ byte2 reg: 0x208 val: 0x22220000 [write leveling after remap]DQ byte3 reg: 0x20C val: 0x2222 ============================================= X-axis: DQS Gating Window Delay (Fine Scale) Y-axis: DQS Gating Window Delay (Coarse Scale) ============================================= 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 -------------------------------------------------------------------------------- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0011:| 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0012:| 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0013:| 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0014:| 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rank 0 coarse tune value selection : 18, 18 18 64 rank 0 coarse = 18 rank 0 fine = 64 00:| 0 0 0 0 0 0 0 0 1 1 1 0 opt_dle value:13 ================================================================== RX DQS perbit delay software calibration ================================================================== 1.0-31 bit dq delay value ================================================================== bit| 0 1 2 3 4 5 6 7 8 9 -------------------------------------- 0 | 0 0 0 0 0 0 0 0 0 0 10 | 0 0 0 0 0 0 0 0 0 0 20 | 0 0 0 0 0 0 0 0 0 0 30 | 0 0 -------------------------------------- ================================================================== 2.dqs window x=pass dqs delay value (min~max)center y=0-7bit DQ of every group input delay:DQS0 =50 DQS1 = 40 DQS2 =53 DQS3 = 44 ================================================================== bit DQS0 bit DQS1 bit DQS2 bit DQS3 0 (19~69)44 8 (5~58)31 16 (23~69)46 24 (15~58)36 1 (19~70)44 9 (7~60)33 17 (22~70)46 25 (15~60)37 2 (21~70)45 10 (9~62)35 18 (25~70)47 26 (17~63)40 3 (18~68)43 11 (11~61)36 19 (21~68)44 27 (17~63)40 4 (21~77)49 12 (17~62)39 20 (27~79)53 28 (21~68)44 5 (21~68)44 13 (15~61)38 21 (25~71)48 29 (18~61)39 6 (21~69)45 14 (13~60)36 22 (25~72)48 30 (16~62)39 7 (25~76)50 15 (16~64)40 23 (31~74)52 31 (18~64)41 ================================================================== 3.dq delay value last ================================================================== bit| 0 1 2 3 4 5 6 7 8 9 -------------------------------------- 0 | 6 6 5 7 1 6 5 0 9 7 10 | 5 4 1 2 4 0 7 7 6 9 20 | 0 5 5 1 8 7 4 4 0 5 30 | 5 3 ================================================================== *DQIDLY1 = 0x7050606 *DQIDLY2 = 0x50601 *DQIDLY3 = 0x4050709 *DQIDLY4 = 0x40201 *DQIDLY5 = 0x9060707 *DQIDLY6 = 0x1050500 *DQIDLY7 = 0x4040708 *DQIDLY8 = 0x3050500 *DRAMC_R0DELDLY = 0x2C352832 [MEM]CONA:F3A2,conf1:F07486A3 DM4BitMux = 1 DQSO 0 in TX per-bit = 2 <= DQSO 0 in WL = 9 DQSO 1 in TX per-bit = 0 <= DQSO 1 in WL = 4 [Warning] DQSO 2 in TX per-bit = 9 > DQSO 2 in WL = 2 [Warning] DQSO 3 in TX per-bit = 8 > DQSO 3 in WL = 0 Tx DQM dly = 0x1189 Tx DQM dly bit4 = 0x0 DRAMC_DQODLY1=79A98989h DRAMC_DQODLY2=8988B99Bh DRAMC_DQODLY3=2103123h DRAMC_DQODLY4=31103014h Tx DQ dly bit4 = 0x0 Tx DQS dly = 0x8949 Tx DQS dly bit4 = 0x0 TX Byte0: DQ - 16, DQS - 17. win_sum= 32 TX Byte1: DQ - 21, DQS - 13. win_sum= 33 TX Byte2: DQ - 8, DQS - 22. win_sum= 29 TX Byte3: DQ - 8, DQS - 22. win_sum= 29 DRAMC calibration takes 651397844 CPU cycles [EMI] DRAMC calibration passed [MEM] complex R/W mem test pass 0:dram_rank_size:80000000 [Dram_Buffer] dram size:-2147483648 [Dram_Buffer] structure size: 1725560 [Dram_Buffer] MAX_TEE_DRAM_SIZE: 0 Boot from SD Card!! [PLFM] Init Boot Device: OK(0) [PART] blksz: 512B [PART] [0x0000000000000000-0x000000000003FFFF] "PRELOADER" (512 blocks) [PART] [0x0000000000000000-0x000000000003FFFF] "MBR" (512 blocks) [PART] [0x0000000000040000-0x00000000000BFFFF] "UBOOT" (1024 blocks) [PART] [0x00000000000C0000-0x00000000000FFFFF] "CONFIG" (512 blocks) [PART] [0x0000000000100000-0x000000000013FFFF] "FACTORY" (512 blocks) [PART] [0x0000000000140000-0x000000000213FFFF] "BOOTIMG" (65536 blocks) [PART] [0x0000000002140000-0x000000000413FFFF] "RECOVERY" (65536 blocks) [PART] [0x0000000004140000-0x000000004413FFFF] "ROOTFS" (2097152 blocks) [PART] [0x0000000044140000-0x000001FFC413FFFF] "USER" (-4194304 blocks) [platform_vusb_on] PASS [TOOL] PMIC not dectect usb cable! [TOOL] <UART> listen ended, receive size:0! [TOOL] <UART> wait sync time 150ms->5ms [TOOL] <UART> receieved data: () Device APC domain init setup: bootloader load uboot ,the address of uboot is 81E00000 [PART]partition name UBOOT [PART]partition start block 0x200 [PART]partition size 0x80000 [PART]partition blks 0x400 [PART]partition flags 0x0 [PART]partition name 0x8 [bean] part->startblk(0x200) bdev->blksz(0x200) part->part_id(8) hdr(0xFFB50000) [BlkDev.c 101 ]partition block size 0x200 ,blks:0xECE000 [BlkDev.c 101 ]partition block erase size 0x200 [PART] load "UBOOT" from 0x0000000000050000 (dev) to 0x81E00000 (mem) [SUCCESS] [PART] load speed: 5978KB/s, 300000 bytes, 49ms [BT_SD_PG] device info 0x8590 0x8A00 0xCB01 0x102 0:dram_rank_size:80000000 [PLFM] md_type[0] = 255 [PLFM] md_type[1] = 255 [PLFM] boot reason: 0 [PLFM] boot mode: 0 [PLFM] META COM0: 0 [PLFM] <0xFFB7CC10>: 0x0 [PLFM] boot time: 1901ms [PLFM] DDR reserve mode: enable = 0, success = 0 [BLDR] jump to 0x81E00000 [BLDR] <0x81E00000>=0xEA0000B8 [BLDR] <0x81E00004>=0xE59FF014
  7. Hello, I have Banana Pi R2 with armbian bionic. Have two wlan cards both USB, both works. But earlier when I used openwrt on x86 my both wlan and lan were bridged and had one IP - which was router IP. Here with armbian wlan hotspot get other IP than armbian itself. Is there any way to change it to bridge? Or best practices is to leave it as is? regards, Maciek