Splitice

These are the 2 patches we ended up with. With thanks to everyone at on the linux-sunxi irc, particularly megi.
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 6b636362379e..ca55c2ae999d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -23,15 +23,21 @@ #include "ccu-sun8i-h3.h" -static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux", -                "osc24M", 0x000, -                8, 5,  /* N */ -                4, 2,  /* K */ -                0, 2,  /* M */ -                16, 2, /* P */ -                BIT(31),   /* gate */ -                BIT(28),   /* lock */ -                CLK_SET_RATE_UNGATE); +static struct ccu_nkmp pll_cpux_clk = { +   .enable     = BIT(31), +   .lock       = BIT(28), +   .n      = _SUNXI_CCU_MULT(8, 5), +   .k      = _SUNXI_CCU_MULT(4, 2), +   .m      = _SUNXI_CCU_DIV_MAX(0, 2, 1), +   .p      = _SUNXI_CCU_DIV_MAX(16, 2, 1), +   .common     = { +       .reg        = 0x000, +       .hw.init    = CLK_HW_INIT("pll-cpux", +                    "osc24M", +                    &ccu_nkmp_ops, +                    CLK_SET_RATE_UNGATE), +   }, +}; /* * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from  
 
 
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 5e7e9cccc172..609e889cae3c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -1129,20 +1129,6 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {    .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets), }; -static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = { -   .common = &pll_cpux_clk.common, -   /* copy from pll_cpux_clk */ -   .enable = BIT(31), -   .lock   = BIT(28), -}; - -static struct ccu_mux_nb sun8i_h3_cpu_nb = { -   .common     = &cpux_clk.common, -   .cm     = &cpux_clk.mux, -   .delay_us   = 1, /* > 8 clock cycles at 24 MHz */ -   .bypass_index   = 1, /* index of 24 MHz oscillator */ -}; - static void __init sunxi_h3_h5_ccu_init(struct device_node *node,                    const struct sunxi_ccu_desc *desc) { @@ -1161,13 +1147,6 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,    writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);    sunxi_ccu_probe(node, reg, desc); - -   /* Gate then ungate PLL CPU after any rate changes */ -   ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb); - -   /* Reparent CPU during PLL CPU rate changes */ -   ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, -                &sun8i_h3_cpu_nb); } static void __init sun8i_h3_ccu_setup(struct device_node *node)  
You may also need to decrease the DDR frequency by 24Mhz in uboot on some boards. No binning on H3 chips, some are inferior.
 
This is not mainlined. Nor am I aware of any effort being put into pushing them upstream.
 
No rights reserved by me. As always apply at your own risk, neither me or my employers provide you with any guarantees.

It's about this issue for sure. I'm yet confirm fix one way or the other yet though. Working on it.