Juanjo

Members
  • Content Count

    10
  • Joined

  • Last visited

About Juanjo

  • Rank
    Member

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Ok. So where is the 5.2 branch your're using so I do the PR against that ?
  2. Oleg Why does the DTBs on your 5.2rc images are different than those produces by your master branch on https://github.com/150balbes/Amlogic_s905-kernel ? I was making the PR but my WiFi wasn't working with the DTB generated by the DTS code but worked by decompiled DTBs from your images, after making this changes on DTSI everything fine: juanjo@bionic:~/devel/Amlogic_s905-kernel$ git diff arch/arm64/boot/dts/amlogic/meson-g12a.dtsi diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index bd85b604c7..6565f5b709 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -200,12 +200,12 @@ apb_efuse: bus@30000 { compatible = "simple-bus"; - reg = <0x0 0x30000 0x0 0x1000>; + reg = <0x0 0x30000 0x0 0x2000>; #address-cells = <2>; #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x30000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; - hwrng: rng { + hwrng: rng@218 { compatible = "amlogic,meson-rng"; reg = <0x0 0x218 0x0 0x4>; }; @@ -2376,7 +2376,7 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; - amlogic,ddr-access-quirk; + amlogic,dram-access-quirk; }; Your DTBs do have "dram-access-quirk" but the DTS code on Github not. Upstream they are using "dram-access-quirk" but your master branch uses it on the DTSI but the source of the drivers does check for "ddr-access-quirk" which was older and buggier version Older: https://patchwork.kernel.org/cover/10940585/ Newer: https://patchwork.kernel.org/patch/10962981/ Or simply the 5.2 branch isn't master ??
  3. Seems to be the same case as mine GT1 Mini works and GT1 Mini-A didn't but did with SEI510 which in my case does have a different ETH PHY but I did manage to make a DTS. Now I need to find some time to do a PR for Balbes fork
  4. Ok. Got it working based on SEI510 Device Tree which booted then I changed some bits to enable GbE. By now have GbE and HDMI works; it seems WiFi too since a scan worked. I suppose I need to do a PR on your GitHub repo ?
  5. To start I did pull out the DTB from Android on the GT1 Mini and the GT1 Mini-A converted to DTS and compared them (diff -u). They are identically They are for 4.9 Kernel so they are too many differences to X96 DTS. I attached it anyway gt1_mini.dts
  6. I though that most of the time with a wrong DTB (but same SoC) at least I'll get some Kernel logs and then a panic or some HW not working. How do I extract the DTB from Android firmware ? It seems that thing doesn't have partitions like plain Linux do. I do have Armbian building knowledge but no Android Then I just to build some DTB from this source ? https://github.com/150balbes/Amlogic_s905-kernel TIA
  7. Hi, I recently got two Beelink GT1 Mini 2GB/32GB boxes. One is GT1 Mini and the other is GT1 Mini-A (note the A). The plain GT1 Mini boots Armbian with the G12A x96 DTB fine and everything looks good. But the GT1 Mini-A doesn't and supposedly the only difference between them is the remote control and Android firmware. I attached serial console the A version and it gets stuck on starting Kernel, tested both 5.89 the one with 5.1 kernel and the new with 5.2rc4 kernel: G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:0;READ:0;0.0; bl2_stage_init1 L0:00000000 L1:00000703 L2:00008067 L3:04000000 S1:00000000 B2:00002000 B1:e0f83180 TE: 105333 BL2 Built : 20:07:05, Aug 28 2018. g12a g16e0318 - guotai.shen@droid11-sz Board ID = 1 Set cpu clk to 24M Set clk81 to 24M CPU clk: 1200 MHz Set clk81 to 166.6M smccc: 0001d8b4 boot_device: 1 -s DDR driver_vesion: LPDDR4_PHY_V_0_1_5 build time: Aug 28 2018 20:06:59 board id: 1 Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x004000, part: 0 fw parse done Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x00c000, part: 0 Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x004000, part: 0 PIEI prepare done Cfg max: 5, cur: 1. Board id: 255. Force loop cfg DDR4 probe Set ddr clk to 912MHz Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x00c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : STREAM 0x00490002 - 0x00000000 0x00000000 INFO : STREAM 0x04020000 - INFO : ERROR : Training has failed! 1D training failed Cfg max: 5, cur: 2. Board id: 255. Force loop cfg DDR3 probe Set ddr clk to 912MHz Load ddrfw from eMMC, src: 0x0002c200, des: 0xfffd0000, size: 0x00c000, part: 0 Check phy result INFO : End of initialization INFO : STREAM 0x00670000 - INFO : STREAM 0x04020000 - INFO : ERROR : Training has failed! 1D training failed Cfg max: 5, cur: 3. Board id: 255. Force loop cfg LPDDR4 probe Set ddr clk to 1200MHz Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x00c000, part: 0 5117Check phy result INFO : STREAM 0x00b00001 - 0x00001000 INFO : STREAM 0x00a70001 - 0x00000018 INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a INFO : STREAM 0x00560006 - 0x00000003 0x00000003 0x00001001 0x0000000a 0x00000000 0x00000960 INFO : STREAM 0x005b0005 - 0x00000000 0x00000044 0x000000a4 0x00000032 0x00000000 INFO : End of CA training INFO : End of initialization INFO : Training has run successfully! Check phy result INFO : STREAM 0x00b00001 - 0x00001000 INFO : STREAM 0x00a70001 - 0x00000018 INFO : STREAM 0x00540003 - 0x00000004 0x00000008 0x0000000a INFO : STREAM 0x00560006 - 0x00000003 0x00000003 0x0000031f 0x0000000a 0x00000000 0x00000960 INFO : STREAM 0x005b0005 - 0x00000000 0x00000044 0x000000a4 0x00000032 0x00000000 INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x00c000, part: 0 Check phy result INFO : STREAM 0x012c0000 - INFO : STREAM 0x01300001 - 0x00001000 INFO : STREAM 0x01270001 - 0x00000018 INFO : STREAM 0x00d40003 - 0x00000004 0x00000008 0x0000000a INFO : STREAM 0x00d60006 - 0x00000003 0x00000003 0x00000061 0x0000000a 0x00000000 0x00000960 INFO : STREAM 0x00db0005 - 0x00000000 0x00000044 0x00000024 0x00000032 0x00000000 INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! channel==0 RxClkDly_Margin_A0==130 ps 10 TxDqDly_Margin_A0==130 ps 10 RxClkDly_Margin_A1==143 ps 11 TxDqDly_Margin_A1==130 ps 10 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==74 VrefDac_Margin_A0==40 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==40 DeviceVref_Margin_A1==40 channel==1 RxClkDly_Margin_A0==91 ps 7 TxDqDly_Margin_A0==143 ps 11 RxClkDly_Margin_A1==117 ps 9 TxDqDly_Margin_A1==130 ps 10 TrainedVREFDQ_A0==74 TrainedVREFDQ_A1==74 VrefDac_Margin_A0==40 DeviceVref_Margin_A0==40 VrefDac_Margin_A1==40 DeviceVref_Margin_A1==40 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 2D training succeed auto size-- 65535DDR cs0 size: 1024MB DDR cs1 size: 1024MB DMC_DDR_CTRL: 00e0001bDDR size: 2048MB DataBus test pass! AddrBus test pass! 100bdlr_step_size ps== 496 result report Enable ddr reg access 00000000 emmc switch 3 ok Authentication key not yet programmed emmc_rpmb_key_is_programmed: error 0x00000007 00000000 emmc switch 0 ok Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x004000, part: 0 Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x0ec000, part: 0 bl2z: ptr: 05127320, size: 00001e50 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR [Image: g12a_v1.1.3327-3761055 2018-07-31 18:47:10 jenkins@walle02-sh] OPS=0x40 ring efuse init 28 0b 40 00 01 1e 12 00 00 08 34 35 4b 48 4b 50 [0.014272 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):40e3f59 NOTICE: BL31: Built : 16:26:05, Jul 18 2018 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass INFO: BL3-2: ATOS-V2.4-84-g55d24eb #1 Wed Apr 11 05:49:14 UTC 2018 arm INFO: BL3-2: Chip: G12A Rev: B (28:B - 40:2) INFO: BL3-2: crypto engine DMA INFO: BL3-2: secure time TEE INFO: BL3-2: CONFIG_DEVICE_SECURE 0xb200000e U-Boot 2015.01-gfe90999-dirty (Mar 30 2019 - 14:20:06) DRAM: 2 GiB Relocation Offset is: 76e80000 spi_post_bind(spifc): req_seq = 0 register usb cfg[0][1] = 0000000077f47458 NAND: get_sys_clk_rate_mtd() 266, clock setting 200! NAND device id: 0 ff ff ff ff ff No NAND device found!!! nand init failed: -6 get_sys_clk_rate_mtd() 266, clock setting 200! NAND device id: 0 ff ff ff ff ff No NAND device found!!! nand init failed: -6 MMC: aml_priv->desc_buf = 0x0000000073e70710 aml_priv->desc_buf = 0x0000000073e72a30 SDIO Port B: 0, SDIO Port C: 1 co-phase 0x3, tx-dly 0, clock 400000 co-phase 0x3, tx-dly 0, clock 400000 co-phase 0x3, tx-dly 0, clock 400000 emmc/sd response timeout, cmd8, status=0x1ff2800 emmc/sd response timeout, cmd55, status=0x1ff2800 co-phase 0x3, tx-dly 0, clock 400000 co-phase 0x3, tx-dly 0, clock 40000000 init_part() 297: PART_TYPE_AML [mmc_init] mmc init success Amlogic multi-dtb tool Multi dtb detected checkhw: hwid = 1 checkhw: DDR size: 0x80000000, loc_name: g12a_s905x2_2g Multi dtb tool version: v2 . Support 2 dtbs. aml_dt soc: g12a platform: s905x2 variant: 2g dtb 0 soc: g12a plat: s905x2 vari: 2g dtb 1 soc: g12a plat: s905x2 vari: 4g Find match dtb: 0 start dts,buffer=0000000073e75280,dt_addr=0000000073e75a80 get_partition_from_dts() 105: ret 0 Amlogic multi-dtb tool Multi dtb detected checkhw: hwid = 1 checkhw: DDR size: 0x80000000, loc_name: g12a_s905x2_2g Multi dtb tool version: v2 . Support 2 dtbs. aml_dt soc: g12a platform: s905x2 variant: 2g dtb 0 soc: g12a plat: s905x2 vari: 2g dtb 1 soc: g12a plat: s905x2 vari: 4g Find match dtb: 0 parts: 14 00: logo 0000000000800000 1 01: recovery 0000000001800000 1 02: misc 0000000000800000 1 03: dto 0000000000800000 1 04: cri_data 0000000000800000 2 05: param 0000000001000000 2 06: boot 0000000001000000 1 07: rsv 0000000001000000 1 08: tee 0000000002000000 1 09: vendor 0000000010000000 1 10: odm 0000000010000000 1 11: system 0000000074000000 1 12: cache 0000000046000000 2 13: data ffffffffffffffff 4 init_part() 297: PART_TYPE_AML eMMC/TSD partition table have been checked OK! check pattern success mmc env offset: 0x4d400000 In: serial Out: serial Err: serial reboot_mode=cold_boot [store]To run cmd[emmc dtb_read 0x1000000 0x40000] _verify_dtb_checksum()-2755: calc 49c3556f, store 49c3556f _verify_dtb_checksum()-2755: calc 49c3556f, store 49c3556f dtb_read()-2972: total valid 2 update_old_dtb()-2953: do nothing Amlogic multi-dtb tool Multi dtb detected checkhw: hwid = 1 checkhw: DDR size: 0x80000000, loc_name: g12a_s905x2_2g Multi dtb tool version: v2 . Support 2 dtbs. aml_dt soc: g12a platform: s905x2 variant: 2g dtb 0 soc: g12a plat: s905x2 vari: 2g dtb 1 soc: g12a plat: s905x2 vari: 4g Find match dtb: 0 amlkey_init() enter! [EFUSE_MSG]keynum is 4 vpu: clk_level in dts: 7 vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100) vpu: vpu_clk_gate_init_off finish vpp: vpp_init vpp: g12a/b osd1 matrix rgb2yuv .............. vpp: g12a/b osd2 matrix rgb2yuv.............. vpp: g12a/b osd3 matrix rgb2yuv.............. aml_config_dtb 608 aml_config_dtb 638 co_phase = <0x00000003> caps2 = "MMC_CAP2_HS200" f_max = "��" status = "disabled" status = "okay" Net: dwmac.ff3f0000amlkey_init() enter! amlkey_init() 71: already init! [EFUSE_MSG]keynum is 4 MACADDR:02:00:00:12:1e:01(from chipid) Start read misc partition datas! info->attemp_times = 0 info->active_slot = 0 info->slot_info[0].bootable = 1 info->slot_info[0].online = 1 info->slot_info[1].bootable = 0 info->slot_info[1].online = 0 info->attemp_times = 0 attemp_times = 0 active slot = 0 wipe_data=successful wipe_cache=successful upgrade_step=2 hpd_state=0 [OSD]load fb addr from dts:/meson-fb [OSD]set initrd_high: 0x7f800000 [OSD]fb_addr for logo: 0x7f800000 [OSD]load fb addr from dts:/meson-fb [OSD]fb_addr for logo: 0x7f800000 [OSD]VPP_OFIFO_SIZE:0xfff01fff [CANVAS]canvas init [CANVAS]addr=0x7f800000 width=5760, height=2160 [OSD]osd_hw.free_dst_data: 0,719,0,575 [OSD]osd1_update_disp_freescale_enable vpp: vpp_matrix_update: 2 cvbs performance type = 9, table = 0 cvbs_config_hdmipll_g12a cvbs_set_vid2_clk amlkey_init() enter! amlkey_init() 71: already init! [EFUSE_MSG]keynum is 4 [KM]Error:f[key_manage_query_size]L507:key[usid] not programed yet [KM]Error:f[key_manage_query_size]L507:key[mac] not programed yet [KM]Error:f[key_manage_query_size]L507:key[deviceid] not programed yet gpio: pin GPIOAO_3 (gpio 3) value is 1 InUsbBurn noSof sof timeout, reset usb phy tuning Hit Enter or space or Ctrl+C key to stop autoboot -- : 1 0 (Re)start USB... USB0: USB3.0 XHCI init start Register 3000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found ** Bad device usb 0 ** ** Bad device usb 1 ** ** Bad device usb 2 ** ** Bad device usb 3 ** card in co-phase 0x2, tx-dly 0, clock 400000 co-phase 0x2, tx-dly 0, clock 400000 co-phase 0x2, tx-dly 0, clock 400000 co-phase 0x2, tx-dly 0, clock 400000 co-phase 0x2, tx-dly 0, clock 40000000 init_part() 282: PART_TYPE_DOS [mmc_init] mmc init success Device: SDIO Port B Manufacturer ID: 3 OEM: 5344 Name: SC16G Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.8 GiB mmc clock: 40000000 Bus Width: 4-bit reading s905_autoscript 1765 bytes read in 5 ms (344.7 KiB/s) ## Executing script at 01020000 ** Bad device usb 0 ** ** Bad device usb 1 ** ** Bad device usb 2 ** ** Bad device usb 3 ** reading zImage 20537352 bytes read in 1132 ms (17.3 MiB/s) reading uInitrd 7869746 bytes read in 433 ms (17.3 MiB/s) reading uEnv.ini 207 bytes read in 4 ms (49.8 KiB/s) reading /dtb/meson-g12a-x96-max.dtb 41673 bytes read in 8 ms (5 MiB/s) libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND [rsvmem] fdt get prop fail. ## Loading init Ramdisk from Legacy Image at 13000000 ... Image Name: uInitrd Image Type: AArch64 Linux RAMDisk Image (gzip compressed) Data Size: 7869682 Bytes = 7.5 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK load dtb from 0x1000000 ...... Amlogic multi-dtb tool Single dtb detected ## Flattened Device Tree blob at 01000000 Booting using the fdt blob at 0x1000000 libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND [rsvmem] fdt get prop fail. Loading Ramdisk to 736ec000, end 73e6d4f2 ... OK Loading Device Tree to 000000001fff2000, end 000000001ffff2c8 ... OK Starting kernel ... uboot time: 6638950 us If you need any more info or can point me to the right direction I'm more than happy to help. TIA
  8. Ok, Patched 2013-10-rc4 to enable SPL_WATCHDOG and that workaround the stuck SPL every 1 of 5 boots. And patched 2018-03-armbian (dev branch) to actually set USDHC3 pins on HummingBoard2 an enable it to actually have eMMC boot support from SPL seems to work, many reboots and no stuck SPL so far. Later will PR it.
  9. I have lots of HummingBoards 2 Edge with eMMC but now got a batch with the new SOM 1.5 and eMMC the original u-boot from next and stable branch (2013-10rc4) get stuck on SPL from time to time on the new SOMs so I'm trying the dev branch which has this new patch: https://github.com/armbian/build/blob/master/patch/u-boot/u-boot-cubox-next/U-Boot-mx6cuboxi-add-support-for-detecting-Revision-1.5-SoMs.patch Copying SPL and u-boot.img to eMMC and booting produce the following: U-Boot SPL 2018.03-armbian (Jun 07 2018 - 16:06:14 -0400) Trying to boot from MMC1 Card did not respond to voltage select! spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### But if I have a SD card which has the old u-boot: U-Boot SPL 2018.03-armbian (Jun 07 2018 - 16:06:14 -0400) Trying to boot from MMC1 U-Boot 2013.10-rc4 (May 11 2018 - 13:06:31) CPU: Freescale i.MX6DL rev1.3 at 792 MHz Reset cause: POR Board: MX6-HummingBoard2 DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 HummingBoard2 U-Boot > And everything goes fine. So it seems that the SPL tries MMC1 which I suppose is SD card so when no card is inserted it get stuck. But when booting from eMMC it does read SPL from eMMC but the new SPL try to read uboot from SD, So how can I force MMC2_2 (I guess this is eMMC) inside the code or see if the new SPL honours the HummingBoards jumpers. TIA