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  1. so armbian uses the bootslpash.armbian file in /lib/firmware/ for the boot logo....how is this generated if we want to change it?
  2. After wasting way to much time on this finally figured it out...in case anyone NEEDs UART on Pin 8,10 (UART2B) this is how you do it Go to amrbian config and edit .dts file disable i2c3 port (shares same pins as UART2B) ...change status to "disabled" in i2c@ff130000 hijack uart2 address to point to UART2B pins instead of UART2C (the debug pins)....change phandle-0 in serial@ff1a0000 to 0x143 now this is all you technically need to do, but this is tied to ttyS2 which is also the serial console output which is configured i believe at the kernel level (if anyone know how to disable let me know), so we need to swap ttyS2 to another interface to voice this so i just changed serial@ff1a0000 to point to ttyS1 by doing below swap serial1 ->serial2 swap uart1 -> uart2 If anyone has an elegant way to do all of the above with a nice dts overlay lmk, have no idea how overlay syntax works. BTW also tried directly hijacking serial1 and serial 3 which are disabled (by changing phandle-0), but it only works in serial@ff1a0000...i guess all UART2 ports (UART2a,b,c) are tied to this address.
  3. So looking around this uart seems to be named uart2b, and is referenced in the current.dts overlay in the armbian-config editor. Figured I could try and edit the rockchip_uar4.dbto file, but guess it needs to be decompiled? EDIT Got it decompile but it does not help, since all that overlay does is disable the SPI port and enable the UART port So in the main overlay file this is what is referenced for uart2b: uart2b { uart2b-xfer { rockchip,pins = <0x04 0x10 0x02 0xb7 0x04 0x11 0x02 0xb4>; phandle = <0x143>; }; }; Would it work to simply copy these pin numbers and put it in the entry for uart4? Only thing im not understanding is each uart port is referenced to one of these "serial" addresses serial0 = "/serial@ff180000"; serial1 = "/serial@ff190000"; serial2 = "/serial@ff1a0000"; serial3 = "/serial@ff1b0000"; serial4 = "/serial@ff370000"; Would I need to create a new one, or can I hijack one of them and point the new pins to it?
  4. stock kernel works, issue is with orange pi 4 has badly designed FPC connector for PCIE lanes. They didn't group the diff pairs so transmission over FPC cable sucks. We had to make a flex ribbon board to correct this and route as diff pairs so Gen 2 2x works great. Might make some extra and release the board if there is enough interest.
  5. Looks like OPi4 has two active UART interfaces (ttyS2, S4). S2 is connected to the back 3 pins which are the debug ports, and S4 is uart on pins 19,21. Is there anyway to bring up another interface for UART on Pins 8, 10? Ive tried adding uart1,2,3 etc in armbianEnv file in /boot as well as console=display but non of this works.
  6. Trying to set frequencies and governor for both types of CPUs on this processor. armbian-config sets the max freq and governor correctly for the two big proccesors but no config for little. Tried cpufreq-set for little, but it does not respect governor. If its set to a freq is stays there indefinitely, and if conservative governor is set the max freq goes back to 1.5. How do we set max freq to 1.2 for little, and governor to conservative and have both stick like big does with armbian-config?
  7. They only expose one PCIE lane on that adapter, and it won't work with M.2 directly or run at Gen2. Might release our custom board, 2x lanes, Gen2 running stable ~1TB/s bandwidth.
  8. what environment does the latest raspberry pi OS use? It looks clean and modern, the stock desktop on armbiam looks a little dated
  9. Ok we just finished our 2x M.2 breakout board (uses both lanes exposed by the PCIE port on the orange pi 4). Is there a similar setting for link width? Its currently picking up a x4 Gen 3 M.2 drive with both link speed downgraded to gen 1 (as expected), and width downgraded to 1x. Should be 2x.
  10. What is the current pcie link speed set for stable Armbian 5.9.x release? I know stock kernels from orange pi have it set to Gen 1 speed. Need to test some Gen 2 hardware and see if it works.
  11. Was the PCIE port ever fixed on this? Has anyone tried a PCIE SSD on it?
  12. Looking for same thing...is there a FEX option to disable the GPU during boot?
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