A weird behavior of Sunvell Q+

[RezaXDI]

Hi everyone,

 

I've got a Q+ device which comes with a "RTL8821CS" wifi/bt module. This device is similar to Tanix TX6 with only a different wifi module. I was trying to make this module work in Armbian. The initial problem was this error :

 

[    4.233422] sunxi-mmc 4021000.mmc: no support for card's volts
[    4.233431] mmc1: error -22 whilst initialising SDIO card

 

So I started investigating and tested different variables inside device tree but nothing worked. Then I decided to compile the kernel again with dynamic debug enabled and then tried to find out what is causing the above error. After some tries, I enabled dyndbg on boot for specific files including drivers/mmc/core/core.c (specific lines) and drivers/mmc/core/regulator.c and rebooted to see what I get and then :

 

[    4.013035] sunxi-mmc 4021000.mmc: allocated mmc-pwrseq
[    4.027677] mmc2: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 21 width 1 timing 0
[    4.044341] sunxi-mmc 4021000.mmc: mmc_regulator_set_vqmmc: found vmmc voltage range of 3300000-3400000uV
[    4.055989] sunxi-mmc 4021000.mmc: Initial signal voltage of 1.8v
[    4.279137] mmc2: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0
[    4.307160] sunxi-mmc 4021000.mmc: initialized, max. request size: 16384 KB, uses new timings mode
[    4.308791] mmc2: clock 400000Hz busmode 2 powermode 2 cs 1 Vdd 21 width 1 timing 0
[    4.311695] mmc2: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0
[    4.314121] sunxi-mmc 4021000.mmc: card claims to support voltages below defined range
[    4.323695] mmc2: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 2
[    4.335731] mmc2: clock 50000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 2
[    4.428712] mmc2: clock 50000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 4 timing 2
[    4.429364] mmc2: new high speed SDIO card at address 0001

 

Now SDIO card gets detected ! If I remove dyndbg then it causes same error again. So I guess enabling dyndbg in the files I mentioned causes a very small delay between operations which is probably enough for the voltages to settle and card gets detected. I have played a lot with delay variables inside mmc-pwrseq but none have worked. Have you guys ever seen such thing ? What do you think is the cause ?