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When running this

 

sudo cat /sys/kernel/debug/clk/clk_summary

 

I get the list of clocks and the specific interest is in these

 

    pll-audio-base                    0        0        0    24576000      50000     0  50000
       pll-audio-8x                   0        0        0    49152000      50000     0  50000
          i2s1                        0        0        0    49152000      50000     0  50000
       pll-audio-4x                   0        0        0    24576000      50000     0  50000
          i2s0                        0        0        0    24576000      50000     0  50000
          i2s2                        0        0        0    24576000      50000     0  50000
       pll-audio-2x                   0        0        0    12288000      50000     0  50000
       pll-audio                      0        0        0    24576000      50000     0  50000
          ac-dig                      0        0        0    24576000      50000     0  50000
          spdif                       0        0        0    24576000      50000     0  50000

 

 

Now, the i2s0 (which interests me) is under pll-audio-4x and has 24576000Hz

So the is20 is clocked at 24576000Hz, but I want it to be clocked at 49152000Hz

The question is this, how can I move the i2s0 under pll-audio-8x with 49152000Hz ?

Can I simply instruct it via a DT overlay that its master clock will be 49152000Hz?

Should I need to re-parent it ? Is there an example on how this can be done via a DT overlay for i2s0 or does it need kernel source patching ? Is it even feasible ?

 

Christos

 

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