[Armbian build PR] - Rockchip64 PCIE PHY reset on probe

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Description

This patch PCIE initialization error after warm reboot. Typical error log after warm reboot:

[    2.510082] rockchip-pcie f8000000.pcie: host bridge /pcie@f8000000 ranges:
[    2.510139] rockchip-pcie f8000000.pcie:      MEM 0x00fa000000..0x00fbdfffff -> 0x00fa000000
[    2.510160] rockchip-pcie f8000000.pcie:       IO 0x00fbe00000..0x00fbefffff -> 0x00fbe00000
[    2.510748] rockchip-pcie f8000000.pcie: no bus scan delay, default to 0 ms
[    2.510795] rockchip-pcie f8000000.pcie: no vpcie12v regulator found
[    3.011274] rockchip-pcie f8000000.pcie: PCIe link training gen1 timeout!
[    3.011373] rockchip-pcie: probe of f8000000.pcie failed with error -110

The root of cause is when device is booted after power on PHY stay in "factory" state. After warm boot PHY stay in previous state and prevent any training and PCIE init fail. Log after fix PHY:

[    2.296993] rockchip-pcie f8000000.pcie: host bridge /pcie@f8000000 ranges:
[    2.297064] rockchip-pcie f8000000.pcie:      MEM 0x00fa000000..0x00fbdfffff -> 0x00fa000000
[    2.297100] rockchip-pcie f8000000.pcie:       IO 0x00fbe00000..0x00fbefffff -> 0x00fbe00000
[    2.298098] rockchip-pcie f8000000.pcie: no bus scan delay, default to 0 ms
[    2.298169] rockchip-pcie f8000000.pcie: no vpcie12v regulator found
[    2.324717] rockchip-pcie f8000000.pcie: wait 0 ms (from device tree) before bus scan
[    2.325477] rockchip-pcie f8000000.pcie: PCI host bridge to bus 0000:00
[    2.325499] pci_bus 0000:00: root bus resource [bus 00-1f]
[    2.325518] pci_bus 0000:00: root bus resource [mem 0xfa000000-0xfbdfffff]
[    2.325537] pci_bus 0000:00: root bus resource [io  0x0000-0xfffff] (bus address [0xfbe00000-0xfbefffff])

How Has This Been Tested?

• [X] Tested on NanoPI R4S with current kernel - OK.
• [X] Tested on NanoPI R4S with edge kernel - OK.

Checklist:

• [X] My code follows the style guidelines of this project
• [X] I have performed a self-review of my own code
• [X] I have commented my code, particularly in hard-to-understand areas
• [X] I have made corresponding changes to the documentation
• [X] My changes generate no new warnings
• [X] Any dependent changes have been merged and published in downstream modules

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