Abusing I2S on H3 experiment

[DrTune]

Hiya,

Goal:

Ok so I'm after a high speed synchronous serial interface (50mhz would be nice) with reasonably flexible clocking options so I can tweak it up and down. The goal is to implement a "fast as possible" SWD debug interface to a Cortex M0; ideally the serial interface could be run arbitrarily fast until the target M0 or the wiring can't handle it.  If can do 48mhz I can basically read/write one 32-bit word per microsecond over swd, so 4MB/sec, and I want to process that a little and send it to a PC (obviously ethernet).  

I especially care about consistent, gap-free, no jitter on this serial interface.

 

So SPI is the obvious choice but I'm also strongly drawn to abusing I2S; I don't care about real audio working so it looks like I can repurpose the H3's audio PLL.  

The H3 I2S hardware looks pretty decent in that it has reasonable size FIFOs and DMA and especially that it appears to allow you to clock the living shit out of it.

 

Referring to the H3 datasheet http://linux-sunxi.org/images/4/4b/Allwinner_H3_Datasheet_V1.2.pdf

 

Page 524 shows the 64x32 bit RX and 128x32 TX fifos, which are pretty generous.

The clock comes from PLL2, the audio pll, which appears to have no other use and it appears will run up to 200mhz 

If you look at page 536 you see the I2S clock divider support as fast as /1 (!) up to /192.  

It's effectively an SPI port (TX+RX synchronously) with extra care to make sure it can run without dropouts (of course, because it's for audio)

The FIFOs have programmable low water and DMA, I mean what could possibly go wrong?

 

The shortest fifo (rx) is 64x32 bits= 2kbit (256 byte). At 100Mhz that's 10ns*2048= 20.48us or 48k FIFO contents/sec, and the H3 can trigger DMA FIFO operations automatically of course.  Half-emptying the RX fifo (if we have high-water mark at 50% to allow for a bunch of dma latency) is 32 32-bit DMA transfers,  which of course is 100Mbit/8=12.5MBytes/sec.

Superficially it seems very doable in terms of the traffic running on the H3 silicon, it may even run faster - however I do not really expect to get a usable 100mbit link out of an orange pi, primarily for pcb/electrical reasons. 

 

By comparison the real SPI controller only has 64x8 bit FIFOs, and the clock selection is less flexible. (with I2S we have our own PLL to play with)

 

Hmmmm.. so looks pretty handy actually. I started off abusing I2S to drive WS2812s but it looks like there's a lot you can do with it; a flexibly & reliably clocked 100mbit bidirectional synchronous link running into a SOC that has plenty of ram and cpu grunt and network capability that costs about $10... mmmm...  

 

Ok, hold my beer...

[Blars]

I'm not I2S expert, but IIRC it alternates between the left and right channels, so you may need to do some data manipulation to make it a single SPI channel.