Rockchip RK3308 (Rock Pi S) – Dynamic Clock management (CCF) blocks I2S-MCLK output pin after switching simple-audio-card from dummy to internal codec

[g.coach]

Hello community,

 

I am working on a multi-channel audio project using a Rock Pi S (Rockchip RK3308) running a modern Mainline Kernel (6.18.y-current-rockchip64). My hardware setup relies on a fixed wiring where the Master Clock (MCLK) is connected to Pin 7 (GPIO2_A4) and BCLK is connected to Pin 12 (GPIO2_A5) using the i2s_8ch_0 controller.

 

The Goal:

We want to keep the working I2S/TDM master device tree foundation but replace the old, silent dummy codec (linux,spdif-dit) with the actual internal hardware codec (rockchip,rk3308-codec), so that ALSA maps the channels correctly instead of routing them into a digital void.

 

Note:

We are explicitly routing the I2S stream to the internal Rockchip SoC codec (acodec, phandle <0x80>) to avoid any external I2C/SPI control loops, so the soundcard registers perfectly in ALSA.

The only remaining issue is forcing the CCF to un-gate the physical MCLK output pin.

 

What works perfectly:

When using the internal hardware codec mapping, the device tree compiles cleanly and ALSA successfully registers the sound card as a hardware device without any parsing errors or deferred probes:

 

card 1: rockchiprk3308t [rockchip,rk3308-toslink], device 0: ff300000.i2s-rk3308-hifi ff560000.codec-0

 

When starting a stream (e.g. via speaker-test or MPD), hw_params confirms active playback at 44100 Hz, Stereo, S16_LE.

The Core Problem:

Although the software pipeline is running perfectly, the physical pins remain dead because the Common Clock Framework (CCF) shuts down the clock output gate. Checking /sys/kernel/debug/clk/clk_summary during active playback reveals the following state:

          clk_i2s0_8ch_tx_src        1       1        0        11289600    0          0     50000      Y
          clk_i2s0_8ch_tx_mux     1       1        0        11289600    0          0     50000      Y
          clk_i2s0_8ch_tx      2       2        0        11289600    0          0     50000      Y                  i2s@ff300000
          clk_i2s0_8ch_tx_out 0       0        0        11289600    0          0     50000      N                     deviceless

 

The internal root clock (clk_i2s0_8ch_tx) is active (Y) and running at the correct frequency, but the actual hardware output gate (clk_i2s0_8ch_tx_out) is strictly forced to inactive (N) by the kernel's runtime power management / clock gating.

Current Device Tree Snippet:

        analog-sound {
                compatible = "simple-audio-card";
                simple-audio-card,name = "rockchip,rk3308-toslink";
                simple-audio-card,format = "i2s";
                simple-audio-card,continuous-clock;
                simple-audio-card,mclk-fs = <0x100>;

                simple-audio-card,cpu {
                        sound-dai = <&i2s_8ch_0>; /* phandle <0xaf> -> i2s@ff300000 */
                        frame-master;
                        bitclock-master;
                };

                simple-audio-card,codec {
                        sound-dai = <&acodec>; /* phandle <0x80> -> codec@ff560000 */
                };
        };

 

The Question:

Since the driver seems to assume a slave configuration or disables the external clock gate due to the acodec binding, how can we officially force clk_i2s0_8ch_tx_out to stay active (Y) during playback within the device tree or standard ALSA configuration, without having to use out-of-tree kernel modules or dirty register overrides?

 

Are there missing properties required in the simple-audio-card routing or the i2s@ff300000 node itself to un-gate the external clock pin when combined with the internal codec?

Any help or pointing towards the correct clock-handling properties for the RK3308 audio subsystem would be highly appreciated.

 

Thanks!