megi
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Posts posted by megi
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@froezus Nice! Thank you. I've changed your patch, so that it uses R_WDOG only on H6.
https://megous.com/dl/tmp/0001-Fix-reset-issue-on-H6-by-using-R_WDOG.patch
It's still a hack, but at least it doesn't touch other SoCs.
U-boot will also need patching, because it doesn't use ATF for reset.
I tested it on Opi3, and it works. :))
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@kexec I've changed the code and tested it on my board and EDID reading works for me with patches that I've sent to the mailing list, today: https://lkml.org/lkml/2019/4/5/857
So hopefully all this will be working in armbian soon.
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4 hours ago, kexec said:
----------------------------------------------------Update--------------------------------------
changing code had no results, neither edid is present nor hdmi started to work as in BSP kernel.
Thanks, I'll look more closely into it, when I'll have some time.
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8 minutes ago, jernej said:
If you plan to submit orangepi 3 DT and HDMI improvements to support OPi 3, please change logic to use voltage regulator framework instead of gpios as it is better description of actual hardware. Additionally, at least in my opinion, this should be property of HDMI PHY and not HDMI controller, but that's debatable.
Ok, that seems reasonable. Thanks.
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I have Orange Pi 3. I don't think more boards would help me.
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Try removing the duplicate hdmi related nodes. You have &hdmi* there multiple times.
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3 hours ago, martinayotte said:
Do you mean others boards, like my OPi3 which have 2GB, would reset in bad DRAM region ?
Maybe, but clearing (BROM should start at 0) RVBARADDR0 prior to reboot did not help make the u-boot reset command work.
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Anyone here wants to try an EDID reading fix?
https://megous.com/git/linux/commit/?h=up/opi3/v1&id=96d9395beba639d89cb1f128d3b93b68d7cd96b2
And adding this to &hdmi node:
+ ddc-enable-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
like here:
https://megous.com/git/linux/commit/?h=up/opi3/v1&id=d046a90b11ae0dab0bb3d86f14e6e8db13c4eedd
may help.
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PineH64 with how much DRAM?
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Maybe setting the register that controls where the CPU starts executing after reset via RVBARADDR register, before triggering the watchdog may help.
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I've tried looking into it. Mainline u-boot has a reset command, wich triggers a watchdog based reboot, and it just locks up the machine, when the watchdog timeout expires. The same thing simply happens in kernel. Kernel tells ATF to reset, ATF does the same thing as u-boot (watchdog based reset), and the SoC locks up.
Presumably, there's some other setup needed on H6 to make the SoC reset correctly. Maybe CPU resets into an incorrect PC adadress. Who knows? I didn't find anything obvious by looking at the reset code in the BSP u-boot/kernel. It will be something less obvious.
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2 hours ago, jernej said:
It's present in 5.0, but just for PineH64. Just add DT bits for OrangePi 3 and it should work.
BTW, if you'll create patches, please send them upstream.
Yes, HDMI works. Enabling it in DTS + the a64-de2 bus in config is enough.
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So, no hurry.
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15 minutes ago, martinayotte said:
Right ! ... and it will soon be on 5.0.y ...
It needs modifications to the H6 OPP table, becase Icenowy told me, that the current table is for the best/fastest H6 SoC bins only.
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I have a working Orange Pi 3 branch here: https://github.com/megous/linux
I haven't tried HDMI yet, but most of the other stuff works, incl. ethernet.
Orangepi 3 h6 allwiner chip
in Allwinner sunxi
Posted
I now have Bluetooth working with mainline linux on Orange Pi 3.
It's in my opi3-5.1 branch. So, test if you like.