Dmitriy

To resolve this problem enough in fex config file on mm2_para change sdc_detmode from 1 to 3. 764 [mmc2_para] 765 sdc_used = 1 ~ 766 sdc_detmode = 3 767 sdc_buswidth = 8 768 sdc_clk = port:PC05<3><1><2><default> 769 sdc_cmd = port:PC06<3><1><2><default> 770 sdc_d0 = port:PC08<3><1><2><default> 771 sdc_d1 = port:PC09<3><1><2><default> 772 sdc_d2 = port:PC10<3><1><2><default> 773 sdc_d3 = port:PC11<3><1><2><default> 774 sdc_d4 = port:PC12<3><1><2><default> 775 sdc_d5 = port:PC13<3><1><2><default> 776 sdc_d6 = port:PC14<3><1><2><default> 777 sdc_d7 = port:PC15<3><1><2><default> 778 emmc_rst = port:PC16<3><1><2><default>

Has anybody resolved this problem? I found only such solution. file linux-sun8i/sun8i/drivers/pinctrl/pinctrl-sunxi.c: 471 static int sunxi_pinconf_set(struct pinctrl_dev *pctldev, 472 unsigned pin, 473 unsigned long config) 474 { 475 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 476 struct sunxi_pin_bank *bank = sunxi_pin_to_bank(pctl, pin); 477 unsigned int pin_bias; 478 void __iomem *reg; 479 u32 val; 480 u32 mask; 481 u16 dlevel; 482 u16 data; 483 u16 func; 484 u16 pull; 485 486 pin_reset_bias(&pin_bias, pin); 487 if (IS_ERR_OR_NULL(bank)) { 488 pr_debug("invalid pin number [%d] to set pinconf\n", pin); 489 return -EINVAL; 490 } 491 switch (SUNXI_PINCFG_UNPACK_TYPE(config)) { 492 case SUNXI_PINCFG_TYPE_DRV: 493 if (strcmp(pin_get_name(pctl->pctl_dev, pin),"PA0")==0) 494 break; 495 dlevel = SUNXI_PINCFG_UNPACK_VALUE(config); 496 val = pinctrl_readl_reg(bank->membase + sunxi_dlevel_reg(pin_bias)); 497 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin_bias); 498 val=(val & ~mask) | (dlevel << sunxi_dlevel_offset(pin_bias)); 499 reg=bank->membase + sunxi_dlevel_reg(pin_bias); 500 pinctrl_write_reg(val,reg); 501 pr_debug("sunxi pconf set pin [%s] drive strength to [LEVEL%d]\n", 502 pin_get_name(pctl->pctl_dev, pin), dlevel); 503 break; 504 case SUNXI_PINCFG_TYPE_PUD: 505 if (strcmp(pin_get_name(pctl->pctl_dev, pin),"PA0")==0) 506 break; 507 pull = SUNXI_PINCFG_UNPACK_VALUE(config); 508 val = pinctrl_readl_reg(bank->membase + sunxi_pull_reg(pin_bias)); 509 mask = PULL_PINS_MASK << sunxi_pull_offset(pin_bias); 510 val=(val & ~mask) | (pull << sunxi_pull_offset(pin_bias)); 511 reg=bank->membase + sunxi_pull_reg(pin_bias); 512 pinctrl_write_reg(val,reg); 513 pr_debug("sunxi pconf set pin [%s] pull to [%d]\n", 514 pin_get_name(pctl->pctl_dev, pin), pull); 515 break; 516 case SUNXI_PINCFG_TYPE_DAT: 517 if (strcmp(pin_get_name(pctl->pctl_dev, pin),"PA0")==0) 518 break; 519 data = SUNXI_PINCFG_UNPACK_VALUE(config); 520 val = pinctrl_readl_reg(bank->membase + sunxi_data_reg(pin_bias)); 521 mask = DATA_PINS_MASK << sunxi_data_offset(pin_bias); 522 val=(val & ~mask) | (data << sunxi_data_offset(pin_bias)); 523 reg=bank->membase + sunxi_data_reg(pin_bias); 524 pinctrl_write_reg(val,reg); 525 pr_debug("sunxi pconf set pin [%s] data to [%d]\n", 526 pin_get_name(pctl->pctl_dev, pin), data); 527 break; 528 case SUNXI_PINCFG_TYPE_FUNC: 529 if (strcmp(pin_get_name(pctl->pctl_dev, pin),"PA0")==0) 530 break; 531 func = SUNXI_PINCFG_UNPACK_VALUE(config); 532 val = pinctrl_readl_reg(bank->membase + sunxi_mux_reg(pin_bias)); 533 mask = MUX_PINS_MASK << sunxi_mux_offset(pin_bias); 534 val=(val & ~mask) | (func << sunxi_mux_offset(pin_bias)); 535 reg=bank->membase + sunxi_mux_reg(pin_bias); 536 pinctrl_write_reg(val,reg); 537 pr_debug("sunxi pconf set pin [%s] func to [%d]\n", 538 pin_get_name(pctl->pctl_dev, pin), func); 539 540 printk(KERN_INFO"dima sunxi pconf set pin [%s] func to [%d]\n", 541 pin_get_name(pctl->pctl_dev, pin), func); 542 543 break; 544 default: 545 pr_debug("invalid sunxi pconf type for set\n"); 546 return -EINVAL; 547 } 548 return 0; 549 } I add if (strcmp(pin_get_name(pctl->pctl_dev, pin),"PA0")==0) break;

EvgeniK45, this is not working. zador.blood.stained, Can you help what file I must to edit?

Hello all. I am using bananapi M2+. I need UART0 for my development. But while booting, it transmits debug (u-boot) information. For example: U-Boot SPL 2016.09-armbian (Oct 24 2016 - 16:40:21) DRAM: 1024 MiB Trying to boot from MMC1 U-Boot 2016.09-armbian (Oct 24 2016 - 16:40:21 +0300) Allwinner Technology CPU: Allwinner H3 (SUN8I 1680) Model: Xunlong Orange Pi PC DRAM: 1 GiB MMC: SUNXI SD/MMC: 0, SUNXI SD/MMC: 1 *** Warning - bad CRC, using default environment How can I disable it?

martinayotte, thank you for advice. jernej I have resolved my problem. I chenged [s_uart0] s_uart_used = 0 s_uart_tx = port:PL02<2><default><default><default> s_uart_rx = port:PL03<2><default><default><default> to s_uart_used =1 and re-compile kernel. After it, the registers R_UART write correct. And I am using R_UART as general UART. Thank you for hint.

BT I need also in my development. Using of external USB to UART bridge is impossible due to other reasons.

Yes, I need for 4 UARTs in my development. The one UART using for BT. Thereby, I need for this R_UART.

Thank you for detailed answer. Do I right understand, what in banana pi m2+ not possible to use R_UART for general purposes such as UART1-UART3? Maybe is possible change some config for it? Or any other solution?

Why do you think so? R_UART connected to pins PL2 and PL 3. It has address 0X01F0 2800 and interrupt vector. And from datasheet: There are 5 UART controllers. All UART controllers can be configured as Serial IrDA. UART0, UART1, UART2, UART3,R_UART? Where do you find this information?

Hello to all! I have banana pi m2+ with Allwinner H3. OS: ARMBIAN Debian GNU/Linux 8 (jessie) 3.4.112-sun8i I program linux kernel driver. And I am can't run R_UART. I write to register any value, and read value alway zero. It seems that APB0 bus is not cloked. Or device R_UART reset asserted. What I do wrong? Sincerely, Dmitriy.