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    km1kze got a reaction from teenytinycactus in Orange Pi Zero Plus2 H5 hardware oddity in VDD_CPUX power circuit   
    Don't remember what was written on them, but if you bought from my link, they're good 
    You can also see a J1 marking on the original mosfet from the orange pi zero H2+
  2. Like
    km1kze got a reaction from 5kft in Orange Pi Zero Plus2 H5 hardware oddity in VDD_CPUX power circuit   
    The mosfets arrived and finaly managed to make a test, and it works! Thank you again 5kft !
    For me it worked with this Armbian version: Armbian_5.34.171121_Orangepizeroplus2-h5_Ubuntu_xenial_next_4.13.14.img, then compiled  with the build compilation tips shown by 5kft  in a previous post. It seems it runs at 1296 Mhz from the start, I didn't need to update cpufrequtils.
    Surprisingly, it stays in idle at a lower temperature than before. Idle now is 38 celsius -although with a temperature meter is around 45. Before it was 55 - real it was with 2-3 degrees more (ambient temperature around 25).
    20:33:36: 1296MHz 0.02 0% 0% 0% 0% 0% 0% 38.2°C 0/11  
    pi@orangepizeroplus2:~$ cpufreq-info -c 1 cpufrequtils 008: cpufreq-info (C) Dominik Brodowski 2004-2009 Report errors and bugs to, please. analyzing CPU 1: driver: cpufreq-dt CPUs which run at the same hardware frequency: 0 1 2 3 CPUs which need to have their frequency coordinated by software: 0 1 2 3 maximum transition latency: 6.24 ms. hardware limits: 240 MHz - 1.30 GHz available frequency steps: 240 MHz, 408 MHz, 648 MHz, 816 MHz, 912 MHz, 960 MHz, 1.01 GHz, 1.06 GHz, 1.10 GHz, 1.15 GHz, 1.25 GHz, 1.30 GHz available cpufreq governors: conservative, userspace, powersave, ondemand, performance, schedutil current policy: frequency should be within 1.30 GHz and 1.30 GHz. The governor "ondemand" may decide which speed to use within this range. current CPU frequency is 1.30 GHz. cpufreq stats: 240 MHz:0.04%, 408 MHz:1.33%, 648 MHz:0.14%, 816 MHz:0.12%, 912 MHz:0.08%, 960 MHz:0.08%, 1.01 GHz:0.07%, 1.06 GHz:0.04%, 1.10 GHz:0.05%, 1.15 GHz:0.04%, 1.25 GHz:0.04%, 1.30 GHz:97.98% (254) pi@orangepizeroplus2:~$ sudo sysbench --test=cpu --cpu-max-prime=20000 --num-threads=4 run && cat /sys/devices/virtual/thermal/thermal_zone0/temp sysbench 0.4.12: multi-threaded system evaluation benchmark Running the test with following options: Number of threads: 4 Doing CPU performance benchmark Threads started! Done. Maximum prime number checked in CPU test: 20000 Test execution summary: total time: 7.0661s total number of events: 10000 total time taken by event execution: 28.2527 per-request statistics: min: 2.82ms avg: 2.83ms max: 5.55ms approx. 95 percentile: 2.83ms Threads fairness: events (avg/stddev): 2500.0000/1.87 execution time (avg/stddev): 7.0632/0.00 56450  
  3. Like
    km1kze reacted to 5kft in Orange Pi Zero Plus2 H5 hardware oddity in VDD_CPUX power circuit   
    I very much hope that those BSN20s will work - I bought mine from that very same seller 
    Regarding increasing the clocks, I've attached a subset of my test patchset for the current mainline sunxi-next kernel (4.14.y) that you could start from.  Hopefully you should be able to just copy this to your "armbian/build/userpatches/kernel/sunxi-next/" directory, then build your kernel as normal (e.g., "./ KERNEL_ONLY=yes KERNEL_CONFIGURE=no KERNEL_KEEP_CONFIG=no BRANCH=next BETA=yes BUILD_KSRC=no BOARD=orangepizeroplus2-h5").  Note that you'll need to update your "/etc/default/cpufrequtils" configuration to set the new min/max speeds (don't forget to reboot or restart the cpufreq daemon after doing this).
    When you do the build, make sure the patch step succeeds - the "z" at the beginning of the filename helps ensure that it is the last patch applied.
    (Note also that on reboot the HDMI driver crashes on my Plus2 - as a temporary workaround I disabled HDMI in the DTS as well.  Also I noticed that the default Armbian OPi plus2 patchset adds the regulator entry - I was confusing this change with my Neo Plus2 patch for this.)
  4. Like
    km1kze reacted to 5kft in Orange Pi Zero Plus2 H5 hardware oddity in VDD_CPUX power circuit   
    I've attached it here as a zip file, hopefully that will work