Efforts to develop firmware for H96 MAX M9 RK3576 TV Box 8G/128G

Hqnicolas · June 1

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Product Specification:

Chipset: Rockchip RK3576 Octa Core ARM Mali G52 MC3

WIFI: WiFi6 11ax 1x1 80 MHz
wifi controller: AP6275P

RAM: DDR4 4GB/8GB

ROM: eMMC 32GB/64GB/128GB

OS: Android 14.0 || Armbian Vendor 6.1

Ethernet: 1000M Standard RJ-45

Bluetooth: BT 5.0
The RK3576 is indeed a lower-cost SoC but features four Cortex-A72 and four Cortex-A53 cores instead

Android Base Files:

H96-RK3576-ANDROID.dts

H96-RK3576-BOX.dtb

RK3576_MiniLoaderAll.bin

wifi controller: AP6275P

Wifi Driver:
https://drive.google.com/file/d/1n6x4tg5Xh24nWllOTJTq1ldVyDkK8W2Q/view?usp=sharing

Flashing Tools:

https://drive.google.com/file/d/1nLgPCBN0qmbzufWDFmISYc92JUpvwMPc/view?usp=sharing

build_armbian.csc:

https://drive.google.com/file/d/1VNR5QJlPylPsce9PI9O2TB3wOpshK2Bh/view?usp=sharing

@hzdm Stock Firmware: method

https://drive.google.com/file/d/1zLGvIxLE6vf8iSTjsyEr-Ly4MZ6ZahBB/view?usp=sharing

Force board Maskrom Mode
Maskrom Pins:

Quote

Edited October 17 by Hqnicolas

Vincenzoernst1 · June 21

indeed this would be a very nice little server 💪

Hqnicolas · June 23

@Avatar Ng @Vincenzoernst1
I have spoted this model on Aliexpress (out of stock)
other anoucement (out of stock)

alternative (out of stock) alternative alternative

Edited September 10 by Hqnicolas

gen ha · June 28

In China, this 8+128GB only costs less than $75

El308 · July 8

Does somebody have the Firmware for this TV-Box?

I went in treble after installing the Nova Launcher, box is now blocked. Need to flash Firmware again

Hqnicolas · July 11

On 7/8/2024 at 1:08 PM, El308 said:

Does somebody have the Firmware for this TV-Box?

need to be dumped
the factory is a mess.....

keep your eyes on (russians)4pda and factory(sh!t dumper)

cmuki · August 26

Hello to all!

Today my box arrived and I took some photos of it. I'm currently checking the testpoints since I couldn't dump the firmware, but I'll update this comment once I succeed. I'll post a bootlog once available.

Be careful not to damage the WiFi antenna when opening the box.

EDIT 1: Added 3 bootlogs, because I couldn't capture everything at once with Putty.

boot2.txt boot3.txt boot1.txt

Edited August 26 by cmuki
Additional info

Hqnicolas · August 26

@pessimism
Did you keep those spare SD card readers?

3 hours ago, cmuki said:

Edited August 26 by Hqnicolas

Hqnicolas · August 26

3 hours ago, cmuki said:

I couldn't dump the firmware

let's try with linux with rkdeveloptool

pessimism · August 27

[mention=211404]pessimism[/mention]
Did you keep those spare SD card readers?

Haha yes, here we go again

Sent from my iPad using Tapatalk

cmuki · August 27

It's me again.

Below are actually the testpoints that I used to get the bootlog. Be advised that they are too narrow for a conventional jumper cable, that's why I had to hold them down while booting. I also used one of the screwholes as a GND.

Here's the dump with rkdeveloptool - https://mega.nz/folder/GAo2DToY#b2LLSVPliw2iH6-fvDCcqw

I used the pinenote-backup for automation since I didn't want to do it manually - https://github.com/talpadk/pinenote-backup and it seems it's successful. Can I also create an image from the dump?

Let me know if I did something incorrectly and have to redo it again.

EDIT: Ran rkdeveloptool rl 0 244285440 dump_h96max9.img, added it to the MEGA folder. The device is in Loader mode; also usb 3.0 needs to be used to connect the device to the computer.

Edited August 27 by cmuki

Hqnicolas · August 27

4 hours ago, cmuki said:

Can I also create an image from the dump?

yes, to create a image you will need to use the rockdev maybe a newer version exist

baseparameter have all information about the image file that you will need to configure rockdev

how @mvpwar make a backup

Quote

/Downloads/Linux_Pack_Firmware/rockdev$ ./mkupdate.sh
start to make update.img...
Android Firmware Package Tool v1.66
------ PACKAGE ------
Add file: ./package-file
Add file: ./package-file done,offset=0x800,size=0x1ce,userspace=0x1
Add file: ./Image/MiniLoaderAll.bin
Add file: ./Image/MiniLoaderAll.bin done,offset=0x1000,size=0x729c0,userspace=0xe6
Add file: ./Image/parameter.txt
Add file: ./Image/parameter.txt done,offset=0x74000,size=0x1aa,userspace=0x1
Add file: ./Image/dtbo.img
Add file: ./Image/dtbo.img done,offset=0x74800,size=0x26f,userspace=0x1
Add file: ./Image/uboot.img
Add file: ./Image/uboot.img done,offset=0x75000,size=0x400000,userspace=0x800
Add file: ./Image/parameter.txt
Add file: ./Image/parameter.txt done,offset=0x475000,size=0x19e,userspace=0x1
Add file: ./Image/rootfs.img
Add file: ./Image/rootfs.img done,offset=0x475800,size=0x11f213e00,userspace=0x23e428
Add CRC...
Make firmware OK!
------ OK ------
********RKImageMaker ver 1.66********
Generating new image, please wait...
Writing head info...
Writing boot file...
Writing firmware...
Generating MD5 data...
MD5 data generated successfully!
New image generated successfully!
Making ./Image/update.img OK.

./mkupdate.sh

this process generate two files:
File1: Linux_Pack_Firmware/rockdev/Image/update.img
File2: Linux_Pack_Firmware/rockdev/update.img

I generally use the File2 to flash my device on upgrade Firmware RKDevTool

I think we need to ask redScorpio to an new decompiler
This is the old for rk3566

to extract DTB file from this DTB image you will need imgutil

example of usage

how to mess with DTS files from android DTB

1.DTS

Quote

/dts-v1/;

/ {
compatible = "rockchip,rk3576-evb\0rockchip,rk3576";
#address-cells = <0x02>;
#size-cells = <0x02>;
model = "Rockchip RK3576 Evaluation board";

aliases {
gpio0 = "/pinctrl/gpio@27320000";
serial0 = "/serial@2ad40000";
spi5 = "/spi@2a340000";
mmc0 = "/mmc@2a330000";
mmc1 = "/mmc@2a310000";
};

syscon@2600a000 {
compatible = "rockchip,rk3576-sys-grf\0syscon\0simple-mfd";
reg = <0x00 0x2600a000 0x00 0x10000>;
u-boot,dm-spl;
status = "okay";
phandle = <0x10000057>;
};

syscon@26040000 {
compatible = "rockchip,rk3576-ioc-grf\0syscon\0simple-mfd";
reg = <0x00 0x26040000 0x00 0xc000>;
u-boot,dm-spl;
status = "okay";
phandle = <0x10000058>;
};

clock-controller@27200000 {
compatible = "rockchip,rk3576-cru";
reg = <0x00 0x27200000 0x00 0x50000>;
rockchip,grf = <0x10000048>;
#clock-cells = <0x01>;
#reset-cells = <0x01>;
u-boot,dm-spl;
status = "okay";
phandle = <0x10000001>;
};

ufs@2a2d0000 {
compatible = "rockchip,rk3576-ufs";
reg = <0x00 0x2a2d0000 0x00 0x10000 0x00 0x2b040000 0x00 0x10000 0x00 0x2601f000 0x00 0x1000 0x00 0x2603c000 0x00 0x1000 0x00 0x2a2e0000 0x00 0x10000>;
reg-names = "hci\0mphy\0hci_grf\0mphy_grf\0hci_apb";
clocks = <0x10000001 0x150 0x10000001 0x14a 0x10000001 0x1df 0x10000001 0x1e1>;
interrupts = <0x00 0x169 0x04>;
power-domains = <0x1000003f 0x07>;
pinctrl-0 = <0x100000ac 0x100000ad>;
pinctrl-names = "default";
resets = <0x10000001 0x2fa>;
reset-names = "rst";
status = "okay";
u-boot,dm-spl;
};

mmc@2a310000 {
compatible = "rockchip,rk3576-dw-mshc\0rockchip,rk3288-dw-mshc";
reg = <0x00 0x2a310000 0x00 0x4000>;
interrupts = <0x00 0xfb 0x04>;
max-frequency = <0xbebc200>;
clocks = <0x10000001 0x130 0x10000001 0x12f>;
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <0x100000ae 0x100000af 0x100000b0 0x100000b1 0x100000b2>;
resets = <0x10000001 0x2b2>;
reset-names = "reset";
rockchip,use-v2-tuning;
status = "okay";
bus-width = <0x04>;
u-boot,dm-spl;
pwr-en-gpios = <0x100000b3 0x0e 0x00>;
};

mmc@2a330000 {
compatible = "rockchip,rk3576-dwcmshc\0rockchip,rk3588-dwcmshc";
reg = <0x00 0x2a330000 0x00 0x10000>;
interrupts = <0x00 0xfd 0x04>;
clocks = <0x10000001 0xff 0x10000001 0x100 0x10000001 0x101 0x10000001 0x102 0x10000001 0x103>;
resets = <0x10000001 0x218 0x10000001 0x219 0x10000001 0x21a 0x10000001 0x21b 0x10000001 0x21c>;
reset-names = "core\0bus\0axi\0block\0timer";
max-frequency = <0xbebc200>;
status = "okay";
bus-width = <0x08>;
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
};

spi@2a340000 {
compatible = "rockchip,sfc";
reg = <0x00 0x2a340000 0x00 0x4000>;
interrupts = <0x00 0xfe 0x04>;
clocks = <0x10000001 0xfd 0x10000001 0xfe>;
#address-cells = <0x01>;
#size-cells = <0x00>;
status = "okay";
u-boot,dm-spl;

flash@0 {
u-boot,dm-spl;
compatible = "spi-nand";
reg = <0x00>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
spi-max-frequency = <0x4c4b400>;
};

flash@1 {
u-boot,dm-spl;
compatible = "jedec,spi-nor";
label = "sfc_nor";
reg = <0x00>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
spi-max-frequency = <0x4c4b400>;
};
};

crypto@2a400000 {
compatible = "rockchip,crypto-v4";
reg = <0x00 0x2a400000 0x00 0x2000>;
interrupts = <0x00 0xb1 0x04>;
clocks = <0x10000001 0x227 0x10000001 0x222 0x10000001 0x228>;
resets = <0x10000001 0x40003>;
reset-names = "crypto-rst";
status = "okay";
u-boot,dm-spl;
};

decompress@2ac30000 {
compatible = "rockchip,hw-decompress";
reg = <0x00 0x2ac30000 0x00 0x1000>;
interrupts = <0x00 0x26 0x04>;
clocks = <0x10000001 0xbf 0x10000001 0xc1 0x10000001 0xc0>;
resets = <0x10000001 0x129>;
reset-names = "dresetn";
status = "okay";
u-boot,dm-spl;
};

serial@2ad40000 {
compatible = "rockchip,rk3576-uart\0snps,dw-apb-uart";
reg = <0x00 0x2ad40000 0x00 0x100>;
interrupts = <0x00 0x4c 0x04>;
clocks = <0x10000001 0x92 0x10000001 0x87>;
reg-shift = <0x02>;
reg-io-width = <0x04>;
dmas = <0x1000004a 0x06 0x1000004a 0x07>;
pinctrl-names = "default";
pinctrl-0 = <0x100000fd>;
status = "okay";
u-boot,dm-spl;
};

pinctrl {
compatible = "rockchip,rk3576-pinctrl";
rockchip,grf = <0x10000058>;
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
u-boot,dm-spl;
phandle = <0x1000011f>;

gpio@27320000 {
compatible = "rockchip,gpio-bank";
reg = <0x00 0x27320000 0x00 0x200>;
interrupts = <0x00 0x99 0x04>;
clocks = <0x10000001 0x206 0x10000001 0x207>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-ranges = <0x1000011f 0x00 0x00 0x20>;
interrupt-controller;
#interrupt-cells = <0x02>;
u-boot,dm-spl;
status = "okay";
phandle = <0x100000b3>;
};

pcfg-pull-up {
bias-pull-up;
u-boot,dm-spl;
phandle = <0x10000124>;
};

pcfg-pull-none {
bias-disable;
u-boot,dm-spl;
phandle = <0x10000120>;
};

pcfg-pull-up-drv-level-2 {
bias-pull-up;
drive-strength = <0x02>;
u-boot,dm-spl;
phandle = <0x10000121>;
};

sdmmc0 {
u-boot,dm-spl;

sdmmc0-bus4 {
rockchip,pins = <0x02 0x00 0x01 0x10000123 0x02 0x01 0x01 0x10000123 0x02 0x02 0x01 0x10000123 0x02 0x03 0x01 0x10000123>;
u-boot,dm-spl;
phandle = <0x100000b1>;
};

sdmmc0-clk {
rockchip,pins = <0x02 0x05 0x01 0x10000123>;
u-boot,dm-spl;
phandle = <0x100000ae>;
};

sdmmc0-cmd {
rockchip,pins = <0x02 0x04 0x01 0x10000123>;
u-boot,dm-spl;
phandle = <0x100000af>;
};

sdmmc0-det {
rockchip,pins = <0x00 0x07 0x01 0x10000124>;
u-boot,dm-spl;
phandle = <0x100000b0>;
};
};
};

chosen {
stdout-path = "/serial@2ad40000";
u-boot,spl-boot-order = "/mmc@2a310000\0/spi@2a340000/flash@0\0/spi@2a340000/flash@1\0same-as-spl";
};

secure-otp@2a480000 {
u-boot,dm-spl;
compatible = "rockchip,rk3576-secure-otp";
reg = <0x00 0x2a480000 0x00 0x10000>;
};
};

2.DTS

Quote

/dts-v1/;

/ {
compatible = "rockchip,rk3576-evb\0rockchip,rk3576";
#address-cells = <0x02>;
#size-cells = <0x02>;
model = "Rockchip RK3576 Evaluation board";

aliases {
gpio0 = "/pinctrl/gpio@27320000";
gpio1 = "/pinctrl/gpio@2ae10000";
gpio2 = "/pinctrl/gpio@2ae20000";
gpio3 = "/pinctrl/gpio@2ae30000";
gpio4 = "/pinctrl/gpio@2ae40000";
serial0 = "/serial@2ad40000";
spi5 = "/spi@2a340000";
mmc0 = "/mmc@2a330000";
mmc1 = "/mmc@2a310000";
};

firmware {
u-boot,dm-pre-reloc;

scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x82000010>;
shmem = <0x1000001c>;
#address-cells = <0x01>;
#size-cells = <0x00>;
u-boot,dm-pre-reloc;

protocol@14 {
reg = <0x14>;
#clock-cells = <0x01>;
u-boot,dm-pre-reloc;
phandle = <0x10000088>;
};
};
};

psci {
compatible = "arm,psci-1.0";
method = "smc";
u-boot,dm-pre-reloc;
status = "okay";
};

syscon@2600a000 {
compatible = "rockchip,rk3576-sys-grf\0syscon\0simple-mfd";
reg = <0x00 0x2600a000 0x00 0x10000>;
u-boot,dm-spl;
status = "okay";
phandle = <0x10000057>;
};

syscon@2601e000 {
compatible = "rockchip,rk3576-usb-grf\0syscon";
reg = <0x00 0x2601e000 0x00 0x1000>;
clocks = <0x10000001 0x14a>;
u-boot,dm-pre-reloc;
phandle = <0x10000044>;
};

syscon@26020000 {
compatible = "rockchip,rk3576-php-grf\0syscon";
reg = <0x00 0x26020000 0x00 0x2000>;
clocks = <0x10000001 0x104>;
u-boot,dm-pre-reloc;
status = "okay";
phandle = <0x10000045>;
};

syscon@26028000 {
compatible = "rockchip,rk3576-pipe-phy-grf\0syscon";
reg = <0x00 0x26028000 0x00 0x2000>;
clocks = <0x10000001 0x13c>;
u-boot,dm-pre-reloc;
status = "okay";
phandle = <0x1000011c>;
};

syscon@2602a000 {
compatible = "rockchip,rk3576-pipe-phy-grf\0syscon";
reg = <0x00 0x2602a000 0x00 0x2000>;
clocks = <0x10000001 0x13d>;
u-boot,dm-pre-reloc;
status = "okay";
phandle = <0x1000011d>;
};

syscon@2602c000 {
compatible = "rockchip,rk3576-usbdpphy-grf\0syscon";
reg = <0x00 0x2602c000 0x00 0x2000>;
clocks = <0x10000001 0x1f4>;
u-boot,dm-pre-reloc;
phandle = <0x10000119>;
};

syscon@2602e000 {
compatible = "rockchip,rk3576-usb2phy-grf\0syscon\0simple-mfd";
reg = <0x00 0x2602e000 0x00 0x4000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
clocks = <0x10000001 0x1f4>;
u-boot,dm-pre-reloc;
phandle = <0x10000118>;

usb2-phy@0 {
compatible = "rockchip,rk3576-usb2phy";
reg = <0x00 0x10>;
resets = <0x10000001 0x80017 0x10000001 0x80009>;
reset-names = "phy\0apb";
clocks = <0x10000001 0x21b>;
clock-output-names = "usb480m_phy0";
#clock-cells = <0x00>;
rockchip,usbctrl-grf = <0x10000044>;
status = "okay";
u-boot,dm-pre-reloc;

otg-port {
#phy-cells = <0x00>;
interrupts = <0x00 0x15e 0x04 0x00 0x15f 0x04 0x00 0x160 0x04>;
interrupt-names = "otg-bvalid\0otg-id\0linestate";
status = "okay";
u-boot,dm-pre-reloc;
phandle = <0x10000040>;
};
};
};

syscon@26040000 {
compatible = "rockchip,rk3576-ioc-grf\0syscon\0simple-mfd";
reg = <0x00 0x26040000 0x00 0xc000>;
u-boot,dm-spl;
status = "okay";
phandle = <0x10000058>;
};

clock-controller@27200000 {
compatible = "rockchip,rk3576-cru";
reg = <0x00 0x27200000 0x00 0x50000>;
rockchip,grf = <0x10000048>;
#clock-cells = <0x01>;
#reset-cells = <0x01>;
u-boot,dm-spl;
status = "okay";
phandle = <0x10000001>;
};

ufs@2a2d0000 {
compatible = "rockchip,rk3576-ufs";
reg = <0x00 0x2a2d0000 0x00 0x10000 0x00 0x2b040000 0x00 0x10000 0x00 0x2601f000 0x00 0x1000 0x00 0x2603c000 0x00 0x1000 0x00 0x2a2e0000 0x00 0x10000>;
reg-names = "hci\0mphy\0hci_grf\0mphy_grf\0hci_apb";
clocks = <0x10000001 0x150 0x10000001 0x14a 0x10000001 0x1df 0x10000001 0x1e1>;
interrupts = <0x00 0x169 0x04>;
power-domains = <0x1000003f 0x07>;
resets = <0x10000001 0x2fa>;
reset-names = "rst";
status = "okay";
u-boot,dm-spl;
};

mmc@2a310000 {
compatible = "rockchip,rk3576-dw-mshc\0rockchip,rk3288-dw-mshc";
reg = <0x00 0x2a310000 0x00 0x4000>;
interrupts = <0x00 0xfb 0x04>;
max-frequency = <0xbebc200>;
clocks = <0x10000001 0x130 0x10000001 0x12f>;
fifo-depth = <0x100>;
resets = <0x10000001 0x2b2>;
reset-names = "reset";
rockchip,use-v2-tuning;
status = "okay";
bus-width = <0x04>;
u-boot,dm-spl;
pwr-en-gpios = <0x100000b3 0x0e 0x00>;
};

mmc@2a330000 {
compatible = "rockchip,rk3576-dwcmshc\0rockchip,rk3588-dwcmshc";
reg = <0x00 0x2a330000 0x00 0x10000>;
interrupts = <0x00 0xfd 0x04>;
clocks = <0x10000001 0xff 0x10000001 0x100 0x10000001 0x101 0x10000001 0x102 0x10000001 0x103>;
resets = <0x10000001 0x218 0x10000001 0x219 0x10000001 0x21a 0x10000001 0x21b 0x10000001 0x21c>;
reset-names = "core\0bus\0axi\0block\0timer";
max-frequency = <0xbebc200>;
status = "okay";
bus-width = <0x08>;
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
};

spi@2a340000 {
compatible = "rockchip,sfc";
reg = <0x00 0x2a340000 0x00 0x4000>;
interrupts = <0x00 0xfe 0x04>;
clocks = <0x10000001 0xfd 0x10000001 0xfe>;
#address-cells = <0x01>;
#size-cells = <0x00>;
status = "okay";
u-boot,dm-spl;

flash@0 {
u-boot,dm-spl;
compatible = "spi-nand";
reg = <0x00>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
spi-max-frequency = <0x4c4b400>;
};

flash@1 {
u-boot,dm-spl;
compatible = "jedec,spi-nor";
label = "sfc_nor";
reg = <0x00>;
spi-tx-bus-width = <0x01>;
spi-rx-bus-width = <0x04>;
spi-max-frequency = <0x4c4b400>;
};
};

crypto@2a400000 {
compatible = "rockchip,crypto-v4";
reg = <0x00 0x2a400000 0x00 0x2000>;
interrupts = <0x00 0xb1 0x04>;
clocks = <0x10000001 0x227 0x10000001 0x222 0x10000001 0x228>;
resets = <0x10000001 0x40003>;
reset-names = "crypto-rst";
status = "okay";
u-boot,dm-spl;
};

rng@2a410000 {
compatible = "rockchip,rkrng";
reg = <0x00 0x2a410000 0x00 0x200>;
interrupts = <0x00 0xb5 0x04>;
clocks = <0x10000001 0x223>;
resets = <0x10000001 0x40004>;
reset-names = "reset";
status = "okay";
u-boot,dm-pre-reloc;
};

decompress@2ac30000 {
compatible = "rockchip,hw-decompress";
reg = <0x00 0x2ac30000 0x00 0x1000>;
interrupts = <0x00 0x26 0x04>;
clocks = <0x10000001 0xbf 0x10000001 0xc1 0x10000001 0xc0>;
resets = <0x10000001 0x129>;
reset-names = "dresetn";
status = "okay";
u-boot,dm-spl;
};

serial@2ad40000 {
compatible = "rockchip,rk3576-uart\0snps,dw-apb-uart";
reg = <0x00 0x2ad40000 0x00 0x100>;
interrupts = <0x00 0x4c 0x04>;
clocks = <0x10000001 0x92 0x10000001 0x87>;
reg-shift = <0x02>;
reg-io-width = <0x04>;
dmas = <0x1000004a 0x06 0x1000004a 0x07>;
status = "okay";
u-boot,dm-spl;
};

adc@2ae00000 {
compatible = "rockchip,rk3576-saradc\0rockchip,rk3588-saradc";
reg = <0x00 0x2ae00000 0x00 0x10000>;
interrupts = <0x00 0x7c 0x04>;
#io-channel-cells = <0x01>;
clocks = <0x10000001 0x84 0x10000001 0x83>;
resets = <0x10000001 0xd6>;
reset-names = "saradc-apb";
status = "okay";
u-boot,dm-pre-reloc;
phandle = <0x10000125>;
};

phy@2b010000 {
compatible = "rockchip,rk3576-usbdp-phy";
reg = <0x00 0x2b010000 0x00 0x10000>;
rockchip,u2phy-grf = <0x10000118>;
rockchip,usb-grf = <0x10000044>;
rockchip,usbdpphy-grf = <0x10000119>;
rockchip,vo-grf = <0x100000a0>;
clocks = <0x10000001 0x21b 0x10000001 0x1dd 0x10000001 0x1db>;
resets = <0x10000001 0x8000f 0x10000001 0x80010 0x10000001 0x80011 0x10000001 0x80012 0x10000001 0x8000c>;
reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb";
status = "okay";
u-boot,dm-pre-reloc;

u3-port {
#phy-cells = <0x00>;
status = "okay";
u-boot,dm-pre-reloc;
phandle = <0x10000041>;
};
};

scmi-shmem@4010f000 {
compatible = "arm,scmi-shmem";
reg = <0x00 0x4010f000 0x00 0x100>;
u-boot,dm-pre-reloc;
phandle = <0x1000001c>;
};

pinctrl {
compatible = "rockchip,rk3576-pinctrl";
rockchip,grf = <0x10000058>;
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
u-boot,dm-spl;
phandle = <0x1000011f>;

gpio@27320000 {
compatible = "rockchip,gpio-bank";
reg = <0x00 0x27320000 0x00 0x200>;
interrupts = <0x00 0x99 0x04>;
clocks = <0x10000001 0x206 0x10000001 0x207>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-ranges = <0x1000011f 0x00 0x00 0x20>;
interrupt-controller;
#interrupt-cells = <0x02>;
u-boot,dm-spl;
status = "okay";
phandle = <0x100000b3>;
};

gpio@2ae10000 {
compatible = "rockchip,gpio-bank";
reg = <0x00 0x2ae10000 0x00 0x200>;
interrupts = <0x00 0x9d 0x04>;
clocks = <0x10000001 0xb7 0x10000001 0xb8>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-ranges = <0x1000011f 0x00 0x20 0x20>;
interrupt-controller;
#interrupt-cells = <0x02>;
u-boot,dm-pre-reloc;
status = "okay";
};

gpio@2ae20000 {
compatible = "rockchip,gpio-bank";
reg = <0x00 0x2ae20000 0x00 0x200>;
interrupts = <0x00 0xa1 0x04>;
clocks = <0x10000001 0xb9 0x10000001 0xba>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-ranges = <0x1000011f 0x00 0x40 0x20>;
interrupt-controller;
#interrupt-cells = <0x02>;
u-boot,dm-pre-reloc;
status = "okay";
};

gpio@2ae30000 {
compatible = "rockchip,gpio-bank";
reg = <0x00 0x2ae30000 0x00 0x200>;
interrupts = <0x00 0xa5 0x04>;
clocks = <0x10000001 0xbb 0x10000001 0xbc>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-ranges = <0x1000011f 0x00 0x60 0x20>;
interrupt-controller;
#interrupt-cells = <0x02>;
u-boot,dm-pre-reloc;
status = "okay";
};

gpio@2ae40000 {
compatible = "rockchip,gpio-bank";
reg = <0x00 0x2ae40000 0x00 0x200>;
interrupts = <0x00 0xa9 0x04>;
clocks = <0x10000001 0xbd 0x10000001 0xbe>;
gpio-controller;
#gpio-cells = <0x02>;
gpio-ranges = <0x1000011f 0x00 0x80 0x20>;
interrupt-controller;
#interrupt-cells = <0x02>;
u-boot,dm-pre-reloc;
status = "okay";
};

pcfg-pull-up {
bias-pull-up;
u-boot,dm-spl;
phandle = <0x10000124>;
};

pcfg-pull-none {
bias-disable;
u-boot,dm-spl;
phandle = <0x10000120>;
};

pcfg-pull-up-drv-level-2 {
bias-pull-up;
drive-strength = <0x02>;
u-boot,dm-spl;
phandle = <0x10000121>;
};

sdmmc0 {
u-boot,dm-spl;

sdmmc0-bus4 {
rockchip,pins = <0x02 0x00 0x01 0x10000123 0x02 0x01 0x01 0x10000123 0x02 0x02 0x01 0x10000123 0x02 0x03 0x01 0x10000123>;
u-boot,dm-spl;
phandle = <0x100000b1>;
};

sdmmc0-clk {
rockchip,pins = <0x02 0x05 0x01 0x10000123>;
u-boot,dm-spl;
phandle = <0x100000ae>;
};

sdmmc0-cmd {
rockchip,pins = <0x02 0x04 0x01 0x10000123>;
u-boot,dm-spl;
phandle = <0x100000af>;
};

sdmmc0-det {
rockchip,pins = <0x00 0x07 0x01 0x10000124>;
u-boot,dm-spl;
phandle = <0x100000b0>;
};
};
};

chosen {
stdout-path = "/serial@2ad40000";
u-boot,spl-boot-order = "/mmc@2a310000\0/spi@2a340000/flash@0\0/spi@2a340000/flash@1\0same-as-spl";
};

secure-otp@2a480000 {
u-boot,dm-spl;
compatible = "rockchip,rk3576-secure-otp";
reg = <0x00 0x2a480000 0x00 0x10000>;
};

adc-keys {
compatible = "adc-keys";
io-channels = <0x10000125 0x01>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <0x1b7740>;
u-boot,dm-pre-reloc;
status = "okay";

volumeup-key {
u-boot,dm-pre-reloc;
linux,code = <0x73>;
label = "volume up";
press-threshold-microvolt = <0x6d6>;
};
};
};

thats all you need to compile a new DTS file for linux
this device uses fragmented DTB file with overlay
every DTB overlay the first

1.dts 2.dts 3.dts 4.dts 5.dts

Edited August 27 by Hqnicolas

cmuki · August 27

Hmm, I think I didn't do the backup correctly, because the baseparamter file is full of "cc" when opening it in Hex editor. Also the backup that I create is 200 MB and the one from mvpwar is 64 GB.

For additional info - VID and PID:

DevNo=1 Vid=0x2207,Pid=0x350e,LocationID=303 Loader

Hqnicolas · August 27

Lets Start with an example:

Leds:

On Android DTS we have:

Quote

   leds {
       compatible = "gpio-leds";
       status = "okay";

       power-green {
           gpios = <0x35 0x1b 0x01>;
           linux,default-trigger = "none";
           default-state = "off";
       };

       power-red {
           gpios = <0x35 0x1c 0x00>; //////// 0x35 is a phandle for gpio@fdd60000 and 0x1c is the pin 0x00 is State
           linux,default-trigger = "none";
           default-state = "off";
       };
   };

       gpio@fdd60000 {
           compatible = "rockchip,gpio-bank";
           reg = <0x00 0xfdd60000 0x00 0x100>;
           interrupts = <0x00 0x21 0x04>;
           clocks = <0x31 0x2e 0x31 0x0c>;
           gpio-controller;
           #gpio-cells = <0x02>;
           gpio-ranges = <0x11b 0x00 0x00 0x20>;
           interrupt-controller;
           #interrupt-cells = <0x02>;
           phandle = <0x35>; ////// 0x35 is the definition for phandle of  gpio@fdd60000
       };

aliases {
gpio0 = "/pinctrl/gpio@fdd60000"; ///////// gpio@fdd60000 is the address for   gpio0

}

and on Linux Rockchip:

Quote



   gpio0: gpio@fdd60000 {
           compatible = "rockchip,gpio-bank";
           reg = <0x0 0xfdd60000 0x0 0x100>;
           interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
           clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
           gpio-controller;
           gpio-ranges = <&pinctrl 0 0 32>;
           #gpio-cells = <2>;
           interrupt-controller;
           #interrupt-cells = <2>;
       };

The following example could be used to describe GPIO pins used as device enable
and bit-banged data signals:

   gpio1: gpio1 {
       gpio-controller;
       #gpio-cells = <2>;
   };
   [...]

   data-gpios = <&gpio1 12 0>,
       <&gpio1 13 0>,
       <&gpio1 14 0>,
       <&gpio1 15 0>;

In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
a local offset to the GPIO line and the second cell represent consumer flags,
such as if the consumer desire the line to be active low (inverted) or open
drain. This is the recommended practice.

#define RK_PA0 0
#define RK_PA1 1
#define RK_PA2 2
#define RK_PA3 3
#define RK_PA4 4
#define RK_PA5 5
#define RK_PA6 6
#define RK_PA7 7
#define RK_PB0 8
#define RK_PB1 9
#define RK_PB2 10
#define RK_PB3 11
#define RK_PB4 12
#define RK_PB5 13
#define RK_PB6 14
#define RK_PB7 15

#define RK_PC0 16
#define RK_PC1 17
#define RK_PC2 18
#define RK_PC3 19
#define RK_PC4 20
#define RK_PC5 21
#define RK_PC6 22
#define RK_PC7 23

#define RK_PD0 24
#define RK_PD1 25
#define RK_PD2 26
#define RK_PD3 27
#define RK_PD4 28
#define RK_PD5 29
#define RK_PD6 30
#define RK_PD7 31

So we can do an Linux compatible with h96 M9 rk3576:

Quote

   leds {
       compatible = "gpio-leds";
       status = "okay";

       power-green {
           gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
           linux,default-trigger = "none";
           default-state = "off";
       };

       power-red {
           gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
           linux,default-trigger = "none";
           default-state = "off";
       };
   };

   gpio0: gpio@fdd60000 {
           compatible = "rockchip,gpio-bank";
           reg = <0x0 0xfdd60000 0x0 0x100>;
           interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
           clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
           gpio-controller;
           gpio-ranges = <&pinctrl 0 0 32>;
           #gpio-cells = <2>;
           interrupt-controller;
           #interrupt-cells = <2>;
       };

Hqnicolas · August 27

use armson siege5 as rk3576 base config

https://wiki.t-firefly.com/en/ROC-RK3576-PC/linux_dts_manual.html

some tools that can help you

you can use this firmware as base to build your linux dts

wifi drivers that can be usefull for rk3576

flashing tools for linux windows and macOS

Edited August 27 by Hqnicolas

Hqnicolas · August 27

https://github.com/Joshua-Riek/linux-rockchip/blob/noble/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-linux.dts

https://github.com/Joshua-Riek/linux-rockchip/blob/noble/arch/arm64/boot/dts/rockchip/rk3576-linux.dtsi
https://github.com/Joshua-Riek/linux-rockchip/blob/noble/arch/arm64/boot/dts/rockchip/rk3576-evb1.dtsi

https://github.com/Joshua-Riek/linux-rockchip/blob/noble/arch/arm64/boot/dts/rockchip/rk3576-linux.dtsi

Overlay this files to create an dts

Edited August 27 by Hqnicolas

cmuki · August 27

@Hqnicolas, thanks for all the resources, I'm going through them, but just hitting potholes along the way.

I managed to grab the output for fdt from u-boot, would that be helpful here? I tried several more things, but to no avail.

screenlog.txt

Hqnicolas · August 27

5 hours ago, cmuki said:

I managed to grab the output for fdt from u-boot,

You will use the same u-boot from roc-rk3576-pc

https://gitlab.com/firefly-linux/manifests/-/tree/master/rk3576?ref_type=heads

https://gitlab.com/firefly-linux/manifests/-/blob/master/rk3576_linux_bsp_next.xml?ref_type=heads

Looking through entire web to find these files:

Rk3576-firefly-demo.dtsi

roc-rk3566-pc.dts

And

EC-R3576PC FD

Nothing found,

looks like somebody make the pooh bear hangry

Edited August 27 by Hqnicolas

cmuki · August 28

Hey!

Firstly, I wanted to create a backup for the box so that @El308 can unbrick it and if I screwed something up, I wanted to create a backup.

I found the Miniloader on Mekotronics' website, uplodaded it below.

Currently doing a full backup with RKDevTool, but will get back to you to ask if I did something incorrectly.

RK3576_MiniLoaderAll.bin

Hqnicolas · August 28

@cmuki
Please be carefull
Mekotronics R57 uses LPDDR5 and UFS flash

this loader has different settings than your box
you need to backup the mini loader from your box.

ask for the original firmware on the factory:
+86 17840901693

+86 13242412680

vivian@h96tvbox.com

sales10@h96tvbox.com

you can extract it from the @mvpwar backup with imgrepackerRK

Edited August 28 by Hqnicolas

Vincenzo Dentamaro · August 28

following your conversation. I need to know if it is possible to install a Ubuntu or debian on these machines.

cmuki · August 28

@Vincenzo Dentamaro work in progress!

@Hqnicolas - Why don't we need the dtb from the box? I finally managed to get it from Android through adb. The backup with the loader from Mekotronics was also successful and I can still boot in Android, so I think it should be usable.

Can I boot from USB or should I nuke the eMMC and try to flash a custom compiled image (that said, I'll have to check out if I can do it myself or I would need your help)?

fdisk -l returns this for the exported image:

box.dtb box.dts

Hqnicolas · August 28

12 minutes ago, cmuki said:

Can I boot from USB

You will need a custom uboot to make it
I don't know if the factory make the android bootloader USB friendly

13 minutes ago, cmuki said:

or should I nuke the eMMC

That's why we are here

13 minutes ago, cmuki said:

a custom compiled image (that said, I'll have to check out if I can do it myself or I would need your help)

that's why you need a custom DTS,
Android DTB = Kernel 4.19 ≠ Mainline DTB = Kernel 6+

I want to train an LLM to do this DTS translation
it's too boring
You will need to create files like this
using armson siege5 as rk3576 base config

and this dts overlays as a start point

cmuki · August 29

Success!

Yesterday late in the evening I managed to boot from usb. What I did was burn Armbian-unofficial_24.11.0-trunk_Armsom-sige5_noble_vendor_6.1.75_minimal to a USB drive, replace the dtb with the one from Android and boot with the commands "usb start" and "run bootcmd_usb0".

I couldn't get ROC's image nor Multiboot (with the replaced dtb) to boot this way.

image.png.51331b30dc4bb1710caeba54ce2717bc.png

EDIT: Installed it to eMMC and ran sbc-bench - results https://0x0.st/Xvsr.bin

When I plug in the HDMI, it crashes Will have to investigate.
dwhdmi-rockchip 27da0000.hdmi: i2c read err!

Edited August 29 by cmuki

Hqnicolas · August 29

4 hours ago, cmuki said:

When I plug in the HDMI, it crashes Will have to investigate.

translate it from android to linux format:

change the armson sige5 vendor DTS for the following:

Quote

   vop@27900000 {
       compatible = "rockchip,rk3576-vop-lit";
       reg = <0x00 0x27900000 0x00 0x200>;
       reg-names = "regs";
       interrupts = <0x00 0x14e 0x04>;
       clocks = <0x02 0x163 0x02 0x164 0x02 0x162>;
       clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
       power-domains = <0x03 0x0d 0x03 0x10>;
       power-domain-names = "pd0\0pd1";
       rockchip,grf = <0xad>;
       rockchip,vo0-grf = <0xae>;
       status = "disabled";
       phandle = <0x222>;

       port {
           #address-cells = <0x01>;
           #size-cells = <0x00>;
           phandle = <0x28>;

           endpoint@0 {
               reg = <0x00>;
               remote-endpoint = <0xaf>;
               phandle = <0x69>;
           };

           endpoint@1 {
               reg = <0x01>;
               remote-endpoint = <0xb0>;
               phandle = <0xd8>;
           };

           endpoint@2 {
               reg = <0x02>;
               remote-endpoint = <0xb1>;
               phandle = <0xe8>;
           };

           endpoint@3 {
               reg = <0x03>;
               remote-endpoint = <0xb2>;
               phandle = <0xe4>;
           };
       };
   };

Quote

   vop-opp-table {
       compatible = "operating-points-v2";
       nvmem-cells = <0x35>;
       nvmem-cell-names = "leakage";
       rockchip,init-freq = <0xab630>;
       rockchip,leakage-voltage-sel = <0x01 0x10 0x00 0x11 0xfe 0x01>;
       phandle = <0xbe>;

       opp-500000000 {
           opp-hz = <0x00 0x1dcd6500>;
           opp-microvolt = <0xaae60 0xaae60 0xc3500>;
       };

       opp-594000000 {
           opp-hz = <0x00 0x2367b880>;
           opp-microvolt = <0xb71b0 0xb71b0 0xc3500>;
           opp-microvolt-L1 = <0xb1008 0xb1008 0xc3500>;
       };

       opp-702000000 {
           opp-hz = <0x00 0x29d7ab80>;
           opp-microvolt = <0xb71b0 0xb71b0 0xc3500>;
           opp-microvolt-L1 = <0xb1008 0xb1008 0xc3500>;
       };
   };

Quote

   hdmi@27da0000 {
       compatible = "rockchip,rk3576-dw-hdmi";
       reg = <0x00 0x27da0000 0x00 0x10000 0x00 0x27db0000 0x00 0x10000>;
       interrupts = <0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x16f 0x04>;
       clocks = <0x02 0x19d 0x02 0x1de 0x02 0x19e 0x02 0x19f 0x02 0x1a7 0x02 0x18e 0x02 0x190 0x02 0x191 0x02 0x164 0x02 0x194 0x29>;
       clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_ebc\0hclk_vo1\0link_clk";
       resets = <0x02 0x409 0x02 0x8001d>;
       reset-names = "ref\0hdp";
       power-domains = <0x03 0x10>;
       pinctrl-names = "default";
       pinctrl-0 = <0xde 0xdf 0xe0>;
       reg-io-width = <0x04>;
       rockchip,grf = <0xad>;
       rockchip,vo0_grf = <0xae>;
       phys = <0x29>;
       phy-names = "hdmi";
       #sound-dai-cells = <0x00>;
       status = "okay";
       enable-gpios = <0xe1 0x08 0x00>;
       rockchip,sda-falling-delay-ns = <0x168>;
       phandle = <0x1a1>;

       ports {
           #address-cells = <0x01>;
           #size-cells = <0x00>;

           port@0 {
               reg = <0x00>;
               #address-cells = <0x01>;
               #size-cells = <0x00>;
               phandle = <0x238>;

               endpoint@0 {
                   reg = <0x00>;
                   remote-endpoint = <0x2e>;
                   status = "okay";
                   phandle = <0xc3>;
               };

               endpoint@1 {
                   reg = <0x01>;
                   remote-endpoint = <0xe2>;
                   status = "disabled";
                   phandle = <0xca>;
               };

               endpoint@2 {
                   reg = <0x02>;
                   remote-endpoint = <0xe3>;
                   status = "disabled";
                   phandle = <0xd1>;
               };

               endpoint@3 {
                   reg = <0x03>;
                   remote-endpoint = <0xe4>;
                   status = "disabled";
                   phandle = <0xb2>;
               };
           };
       };
   };

Quote

   edp@27dc0000 {
       compatible = "rockchip,rk3576-edp";
       reg = <0x00 0x27dc0000 0x00 0x1000>;
       interrupts = <0x00 0x16d 0x04>;
       clocks = <0x02 0x1a1 0x02 0x1a0 0x02 0x1a2 0x02 0x194>;
       clock-names = "dp\0pclk\0spdif\0hclk";
       resets = <0x02 0x40e 0x02 0x40d>;
       reset-names = "dp\0apb";
       phys = <0xe5>;
       phy-names = "dp";
       power-domains = <0x03 0x10>;
       rockchip,grf = <0xae>;
       status = "disabled";
       phandle = <0x239>;

       ports {
           #address-cells = <0x01>;
           #size-cells = <0x00>;

           port@0 {
               reg = <0x00>;
               #address-cells = <0x01>;
               #size-cells = <0x00>;

               endpoint@0 {
                   reg = <0x00>;
                   remote-endpoint = <0xe6>;
                   status = "disabled";
                   phandle = <0xc2>;
               };

               endpoint@1 {
                   reg = <0x01>;
                   remote-endpoint = <0x2d>;
                   status = "disabled";
                   phandle = <0xc9>;
               };

               endpoint@2 {
                   reg = <0x02>;
                   remote-endpoint = <0xe7>;
                   status = "disabled";
                   phandle = <0xd0>;
               };

               endpoint@3 {
                   reg = <0x03>;
                   remote-endpoint = <0xe8>;
                   status = "disabled";
                   phandle = <0xb1>;
               };
           };
       };
   };

Quote

       hdmi_tx {

           hdmi_txm0-pins {
               rockchip,pins = <0x04 0x10 0x09 0x194 0x04 0x11 0x09 0x194>;
               phandle = <0xde>;
           };

           hdmi_txm1-pins {
               rockchip,pins = <0x00 0x13 0x09 0x194 0x00 0x0e 0x09 0x194>;
               phandle = <0x3ae>;
           };

           hdmi-tx-scl {
               rockchip,pins = <0x04 0x12 0x09 0x194>;
               phandle = <0xdf>;
           };

           hdmi-tx-sda {
               rockchip,pins = <0x04 0x13 0x09 0x194>;
               phandle = <0xe0>;
           };
       };

Edited August 29 by Hqnicolas

cmuki · August 29

Hey, @Hqnicolas!

When comparing the two files (my dts and the Armsom), maybe the bigest one is this one below:

Also - the problem seems to be when plugging and unplugging the hdmi cable - with it in the box it boots and I can see an output on my display.

And a question - since the box was running (allegedly) Android 14, which is using Kernel 6.1, would the difference between the DTBs be that big (Android DTB = Kernel 4.19 ≠ Mainline DTB = Kernel 6+ as you said)?

Edited August 29 by cmuki

Hqnicolas · August 29

24 minutes ago, cmuki said:

would the difference between the DTBs be that big

I think you can use the vendor kernel 6.1 with Android 14 DTS

the diffefence only happend for mainline linux

Can you share some benchmarks for chromium for video decoding?
also install glmark2-es2-wayland and run it

try to compile the Joshua 6.1

it uses github CI/CD method to compile online
here is my example how i did it: to enable rk3566 h96

you can edit this file to make it work on your box

Edited August 29 by Hqnicolas

Hqnicolas · August 29

6 hours ago, cmuki said:

Success!

congratulations!
bring the compile commands to the public for other users to reproduce

cmuki · August 29

How to get DB and boot into Armbian:

1. Connected to the TV box via ethernet and got the DTB through ADB - https://github.com/warpme/minimyth2/wiki/Getting-device-tree-from-TVbox-vendor-Android (couldn't get usb to work with ADB).

2. Cloned https://github.com/armbian/build, ran ./compile.sh and went with all default Options - Do not change the kernel configuration -> Show CSC/WIP/EOS/TVB -> armsom-sige5 -> vendor -> noble -> Image with console interface (server) -> Minimal image with console interface.

3. Flashed it on a USB Drive with USB Imager.

4. (On Linux) replaced the dtb file rk3576-armsom-sige5 with the Android dtb (I just did it the lazy way and renamed it the same way - rk3576-armsom-sige5).

5. Connecting to the box with UART, I was able to go to the U-boot menu this way:
- while booting, spam ctrl+c and you'll see a faint console:~/ line between all the bootlog lines. If you don't see it, you need to toggle the power on the box;
- typing "su" and enter - that way you gain root;
- type "reboot", enter and spam ctrl+c again to interrupt the boot process.

6. Plugging in the USB Drive (and the ethernet cable at this point) in the USB 3 port, you should run "usb start" and confirm that 1 Storage device is active (if not, you can unplug and plug the drive and run "usb reset" until it shows up) and run "run bootcmd_usb0".

7. Still using UART, you can set a root password and create an account through screen and ssh in the box after that.

Problems:

I didn't manage to get a desktop environment going - I only saw the Ubuntu 24.04 loading screen and nothing after that. After installing something (I think related to the DE or GPU drivers) I couldn't reboot cleanly (after unbricking and reisntalling Armbian now rebooting works as expected).

After reinstalling, the MAC Address of the eth0 is different.

Unbrick:

I managed to brick it after flying too close to the Sun and changing the kernel from armbian-config - the device was trying to boot the new kernel, but was getting stuck after ethernet and iommu. The worse thing was that the USB was not working during in the u-boot menu, meaning I couldn't boot from the USB drive. To unbrick it, from the u-boot menu I put the device in Loader mode by running "rockusb (I think it was rockusb 0 mmc 0 - there are instructions)" and reflashing the MY CUSTOM IMAGE with the correct DTB (from the Mega folder) with "rkdeveloptool write 0 rockchip.img" (there are probably better ways to do such an image, but I used ddrescue to create an img of the USB Drive). Be advised that I couldn't put the device is Maskrom mode with rkdeveloptool.

Edited August 29 by cmuki

cmuki · August 31

Hey, it's me again!

Today I was playing around an unhealthy amount of time with the box - most of it went to trying to compile different images.

Sadly, I was unsuccessful with compiling (and it took most of my time today) ubuntu-rockchip even though it has the ArmSoM Sige 5 image - the board didn't want to boot.

I tried later compiling a full image with armbian/build, but I saw really late that only building from main is supported - D'OH!

That's why I downloaded the Gnome image from here, changed the DTBs once again and was able to boot with a Desktop environment. Video playback (not HW accelerated) works, but fullscreen 1080p youtube video stutters. There is also sound from the HDMI!

But, once again - once rebooted, the box doesn't reboot and hangs and I can't plug and unplug the HDMI for the same reason.

I'm not sure what else I can do at the moment except provide some logs and files.

https://paste.armbian.com/eqodoposub

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Efforts to develop firmware for H96 MAX M9 RK3576 TV Box 8G/128G

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