usual user

That's the advantage when you use a device that doesn't have a PMIC and only goes into deep sleep mode for Off Mode. This is only supported by the proprietary, closed-source manufacturer firmware, for which of course no publicly available API description exists. Mainline support will therefore most likely not become available. So it basically just leaves reverse engineering and an out-of-tree implementation. Good luck.

Your previous post reminded me that the board supplier changed the BOM of the ODROID-N2+ by using a different SPI flash vendor. He hacked the support for it into his legacy firmware build without making any further note about it. It took some effort of reverse engineering to figure that out. Mainline hasn't picked up this additional driver activation to this day, but I still keep it in my builds anyway. In my latest build for the ODROID-HC4, I also included this driver to see if they might have gone about it in the same way. But your confirmation shows that this is probably not the case. Since I don't have an ODROId-HC4 with the behavior you described on hand, I can't analyze any further what the cause of it is. These days, I also mostly avoid devices with Amlogic SoCs because of their strict closed-source policy and lack of mainline support. And the board manufacturer isn't much more helpful on this point either. Devices powered by Rockchip are much more appealing objects. So you have to help yourself if you want to find a solution.

Just a shot in the dark, does this build work better?

As long as you do not provide proper serial console logs, no one can tell what is going on. I can't help you in this situation any further, and you have to find a solution for yourself.

Nope, my build is based on current mainline and even build on target (aarch64). I.e. no cross-compiling involved. Oh, by the way, in my build bootstd scans any attached storage for a valid bootflow and uses the first found one. The used hardware interface dosen't matter and even network is valid.

Usually I do that via the U-Boot console, since I build my firmware with SPI command support for devices with SPI flash. With an added convenience command, it's just a "==> run mmc-fw-to-sf" to transfer firmware currently running from microSD. So everything is self-contained, no external components involved.

You made me curious, so I rebooted for the first time after my previous report to activate my current versions. I' m now at kernel 7.0.0-0.rc1.15.fc45.aarch64 and U-Boot 2026.07-rc1 (May 22 2026 - 00:00:00 +0000). No regressions can be observed and it works as fast as before.

The first iteration of mainline kernel driver support has just been posted. So a kernel build with this patch set applied should give a playground for initial experiments.

It happened a few days ago that I rebuilt my complete firmware package to try something with another device. An HC4 firmware binary also automatically falls out in this process. If you like, you can put it on a microSD card (dd bs=512 seek=1 conv=notrunc,fsync if=u-boot-meson.bin of=/dev/${entire-device-to-be-used}), place the prepared microSD card in your HC4 and start it with the boot button pressed. Check whether it meets your expectations, and if all tests are successful, you can transfer it to the SPI flash.

The one from my firmware build.

Since I haven't restarted the M1 for some time, I am currently still at: # uptime 12:56:23 up 115 days, 1:51, 5 users, load average: 1.76, 1.26, 0.92 # uname -a Linux micro-015 6.18.0-65.fc44.aarch64 #1 SMP PREEMPT_DYNAMIC Sun Dec 7 20:40:45 CET 2025 aarch64 GNU/Linux I still get: So nothing to complain about.

According to the circuit diagram, the reset button is connected to the hardware reset lines, so nothing can prevent forcing the reset state.

At least that explains the result of the nvme scan command. Now it remains to find out why this is the case, but since improvements are still pending for PCIe support even in the mainline kernel, the question arises whether all of this has already been migrated into the firmware.

u-boot-rockchip-spi.bin is a firmware. Out of pure curiosity, what is the result of 'pci enum' on the firmware console?

IMHO, OP wants to boot OS from NVME while the firmware is stored in the SPI flash, but he is using firmware in which the necessary support is not enabled.