https://forum.armbian.com/topic/12227-rockpi-4-spi/RockPI 4 SPI

[Marko Buršič]

I have tried the following:

------------------------------------------------------------------------
CONVERT dtb to dts
------------------------------------------------------------------------
dtc -I dtb -O dts /boot/dtb-4.4.192-rockchip64/rockchip/rk3399-rockpi4b.dtb -o /boot/dtb-4.4.192-rockchip64/rockchip/rk3399-rockpi4b.dts

------------------------------------------------------------------------
EDIT dts
------------------------------------------------------------------------
nano /boot/dtb-4.4.192-rockchip64/rockchip/rk3399-rockpi4b.dts

 

----------------------------------------------------------------------------------

uart4 enabled:

    serial@ff370000 {
        compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
        reg = < 0x00 0xff370000 0x00 0x100 >;
        clocks = < 0x31 0x06 0x31 0x22 >;
        clock-names = "baudclk\0apb_pclk";
        interrupts = < 0x00 0x66 0x04 0x00 >;
        reg-shift = < 0x02 >;
        reg-io-width = < 0x04 >;
        pinctrl-names = "default";
        pinctrl-0 = < 0x81 >;
        status = "okay";
        assigned-clocks = < 0x31 0x0c >;
        assigned-clock-parents = < 0x31 0x01 >;
        phandle = < 0x114 >;
    };

 

uart4 disable as it uses the same pins as SPI1:

    serial@ff370000 {
        compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
        reg = < 0x00 0xff370000 0x00 0x100 >;
        clocks = < 0x31 0x06 0x31 0x22 >;
        clock-names = "baudclk\0apb_pclk";
        interrupts = < 0x00 0x66 0x04 0x00 >;
        reg-shift = < 0x02 >;
        reg-io-width = < 0x04 >;
        pinctrl-names = "default";
        pinctrl-0 = < 0x81 >;
        status = "disable";
        assigned-clocks = < 0x31 0x0c >;
        assigned-clock-parents = < 0x31 0x01 >;
        phandle = < 0x114 >;
    };

 

 

spi1 is disabled:

    spi@ff1d0000 {
        compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
        reg = < 0x00 0xff1d0000 0x00 0x1000 >;
        clocks = < 0x08 0x48 0x08 0x15c >;
        clock-names = "spiclk\0apb_pclk";
        dmas = < 0x41 0x0c 0x41 0x0d >;
        dma-names = "tx\0rx";
        interrupts = < 0x00 0x35 0x04 0x00 >;
        pinctrl-names = "default";
        pinctrl-0 = < 0x4d 0x4e 0x4f 0x50 >;
        #address-cells = < 0x01 >;
        #size-cells = < 0x00 >;
        status = "disabled";
        phandle = < 0x106 >;
    };

SP1 enable:

    spi@ff1d0000 {
        compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
        reg = < 0x00 0xff1d0000 0x00 0x1000 >;
        clocks = < 0x08 0x48 0x08 0x15c >;
        clock-names = "spiclk\0apb_pclk";
        dmas = < 0x41 0x0c 0x41 0x0d >;
        dma-names = "tx\0rx";
        interrupts = < 0x00 0x35 0x04 0x00 >;
        pinctrl-names = "default";
        pinctrl-0 = < 0x4d 0x4e 0x4f 0x50 >;
        #address-cells = < 0x01 >;
        #size-cells = < 0x00 >;
        status = "okay";
        phandle = < 0x106 >;
    };
    
save CTRL-O
exit: CTRL-X

------------------------------------------------------------------------
CONVERT (BACK) dts to dtb
------------------------------------------------------------------------            
dtc -I dts -O dtb /boot/dtb-4.4.192-rockchip64/rockchip/rk3399-rockpi4b.dts -o /boot/dtb-4.4.192-rockchip64/rockchip/rk3399-rockpi4b.dtb

reboot

 

And it never wakes up again! Is there any way to make the SPI working on this board??

 

[Marko Buršič]

OK. I have downloaded Armbian buster server 5.3.11. It has overlays scripts for this, but I  don't know hot to use them.  Is there any example if I want to enable SPI1 and have two CS : predifined one for channel 0 and channel 1 aka cs-gpios?

 

[martinayotte]

24 minutes ago, Marko Buršič said:

Is there any example if I want to enable SPI1 and have two CS : predifined one for channel 0 and channel 1 aka cs-gpios?

Dual CS isn't yet supported. You can only use channel 0 for the moment, except if you manually handle gpios yourself.

[Marko Buršič]

Can you give an advice how to properly configure armbianEnv.txt?

 

From this post: 

 

 

You have written:

Quote

 

overlays=spi-spidev uart4

param_spidev_spi_bus=2

 

 

OK, so if I want i2c7 and spi1, this have to be:

overlays=spi-spidev i2c7

param spidev spi bus=1

 

Is this correct? However I don't understand if for example the board could have more spi enbled at the same time, what would the configuration look like?

[martinayotte]

13 minutes ago, Marko Buršič said:

overlays=spi-spidev i2c7

param_spidev_spi_bus=1

 

Is this correct?

Yes, except the typo of missing underscores, it is correct as long as you don't have SPINOR Flash soldered on bottom side of the board, since it is using CS0.

13 minutes ago, Marko Buršič said:

However I don't understand if for example the board could have more spi enbled at the same time, what would the configuration look like?

For multiple SPIs, you need to write a custom overlay yourself. For spi-add-cs1, we will provide it some days in the futur, it only available for AllWinners for now, not for Rockchip or Meson.

[Marko Buršič]

OK. Have tried:

verbosity=1
overlay_prefix=rockchip
rootdev=UUID=a6a7d2a3-adf5-4eeb-8d46-077de81311c5
rootfstype=ext4
overlays=spi-spidev i2c7
param_spidev_spi_bus=1
usbstoragequirks=0x2537:0x1066:u,0x2537:0x1068:u
 

the usbstoragequirks was added automatically.

I got /dev/SPI1.0 and /dev/i2c-7 The I2C works, as I can detect the RTC connected, don't know if SPI is working, but at least now is added as device.

[Marko Buršič]

2 minutes ago, martinayotte said:

Yes, except the typo of missing underscores, it is correct as long as you don't have SPINOR Flash soldered on bottom side of the board, since it is using CS0.

For multiple SPIs, you need to write a custom overlay yourself. For spi-add-cs1, we will provide it some days in the futur, it only available for AllWinners for now, not for Rockchip or Meson.

Thank you. At this time I don't have SPI flash and the CE0 is free, that's why I was asking in case I would need cs-gpio for CE1. 

[martinayotte]

Just now, Marko Buršič said:

don't know if SPI is working, but at least now is added as device.

You can make minimal test byt using a loopback wire between MISO/MOSI, and run ./spidev_test from :

https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c

 

[martinayotte]

Just now, Marko Buršič said:

that's why I was asking in case I would need cs-gpio for CE1.

I'm not even sure if there is cs-gpio support in Rockchip, it is another thing-to-do on top of spi-add-cs1 overlay.

[Marko Buršič]

9 minutes ago, martinayotte said:

You can make minimal test byt using a loopback wire between MISO/MOSI, and run ./spidev_test from :

https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c

 

Sorry my ignorance, I am noob in building the code. Can you please give me an advice how should I proceed? 

[martinayotte]

18 minutes ago, Marko Buršič said:

I am noob in building the code.

Grab the file and compile it, then run it :

wget https://github.com/torvalds/linux/blob/master/tools/spi/spidev_test.c
gcc -o spidev_test spidev_test.c
./spidev_test -D /dev/spidev1.0

 

[Marko Buršič]

Thank you @martinayotte very much. Although your procedure doesn't work for me, because the downloaded file I got was a html doc file. But I have found this link:

 

https://github.com/rm-hull/spidev-test

 

It is described in step by step. I did patch the code with /dev/spi1.0 , compiled and run the test with jumper wires. This is the result, The loopback works great.

 

root@rockpi:/spidev-test# ./spidev_test -v
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....▒..................▒.
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....▒..................▒.
 

[martinayotte]

11 minutes ago, Marko Buršič said:

because the downloaded file I got was a html doc file.

Sorry, I forgot to use "raw" URL which is https://raw.githubusercontent.com/torvalds/linux/master/tools/spi/spidev_test.c

 

[p-i-u.de]

On 11/21/2019 at 9:49 PM, martinayotte said:

I'm not even sure if there is cs-gpio support in Rockchip, it is another thing-to-do on top of spi-add-cs1 overlay.

 

to what I understood it seems to be possible

 

https://patchwork.kernel.org/patch/9780471/

 

if you can tell me what work is to do maybe I can help

[martinayotte]

9 hours ago, p-i-u.de said:

if you can tell me what work is to do maybe I can help

I've seen this patch from 2017 last week, but I don't understand why it has not been approved and merged yet.

 

Maybe you can try to save it under userpatches/kernel/rockchip64-dev/ folder and try to build a DEV image ...

 

EDIT : Oh ! This patch is so old, it didn't applied at all. I had to revamp it and restart a new build. Will test later ...

 

EDIT2 : It is now seems to work, although I didn't check with a scope yet and/or a device ...

[martinayotte]

Here are the patch and the custom overlay :

 

rockpro-spidev1-1.dts rockpro-spidev1-1.dtbo add-csgpio-to-rockchip-spi.patch

[p-i-u.de]

On 12/6/2019 at 9:02 PM, martinayotte said:

Here are the patch and the custom overlay :

 

rockpro-spidev1-1.dts 576 B · 2 downloads rockpro-spidev1-1.dtbo 427 B · 0 downloads add-csgpio-to-rockchip-spi.patch 2.27 kB · 2 downloads

 

I have a device to check,.

Hmmmh should we do some advocacy work to get the patch into the mainline Kernel? As from the post to me it seems that has simply just forgotten

[martinayotte]

2 hours ago, p-i-u.de said:

should we do some advocacy work to get the patch into the mainline Kernel?

If your testing succeed, I will add the patch permanently into the builds ...

[p-i-u.de]

18 hours ago, martinayotte said:

If your testing succeed, I will add the patch permanently into the builds ...

actually I meant to get the patch in the upstream kernel sources. I've currently setting up my build environment and will start a build.

Will need a few days until I'm done with testing, as I can just use certain timeslice each day to not interfere with my other projects.

[p-i-u.de]

On 12/10/2019 at 3:28 PM, martinayotte said:

If your testing succeed, I will add the patch permanently into the builds ...

 

I have built the custom kernel with this patch being applied, changed the target path to 

target-path = "/spi@ff1e0000";

as SPI1 is not usable on rock pi 4, 

compiled with dtc and moved it to /boot/dtb/rockchip/overlay/rockchip-spidev2-1.dtbo

having this in /boot/armbianEnv.txt

 

overlays=spidev2-1

 

Now when I reboot I get 

 

/dev/spidev0.1

 

So, what wonders me is, a) why does it come up as spidev0 and b) how do I know which gpio pin is used for CS? Otherwise I'm ready to test

What do I miss?

 

[martinayotte]

6 minutes ago, p-i-u.de said:

as SPI1 is not usable on rock pi 4,

Why ? When I wrote the above overlay, it was using SPI1 along with GPIO1_B2 as the CS pin.

[p-i-u.de]

2 hours ago, martinayotte said:

Why ? When I wrote the above overlay, it was using SPI1 along with GPIO1_B2 as the CS pin.

AFAIK, as that used for the internal SPI Flash ( I got a Rev 1.4 Board), however I can test tomorrow if it works with the default values

[martinayotte]

17 hours ago, p-i-u.de said:

as that used for the internal SPI Flash

Flash is under /dev/spidev0.0, while the cs-gpio is under /dev/spidev0.1, therefore should be no conflict ...

[p-i-u.de]

On 12/11/2019 at 7:16 PM, martinayotte said:

Why ? When I wrote the above overlay, it was using SPI1 along with GPIO1_B2 as the CS pin.

 

I used your original dtbo and cabled  my device to 

 

GPIO1_B0 = MOSI,  GPIO1_A7= MISO,  GPIO1_B1 = CLK, GPIO1_B2 = CS

 

unfortunately it does not work. the dtbo as you already mentioned brings up spidev under spidev0.1. 

 

One question from what source do you got your information about how to set up you dts file?

I've read the Device Tree Documentation and also looked at the patch however from that information I do not know what parameters to set in the dts, I would like to help out on this topic so that's why I'm asking

[martinayotte]

20 minutes ago, p-i-u.de said:

unfortunately it does not work.

As I said, I didn't tested it with real hardware ...

20 minutes ago, p-i-u.de said:

GPIO1_B2 = CS

My mistake in my explanation and my overlay : GPIO1_B2 is CS0 for spidev0.0 of the flash, my overlay is providing a CS1 for spidev0.1 using the GPIO1_B5 pin for the RockPro64 header, but it is not present on RockPi, so let choose another one. But this time, I will need to test first on real hardware, since maybe the CS-GPIO patch is maybe not working properly ...

 

[p-i-u.de]

5 minutes ago, martinayotte said:

As I said, I didn't tested it with real hardware ...

My mistake in my explanation and my overlay : GPIO1_B2 is CS0 for spidev0.0 of the flash, my overlay is providing a CS1 for spidev0.1 using the GPIO1_B5 pin for the RockPro64 header, but it is not present on RockPi, so let choose another one. But this time, I will need to test first on real hardware, since maybe the CS-GPIO patch is maybe not working properly ...

 

I can do the test for you, as I've already set up everything, so just need the CS Pin number

[martinayotte]

4 minutes ago, p-i-u.de said:

so just need the CS Pin number

I'm thinking about using GPIO3_C0 on pin 32, but then in the overlay we need to change the line to "cs-gpio = <0>, <3 16 1 0xae>;"

I'm currently not seeing this pin toggling, so I'm adding debug prints in the kernel to figure out ...

[p-i-u.de]

5 hours ago, martinayotte said:

I'm thinking about using GPIO3_C0 on pin 32, but then in the overlay we need to change the line to "cs-gpio = <0>, <3 16 1 0xae>;"

I'm currently not seeing this pin toggling, so I'm adding debug prints in the kernel to figure out ...

 

Also on my end using real hardware, there is no output. Let me know if I can help further. How did you compute the numbers 3 16 to match GPIO3_C0? This is something I didn't figure out yet, is there any document?

[martinayotte]

16 hours ago, p-i-u.de said:

How did you compute the numbers 3 16 to match GPIO3_C0? This is something I didn't figure out yet, is there any document?

On GPIO3, A0-7 is 0-7, B0-B7 is 8-15, so C0 is 16. This can also be confirmed by looking at existing DTS where GPIO3_C0 is shared with UART3_CTS which is also 3/16 .

[Marko Buršič]

Unfortunately I already deployed my RockPi 4B v1.3  in a project. Maybe I will get a new one (currently still thinking which one would better suit NanoPi M4V2 or RockPi 4), but I would like to advise something: The RockPi 4 has a flash on SPI1 and not on SPI0. The flash wasn't soldered on my board.  I enabled the SPI1 with

overlays=spi-spidev 

param_spidev_spi_bus=1

 

GPIO1_B0 = SPI1 TXD

GPIO1_A7 = SPI1 RXD

GPIO1_B1 = SPI1 CLK

GPIO1_B2 = SPI1 CS0

 

And it was working OK. IMO, the good candidate for CS1 is GPIO4_D5 to get SPI1.1 device. So please, don't mess things that are already working properly. I don't understand why user @p-i-u.de messed up with renumbering the SPI channels and it gets /dev/spidev0.0 , SPI0 is already shared with ETH-PHY on RockPi 4.