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vr@m

Help on Buffer strength GPIO

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Good morning all, how are you?. I'm looking for help on knowing about the buffer strength on an H3 board, I've been looking on the H3 SoC datasheet and found this about GPIO's:

 

Buffer Strength defines drive strength of the associated output buffer.

 

but I don't know if the buffer is the entire port or not because I can't find any other reference to it and I don't want to fry the board.

 

Can anyone explain me this?.

 

Thanks in advance dor the help. 

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Buffer Strength of H3 GPIOs is 20mA per output pins. Of course, if you have tons of GPIOs with this strength, it will sums up and the power needed will be high, that could be an issue depending of PCB design.

 

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On 10/21/2018 at 9:01 AM, martinayotte said:

Buffer Strength of H3 GPIOs is 20mA per output pins. Of course, if you have tons of GPIOs with this strength, it will sums up and the power needed will be high, that could be an issue depending of PCB design.

 

Well, I ask this because in the nanopi M1 wiki says this:

 

Quote

All pins are 3.3V and output current is 5mA. It can drive small loads. No IO pins can drive a load.

 and in the datasheet of the H3 chips says this (page 73):

 

Quote

All pins are 3.3V and output current is 5mA. It can drive small loads. No IO pins can drive a load.

 

so I don't know which one to believe and I couldn't find more information

 

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8 hours ago, vr@m said:

and in the datasheet of the H3 chips says this (page 73)

I think you mistakenly copy twice the same quote ...

8 hours ago, vr@m said:

I don't know which one to believe

I would believe into the Allwinner H3 Datasheet ...

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The problem here is that the datasheet says that the buffer strength is 20mA but I couldn´t find any reference of if the buffer strenth is reffering to the hole port or only one pin (I don't think one pin is capable of manage 20 mA), the pin description on the datasheet says on every GPIO pin  "Buffer strength: 20 mA" but...If I've read well the schematic the GPIO pins (phisical pin header) are all connected directly to the H3's pins so imagine 40 pins draining 20 mA (exaggerating here) and obviously I don't want to burn the board

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9 hours ago, vr@m said:

so imagine 40 pins draining 20 mA (exaggerating here) and obviously I don't want to burn the board

As I've said earlier, it 20mA per pin ! I've also said that if you sums up many pins, it is up to the quality of the PCB design if it could handle that, for your example 40 pins multiply 20mA, this means that the VCC would need to supply a total 800mA to the SoC, if VCC lines on PCB are not huge enough, this will produce a voltage drop on those lines and maybe the SoC will brownout and reset/crash.

 

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4 hours ago, vr@m said:

surprised that this SOC is capable of drain 20mA per pin

This kind of buffer strength is pretty normal ...

If you need more, such 500mA per pin, you can add MOSFET or DARLINGTON, or chip like ULN2803, which is in fact an array of 8 darlingtons.

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It's my understanding that Allwinner GPIO's have configurable output drive levels.

They're configured with the Px_DRVx_REG registers. There are 4 levels, from Level 0 to Level 3. The default is Level 1.

I don't know what current corresponds to each level, it used to be  10mA, 20mA, 30mA and 40mA with the A20's. Level 1 is 20mA, which as the default for the register, matches the data sheet maximum drive strength.

 

Personally, I'd put my own buffer on a GPIO if it's driving more than a few mA.

 

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18 hours ago, martinayotte said:

This kind of buffer strength is pretty normal ...

If you need more, such 500mA per pin, you can add MOSFET or DARLINGTON, or chip like ULN2803, which is in fact an array of 8 darlingtons.

Thanks for the info, once again :D. My doubt was because I normally use PIC microcontrollers wich which has even electrical diagrams equivalents to whats inside in the datasheet so the developer can know without a risk of mistake to what is the buffer and when I've checked this datasheet that is not clear to me. 

 

Of course, making it clear that there are huge differences between a PIC microcontroller and a SoC like the Allwinner H3 or any other SoC.

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12 hours ago, chrisf said:

It's my understanding that Allwinner GPIO's have configurable output drive levels.

They're configured with the Px_DRVx_REG registers. There are 4 levels, from Level 0 to Level 3. The default is Level 1.

I don't know what current corresponds to each level, it used to be  10mA, 20mA, 30mA and 40mA with the A20's. Level 1 is 20mA, which as the default for the register, matches the data sheet maximum drive strength.

 

Personally, I'd put my own buffer on a GPIO if it's driving more than a few mA.

 

Thank you for the info @chrisf, I'm gonna check that in the datasheet.

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