CSC Armbian for RK322X TV Boxes


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@jock here I am again, I have some interesting information that I discovered doing experiments.
if you remember, some time ago I did some experiments with xorg and acceleration media files on legacy kernels
I had "found" that xorg worked with both the "modesetting" and "armsoc" driver but found that armsoc was definitely much slower than modesetting
https://forum.armbian.com/topic/12656-csc-armbian-for-rk322x-tv-boxes/?do=findComment&comment=104900

 


so I wanted to experiment with the 5.6 kernel as well....
here's what i found:

on legacy kernel, I found that armsoc and libmali (specifically libmali-rk-utgard-400-r7p0-x11_1.7-1_armhf.deb) conflict, in fact uninstalling this library, and starting xorg with armsoc driver, x11 goes fast. obviously, however, the functionality of opengles is lost. but it does not matter. I wanted to check.
I found relevant information that could also be functional on kernel 5.6.
investigating I saw that an armsoc driver was available on the apt repositories, I tried to install it but nothing, x11 did not start.
So i tried to install xserver-xorg-video-armsoc_1.4-2_armhf.deb of the legacy kernel media pack and it works! x11 starts .. well partially, we lost the window manager, the background and the desktop icons (all black) but we see that the acceleration is active and all there !, so I tried to mix the LIMA drivers with armsoc and it seems to work, or at least glxinfo tells me that the opengl mali 400 acceleration is present.

Section "ServerFlags"
        Option  "AutoAddGPU" "off"
EndSection

Section "Device"
    Identifier  "armsoc"
    Driver      "armsoc"
EndSection


Section "OutputClass"
        Identifier "Lima"
        MatchDriver "armsoc"
        Driver "modesetting"
        Option "PrimaryGPU" "true"
EndSection



now it is evident that the armsoc driver does not work because I assume it is compiled for the legacy kernel
I also searched the net to understand why this driver works, and the one in the repository doesn't.
and that's because this version is compatible with rockchip soc!


https://github.com/paolosabatino/xf86-video-armsoc

Quote

The currently supported DRM drivers are: - pl111 - exynos - kirin - meson - rockchip - sti - sun4i

 


Now I assume that by compiling these armsoc drivers for kernel 5.6 there is a good chance it will work correctly, and can be mixed with the LIMA 3D driver.

my limitation from trying at the moment, is that I don't know how to compile these, I've never done a cross compilation, and don't know (currently) how to do it. And I don't even know how to create installable .deb files from a build (my other current limitation)

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Armbian is a community driven open source project. Do you like to contribute your code?

 

Has anyone managed to make IR control work?

 

root@rk322x-box:~# ir-keytable
/sys/class/rc/: No such file or directory
No devices found


root@rk322x-box:~# lsmod
Module                  Size  Used by
lz4                    16384  4
lz4_compress           16384  1 lz4
ssv6x5x               483328  0
mali                  229376  0
snd_soc_rk3228         16384  1
lzo                    16384  4
zram                   24576  2
sch_fq_codel           20480  6
ip_tables              24576  0
autofs4                32768  0


 

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20 hours ago, fabiobassa said:


2) ehmm.... that repository is another work of jock :-)

LOL  I didn't associate, stupid me, I'm distracted.

 

 

Quote

1) download the kernel headers and compile on the board itself, no cross compile. the board is powerfull enough to compile

 


i will try, but i don't know if i will succeed, the last time i compiled a kernel, those rare times i did it was over ten years ago

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@jock @fabiobassa I was able to compile the module armsoc,
but unfortunately i can't start it, probably something is missing, i compiled it with everything by default .. here's what the xorg log result is, i get it find the screen but it's not usable, i tried to configure xorg with a section screen with custom resolutions, but I can't go further, I always get the same error.
here the log:

Spoiler

 


X.Org X Server 1.20.8
X Protocol Version 11, Revision 0
[    50.488] Build Operating System: Linux 4.4.0-177-generic armv7l Ubuntu
[    50.488] Current Operating System: Linux rk322x-box 5.6.19-rk322x #trunk SMP PREEMPT Sun Aug 16 09:48:44 UTC 2020 armv7l
[    50.488] Kernel command line: earlyprintk root=UUID=ecd18205-a6fd-4a3d-a439-9e82f693a091 console=ttyS2,115200n8 console=tty1 rootwait rootfstype=ext4  consoleblank=0 loglevel=1 ubootpart=9808d0dd-01 usb-storage.quirks=0x2537:0x1066:u,0x2537:0x1068:u coherent_pool=2M  cgroup_enable=cpuset cgroup_memory=1 cgroup_enable=memory swapaccount=1 earlyprintk=uart8250,mmio32,0x11030000
[    50.489] Build Date: 24 June 2020  06:00:21AM
[    50.489] xorg-server 2:1.20.8-2ubuntu2.2 (For technical support please see http://www.ubuntu.com/support) 
[    50.489] Current version of pixman: 0.38.4
[    50.489] 	Before reporting problems, check http://wiki.x.org
	to make sure that you have the latest version.
[    50.489] Markers: (--) probed, (**) from config file, (==) default setting,
	(++) from command line, (!!) notice, (II) informational,
	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[    50.489] (==) Log file: "/var/log/Xorg.0.log", Time: Sun Aug 23 17:58:16 2020
[    50.490] (==) Using config directory: "/etc/X11/xorg.conf.d"
[    50.490] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
[    50.491] (==) No Layout section.  Using the first Screen section.
[    50.491] (**) |-->Screen "Default Screen" (0)
[    50.491] (**) |   |-->Monitor "Monitor0"
[    50.493] (**) |   |-->Device "armsoc"
[    50.493] (**) Option "AutoAddGPU" "off"
[    50.493] (==) Automatically adding devices
[    50.493] (==) Automatically enabling devices
[    50.493] (**) Not automatically adding GPU devices
[    50.493] (==) Automatically binding GPU devices
[    50.493] (==) Max clients allowed: 256, resource mask: 0x1fffff
[    50.493] (WW) The directory "/usr/share/fonts/X11/cyrillic" does not exist.
[    50.493] 	Entry deleted from font path.
[    50.493] (WW) The directory "/usr/share/fonts/X11/100dpi/" does not exist.
[    50.493] 	Entry deleted from font path.
[    50.494] (WW) The directory "/usr/share/fonts/X11/75dpi/" does not exist.
[    50.494] 	Entry deleted from font path.
[    50.494] (WW) The directory "/usr/share/fonts/X11/Type1" does not exist.
[    50.494] 	Entry deleted from font path.
[    50.494] (WW) The directory "/usr/share/fonts/X11/100dpi" does not exist.
[    50.494] 	Entry deleted from font path.
[    50.494] (WW) The directory "/usr/share/fonts/X11/75dpi" does not exist.
[    50.494] 	Entry deleted from font path.
[    50.494] (==) FontPath set to:
	/usr/share/fonts/X11/misc,
	built-ins
[    50.494] (==) ModulePath set to "/usr/lib/xorg/modules"
[    50.494] (II) The server relies on udev to provide the list of input devices.
	If no devices become available, reconfigure udev or disable AutoAddDevices.
[    50.494] (II) Loader magic: 0x60a008
[    50.494] (II) Module ABI versions:
[    50.494] 	X.Org ANSI C Emulation: 0.4
[    50.494] 	X.Org Video Driver: 24.1
[    50.494] 	X.Org XInput driver : 24.1
[    50.494] 	X.Org Server Extension : 10.0
[    50.498] (++) using VT number 7

[    50.498] (II) systemd-logind: logind integration requires -keeptty and -keeptty was not provided, disabling logind integration
[    50.502] (II) xfree86: Adding drm device (/dev/dri/card1)
[    50.504] (II) xfree86: Adding drm device (/dev/dri/card0)
[    50.507] (II) no primary bus or device found
[    50.507] 	falling back to /sys/devices/platform/20000000.gpu/drm/card1
[    50.508] (II) LoadModule: "glx"
[    50.509] (II) Loading /usr/lib/xorg/modules/extensions/libglx.so
[    50.514] (II) Module glx: vendor="X.Org Foundation"
[    50.514] 	compiled for 1.20.8, module version = 1.0.0
[    50.514] 	ABI class: X.Org Server Extension, version 10.0
[    50.514] (II) LoadModule: "armsoc"
[    50.515] (II) Loading /usr/lib/xorg/modules/drivers/armsoc_drv.so
[    50.516] (II) Module armsoc: vendor="X.Org Foundation"
[    50.516] 	compiled for 1.20.8, module version = 1.4.1
[    50.516] 	Module class: X.Org Video Driver
[    50.516] 	ABI class: X.Org Video Driver, version 24.1
[    50.516] (II) ARMSOC: Driver for ARM Mali compatible chipsets
[    50.517] (II) ARMSOCPlatformProbe: bus ID: 20000000.gpu
[    50.517] (WW) VGA arbiter: cannot open kernel arbiter, no multi-card support
[    50.517] (**) ARMSOC(0): Depth 24, (--) framebuffer bpp 32
[    50.517] (==) ARMSOC(0): RGB weight 888
[    50.517] (==) ARMSOC(0): Using gamma correction (1.0, 1.0, 1.0)
[    50.518] (==) ARMSOC(0): Default visual is TrueColor
[    50.518] (II) Using FD -1 passed in from server
[    50.518] (II) Opening driver [NULL], bus_id [20000000.gpu]
[    50.524] (II) Opened DRM
[    50.524] (II)    DeviceName is [/dev/dri/card1]
[    50.524] (II)    bus_id is [20000000.gpu]
[    50.524] (II)    DriverName is [lima]
[    50.525] (II)    version is [1.1.0]
[    50.525] (II) DRM FD passed from server. Ignoring close request
[    50.525] (II) UnloadModule: "armsoc"
[    50.525] (EE) Screen(s) found, but none have a usable configuration.
[    50.525] (EE) 
Fatal server error:
[    50.525] (EE) no screens found(EE) 
[    50.525] (EE) 
Please consult the The X.Org Foundation support 
	 at http://wiki.x.org
 for help. 
[    50.525] (EE) Please also check the log file at "/var/log/Xorg.0.log" for additional information.
[    50.526] (EE) 
[    50.601] (EE) Server terminated with error (1). Closing log file.

 

 

 



 

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On 8/23/2020 at 5:55 AM, Gabriel Vinicius said:

 

Has anyone managed to make IR control work?

 

root@rk322x-box:~# ir-keytable
/sys/class/rc/: No such file or directory
No devices found

i'm not an expert, but i just try a guess, maybe the IR system, in these tvbox, depends from box to box, you should check the dts tree (the original one from your tvbox) and see how it's configured inside, then i don't know how the kernel is put if there is or isn't the right driver.

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@Gabriel Vinicius

You're right, the IR kernel module is not enabled in legacy kernel. This is a mistake I will correct as soon as I can.

It works fine on mainline kernel though. Since most of the remotes shipped with rk3229 boxes uses the NEC protocol, you can probably successfully test it running ir-keytable -p NEC -t and pressing the remote keys.

 

@nokirunner

I tested Lima driver on 5.7 and 5.8, but performance is always the same. The kernel driver is only a small part of the whole, most of the important code is in Mesa project, which contains the actual OpenGL implementation for the Mali-400, so until Mesa is updated to the latest stable version in Ubuntu/Debian or you compile the latest development Mesa, you won't see any real progress.

 

By the way, I think that the Lima driver is not yet very well optimized yet, there is some bottleneck somewhere that makes it work so slowly in X.org. I also tried Gnome 3 on a poor rk3228a (kernel 5.6) and, incredibly, it seems to work a bit better than xfce. It is still slow, but at least has a rich graphics and does not stutter like xfce do.

As the Mesa developer said also in the issue regarding the slow performance of the Allwinner A20, modesetting x.org driver seems not to be really friendly with Lima driver and, in general, with embedded graphics. Panfrost suffers too, for example, and is not so snappier as it used to be with armsoc.

 

I didn't try armsoc yet, I don't even know if it could work or not: actually the kernel is not involved in compiling armsoc, since it only interacts with the DRM bits via "dumb buffers", but I'm skeptic about its interaction with lima driver. You should try to force it using /dev/dri/card0 using some xorg.conf option (DRICard maybe, but man armsoc could help you) and see what happens: if it works (eg: fast 2D) probably you won't be able to use hardware acceleration for 3d games.

 

Lastly, the armsoc driver packaged with armbian is an old one that does not use generic dumb buffers, but instead specific IOCTLs and works only on some DRM drivers found in very old kernels. Don't use it.

 

Ah, a last note... I have an AmLogic S905 box around here too, it has Mali-450 GPU, which is much faster than Mali-400, and also faster DDR3 memory. There Lima driver works much better for 2D out of the box, but still I have the feeling it is not perfectly fluid and optimized as it should be.

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@jockwell, thanks for the explanations.
the fact is that there is certainly something badly designed right now.
we hope for notable improvements in the future.

i managed to compile and install the latest mesa with the latest LIMA driver updates, but nothing has changed.

the last test I would like to do is to install the dri module for the kernel with the latest patches, but I would not want to recompile the whole kernel, but only the module I need, I wonder if I can do it while using an older kernel. ...
this:
https://github.com/torvalds/linux/commits/master/drivers/gpu/drm/lima

but also this, which I understand is the display driver, and takes care of interfacing with the hdmi manages the resolutions of the monitors and so on ..

(which apparently, according to the LIMA documentation, must be started with xorg together with LIMA, but reading you and how you configured xorg, it seems to me that you have totally ignored the existence of this other "display driver" and that must be "mixed" with the LIMA driver)

https://github.com/torvalds/linux/commits/master/drivers/gpu/drm/rockchip

 

according to the LIMA documentation, the two drivers must be combined in this way:
(pay particular attention to that MatchDriver "display DRM driver" ... which must be replaced with "rockchip" or other drivers according to the various brands of the various socs)

Section "ServerFlags"
        Option  "AutoAddGPU" "off"
        Option "Debug" "dmabuf_capable"
EndSection

Section "OutputClass"
        Identifier "Lima"
        MatchDriver "<display DRM driver>"
        Driver "modesetting"
        Option "PrimaryGPU" "true"
EndSection


 

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Out of curiosity I built the armsoc driver for my rk3399. I can confirm your observation of the faster display output. Of course, there is no 3D acceleration because the driver has no way to delegate 3D requests to the 3D render node. The armada driver (you want the unstable-devel branch) I use for my imx6 has such an ability and surpasses the rk3399 with modesetting despite the lower specification for now.

IMHO armsoc is a dead end until it gets a similar ability. And using glamor with its unnecessary scanout indirection via 3d is also a bad idea. We are all in the same boot, no xorg driver to glue all IPs in an efficient manner together available.

xorg-rockchip-modesetting.logxorg-rockchip-armsoc.logxorg-imx-armada.log

Edited by usual user
attach correct xorg-rockchip-armsoc.log
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9 hours ago, nokirunner said:

according to the LIMA documentation, the two drivers must be combined in this way:
(pay particular attention to that MatchDriver "display DRM driver" ... which must be replaced with "rockchip" or other drivers according to the various brands of the various socs)

 

That's the DRM driver built in the kernel. I'm no expert in DRM matter, but this is the general idea I made up: the 3d chip (Mali) can't access the 2D framebuffer; the SoC instead can, precisely on rockchip SoCs it is the VOP that has access to it. With "MatchDriver" configuration line you tell the modesetting driver that it has to connect to the rockchip DRM in the kernel.

 

Since the DRM interface is pretty standard among various SoCs on recent mainline kernels, it does not really matter. If you take a look to the armsoc source code (my variant), you will see that the Allwinner (sunxi), Rockchip and AmLogic DRM (meson) interfaces and they are exactly the same code: I copy-pasted and it just works, only the DRM name to connect to changes, but the core code of armsoc uses the standard dumb buffers DRM interface from the kernel.

Modesetting does the same thing to connect to the kernel DRM, you may optionally tell it which is the DRM to connect to (or the "card").

 

As @usual user also said, the general slowness comes from the glamor "acceleration", which uses the Mali 3D OpenGL for 2D things, instead of leverage the DRM things for 2D.

I suspect that if you disable the glamor acceleration for modesetting with:

Section "Device"
	Identifier "Lima"
	Driver "modesetting"
	Option "AccelMethod" "none"
	Option "kmsdev" "/dev/dri/card1"
EndSection

you end up with decent 2D and no 3D: modesetting will behave like armsoc for 2D, but differently from armsoc, it will totally ignore the 3D part. (hint: you may have to change card1 to card0 on your box)

 

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@jockMine are obviously just guesses of reasoning, based on the information I gathered, but I couldn't test .
You will probably be right, being much more grounded and experienced.
Only for fun I like to test things to verify, maybe you never know, with a bit of (culo) some miracle happens.
I checked the drm kernel folder, there is only the module LIMA, why is not the there rockchip module also?
one thing is certain and makes me suspect that something has gone wrong, something is wrong with the monitor recognition, only one resolution comes out, and the refresh management marks "zero" (showing that it is broken), perhaps, and it's just a guess, this module is not compiled.
FYc3pPd.png

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On 8/23/2020 at 5:55 AM, Gabriel Vinicius said:

 

Has anyone managed to make IR control work?

 

root@rk322x-box:~# ir-keytable
/sys/class/rc/: No such file or directory
No devices found

 


 

Hello, I updated the legacy images with the new kernel module.

If you want to upgrade without reinstalling the full system, you can install the kernel image package downloading it from here: <https://drive.google.com/file/d/1x1ReMTWc1ymEqHT8ahc9wZADfSQGkkCF/view?usp=sharing>

I didn't test the images, I guess they work though.

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1 hour ago, jock said:

You don't see the rockchip module there because it is not compiled as an external module

You will also not see it as built-in, the Rockchip display subsystem will be provided by DesignWare IP. The rockchip driver functionality will be provided by the dw_hdmi module. It will provide a cardX node in /dev/dri/. The 3d Mali GPU IP will use either the lima or panfrost module depending which flavor of Mali your device has. It will provide a renderDXXX node in /dev/dri/. Its companion cardX node is of no use and is only there for drm implementation reasons. The ddx xorg driver (modesetting, armsoc, armada, ...) will use the cardX node for display output. Since Xwindow doesn't know what hardware you have, you can use this stanza to give it a hint instead of let it guess which cardX node to use:

Section "OutputClass"
    Identifier   "dwhdmi-rockchip"
    MatchDriver  "rockchip"
    Option       "PrimaryGPU"      "TRUE"
EndSection

This stanza will force instead of autoprobe which ddx driver is to be used:

Section "Device"
    Identifier   "KMS-1"
    Driver       "armsoc"
EndSection

For the ddx driver to support 3d on a different IP it needs the functionality of a submodule (glamoregl for modesetting, etnaviv_drm for armada, but I'm not aware of one for armsoc) to access it via the renderDXXX node. The IPs will exchange buffers via dma_buf with zero copy. The armada driver can configure which submodule to use, so you can combine the i.MX display subsystem with any GPU IP you have a suitable submodule for.

drmdevice-rockchip.log

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On 8/25/2020 at 4:20 PM, usual user said:

You will also not see it as built-in, the Rockchip display subsystem will be provided by DesignWare IP. The rockchip driver functionality will be provided by the dw_hdmi module. It will provide a cardX node in /dev/dri/. The 3d Mali GPU IP will use either the lima or panfrost module depending which flavor of Mali your device has. It will provide a renderDXXX node in /dev/dri/. Its companion cardX node is of no use and is only there for drm implementation reasons. The ddx xorg driver (modesetting, armsoc, armada, ...) will use the cardX node for display output. Since Xwindow doesn't know what hardware you have, you can use this stanza to give it a hint instead of let it guess which cardX node to use:


Section "OutputClass"
    Identifier   "dwhdmi-rockchip"
    MatchDriver  "rockchip"
    Option       "PrimaryGPU"      "TRUE"
EndSection

 

drmdevice-rockchip.log 1.86 kB · 3 downloads

I tried this on my rk232x based device and i suspect it doesn't work.
If I put "modesetting" as driver then it recognizes  rockchip and vdpau-rockchip, but with the method described by you I don't get the same result, it tells me that the driver rockchip is not found and starts the same through modesetting ... I suspect that for the rk322x it does not work ... and I also suspect that it is for this reason that glamoregl even if it seems to start does not work as 2d acceleration ... this driver dri is not optimized  at all (or partially brocken) for rk322x  at least the 5.6 kernel, maybe the latest versions like the upcoming kernel 5.9 already contain these fixes.

edit :
in fact there seems to be no trace of rk3228 registers.


https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
(Visual Output Processor) is the Display Controller for the Rockchip series of SoCs which transfers the image data from a video memory buffer to an external LCD interface
look only other rockchip socs :

Spoiler

 


/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
 * Author:Mark Yao <mark.yao@rock-chips.com>
 */

#ifndef _ROCKCHIP_VOP_REG_H
#define _ROCKCHIP_VOP_REG_H

/* rk3288 register definition */
#define RK3288_REG_CFG_DONE			0x0000
#define RK3288_VERSION_INFO			0x0004
#define RK3288_SYS_CTRL				0x0008
#define RK3288_SYS_CTRL1			0x000c
#define RK3288_DSP_CTRL0			0x0010
#define RK3288_DSP_CTRL1			0x0014
#define RK3288_DSP_BG				0x0018
#define RK3288_MCU_CTRL				0x001c
#define RK3288_INTR_CTRL0			0x0020
#define RK3288_INTR_CTRL1			0x0024
#define RK3288_WIN0_CTRL0			0x0030
#define RK3288_WIN0_CTRL1			0x0034
#define RK3288_WIN0_COLOR_KEY			0x0038
#define RK3288_WIN0_VIR				0x003c
#define RK3288_WIN0_YRGB_MST			0x0040
#define RK3288_WIN0_CBR_MST			0x0044
#define RK3288_WIN0_ACT_INFO			0x0048
#define RK3288_WIN0_DSP_INFO			0x004c
#define RK3288_WIN0_DSP_ST			0x0050
#define RK3288_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3288_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3288_WIN0_SCL_OFFSET			0x005c
#define RK3288_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3288_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3288_WIN0_FADING_CTRL			0x0068
#define RK3288_WIN0_CTRL2			0x006c

/* win1 register */
#define RK3288_WIN1_CTRL0			0x0070
#define RK3288_WIN1_CTRL1			0x0074
#define RK3288_WIN1_COLOR_KEY			0x0078
#define RK3288_WIN1_VIR				0x007c
#define RK3288_WIN1_YRGB_MST			0x0080
#define RK3288_WIN1_CBR_MST			0x0084
#define RK3288_WIN1_ACT_INFO			0x0088
#define RK3288_WIN1_DSP_INFO			0x008c
#define RK3288_WIN1_DSP_ST			0x0090
#define RK3288_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3288_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3288_WIN1_SCL_OFFSET			0x009c
#define RK3288_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3288_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3288_WIN1_FADING_CTRL			0x00a8
/* win2 register */
#define RK3288_WIN2_CTRL0			0x00b0
#define RK3288_WIN2_CTRL1			0x00b4
#define RK3288_WIN2_VIR0_1			0x00b8
#define RK3288_WIN2_VIR2_3			0x00bc
#define RK3288_WIN2_MST0			0x00c0
#define RK3288_WIN2_DSP_INFO0			0x00c4
#define RK3288_WIN2_DSP_ST0			0x00c8
#define RK3288_WIN2_COLOR_KEY			0x00cc
#define RK3288_WIN2_MST1			0x00d0
#define RK3288_WIN2_DSP_INFO1			0x00d4
#define RK3288_WIN2_DSP_ST1			0x00d8
#define RK3288_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3288_WIN2_MST2			0x00e0
#define RK3288_WIN2_DSP_INFO2			0x00e4
#define RK3288_WIN2_DSP_ST2			0x00e8
#define RK3288_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3288_WIN2_MST3			0x00f0
#define RK3288_WIN2_DSP_INFO3			0x00f4
#define RK3288_WIN2_DSP_ST3			0x00f8
#define RK3288_WIN2_FADING_CTRL			0x00fc
/* win3 register */
#define RK3288_WIN3_CTRL0			0x0100
#define RK3288_WIN3_CTRL1			0x0104
#define RK3288_WIN3_VIR0_1			0x0108
#define RK3288_WIN3_VIR2_3			0x010c
#define RK3288_WIN3_MST0			0x0110
#define RK3288_WIN3_DSP_INFO0			0x0114
#define RK3288_WIN3_DSP_ST0			0x0118
#define RK3288_WIN3_COLOR_KEY			0x011c
#define RK3288_WIN3_MST1			0x0120
#define RK3288_WIN3_DSP_INFO1			0x0124
#define RK3288_WIN3_DSP_ST1			0x0128
#define RK3288_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3288_WIN3_MST2			0x0130
#define RK3288_WIN3_DSP_INFO2			0x0134
#define RK3288_WIN3_DSP_ST2			0x0138
#define RK3288_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3288_WIN3_MST3			0x0140
#define RK3288_WIN3_DSP_INFO3			0x0144
#define RK3288_WIN3_DSP_ST3			0x0148
#define RK3288_WIN3_FADING_CTRL			0x014c
/* hwc register */
#define RK3288_HWC_CTRL0			0x0150
#define RK3288_HWC_CTRL1			0x0154
#define RK3288_HWC_MST				0x0158
#define RK3288_HWC_DSP_ST			0x015c
#define RK3288_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3288_HWC_DST_ALPHA_CTRL		0x0164
#define RK3288_HWC_FADING_CTRL			0x0168
/* post process register */
#define RK3288_POST_DSP_HACT_INFO		0x0170
#define RK3288_POST_DSP_VACT_INFO		0x0174
#define RK3288_POST_SCL_FACTOR_YRGB		0x0178
#define RK3288_POST_SCL_CTRL			0x0180
#define RK3288_POST_DSP_VACT_INFO_F1		0x0184
#define RK3288_DSP_HTOTAL_HS_END		0x0188
#define RK3288_DSP_HACT_ST_END			0x018c
#define RK3288_DSP_VTOTAL_VS_END		0x0190
#define RK3288_DSP_VACT_ST_END			0x0194
#define RK3288_DSP_VS_ST_END_F1			0x0198
#define RK3288_DSP_VACT_ST_END_F1		0x019c
/* register definition end */

/* rk3368 register definition */
#define RK3368_REG_CFG_DONE			0x0000
#define RK3368_VERSION_INFO			0x0004
#define RK3368_SYS_CTRL				0x0008
#define RK3368_SYS_CTRL1			0x000c
#define RK3368_DSP_CTRL0			0x0010
#define RK3368_DSP_CTRL1			0x0014
#define RK3368_DSP_BG				0x0018
#define RK3368_MCU_CTRL				0x001c
#define RK3368_LINE_FLAG			0x0020
#define RK3368_INTR_EN				0x0024
#define RK3368_INTR_CLEAR			0x0028
#define RK3368_INTR_STATUS			0x002c
#define RK3368_WIN0_CTRL0			0x0030
#define RK3368_WIN0_CTRL1			0x0034
#define RK3368_WIN0_COLOR_KEY			0x0038
#define RK3368_WIN0_VIR				0x003c
#define RK3368_WIN0_YRGB_MST			0x0040
#define RK3368_WIN0_CBR_MST			0x0044
#define RK3368_WIN0_ACT_INFO			0x0048
#define RK3368_WIN0_DSP_INFO			0x004c
#define RK3368_WIN0_DSP_ST			0x0050
#define RK3368_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3368_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3368_WIN0_SCL_OFFSET			0x005c
#define RK3368_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3368_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3368_WIN0_FADING_CTRL			0x0068
#define RK3368_WIN0_CTRL2			0x006c
#define RK3368_WIN1_CTRL0			0x0070
#define RK3368_WIN1_CTRL1			0x0074
#define RK3368_WIN1_COLOR_KEY			0x0078
#define RK3368_WIN1_VIR				0x007c
#define RK3368_WIN1_YRGB_MST			0x0080
#define RK3368_WIN1_CBR_MST			0x0084
#define RK3368_WIN1_ACT_INFO			0x0088
#define RK3368_WIN1_DSP_INFO			0x008c
#define RK3368_WIN1_DSP_ST			0x0090
#define RK3368_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3368_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3368_WIN1_SCL_OFFSET			0x009c
#define RK3368_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3368_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3368_WIN1_FADING_CTRL			0x00a8
#define RK3368_WIN1_CTRL2			0x00ac
#define RK3368_WIN2_CTRL0			0x00b0
#define RK3368_WIN2_CTRL1			0x00b4
#define RK3368_WIN2_VIR0_1			0x00b8
#define RK3368_WIN2_VIR2_3			0x00bc
#define RK3368_WIN2_MST0			0x00c0
#define RK3368_WIN2_DSP_INFO0			0x00c4
#define RK3368_WIN2_DSP_ST0			0x00c8
#define RK3368_WIN2_COLOR_KEY			0x00cc
#define RK3368_WIN2_MST1			0x00d0
#define RK3368_WIN2_DSP_INFO1			0x00d4
#define RK3368_WIN2_DSP_ST1			0x00d8
#define RK3368_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3368_WIN2_MST2			0x00e0
#define RK3368_WIN2_DSP_INFO2			0x00e4
#define RK3368_WIN2_DSP_ST2			0x00e8
#define RK3368_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3368_WIN2_MST3			0x00f0
#define RK3368_WIN2_DSP_INFO3			0x00f4
#define RK3368_WIN2_DSP_ST3			0x00f8
#define RK3368_WIN2_FADING_CTRL			0x00fc
#define RK3368_WIN3_CTRL0			0x0100
#define RK3368_WIN3_CTRL1			0x0104
#define RK3368_WIN3_VIR0_1			0x0108
#define RK3368_WIN3_VIR2_3			0x010c
#define RK3368_WIN3_MST0			0x0110
#define RK3368_WIN3_DSP_INFO0			0x0114
#define RK3368_WIN3_DSP_ST0			0x0118
#define RK3368_WIN3_COLOR_KEY			0x011c
#define RK3368_WIN3_MST1			0x0120
#define RK3368_WIN3_DSP_INFO1			0x0124
#define RK3368_WIN3_DSP_ST1			0x0128
#define RK3368_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3368_WIN3_MST2			0x0130
#define RK3368_WIN3_DSP_INFO2			0x0134
#define RK3368_WIN3_DSP_ST2			0x0138
#define RK3368_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3368_WIN3_MST3			0x0140
#define RK3368_WIN3_DSP_INFO3			0x0144
#define RK3368_WIN3_DSP_ST3			0x0148
#define RK3368_WIN3_FADING_CTRL			0x014c
#define RK3368_HWC_CTRL0			0x0150
#define RK3368_HWC_CTRL1			0x0154
#define RK3368_HWC_MST				0x0158
#define RK3368_HWC_DSP_ST			0x015c
#define RK3368_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3368_HWC_DST_ALPHA_CTRL		0x0164
#define RK3368_HWC_FADING_CTRL			0x0168
#define RK3368_HWC_RESERVED1			0x016c
#define RK3368_POST_DSP_HACT_INFO		0x0170
#define RK3368_POST_DSP_VACT_INFO		0x0174
#define RK3368_POST_SCL_FACTOR_YRGB		0x0178
#define RK3368_POST_RESERVED			0x017c
#define RK3368_POST_SCL_CTRL			0x0180
#define RK3368_POST_DSP_VACT_INFO_F1		0x0184
#define RK3368_DSP_HTOTAL_HS_END		0x0188
#define RK3368_DSP_HACT_ST_END			0x018c
#define RK3368_DSP_VTOTAL_VS_END		0x0190
#define RK3368_DSP_VACT_ST_END			0x0194
#define RK3368_DSP_VS_ST_END_F1			0x0198
#define RK3368_DSP_VACT_ST_END_F1		0x019c
#define RK3368_PWM_CTRL				0x01a0
#define RK3368_PWM_PERIOD_HPR			0x01a4
#define RK3368_PWM_DUTY_LPR			0x01a8
#define RK3368_PWM_CNT				0x01ac
#define RK3368_BCSH_COLOR_BAR			0x01b0
#define RK3368_BCSH_BCS				0x01b4
#define RK3368_BCSH_H				0x01b8
#define RK3368_BCSH_CTRL			0x01bc
#define RK3368_CABC_CTRL0			0x01c0
#define RK3368_CABC_CTRL1			0x01c4
#define RK3368_CABC_CTRL2			0x01c8
#define RK3368_CABC_CTRL3			0x01cc
#define RK3368_CABC_GAUSS_LINE0_0		0x01d0
#define RK3368_CABC_GAUSS_LINE0_1		0x01d4
#define RK3368_CABC_GAUSS_LINE1_0		0x01d8
#define RK3368_CABC_GAUSS_LINE1_1		0x01dc
#define RK3368_CABC_GAUSS_LINE2_0		0x01e0
#define RK3368_CABC_GAUSS_LINE2_1		0x01e4
#define RK3368_FRC_LOWER01_0			0x01e8
#define RK3368_FRC_LOWER01_1			0x01ec
#define RK3368_FRC_LOWER10_0			0x01f0
#define RK3368_FRC_LOWER10_1			0x01f4
#define RK3368_FRC_LOWER11_0			0x01f8
#define RK3368_FRC_LOWER11_1			0x01fc
#define RK3368_IFBDC_CTRL			0x0200
#define RK3368_IFBDC_TILES_NUM			0x0204
#define RK3368_IFBDC_FRAME_RST_CYCLE		0x0208
#define RK3368_IFBDC_BASE_ADDR			0x020c
#define RK3368_IFBDC_MB_SIZE			0x0210
#define RK3368_IFBDC_CMP_INDEX_INIT		0x0214
#define RK3368_IFBDC_VIR			0x0220
#define RK3368_IFBDC_DEBUG0			0x0230
#define RK3368_IFBDC_DEBUG1			0x0234
#define RK3368_LATENCY_CTRL0			0x0250
#define RK3368_RD_MAX_LATENCY_NUM0		0x0254
#define RK3368_RD_LATENCY_THR_NUM0		0x0258
#define RK3368_RD_LATENCY_SAMP_NUM0		0x025c
#define RK3368_WIN0_DSP_BG			0x0260
#define RK3368_WIN1_DSP_BG			0x0264
#define RK3368_WIN2_DSP_BG			0x0268
#define RK3368_WIN3_DSP_BG			0x026c
#define RK3368_SCAN_LINE_NUM			0x0270
#define RK3368_CABC_DEBUG0			0x0274
#define RK3368_CABC_DEBUG1			0x0278
#define RK3368_CABC_DEBUG2			0x027c
#define RK3368_DBG_REG_000			0x0280
#define RK3368_DBG_REG_001			0x0284
#define RK3368_DBG_REG_002			0x0288
#define RK3368_DBG_REG_003			0x028c
#define RK3368_DBG_REG_004			0x0290
#define RK3368_DBG_REG_005			0x0294
#define RK3368_DBG_REG_006			0x0298
#define RK3368_DBG_REG_007			0x029c
#define RK3368_DBG_REG_008			0x02a0
#define RK3368_DBG_REG_016			0x02c0
#define RK3368_DBG_REG_017			0x02c4
#define RK3368_DBG_REG_018			0x02c8
#define RK3368_DBG_REG_019			0x02cc
#define RK3368_DBG_REG_020			0x02d0
#define RK3368_DBG_REG_021			0x02d4
#define RK3368_DBG_REG_022			0x02d8
#define RK3368_DBG_REG_023			0x02dc
#define RK3368_DBG_REG_028			0x02f0
#define RK3368_MMU_DTE_ADDR			0x0300
#define RK3368_MMU_STATUS			0x0304
#define RK3368_MMU_COMMAND			0x0308
#define RK3368_MMU_PAGE_FAULT_ADDR		0x030c
#define RK3368_MMU_ZAP_ONE_LINE			0x0310
#define RK3368_MMU_INT_RAWSTAT			0x0314
#define RK3368_MMU_INT_CLEAR			0x0318
#define RK3368_MMU_INT_MASK			0x031c
#define RK3368_MMU_INT_STATUS			0x0320
#define RK3368_MMU_AUTO_GATING			0x0324
#define RK3368_WIN2_LUT_ADDR			0x0400
#define RK3368_WIN3_LUT_ADDR			0x0800
#define RK3368_HWC_LUT_ADDR			0x0c00
#define RK3368_GAMMA_LUT_ADDR			0x1000
#define RK3368_CABC_GAMMA_LUT_ADDR		0x1800
#define RK3368_MCU_BYPASS_WPORT			0x2200
#define RK3368_MCU_BYPASS_RPORT			0x2300
/* rk3368 register definition end */

#define RK3366_REG_CFG_DONE			0x0000
#define RK3366_VERSION_INFO			0x0004
#define RK3366_SYS_CTRL				0x0008
#define RK3366_SYS_CTRL1			0x000c
#define RK3366_DSP_CTRL0			0x0010
#define RK3366_DSP_CTRL1			0x0014
#define RK3366_DSP_BG				0x0018
#define RK3366_MCU_CTRL				0x001c
#define RK3366_WB_CTRL0				0x0020
#define RK3366_WB_CTRL1				0x0024
#define RK3366_WB_YRGB_MST			0x0028
#define RK3366_WB_CBR_MST			0x002c
#define RK3366_WIN0_CTRL0			0x0030
#define RK3366_WIN0_CTRL1			0x0034
#define RK3366_WIN0_COLOR_KEY			0x0038
#define RK3366_WIN0_VIR				0x003c
#define RK3366_WIN0_YRGB_MST			0x0040
#define RK3366_WIN0_CBR_MST			0x0044
#define RK3366_WIN0_ACT_INFO			0x0048
#define RK3366_WIN0_DSP_INFO			0x004c
#define RK3366_WIN0_DSP_ST			0x0050
#define RK3366_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3366_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3366_WIN0_SCL_OFFSET			0x005c
#define RK3366_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3366_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3366_WIN0_FADING_CTRL			0x0068
#define RK3366_WIN0_CTRL2			0x006c
#define RK3366_WIN1_CTRL0			0x0070
#define RK3366_WIN1_CTRL1			0x0074
#define RK3366_WIN1_COLOR_KEY			0x0078
#define RK3366_WIN1_VIR				0x007c
#define RK3366_WIN1_YRGB_MST			0x0080
#define RK3366_WIN1_CBR_MST			0x0084
#define RK3366_WIN1_ACT_INFO			0x0088
#define RK3366_WIN1_DSP_INFO			0x008c
#define RK3366_WIN1_DSP_ST			0x0090
#define RK3366_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3366_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3366_WIN1_SCL_OFFSET			0x009c
#define RK3366_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3366_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3366_WIN1_FADING_CTRL			0x00a8
#define RK3366_WIN1_CTRL2			0x00ac
#define RK3366_WIN2_CTRL0			0x00b0
#define RK3366_WIN2_CTRL1			0x00b4
#define RK3366_WIN2_VIR0_1			0x00b8
#define RK3366_WIN2_VIR2_3			0x00bc
#define RK3366_WIN2_MST0			0x00c0
#define RK3366_WIN2_DSP_INFO0			0x00c4
#define RK3366_WIN2_DSP_ST0			0x00c8
#define RK3366_WIN2_COLOR_KEY			0x00cc
#define RK3366_WIN2_MST1			0x00d0
#define RK3366_WIN2_DSP_INFO1			0x00d4
#define RK3366_WIN2_DSP_ST1			0x00d8
#define RK3366_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3366_WIN2_MST2			0x00e0
#define RK3366_WIN2_DSP_INFO2			0x00e4
#define RK3366_WIN2_DSP_ST2			0x00e8
#define RK3366_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3366_WIN2_MST3			0x00f0
#define RK3366_WIN2_DSP_INFO3			0x00f4
#define RK3366_WIN2_DSP_ST3			0x00f8
#define RK3366_WIN2_FADING_CTRL			0x00fc
#define RK3366_WIN3_CTRL0			0x0100
#define RK3366_WIN3_CTRL1			0x0104
#define RK3366_WIN3_VIR0_1			0x0108
#define RK3366_WIN3_VIR2_3			0x010c
#define RK3366_WIN3_MST0			0x0110
#define RK3366_WIN3_DSP_INFO0			0x0114
#define RK3366_WIN3_DSP_ST0			0x0118
#define RK3366_WIN3_COLOR_KEY			0x011c
#define RK3366_WIN3_MST1			0x0120
#define RK3366_WIN3_DSP_INFO1			0x0124
#define RK3366_WIN3_DSP_ST1			0x0128
#define RK3366_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3366_WIN3_MST2			0x0130
#define RK3366_WIN3_DSP_INFO2			0x0134
#define RK3366_WIN3_DSP_ST2			0x0138
#define RK3366_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3366_WIN3_MST3			0x0140
#define RK3366_WIN3_DSP_INFO3			0x0144
#define RK3366_WIN3_DSP_ST3			0x0148
#define RK3366_WIN3_FADING_CTRL			0x014c
#define RK3366_HWC_CTRL0			0x0150
#define RK3366_HWC_CTRL1			0x0154
#define RK3366_HWC_MST				0x0158
#define RK3366_HWC_DSP_ST			0x015c
#define RK3366_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3366_HWC_DST_ALPHA_CTRL		0x0164
#define RK3366_HWC_FADING_CTRL			0x0168
#define RK3366_HWC_RESERVED1			0x016c
#define RK3366_POST_DSP_HACT_INFO		0x0170
#define RK3366_POST_DSP_VACT_INFO		0x0174
#define RK3366_POST_SCL_FACTOR_YRGB		0x0178
#define RK3366_POST_RESERVED			0x017c
#define RK3366_POST_SCL_CTRL			0x0180
#define RK3366_POST_DSP_VACT_INFO_F1		0x0184
#define RK3366_DSP_HTOTAL_HS_END		0x0188
#define RK3366_DSP_HACT_ST_END			0x018c
#define RK3366_DSP_VTOTAL_VS_END		0x0190
#define RK3366_DSP_VACT_ST_END			0x0194
#define RK3366_DSP_VS_ST_END_F1			0x0198
#define RK3366_DSP_VACT_ST_END_F1		0x019c
#define RK3366_PWM_CTRL				0x01a0
#define RK3366_PWM_PERIOD_HPR			0x01a4
#define RK3366_PWM_DUTY_LPR			0x01a8
#define RK3366_PWM_CNT				0x01ac
#define RK3366_BCSH_COLOR_BAR			0x01b0
#define RK3366_BCSH_BCS				0x01b4
#define RK3366_BCSH_H				0x01b8
#define RK3366_BCSH_CTRL			0x01bc
#define RK3366_CABC_CTRL0			0x01c0
#define RK3366_CABC_CTRL1			0x01c4
#define RK3366_CABC_CTRL2			0x01c8
#define RK3366_CABC_CTRL3			0x01cc
#define RK3366_CABC_GAUSS_LINE0_0		0x01d0
#define RK3366_CABC_GAUSS_LINE0_1		0x01d4
#define RK3366_CABC_GAUSS_LINE1_0		0x01d8
#define RK3366_CABC_GAUSS_LINE1_1		0x01dc
#define RK3366_CABC_GAUSS_LINE2_0		0x01e0
#define RK3366_CABC_GAUSS_LINE2_1		0x01e4
#define RK3366_FRC_LOWER01_0			0x01e8
#define RK3366_FRC_LOWER01_1			0x01ec
#define RK3366_FRC_LOWER10_0			0x01f0
#define RK3366_FRC_LOWER10_1			0x01f4
#define RK3366_FRC_LOWER11_0			0x01f8
#define RK3366_FRC_LOWER11_1			0x01fc
#define RK3366_INTR_EN0				0x0280
#define RK3366_INTR_CLEAR0			0x0284
#define RK3366_INTR_STATUS0			0x0288
#define RK3366_INTR_RAW_STATUS0			0x028c
#define RK3366_INTR_EN1				0x0290
#define RK3366_INTR_CLEAR1			0x0294
#define RK3366_INTR_STATUS1			0x0298
#define RK3366_INTR_RAW_STATUS1			0x029c
#define RK3366_LINE_FLAG			0x02a0
#define RK3366_VOP_STATUS			0x02a4
#define RK3366_BLANKING_VALUE			0x02a8
#define RK3366_WIN0_DSP_BG			0x02b0
#define RK3366_WIN1_DSP_BG			0x02b4
#define RK3366_WIN2_DSP_BG			0x02b8
#define RK3366_WIN3_DSP_BG			0x02bc
#define RK3366_WIN2_LUT_ADDR			0x0400
#define RK3366_WIN3_LUT_ADDR			0x0800
#define RK3366_HWC_LUT_ADDR			0x0c00
#define RK3366_GAMMA0_LUT_ADDR			0x1000
#define RK3366_GAMMA1_LUT_ADDR			0x1400
#define RK3366_CABC_GAMMA_LUT_ADDR		0x1800
#define RK3366_MCU_BYPASS_WPORT			0x2200
#define RK3366_MCU_BYPASS_RPORT			0x2300
#define RK3366_MMU_DTE_ADDR			0x2400
#define RK3366_MMU_STATUS			0x2404
#define RK3366_MMU_COMMAND			0x2408
#define RK3366_MMU_PAGE_FAULT_ADDR		0x240c
#define RK3366_MMU_ZAP_ONE_LINE			0x2410
#define RK3366_MMU_INT_RAWSTAT			0x2414
#define RK3366_MMU_INT_CLEAR			0x2418
#define RK3366_MMU_INT_MASK			0x241c
#define RK3366_MMU_INT_STATUS			0x2420
#define RK3366_MMU_AUTO_GATING			0x2424

/* rk3399 register definition */
#define RK3399_REG_CFG_DONE			0x0000
#define RK3399_VERSION_INFO			0x0004
#define RK3399_SYS_CTRL				0x0008
#define RK3399_SYS_CTRL1			0x000c
#define RK3399_DSP_CTRL0			0x0010
#define RK3399_DSP_CTRL1			0x0014
#define RK3399_DSP_BG				0x0018
#define RK3399_MCU_CTRL				0x001c
#define RK3399_WB_CTRL0				0x0020
#define RK3399_WB_CTRL1				0x0024
#define RK3399_WB_YRGB_MST			0x0028
#define RK3399_WB_CBR_MST			0x002c
#define RK3399_WIN0_CTRL0			0x0030
#define RK3399_WIN0_CTRL1			0x0034
#define RK3399_WIN0_COLOR_KEY			0x0038
#define RK3399_WIN0_VIR				0x003c
#define RK3399_WIN0_YRGB_MST			0x0040
#define RK3399_WIN0_CBR_MST			0x0044
#define RK3399_WIN0_ACT_INFO			0x0048
#define RK3399_WIN0_DSP_INFO			0x004c
#define RK3399_WIN0_DSP_ST			0x0050
#define RK3399_WIN0_SCL_FACTOR_YRGB		0x0054
#define RK3399_WIN0_SCL_FACTOR_CBR		0x0058
#define RK3399_WIN0_SCL_OFFSET			0x005c
#define RK3399_WIN0_SRC_ALPHA_CTRL		0x0060
#define RK3399_WIN0_DST_ALPHA_CTRL		0x0064
#define RK3399_WIN0_FADING_CTRL			0x0068
#define RK3399_WIN0_CTRL2			0x006c
#define RK3399_WIN1_CTRL0			0x0070
#define RK3399_WIN1_CTRL1			0x0074
#define RK3399_WIN1_COLOR_KEY			0x0078
#define RK3399_WIN1_VIR				0x007c
#define RK3399_WIN1_YRGB_MST			0x0080
#define RK3399_WIN1_CBR_MST			0x0084
#define RK3399_WIN1_ACT_INFO			0x0088
#define RK3399_WIN1_DSP_INFO			0x008c
#define RK3399_WIN1_DSP_ST			0x0090
#define RK3399_WIN1_SCL_FACTOR_YRGB		0x0094
#define RK3399_WIN1_SCL_FACTOR_CBR		0x0098
#define RK3399_WIN1_SCL_OFFSET			0x009c
#define RK3399_WIN1_SRC_ALPHA_CTRL		0x00a0
#define RK3399_WIN1_DST_ALPHA_CTRL		0x00a4
#define RK3399_WIN1_FADING_CTRL			0x00a8
#define RK3399_WIN1_CTRL2			0x00ac
#define RK3399_WIN2_CTRL0			0x00b0
#define RK3399_WIN2_CTRL1			0x00b4
#define RK3399_WIN2_VIR0_1			0x00b8
#define RK3399_WIN2_VIR2_3			0x00bc
#define RK3399_WIN2_MST0			0x00c0
#define RK3399_WIN2_DSP_INFO0			0x00c4
#define RK3399_WIN2_DSP_ST0			0x00c8
#define RK3399_WIN2_COLOR_KEY			0x00cc
#define RK3399_WIN2_MST1			0x00d0
#define RK3399_WIN2_DSP_INFO1			0x00d4
#define RK3399_WIN2_DSP_ST1			0x00d8
#define RK3399_WIN2_SRC_ALPHA_CTRL		0x00dc
#define RK3399_WIN2_MST2			0x00e0
#define RK3399_WIN2_DSP_INFO2			0x00e4
#define RK3399_WIN2_DSP_ST2			0x00e8
#define RK3399_WIN2_DST_ALPHA_CTRL		0x00ec
#define RK3399_WIN2_MST3			0x00f0
#define RK3399_WIN2_DSP_INFO3			0x00f4
#define RK3399_WIN2_DSP_ST3			0x00f8
#define RK3399_WIN2_FADING_CTRL			0x00fc
#define RK3399_WIN3_CTRL0			0x0100
#define RK3399_WIN3_CTRL1			0x0104
#define RK3399_WIN3_VIR0_1			0x0108
#define RK3399_WIN3_VIR2_3			0x010c
#define RK3399_WIN3_MST0			0x0110
#define RK3399_WIN3_DSP_INFO0			0x0114
#define RK3399_WIN3_DSP_ST0			0x0118
#define RK3399_WIN3_COLOR_KEY			0x011c
#define RK3399_WIN3_MST1			0x0120
#define RK3399_WIN3_DSP_INFO1			0x0124
#define RK3399_WIN3_DSP_ST1			0x0128
#define RK3399_WIN3_SRC_ALPHA_CTRL		0x012c
#define RK3399_WIN3_MST2			0x0130
#define RK3399_WIN3_DSP_INFO2			0x0134
#define RK3399_WIN3_DSP_ST2			0x0138
#define RK3399_WIN3_DST_ALPHA_CTRL		0x013c
#define RK3399_WIN3_MST3			0x0140
#define RK3399_WIN3_DSP_INFO3			0x0144
#define RK3399_WIN3_DSP_ST3			0x0148
#define RK3399_WIN3_FADING_CTRL			0x014c
#define RK3399_HWC_CTRL0			0x0150
#define RK3399_HWC_CTRL1			0x0154
#define RK3399_HWC_MST				0x0158
#define RK3399_HWC_DSP_ST			0x015c
#define RK3399_HWC_SRC_ALPHA_CTRL		0x0160
#define RK3399_HWC_DST_ALPHA_CTRL		0x0164
#define RK3399_HWC_FADING_CTRL			0x0168
#define RK3399_HWC_RESERVED1			0x016c
#define RK3399_POST_DSP_HACT_INFO		0x0170
#define RK3399_POST_DSP_VACT_INFO		0x0174
#define RK3399_POST_SCL_FACTOR_YRGB		0x0178
#define RK3399_POST_RESERVED			0x017c
#define RK3399_POST_SCL_CTRL			0x0180
#define RK3399_POST_DSP_VACT_INFO_F1		0x0184
#define RK3399_DSP_HTOTAL_HS_END		0x0188
#define RK3399_DSP_HACT_ST_END			0x018c
#define RK3399_DSP_VTOTAL_VS_END		0x0190
#define RK3399_DSP_VACT_ST_END			0x0194
#define RK3399_DSP_VS_ST_END_F1			0x0198
#define RK3399_DSP_VACT_ST_END_F1		0x019c
#define RK3399_PWM_CTRL				0x01a0
#define RK3399_PWM_PERIOD_HPR			0x01a4
#define RK3399_PWM_DUTY_LPR			0x01a8
#define RK3399_PWM_CNT				0x01ac
#define RK3399_BCSH_COLOR_BAR			0x01b0
#define RK3399_BCSH_BCS				0x01b4
#define RK3399_BCSH_H				0x01b8
#define RK3399_BCSH_CTRL			0x01bc
#define RK3399_CABC_CTRL0			0x01c0
#define RK3399_CABC_CTRL1			0x01c4
#define RK3399_CABC_CTRL2			0x01c8
#define RK3399_CABC_CTRL3			0x01cc
#define RK3399_CABC_GAUSS_LINE0_0		0x01d0
#define RK3399_CABC_GAUSS_LINE0_1		0x01d4
#define RK3399_CABC_GAUSS_LINE1_0		0x01d8
#define RK3399_CABC_GAUSS_LINE1_1		0x01dc
#define RK3399_CABC_GAUSS_LINE2_0		0x01e0
#define RK3399_CABC_GAUSS_LINE2_1		0x01e4
#define RK3399_FRC_LOWER01_0			0x01e8
#define RK3399_FRC_LOWER01_1			0x01ec
#define RK3399_FRC_LOWER10_0			0x01f0
#define RK3399_FRC_LOWER10_1			0x01f4
#define RK3399_FRC_LOWER11_0			0x01f8
#define RK3399_FRC_LOWER11_1			0x01fc
#define RK3399_AFBCD0_CTRL			0x0200
#define RK3399_AFBCD0_HDR_PTR			0x0204
#define RK3399_AFBCD0_PIC_SIZE			0x0208
#define RK3399_AFBCD0_STATUS			0x020c
#define RK3399_AFBCD1_CTRL			0x0220
#define RK3399_AFBCD1_HDR_PTR			0x0224
#define RK3399_AFBCD1_PIC_SIZE			0x0228
#define RK3399_AFBCD1_STATUS			0x022c
#define RK3399_AFBCD2_CTRL			0x0240
#define RK3399_AFBCD2_HDR_PTR			0x0244
#define RK3399_AFBCD2_PIC_SIZE			0x0248
#define RK3399_AFBCD2_STATUS			0x024c
#define RK3399_AFBCD3_CTRL			0x0260
#define RK3399_AFBCD3_HDR_PTR			0x0264
#define RK3399_AFBCD3_PIC_SIZE			0x0268
#define RK3399_AFBCD3_STATUS			0x026c
#define RK3399_INTR_EN0				0x0280
#define RK3399_INTR_CLEAR0			0x0284
#define RK3399_INTR_STATUS0			0x0288
#define RK3399_INTR_RAW_STATUS0			0x028c
#define RK3399_INTR_EN1				0x0290
#define RK3399_INTR_CLEAR1			0x0294
#define RK3399_INTR_STATUS1			0x0298
#define RK3399_INTR_RAW_STATUS1			0x029c
#define RK3399_LINE_FLAG			0x02a0
#define RK3399_VOP_STATUS			0x02a4
#define RK3399_BLANKING_VALUE			0x02a8
#define RK3399_MCU_BYPASS_PORT			0x02ac
#define RK3399_WIN0_DSP_BG			0x02b0
#define RK3399_WIN1_DSP_BG			0x02b4
#define RK3399_WIN2_DSP_BG			0x02b8
#define RK3399_WIN3_DSP_BG			0x02bc
#define RK3399_YUV2YUV_WIN			0x02c0
#define RK3399_YUV2YUV_POST			0x02c4
#define RK3399_AUTO_GATING_EN			0x02cc
#define RK3399_WIN0_CSC_COE			0x03a0
#define RK3399_WIN1_CSC_COE			0x03c0
#define RK3399_WIN2_CSC_COE			0x03e0
#define RK3399_WIN3_CSC_COE			0x0400
#define RK3399_HWC_CSC_COE			0x0420
#define RK3399_BCSH_R2Y_CSC_COE			0x0440
#define RK3399_BCSH_Y2R_CSC_COE			0x0460
#define RK3399_POST_YUV2YUV_Y2R_COE		0x0480
#define RK3399_POST_YUV2YUV_3X3_COE		0x04a0
#define RK3399_POST_YUV2YUV_R2Y_COE		0x04c0
#define RK3399_WIN0_YUV2YUV_Y2R			0x04e0
#define RK3399_WIN0_YUV2YUV_3X3			0x0500
#define RK3399_WIN0_YUV2YUV_R2Y			0x0520
#define RK3399_WIN1_YUV2YUV_Y2R			0x0540
#define RK3399_WIN1_YUV2YUV_3X3			0x0560
#define RK3399_WIN1_YUV2YUV_R2Y			0x0580
#define RK3399_WIN2_YUV2YUV_Y2R			0x05a0
#define RK3399_WIN2_YUV2YUV_3X3			0x05c0
#define RK3399_WIN2_YUV2YUV_R2Y			0x05e0
#define RK3399_WIN3_YUV2YUV_Y2R			0x0600
#define RK3399_WIN3_YUV2YUV_3X3			0x0620
#define RK3399_WIN3_YUV2YUV_R2Y			0x0640
#define RK3399_WIN2_LUT_ADDR			0x1000
#define RK3399_WIN3_LUT_ADDR			0x1400
#define RK3399_HWC_LUT_ADDR			0x1800
#define RK3399_CABC_GAMMA_LUT_ADDR		0x1c00
#define RK3399_GAMMA_LUT_ADDR			0x2000
/* rk3399 register definition end */

/* rk3328 register definition end */
#define RK3328_REG_CFG_DONE			0x00000000
#define RK3328_VERSION_INFO			0x00000004
#define RK3328_SYS_CTRL				0x00000008
#define RK3328_SYS_CTRL1			0x0000000c
#define RK3328_DSP_CTRL0			0x00000010
#define RK3328_DSP_CTRL1			0x00000014
#define RK3328_DSP_BG				0x00000018
#define RK3328_AUTO_GATING_EN			0x0000003c
#define RK3328_LINE_FLAG			0x00000040
#define RK3328_VOP_STATUS			0x00000044
#define RK3328_BLANKING_VALUE			0x00000048
#define RK3328_WIN0_DSP_BG			0x00000050
#define RK3328_WIN1_DSP_BG			0x00000054
#define RK3328_DBG_PERF_LATENCY_CTRL0		0x000000c0
#define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0	0x000000c4
#define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0	0x000000c8
#define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0	0x000000cc
#define RK3328_INTR_EN0				0x000000e0
#define RK3328_INTR_CLEAR0			0x000000e4
#define RK3328_INTR_STATUS0			0x000000e8
#define RK3328_INTR_RAW_STATUS0			0x000000ec
#define RK3328_INTR_EN1				0x000000f0
#define RK3328_INTR_CLEAR1			0x000000f4
#define RK3328_INTR_STATUS1			0x000000f8
#define RK3328_INTR_RAW_STATUS1			0x000000fc
#define RK3328_WIN0_CTRL0			0x00000100
#define RK3328_WIN0_CTRL1			0x00000104
#define RK3328_WIN0_COLOR_KEY			0x00000108
#define RK3328_WIN0_VIR				0x0000010c
#define RK3328_WIN0_YRGB_MST			0x00000110
#define RK3328_WIN0_CBR_MST			0x00000114
#define RK3328_WIN0_ACT_INFO			0x00000118
#define RK3328_WIN0_DSP_INFO			0x0000011c
#define RK3328_WIN0_DSP_ST			0x00000120
#define RK3328_WIN0_SCL_FACTOR_YRGB		0x00000124
#define RK3328_WIN0_SCL_FACTOR_CBR		0x00000128
#define RK3328_WIN0_SCL_OFFSET			0x0000012c
#define RK3328_WIN0_SRC_ALPHA_CTRL		0x00000130
#define RK3328_WIN0_DST_ALPHA_CTRL		0x00000134
#define RK3328_WIN0_FADING_CTRL			0x00000138
#define RK3328_WIN0_CTRL2			0x0000013c
#define RK3328_DBG_WIN0_REG0			0x000001f0
#define RK3328_DBG_WIN0_REG1			0x000001f4
#define RK3328_DBG_WIN0_REG2			0x000001f8
#define RK3328_DBG_WIN0_RESERVED		0x000001fc
#define RK3328_WIN1_CTRL0			0x00000200
#define RK3328_WIN1_CTRL1			0x00000204
#define RK3328_WIN1_COLOR_KEY			0x00000208
#define RK3328_WIN1_VIR				0x0000020c
#define RK3328_WIN1_YRGB_MST			0x00000210
#define RK3328_WIN1_CBR_MST			0x00000214
#define RK3328_WIN1_ACT_INFO			0x00000218
#define RK3328_WIN1_DSP_INFO			0x0000021c
#define RK3328_WIN1_DSP_ST			0x00000220
#define RK3328_WIN1_SCL_FACTOR_YRGB		0x00000224
#define RK3328_WIN1_SCL_FACTOR_CBR		0x00000228
#define RK3328_WIN1_SCL_OFFSET			0x0000022c
#define RK3328_WIN1_SRC_ALPHA_CTRL		0x00000230
#define RK3328_WIN1_DST_ALPHA_CTRL		0x00000234
#define RK3328_WIN1_FADING_CTRL			0x00000238
#define RK3328_WIN1_CTRL2			0x0000023c
#define RK3328_DBG_WIN1_REG0			0x000002f0
#define RK3328_DBG_WIN1_REG1			0x000002f4
#define RK3328_DBG_WIN1_REG2			0x000002f8
#define RK3328_DBG_WIN1_RESERVED		0x000002fc
#define RK3328_WIN2_CTRL0			0x00000300
#define RK3328_WIN2_CTRL1			0x00000304
#define RK3328_WIN2_COLOR_KEY			0x00000308
#define RK3328_WIN2_VIR				0x0000030c
#define RK3328_WIN2_YRGB_MST			0x00000310
#define RK3328_WIN2_CBR_MST			0x00000314
#define RK3328_WIN2_ACT_INFO			0x00000318
#define RK3328_WIN2_DSP_INFO			0x0000031c
#define RK3328_WIN2_DSP_ST			0x00000320
#define RK3328_WIN2_SCL_FACTOR_YRGB		0x00000324
#define RK3328_WIN2_SCL_FACTOR_CBR		0x00000328
#define RK3328_WIN2_SCL_OFFSET			0x0000032c
#define RK3328_WIN2_SRC_ALPHA_CTRL		0x00000330
#define RK3328_WIN2_DST_ALPHA_CTRL		0x00000334
#define RK3328_WIN2_FADING_CTRL			0x00000338
#define RK3328_WIN2_CTRL2			0x0000033c
#define RK3328_DBG_WIN2_REG0			0x000003f0
#define RK3328_DBG_WIN2_REG1			0x000003f4
#define RK3328_DBG_WIN2_REG2			0x000003f8
#define RK3328_DBG_WIN2_RESERVED		0x000003fc
#define RK3328_WIN3_CTRL0			0x00000400
#define RK3328_WIN3_CTRL1			0x00000404
#define RK3328_WIN3_COLOR_KEY			0x00000408
#define RK3328_WIN3_VIR				0x0000040c
#define RK3328_WIN3_YRGB_MST			0x00000410
#define RK3328_WIN3_CBR_MST			0x00000414
#define RK3328_WIN3_ACT_INFO			0x00000418
#define RK3328_WIN3_DSP_INFO			0x0000041c
#define RK3328_WIN3_DSP_ST			0x00000420
#define RK3328_WIN3_SCL_FACTOR_YRGB		0x00000424
#define RK3328_WIN3_SCL_FACTOR_CBR		0x00000428
#define RK3328_WIN3_SCL_OFFSET			0x0000042c
#define RK3328_WIN3_SRC_ALPHA_CTRL		0x00000430
#define RK3328_WIN3_DST_ALPHA_CTRL		0x00000434
#define RK3328_WIN3_FADING_CTRL			0x00000438
#define RK3328_WIN3_CTRL2			0x0000043c
#define RK3328_DBG_WIN3_REG0			0x000004f0
#define RK3328_DBG_WIN3_REG1			0x000004f4
#define RK3328_DBG_WIN3_REG2			0x000004f8
#define RK3328_DBG_WIN3_RESERVED		0x000004fc

#define RK3328_HWC_CTRL0			0x00000500
#define RK3328_HWC_CTRL1			0x00000504
#define RK3328_HWC_MST				0x00000508
#define RK3328_HWC_DSP_ST			0x0000050c
#define RK3328_HWC_SRC_ALPHA_CTRL		0x00000510
#define RK3328_HWC_DST_ALPHA_CTRL		0x00000514
#define RK3328_HWC_FADING_CTRL			0x00000518
#define RK3328_HWC_RESERVED1			0x0000051c
#define RK3328_POST_DSP_HACT_INFO		0x00000600
#define RK3328_POST_DSP_VACT_INFO		0x00000604
#define RK3328_POST_SCL_FACTOR_YRGB		0x00000608
#define RK3328_POST_RESERVED			0x0000060c
#define RK3328_POST_SCL_CTRL			0x00000610
#define RK3328_POST_DSP_VACT_INFO_F1		0x00000614
#define RK3328_DSP_HTOTAL_HS_END		0x00000618
#define RK3328_DSP_HACT_ST_END			0x0000061c
#define RK3328_DSP_VTOTAL_VS_END		0x00000620
#define RK3328_DSP_VACT_ST_END			0x00000624
#define RK3328_DSP_VS_ST_END_F1			0x00000628
#define RK3328_DSP_VACT_ST_END_F1		0x0000062c
#define RK3328_BCSH_COLOR_BAR			0x00000640
#define RK3328_BCSH_BCS				0x00000644
#define RK3328_BCSH_H				0x00000648
#define RK3328_BCSH_CTRL			0x0000064c
#define RK3328_FRC_LOWER01_0			0x00000678
#define RK3328_FRC_LOWER01_1			0x0000067c
#define RK3328_FRC_LOWER10_0			0x00000680
#define RK3328_FRC_LOWER10_1			0x00000684
#define RK3328_FRC_LOWER11_0			0x00000688
#define RK3328_FRC_LOWER11_1			0x0000068c
#define RK3328_DBG_POST_REG0			0x000006e8
#define RK3328_DBG_POST_RESERVED		0x000006ec
#define RK3328_DBG_DATAO			0x000006f0
#define RK3328_DBG_DATAO_2			0x000006f4

/* sdr to hdr */
#define RK3328_SDR2HDR_CTRL			0x00000700
#define RK3328_EOTF_OETF_Y0			0x00000704
#define RK3328_RESERVED0001			0x00000708
#define RK3328_RESERVED0002			0x0000070c
#define RK3328_EOTF_OETF_Y1			0x00000710
#define RK3328_EOTF_OETF_Y64			0x0000080c
#define RK3328_OETF_DX_DXPOW1			0x00000810
#define RK3328_OETF_DX_DXPOW64			0x0000090c
#define RK3328_OETF_XN1				0x00000910
#define RK3328_OETF_XN63			0x00000a08

/* hdr to sdr */
#define RK3328_HDR2SDR_CTRL			0x00000a10
#define RK3328_HDR2SDR_SRC_RANGE		0x00000a14
#define RK3328_HDR2SDR_NORMFACEETF		0x00000a18
#define RK3328_RESERVED0003			0x00000a1c
#define RK3328_HDR2SDR_DST_RANGE		0x00000a20
#define RK3328_HDR2SDR_NORMFACCGAMMA		0x00000a24
#define RK3328_EETF_OETF_Y0			0x00000a28
#define RK3328_SAT_Y0				0x00000a2c
#define RK3328_EETF_OETF_Y1			0x00000a30
#define RK3328_SAT_Y1				0x00000ab0
#define RK3328_SAT_Y8				0x00000acc

#define RK3328_HWC_LUT_ADDR			0x00000c00

/* rk3036 register definition */
#define RK3036_SYS_CTRL			0x00
#define RK3036_DSP_CTRL0		0x04
#define RK3036_DSP_CTRL1		0x08
#define RK3036_INT_STATUS		0x10
#define RK3036_ALPHA_CTRL		0x14
#define RK3036_WIN0_COLOR_KEY		0x18
#define RK3036_WIN1_COLOR_KEY		0x1c
#define RK3036_WIN0_YRGB_MST		0x20
#define RK3036_WIN0_CBR_MST		0x24
#define RK3036_WIN1_VIR			0x28
#define RK3036_AXI_BUS_CTRL		0x2c
#define RK3036_WIN0_VIR			0x30
#define RK3036_WIN0_ACT_INFO		0x34
#define RK3036_WIN0_DSP_INFO		0x38
#define RK3036_WIN0_DSP_ST		0x3c
#define RK3036_WIN0_SCL_FACTOR_YRGB	0x40
#define RK3036_WIN0_SCL_FACTOR_CBR	0x44
#define RK3036_WIN0_SCL_OFFSET		0x48
#define RK3036_HWC_MST			0x58
#define RK3036_HWC_DSP_ST		0x5c
#define RK3036_DSP_HTOTAL_HS_END	0x6c
#define RK3036_DSP_HACT_ST_END		0x70
#define RK3036_DSP_VTOTAL_VS_END	0x74
#define RK3036_DSP_VACT_ST_END		0x78
#define RK3036_DSP_VS_ST_END_F1		0x7c
#define RK3036_DSP_VACT_ST_END_F1	0x80
#define RK3036_GATHER_TRANSFER		0x84
#define RK3036_VERSION_INFO		0x94
#define RK3036_REG_CFG_DONE		0x90
#define RK3036_WIN1_MST			0xa0
#define RK3036_WIN1_ACT_INFO		0xb4
#define RK3036_WIN1_DSP_INFO		0xb8
#define RK3036_WIN1_DSP_ST		0xbc
#define RK3036_WIN1_SCL_FACTOR_YRGB	0xc0
#define RK3036_WIN1_SCL_OFFSET		0xc8
#define RK3036_BCSH_CTRL		0xd0
#define RK3036_BCSH_COLOR_BAR		0xd4
#define RK3036_BCSH_BCS			0xd8
#define RK3036_BCSH_H			0xdc
#define RK3036_WIN1_LUT_ADDR		0x400
#define RK3036_HWC_LUT_ADDR		0x800
/* rk3036 register definition end */

/* rk3126 register definition */
#define RK3126_WIN1_MST			0x4c
#define RK3126_WIN1_DSP_INFO		0x50
#define RK3126_WIN1_DSP_ST		0x54
/* rk3126 register definition end */

/* px30 register definition */
#define PX30_REG_CFG_DONE			0x00000
#define PX30_VERSION				0x00004
#define PX30_DSP_BG				0x00008
#define PX30_MCU_CTRL				0x0000c
#define PX30_SYS_CTRL0				0x00010
#define PX30_SYS_CTRL1				0x00014
#define PX30_SYS_CTRL2				0x00018
#define PX30_DSP_CTRL0				0x00020
#define PX30_DSP_CTRL2				0x00028
#define PX30_VOP_STATUS				0x0002c
#define PX30_LINE_FLAG				0x00030
#define PX30_INTR_EN				0x00034
#define PX30_INTR_CLEAR				0x00038
#define PX30_INTR_STATUS			0x0003c
#define PX30_WIN0_CTRL0				0x00050
#define PX30_WIN0_CTRL1				0x00054
#define PX30_WIN0_COLOR_KEY			0x00058
#define PX30_WIN0_VIR				0x0005c
#define PX30_WIN0_YRGB_MST0			0x00060
#define PX30_WIN0_CBR_MST0			0x00064
#define PX30_WIN0_ACT_INFO			0x00068
#define PX30_WIN0_DSP_INFO			0x0006c
#define PX30_WIN0_DSP_ST			0x00070
#define PX30_WIN0_SCL_FACTOR_YRGB		0x00074
#define PX30_WIN0_SCL_FACTOR_CBR		0x00078
#define PX30_WIN0_SCL_OFFSET			0x0007c
#define PX30_WIN0_ALPHA_CTRL			0x00080
#define PX30_WIN1_CTRL0				0x00090
#define PX30_WIN1_CTRL1				0x00094
#define PX30_WIN1_VIR				0x00098
#define PX30_WIN1_MST				0x000a0
#define PX30_WIN1_DSP_INFO			0x000a4
#define PX30_WIN1_DSP_ST			0x000a8
#define PX30_WIN1_COLOR_KEY			0x000ac
#define PX30_WIN1_ALPHA_CTRL			0x000bc
#define PX30_HWC_CTRL0				0x000e0
#define PX30_HWC_CTRL1				0x000e4
#define PX30_HWC_MST				0x000e8
#define PX30_HWC_DSP_ST				0x000ec
#define PX30_HWC_ALPHA_CTRL			0x000f0
#define PX30_DSP_HTOTAL_HS_END			0x00100
#define PX30_DSP_HACT_ST_END			0x00104
#define PX30_DSP_VTOTAL_VS_END			0x00108
#define PX30_DSP_VACT_ST_END			0x0010c
#define PX30_DSP_VS_ST_END_F1			0x00110
#define PX30_DSP_VACT_ST_END_F1			0x00114
#define PX30_BCSH_CTRL				0x00160
#define PX30_BCSH_COL_BAR			0x00164
#define PX30_BCSH_BCS				0x00168
#define PX30_BCSH_H				0x0016c
#define PX30_FRC_LOWER01_0			0x00170
#define PX30_FRC_LOWER01_1			0x00174
#define PX30_FRC_LOWER10_0			0x00178
#define PX30_FRC_LOWER10_1			0x0017c
#define PX30_FRC_LOWER11_0			0x00180
#define PX30_FRC_LOWER11_1			0x00184
#define PX30_MCU_RW_BYPASS_PORT			0x0018c
#define PX30_WIN2_CTRL0				0x00190
#define PX30_WIN2_CTRL1				0x00194
#define PX30_WIN2_VIR0_1			0x00198
#define PX30_WIN2_VIR2_3			0x0019c
#define PX30_WIN2_MST0				0x001a0
#define PX30_WIN2_DSP_INFO0			0x001a4
#define PX30_WIN2_DSP_ST0			0x001a8
#define PX30_WIN2_COLOR_KEY			0x001ac
#define PX30_WIN2_ALPHA_CTRL			0x001bc
#define PX30_BLANKING_VALUE			0x001f4
#define PX30_FLAG_REG_FRM_VALID			0x001f8
#define PX30_FLAG_REG				0x001fc
#define PX30_HWC_LUT_ADDR			0x00600
#define PX30_GAMMA_LUT_ADDR			0x00a00
/* px30 register definition end */

/* rk3188 register definition */
#define RK3188_SYS_CTRL			0x00
#define RK3188_DSP_CTRL0		0x04
#define RK3188_DSP_CTRL1		0x08
#define RK3188_INT_STATUS		0x10
#define RK3188_WIN0_YRGB_MST0		0x20
#define RK3188_WIN0_CBR_MST0		0x24
#define RK3188_WIN0_YRGB_MST1		0x28
#define RK3188_WIN0_CBR_MST1		0x2c
#define RK3188_WIN_VIR			0x30
#define RK3188_WIN0_ACT_INFO		0x34
#define RK3188_WIN0_DSP_INFO		0x38
#define RK3188_WIN0_DSP_ST		0x3c
#define RK3188_WIN0_SCL_FACTOR_YRGB	0x40
#define RK3188_WIN0_SCL_FACTOR_CBR	0x44
#define RK3188_WIN1_MST			0x4c
#define RK3188_WIN1_DSP_INFO		0x50
#define RK3188_WIN1_DSP_ST		0x54
#define RK3188_DSP_HTOTAL_HS_END	0x6c
#define RK3188_DSP_HACT_ST_END		0x70
#define RK3188_DSP_VTOTAL_VS_END	0x74
#define RK3188_DSP_VACT_ST_END		0x78
#define RK3188_REG_CFG_DONE		0x90
/* rk3188 register definition end */

/* rk3066 register definition */
#define RK3066_SYS_CTRL0		0x00
#define RK3066_SYS_CTRL1		0x04
#define RK3066_DSP_CTRL0		0x08
#define RK3066_DSP_CTRL1		0x0c
#define RK3066_INT_STATUS		0x10
#define RK3066_MCU_CTRL			0x14
#define RK3066_BLEND_CTRL		0x18
#define RK3066_WIN0_COLOR_KEY_CTRL	0x1c
#define RK3066_WIN1_COLOR_KEY_CTRL	0x20
#define RK3066_WIN2_COLOR_KEY_CTRL	0x24
#define RK3066_WIN0_YRGB_MST0		0x28
#define RK3066_WIN0_CBR_MST0		0x2c
#define RK3066_WIN0_YRGB_MST1		0x30
#define RK3066_WIN0_CBR_MST1		0x34
#define RK3066_WIN0_VIR			0x38
#define RK3066_WIN0_ACT_INFO		0x3c
#define RK3066_WIN0_DSP_INFO		0x40
#define RK3066_WIN0_DSP_ST		0x44
#define RK3066_WIN0_SCL_FACTOR_YRGB	0x48
#define RK3066_WIN0_SCL_FACTOR_CBR	0x4c
#define RK3066_WIN0_SCL_OFFSET		0x50
#define RK3066_WIN1_YRGB_MST		0x54
#define RK3066_WIN1_CBR_MST		0x58
#define RK3066_WIN1_VIR			0x5c
#define RK3066_WIN1_ACT_INFO		0x60
#define RK3066_WIN1_DSP_INFO		0x64
#define RK3066_WIN1_DSP_ST		0x68
#define RK3066_WIN1_SCL_FACTOR_YRGB	0x6c
#define RK3066_WIN1_SCL_FACTOR_CBR	0x70
#define RK3066_WIN1_SCL_OFFSET		0x74
#define RK3066_WIN2_MST			0x78
#define RK3066_WIN2_VIR			0x7c
#define RK3066_WIN2_DSP_INFO		0x80
#define RK3066_WIN2_DSP_ST		0x84
#define RK3066_HWC_MST			0x88
#define RK3066_HWC_DSP_ST		0x8c
#define RK3066_HWC_COLOR_LUT0		0x90
#define RK3066_HWC_COLOR_LUT1		0x94
#define RK3066_HWC_COLOR_LUT2		0x98
#define RK3066_DSP_HTOTAL_HS_END	0x9c
#define RK3066_DSP_HACT_ST_END		0xa0
#define RK3066_DSP_VTOTAL_VS_END	0xa4
#define RK3066_DSP_VACT_ST_END		0xa8
#define RK3066_DSP_VS_ST_END_F1		0xac
#define RK3066_DSP_VACT_ST_END_F1	0xb0
#define RK3066_REG_CFG_DONE		0xc0
#define RK3066_MCU_BYPASS_WPORT		0x100
#define RK3066_MCU_BYPASS_RPORT		0x200
#define RK3066_WIN2_LUT_ADDR		0x400
#define RK3066_DSP_LUT_ADDR		0x800
/* rk3066 register definition end */

#endif /* _ROCKCHIP_VOP_REG_H */

 

 

 


edit2: better investingating
maybe 14 june 2020 is added a basic hdmi support for rk3228 ... (is valid also for rk3229 ?)
https://github.com/torvalds/linux/commit/53ffa1ee8de2cdfb0fcbef798486ba9c7f9316fd#diff-0f18fb301f41340ce62f8d1b44e1247e

evidenced code here:

Spoiler

 


drm/rockchip: dw_hdmi: add basic rk3228 support

Like the RK3328, RK322x SoCs offer a Synopsis DesignWare HDMI transmitter
and an Innosilicon HDMI PHY.

Add a new dw_hdmi_plat_data struct, rk3228_hdmi_drv_data.
Assign a set of mostly generic rk3228_hdmi_phy_ops functions.
Add dw_hdmi_rk3228_setup_hpd() to enable the HDMI HPD and DDC lines.





#include "rockchip_drm_drv.h"
#include "rockchip_drm_vop.h"
#include "rockchip_drm_vop.h"


#define RK3228_GRF_SOC_CON2		0x0408
#define RK3228_HDMI_SDAIN_MSK		BIT(14)
#define RK3228_HDMI_SCLIN_MSK		BIT(13)
#define RK3228_GRF_SOC_CON6		0x0418
#define RK3228_HDMI_HPD_VSEL		BIT(6)
#define RK3228_HDMI_SDA_VSEL		BIT(5)
#define RK3228_HDMI_SCL_VSEL		BIT(4)

 

 

 

 

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2 hours ago, usual user said:

Can you please attach your /var/log/Xorg.0.log?

Xorg driver as "rockchip"
Xorg.0_driver_as_rockchip.log
Xorg driver as "modesetting"
Xorg.0_driver_as_modesetting.log

 

Quote

That commit was in 2019 and should be available since 5.2.

my mistake, I don't know where I saw "2020" ,perhaps  searching and scrolling through this chronology I got confused with the latest HDMI commit
https://github.com/torvalds/linux/commits/master/drivers/gpu/drm/rockchip

 

what is the command to see the devices tree like the one you attached?

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Here my log analysis.

Xorg.0_driver_as_modesetting.log:

The Section "OutputClass" finds the rockchip KMS device and identifies the card node.

[    31.046] (**) OutputClass "dwhdmi-rockchip" setting /dev/dri/card0 as PrimaryGPU

No

Section "Device"
    Identifier   "KMS-1"
    Driver       "modesetting"
EndSection

so driver auto probing with modesetting and fbdev.

[    31.206] (II) LoadModule: "modesetting"
[    31.214] (II) LoadModule: "fbdev"

modesetting initializes with KMS device and glamor is loading.

[    31.262] (II) modeset(0): using drv /dev/dri/card0
[    31.285] (II) Loading sub module "glamoregl"

glamor is associating with GPU device

[    36.175] (II) modeset(0): glamor X acceleration enabled on Mali400

fbdev gets unloaded.

[    36.195] (II) UnloadModule: "fbdev"

All is set up properly and Xwindow is working as best as possibly with modesetting. modesetting does not use acceleration functions from KMS by design and shifts all 2D actions to the 3D GPU, regardless of whether it is emulated by software or accelerated by hardware.

You can test with the attached glxgears script started from a terminal window.

 

Xorg.0_driver_as_rockchip.log:

No "Section "OutputClass" so no KMS device identification.

No Section "Device" so driver auto probing with modesetting and fbdev.

[    53.702] (II) LoadModule: "modesetting"
[    53.704] (II) LoadModule: "fbdev"

modesetting initializes with GPU (Mali) device because of fall back.

[    53.694] 	falling back to /sys/devices/platform/20000000.gpu/drm/card1
[    53.707] (WW) Falling back to old probe method for modesetting

modesetting outputs to a not display capable device because a rendernode has no scan-out facility.

 

fbdev is associating with framebuffer device

[    54.354] (II) FBDEV(1): hardware: rockchipdrmfb (video memory: 3600kB)

I am confused what is going on here and not sure what this proves.

Now I see. In the end you get fbdev with swrast. With this stanza you should get the same observation in the performance:

Section "OutputClass"
    Identifier   "dwhdmi-rockchip"
    MatchDriver  "rockchip"
    Option       "PrimaryGPU"      "TRUE"
EndSection

Section "Device"
    Identifier   "KMS-1"
    Driver       "fbdev"
EndSection

 

4 hours ago, nokirunner said:

what is the command to see the devices tree like the one you attached?

"drmdevice" located at libdrm

glxgears

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3 hours ago, usual user said:

Now I see. In the end you get fbdev with swrast. With this stanza you should get the same observation in the performance:


Section "OutputClass"
    Identifier   "dwhdmi-rockchip"
    MatchDriver  "rockchip"
    Option       "PrimaryGPU"      "TRUE"
EndSection

Section "Device"
    Identifier   "KMS-1"
    Driver       "fbdev"
EndSection

 



with this configuration I get a decent "2d acceleration" on card0 there is no trace of glamoregl, and there is no trace of 3d acceleration, in fact MESA tells me that it is in softrender on cpu via llvmpipe

I also did a test putting modesetting in place of fbdev and glamoregl immediately comes back, 3d acceleration is activated on MALI, but there is a terribly slow 2D.

At this point I give up. it is evident there is something broken somewhere.

I would be curious to know if the same thing happens on other rk322x Major sister socs or is it just a problem of these rk322x socs

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2 hours ago, nokirunner said:

At this point I give up. it is evident there is something broken somewhere.

Everything is as expected.
 - modesetting doesn't have 2D acceleration, but 3D hardware acceleration support over glamour.
 - fbdev has some 2d acceleration via KMS frambuffer emulation, but no 3d hardware
   acceleration support.
 - armsoc seems to have no real 2d acceleration support and no 3d acceleration as I see
   no suitable sub module.

Wayland can use full KMS and 3d acceleration. E.g. Weston with the the drm-backend is running full accelerated. For example, to get a similar flow with Xwindow, armsoc must receive adequate KMS acceleration support and a sub module for 3D acceleration. But there is not much development for ddx drivers anymore. Every new development is Wayland focused. Think it's time to look for a suitable Waland compositor.

glmark2-es2-wayland.logglmark2-es2-Xwindow.log

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4 hours ago, usual user said:

- modesetting doesn't have 2D acceleration, but 3D hardware acceleration support over glamour.

Yes, but obviously something goes wrong with glamoregl, because not only is there no 2d acceleration, but everything becomes so slow that it is almost not usable.   In my opinion it is as if channels some registers that should use hardware of any kind for the correct use, but here something is not going well, which worsens the situation even compared to a context without acceleration at all. That's what I wanted to highlight.

all obviously refers to my hardware based on soc rk322x exsperience.

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On 8/25/2020 at 2:20 PM, jock said:

Hello, I updated the legacy images with the new kernel module.

If you want to upgrade without reinstalling the full system, you can install the kernel image package downloading it from here: <https://drive.google.com/file/d/1x1ReMTWc1ymEqHT8ahc9wZADfSQGkkCF/view?usp=sharing>

I didn't test the images, I guess they work though.

@Gabriel Vinicius did you then do a test with the ir and this new image? it works??

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On 8/18/2020 at 11:52 AM, hexdump said:

you might have a look at this, but you are on your own then (no warranties or support from my side) - for me it worked to get my h96max h2 which cannot boot from sd card too working by installing an adjusted u-boot - https://github.com/hexdump0815/u-boot-misc/blob/master/readme.rk3328-no-sd-boot

Been trying to build this SW on a Linux Mint laptop, when I get to "make PLAT=rk3328 DEBUG=1 bl31" the result is:

 

  CC      bl31/bl31_context_mgmt.c
gcc: error: unrecognized command line option ‘-mstrict-align’; did you mean ‘-Wstrict-aliasing’?
make: *** [Makefile:1070: build/rk3328/debug/bl31/bl31_context_mgmt.o] Error 1

 

Can somebody more experienced than me please give me a hint on what to do about it?

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@Reddwarf please keep on the subjects of the threads - this one here is about rk322x and not rk3328 ... to me it looks like you are trying to compile arm code on an intel machine maybe - for that you'll need to cross compile or compile native on an arm machine ... followup if needed please in a separate thread

 

best wishes - hexdump

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9 hours ago, usual user said:

Everything is as expected.
 - modesetting doesn't have 2D acceleration, but 3D hardware acceleration support over glamour.
 - fbdev has some 2d acceleration via KMS frambuffer emulation, but no 3d hardware
   acceleration support.
 - armsoc seems to have no real 2d acceleration support and no 3d acceleration as I see
   no suitable sub module.

Wayland can use full KMS and 3d acceleration. E.g. Weston with the the drm-backend is running full accelerated. For example, to get a similar flow with Xwindow, armsoc must receive adequate KMS acceleration support and a sub module for 3D acceleration. But there is not much development for ddx drivers anymore. Every new development is Wayland focused. Think it's time to look for a suitable Waland compositor.

glmark2-es2-wayland.log 2.81 kB · 2 downloads glmark2-es2-Xwindow.log 2.81 kB · 2 downloads

Thanks for the explanations, I read some of the DRM documentation from the linux kernel and understood some of the /dev/dri/card* and /dev/dri/render* things.

I took a look into the Lima driver to see some references, but I need to read the documentation again because there still are lots of shadows.

 

About the X11 modules, I'm a bit puzzled because I know that modesetting has 2D acceleration, but uses OpenGL to do drawing and compositing, so it uses the 3D capabilities to do 2D job, with horrible performance on our SoCs as we can see.

I'm pretty sure that in the old days when Lima was still not there, modesetting was just able to use KMS/DRM sort of "acceleration", with 2D performance on par with armsoc.

Armsoc has decent 2D performance on 4.4 kernel, but it should work also on mainline if you blacklist Lima driver. it used to work with Mali proprietary driver even on mainline kernel. I took a look into armsoc code, I see it loads EXA and fbdev submodules and nothing else, it provides an internal framework to implement some accelerated function via EXA: normally it is "null" acceleration (source file: armsoc_exa_null.c), but there also forks which use 2D blocks provided by hardware like this for Samsung Exynos which, I suppose, leverages G2D acceleration (see: armsoc_exa_g2d.c).

By the way, when Armsoc is paired with Mali proprietary kernel driver and Mali proprietary userland OpenGL ES libraries, allows accelerated 3D graphics even on mainline kernel via regular DRM dumb buffers. I tested it a lot on rk3288 (Mali T760-MP4), but never really tried on rk322x. If you use modesetting driver along with proprietary Mali things, you can't have 3D acceleration.

This makes up my last confused thought: why armsoc, even without any paired submodule, allows 3D acceleration? Also, looking into the rockchip repository for something interesting, I found a libdrm fork with an implementation of rockchip_drm library that uses the RGA 2D blocks: https://github.com/rockchip-linux/libdrm-rockchip

It is flagged as "deprecated", but maybe could be used to implement some decent 2D... but don't see any direct connection to 3D bits (maybe it is hidden behind the Buffer Object creation via kernel DRM IOCTLs?)

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12 hours ago, jock said:

I know that modesetting has 2D acceleration, but uses OpenGL to do drawing and compositing, so it uses the 3D capabilities to do 2D job, with horrible performance on our SoCs as we can see.

This is all about where the memory is located where the operations takes place. In PC world there is only one "GPU" IP. It is implementing everything. Display engine for scan-out and GPU for OpenGL. Once the GPU has rendered directly to the scan-out memory the hardware of the display subsystem outputs it to the monitor. So offloading anything on OpenGl is a good idea. It is a device independent standard and doing composition for movie video is also a fast path. There is no need to support display subsystem acceleration in the CPU area.

But we are dealing with SOCs. They have several IPs where the memory they are dealing with is separated. I.e. They need to pass around memory buffers so that they can work on data that they share. The buffer format has to be identical between different IPs otherwise  you have to convert. A "dumb buffer" format is always possible but you loose acceleration features of special formats. But this requires device dependent knowledge. E.g. a display subsystem may support NV12 format for scan-out. Uploading NV12 data for compositing on the 3d GPU and then forwarding via dump buffer to the display subsystem will not improve the performance, but forwarding via dma_buf to the display subsystem will.

The impact of improper buffer pass around can be seen by the uploaded glmark2 logs. The 3d performance is decreasing cause the GPU can not be served fast enough.
The armada driver implements buffer pass around via etnaviv_gpu for i.MX6 in a device dependent manner and uses dma_buf for zero copy.  See buffer-flow.pdf for the ways the buffers have to travel. modesetting and armsoc are missing this support, hence the low performance. Maybe the armada source can serve as a template for what is required.

12 hours ago, jock said:

I'm pretty sure that in the old days when Lima was still not there, modesetting was just able to use KMS/DRM sort of "acceleration", with 2D performance on par with armsoc.

As both use the same method for buffer pass around, this is expected. modesetting is only optimized for PC like scenarios.

 

12 hours ago, jock said:

Armsoc has decent 2D performance on 4.4 kernel, but it should work also on mainline if you blacklist Lima driver.

Armsoc is only dealing with the display subsystem. It does not interact with lima or panfrost it is falling back to swrast as no armsoc_dri for mainline is available.

 (EE) AIGLX error: dlopen of /usr/lib64/dri/armsoc_dri.so failed (/usr/lib64/dri/armsoc_dri.so: cannot open shared object file: No such file or directory)
 (EE) AIGLX error: unable to load driver armsoc
 (II) IGLX: Loaded and initialized swrast
 (II) GLX: Initialized DRISWRAST GL provider for screen 0

In the Mali proprietary case that code took care for the proper buffer pass around via the proprietary kernel interface. But that doesn't belong in the Mesa counterpart, as it only cares about OpenGL and it doesn't matter how IPs interact. It provides only buffer import and export. For mainline in xorg the submodule is the proper place. For Weston it is the drm-backend which it already has.

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this is where the big players start playing and everything becomes so dark that I can only catch small shreds of light. :lol:

but I try to ask a question:
why when we force "modesetting" on card1 we have 2D acceleration but the 3D acceleration disappears? or rather, it is channeled to the cpu through softrender llvmpipe ...
wouldn't it be the easiest way to try  change the code by telling it to use the 3d acceleration libraries in these conditions?
do you think it is possible to do such a thing?

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@nokirunner and others

pardon if i say a totally dumb thing, but on legacy kernel there was a way to obtain both x org and accelerated things:

was to EXIT xserver with a init 3 , go into a shell and from there , from cli, launch the appropriate video player with appropriate libraries.
It is necessary to unload some dll and charge back some others.

 

At least on 4.4
When it comes mainline kernel I hold my arms in air 

Again this is what PERSONALLY have understood ater 1.000.000 of post read :mellow: :D

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18 hours ago, hexdump said:

@Reddwarf please keep on the subjects of the threads - this one here is about rk322x and not rk3328 ... to me it looks like you are trying to compile arm code on an intel machine maybe - for that you'll need to cross compile or compile native on an arm machine ... followup if needed please in a separate thread

 

best wishes - hexdump

Started a new topic about building problems on ARM platform, can you please help?

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1 hour ago, fabiobassa said:

At least on 4.4
When it comes mainline kernel I hold my arms in air 

well, lately I got excited with the mainline kernel for more reasons, I thought that with a bit of cunning and a few tricks I would be able to fit both accelerations by force ... well it's obvious that it's not as simple as I thought ..
I did this also because I see the 4.4 kernel as a dead end, we might as well concentrate the forces with the new ones, also because many improvements are still in sight, both on the gpu side and in other functions in general. (hoping these problems with the rk322x socs will be solved)

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