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kalikopfnuss

h6 allwinner tv box need help!!!!

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I have a small problem I have quite a lot of sites as well as forum sites visited and find a solution my tv box h6 allwinner see picture. I would like to operate tv box with linux would nice who you may have a few helpful tips have Thank you.

 

 

ich habe ein kleines problem ich habe schon ziehmlich viele webseiten so wie forum seiten besucht und finde ein keine lösung meine tv box h6 allwinner siehe bild .

ich würde gerne tv box mit linux betreiben wäre schön wen ihr eventuell ein paar hilfreicht tips hab

danke.

h6.png

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Since with the ARM architecture it is not only necessary to know which components are soldered on the SBC but also know how exactly they are connected each other it is elementary to know if and which common (by Armbian supported) SBC the TV box is built around if it is not a custom built by the manufacturer.

 

And even then it might not help you since the Allwinner H6 and all boards based on it are still in development state and do not come with any support.

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this box i would not recommend: one i got was in the end 2+16g instead of the promised 4+32g - furthermore the allwinner h6 u-boot is not booting it (maybe some new memory timing issues - the cpu is a h6 for sure, i checked) and i was not able to get a serial console working on it - there are connection points, which look very much like serial, but i was only able to get garbage from it ...

 

@jernej - there was someone on the libreelec forum, who had problems too with another box not booting well due to probably memory timing issues - do you have any idea of how to potentially solve this? do you maybe have an idea what might be wrong with the serial console? i tried all possible combinations of serial settings, but only get garbage on boot and without working serial output it is hard to debug the boot problems ...

 

best wishes - hexdump

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its not a trivial problem (i usually get serial consoles working easily) - i tried close to all speeds etc. ... its either that the connectors are not for the serial console (but they really look like: 4 connectors, one is mass, another seems to be vcc and the other two in the middle go directly to the soc chip), there are maybe some electrical components missing to make it work properly or u-boot output is somehow scrambled (never seen something like this so far) ... these are at least my guesses ...

 

best wishes - hexdump

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18 hours ago, hexdump said:

there was someone on the libreelec forum, who had problems too with another box not booting well due to probably memory timing issues - do you have any idea of how to potentially solve this?

Unfortunatelly no. It's hard to do anything without HW.

18 hours ago, hexdump said:

do you maybe have an idea what might be wrong with the serial console? i tried all possible combinations of serial settings, but only get garbage on boot and without working serial output it is hard to debug the boot problems ...

At this point logic analyzer would be very helpful. Do you have one? Anyway, Android should be very chatty over serial...

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@jernej - update :) ... i finally discovered a proper serial console on this one, so at least the sending port (somewhere hidden in the middle of the board), so that i can at least see the boot output now ... i tried to boot your latest nightly tanix tx6 libreelec build and got:

 

U-Boot SPL 2020.01-rc1 (Jan 03 2020 - 13:07:27 +0100)
DRAM:Error while initializing DRAM PHY!

resetting ...

U-Boot SPL 2020.01-rc1 (Jan 03 2020 - 13:07:27 +0100)
DRAM:Error while initializing DRAM PHY!

resetting ...

U-Boot SPL 2020.01-rc1 (Jan 03 2020 - 13:07:27 +0100)
DRAM: 2048 MiB
Trying to boot from MMC1
NOTICE:  BL31: v2.1(release):9.0.0-2414-g587404e2e1
NOTICE:  BL31: Built : 11:56:22, Jan  3 2020
NOTICE:  BL31: Detected Allwinner H6 SoC (1728)
NOTICE:  BL31: Found U-Boot DTB at 0xc07a970, model: Eachlink H6 Mini
NOTICE:  PMIC: Probing AXP805
ER

 

which looks interesting - usually it just loops with the error, but it looks like sometimes it manages to initialize things halfway properly ... do you have any idea how to maybe move on from here?

 

here is the serial port output of the stock android stuff: https://pastebin.com/raw/VMi3Hi9B

 

a lot of thanks in advance and best wishes - hexdump

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@jernej - i have just closed the box after soldering the serial connection to it :) ... but i checked before and all chips were super micro d9prz if that makes sense ... worst case i can open it again

 

update: reopened :) ... the top four have 3x 3hk77 + 1x 3fk77 and the bottom ones are 1x 3ek77, 2x fk77 and 1x 3hk77 ... the box has in theory 2gb of ram, but according to google the chips would be the 4g - ?

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5 minutes ago, hexdump said:

but i checked before and all chips were super micro d9prz if that makes sense ...

I can't find anything under that name. BTW, Android boot log would also help - at the very beginning, RAM configuration is printed although in a bit encrypted form.

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@jernej - yes - all of them and above the d9prz there is the 3xk77 marking like i updated it 3 postings up

 

update: MT41K512M4DA-107:K would mean, that the 2gb the box is supposed to have are correct then ...

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So I guess 3xk77 means lot number. It seems that eventually DRAM controller is properly initialized, so it can be some kind of timing issue. I'll make a patch which will make verbose output of RAM initialization so we can see where it went wrong a bit later.

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But for starters, you can add "#define DEBUG" at the very top of the file (before includes) arch/arm/mach-sunxi/dram_sun50i_h6.c. This should print some more info.

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@jernej - this is the output with DEBUG enabled:

 

U-Boot SPL 2019.07-rc4-17588-g0229ee3784-dirty (Jan 05 2020 - 19:01:02 +0100)
DRAM:PLL = b0003600
DRAM PHY PGSR0 = 20003d
DRAM PHY DX0RSR0 = 0
DRAM PHY DX1RSR0 = 0
DRAM PHY DX2RSR0 = 0
DRAM PHY DX3RSR0 = 0
Error while initializing DRAM PHY!

resetting ...

 

as i was not sure which u-boot sources to use i used https://github.com/jernejsk/u-boot/tree/h6-ddr3-half-dq with the eachlink_h6_mini_defconfig as i remember that this one was working the last time i played around with the h6 u-boot - should i maybe use another one?

 

i also searched for my old u-boot 32/64bit build with the libdram blob which gives me (maybe gives you some hints too?):

 

U-Boot SPL 2018.11-g458f795e53-dirty (Jun 06 2019 - 18:37:37 +0200)
DRAM:DRAM VERSION IS V2_2
DRAM CLK =840 MHZ
DRAM Type =3 (3:DDR3,4:DDR4,6:LPDDR2,7:LPDDR3)
DRAM zq value: 3b3bfb
IPRD=590059--PGCR0=f7d--PLL=b0004500
DRAM SIZE =2048 M
DRAM simple test OK.
 2048 MiB
Trying to boot from MMC1
NOTICE:  BL31: v2.0(debug):v2.0-337-g19b56cf4
NOTICE:  BL31: Built : 00:08:51, Dec  6 2018
NOTICE:  BL31: Detected Allwinner H6 SoC (1728)
NOTICE:  BL31: Found U-Boot DTB at 0xc06dc20, model: Eachlink H6 Mini
INFO:    ARM GICv2 driver initialized
NOTICE:  PMIC: Probing AXP805
IN

 

best wishes - hexdump

 

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@jernej - yes, always DRAM PHY PGSR0 = 20003d

 

update: in case this helps - this is the boot0 timing dumped from emmc as described here: https://github.com/apritzel/u-boot/issues/4#issuecomment-500612569 running a fully 32bit u-boot with libdram and bl31 blob from the H6 1.0 BSP u-boot included into apritzels eachlink mainline u-boot - this one boots to the u-boot cmdline at least :)

 

.dram_clk = 648,
.dram_type = 3,
.dram_zq = 0x3b3bfb,
.dram_odt_en = 1,
.dram_para1 = 0x30fb,
.dram_para2 = 0x08000000,
.dram_mr0 = 0x1a70,
.dram_mr1 = 0x40,
.dram_mr2 = 0x18,
.dram_mr3 = 0x0,
.dram_mr4 = 0x0,
.dram_mr5 = 0x400,
.dram_mr6 = 0x848,
.dram_tpr0 = 0x1248a152,
.dram_tpr1 = 0x11b1a94d,
.dram_tpr2 = 0x0067204f,
.dram_tpr3 = 0x78787896,
.dram_tpr4 = 0x0,
.dram_tpr5 = 0x0,
.dram_tpr6 = 0x09090900,
.dram_tpr7 = 0x1e36a142,
.dram_tpr8 = 0x0,
.dram_tpr9 = 0x0,
.dram_tpr10 = 0x0,
.dram_tpr11 = 0x0,
.dram_tpr12 = 0x1212,
.dram_tpr13 = 0x6003,

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@hexdump what about http://ix.io/26IG ? Now I'm nitpicking differences between mainline U-Boot and libdram. Not sure what is the issue. Worst case would be to print out all DRAM PHY registers and compare them with libdram...

 

EDIT: Issue is in Write Leveling alghoritm (0x200000), but I don't know why. Timings should be more or less same as in libdram.

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@hexdump I'm using upstream U-Boot, currently at 8d8ee47e03 ("env: Add CONFIG_SYS_RELOC_GD_ENV_ADDR symbol"). All relevant patches were merged upstream for some time now, so there is no reason to use forks at this point.

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@jernej - sadly still the same:

 

U-Boot SPL 2020.01-rc3-00007-g8d8ee47e03-dirty (Jan 07 2020 - 21:51:23 +0100)
DRAM:PLL = b0003600
DRAM PHY PGSR0 = 20003d
DRAM PHY DX0RSR0 = 0
DRAM PHY DX1RSR0 = 0
DRAM PHY DX2RSR0 = 0
DRAM PHY DX3RSR0 = 0
Error while initializing DRAM PHY!

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