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About jernej

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  1. Yes, you are missing something. Lima doesn't support video decoding. What you need is Cedrus. But using it is another story (currently a mess).
  2. @hexdump another patch to test:
  3. @hexdump can you please read out location 0x3006100 with either devmem from Linux or md.b from U-Boot? I suspect it will be 7, but it might be 3.
  4. I'm not sure, Android settings should work
  5. @hexdump that would be changed only in config file (CONFIG_DRAM_CLK). BTW, semi working variant is set to lower frequency.
  6. @hexdump Out of curiosity, why do you have different DRAM PLL settings in different reports? In this one frequency is 576 MHz (DRAM:PLL = b0003500) but for example in this one is 672 MHz (DRAM:PLL = b0003600). Did you change that in config file? Edit: According to Android boot log, it should be set to 576 MHz. Can you try if lowering frequency helps?
  7. @hexdump it really seems to be ATF issue. Try to comment out AXP805 initialization and make sure DT you are using doesn't have nodes for it. If still doesn't work, I suggest you contact apritzel.
  8. @hexdump Interesting, so mainline U-Boot fails in ATF, no matter which DRAM init method is used (libdram vs open source)? I think it can be related to the fact that we have old libdram ("V2_2"), while Android you have uses newer version ("V2_78"). Let's try to find newer blob... In worst case we could also analyze dumped U-Boot from your box, but a lot of information would be omitted. Can you try ? I changed two fields according to Zynq documentation with similar DRAM controller. This may be fixed in newer libdram versions... edit: this one is V2_5: edit2: and this V2_7: but now I don't know where to look for newer ones...
  9. @hexdump there is only one more DDR3 PHY specific difference I could find:
  10. @hexdump I'm using upstream U-Boot, currently at 8d8ee47e03 ("env: Add CONFIG_SYS_RELOC_GD_ENV_ADDR symbol"). All relevant patches were merged upstream for some time now, so there is no reason to use forks at this point.
  11. @hexdump what about ? Now I'm nitpicking differences between mainline U-Boot and libdram. Not sure what is the issue. Worst case would be to print out all DRAM PHY registers and compare them with libdram... EDIT: Issue is in Write Leveling alghoritm (0x200000), but I don't know why. Timings should be more or less same as in libdram.
  12. @hexdump is error always the same, e.g. you always see DRAM PHY PGSR0 = 20003d ?
  13. @hexdump what about ?
  14. can you dump DT file from running Android? It holds few other DRAM settings which are important.
  15. @hexdump not really, DRAM initialization is pretty SoC specific.