Jump to content

Efforts to develop firmware for H96 MAX V56 RK3566 4G/32G


Hqnicolas

Recommended Posts

ūüŹÜ¬†help to add other boards in armbian standart, you don't need to be a programmer to help the community,
just need a copy of the ARM BOARD and a x86 computer to compile new versions.

 

If you like what you see here and want to help: Donate Armbian, the like button only costs a few dollars.

Armbian Needs you help!


This Armbian adventure was summarized in my Public Github Repository.

 

                            Tutorial SD-Card Version v0.5 ARMBIAN23 BETA unofficial

 

 

 

Software description:

V0.5 = @armbian The Armbian SD card image "Compiled From Armbian Project"

V0.8 = @hzdm Project with Mainline Bootloader "Boot the 64gb Emmc Armbian with Mainline Rockchip"
V0.9 = @hzdm Release Mainline Bootloader "Boot the 32gb and 64gb Emmc Armbian with Mainline Rockchip"

V1.0 = @hotnikq The Armbian SD card inside the Android Legacy Rockchip Image "Glued Image: Android boot for Linux" 

V1.2 = @ning Release Device Tree and Bootloader to longterm 6.6.27 Kernel "Boot with Mainline Rockchip"

V1.3 = @Hqnicolas Github PR Enable h96 Rk3566 TV-Box device for Kernel 6.8

 

Video drivers:
https://developer.arm.com/downloads/-/mali-drivers/bifrost-kernel 

https://docs.mesa3d.org/download.html 

https://docs.mesa3d.org/drivers/panfrost.html 

 

Wifi Drivers:
https://drive.google.com/file/d/1B1LmAylalETcnBEWiPiJHL0MjK5xlIV4/view?usp=sharing

 

Or Just Live install Wifi Driver:

cd /lib/firmware/brcm/
sudo wget https://github.com/LibreELEC/brcmfmac_sdio-firmware/raw/master/BCM4335A0.hcd
sudo wget https://github.com/CoreELEC/brcmfmac_sdio-firmware-aml/raw/master/firmware/brcm/fw_bcm4335b0_ag.bin
sudo ln -s fw_bcm4335b0_ag.bin brcmfmac4335-sdio.h96-TVbox,rk3566.bin
sudo reboot now

nmcli dev wifi

 

Quote

sudo cat > /lib/firmware/brcm/brcmfmac4335-sdio.txt << "EOF"
# bcm94335wlcspMS_ES50_RC171p24p23_04052013_AM_mdfy_PAparam.txt -- 4/5/2013 by Murata, based on bcm94335wlcspMS_ES50_RC171p24p20_04022013_AM.txt, changed PA parameters and txidxcap parameters and ccode.
# bcm94335wlcspMS_ES50_RC171p24p20_04022013_AM.txt -- 4/2/2013 by Broadcom Corporation
# Use with AARDVARK_REL_6_30_171_24_23 -- Murata BCM4335 WLCSP 11AC Module
# Sample variables file for Murata Type-XJ ES5.0 (0x00 0x11) -- bcm94335wlcspMS_AM_P400.txt as original
sromrev=11
boardrev=0x1500
boardtype=0x064b
boardflags=0x10401001
boardflags2=0x0
#updated boardflags3 for forcing to enable external LPO
boardflags3=0x0800c08b
macaddr=00:90:4c:c5:12:38
#ccode modified by Murata
#ccode=0
ccode=XS
regrev=0
antswitch=0
pdgain5g=1
pdgain2g=1
tworangetssi2g=0
tworangetssi5g=0
femctrl=4
vendid=0x14e4
devid=0x43ae
manfid=0x2d0
#prodid=0x052e
nocrc=1
#otpimagesize=502
xtalfreq=37400
extpagain2g=1
extpagain5g=1
rxgains2gelnagaina0=2
rxgains2gtrisoa0=6
rxgains2gtrelnabypa0=1
rxgains5gelnagaina0=3
rxgains5gtrisoa0=5
rxgains5gtrelnabypa0=1
rxchain=1
txchain=1
aa2g=1
aa5g=1
ag0=0
ag1=0
tssipos5g=1
tssipos2g=1
#PA parameters (2G20M/2G40M/5G20M/5G40M/5G80M)
#PA parameters modified by Murata
#pa2ga0=-208,6208,-764
#pa2ga1=-203,6429,-793
#pa5ga0=-167,5736,-685,-157,5669,-670,-157,5548,-665,-141,5621,-664
#pa5ga1=-101,6543,-735,-99,6452,-731,-147,5743,-695,-75,6468,-723
#pa5ga2=-172,5903,-708,-160,5868,-698,-113,6264,-722,-125,5915,-684
pa2ga0=0xff31,0x1759,0xFD1D
pa2ga1=0xff35,0x18BB,0xFCEC
pa5ga0=0xff78,0x1715,0xFD49,0xff89,0x1714,0xFD57,0xff86,0x1652,0xFD62,0xffa9,0x1760,0xFD5E
pa5ga1=0xff56,0x1596,0xFD5F,0xff88,0x1764,0xFD45,0xff89,0x1632,0xFD65,0xff69,0x160E,0xFD49
pa5ga2=0xff5a,0x1667,0xFD4E,0xff5f,0x15F7,0xFD5E,0xff5a,0x1531,0xFD68,0xff6e,0x1587,0xFD6A
# Default Target Power for 2G -- 17dBm(11)/14dBm(54)/13dBm(MCS7,MCS8)/16dBm(6,MCS0)
maxp2ga0=74
cckbw202gpo=0
cckbw20ul2gpo=0
dot11agofdmhrbw202gpo=0x6666
ofdmlrbw202gpo=0x0022
mcsbw202gpo=0x88866662
# Default Target Power for 5G -- 14dBm(54)/13dBm(HT20-MCS7,VHT20-MCS8)/12dBm(HT40-MCS7,VHT40-MCS9)/11dBm(VHT80-MCS8/MCS9)/16dBm(6,20HT-MCS0)
maxp5ga0=74,74,74,74
# Low
mcslr5glpo=0
mcsbw205glpo=0x88866662
mcsbw405glpo=0xAAA88884
mcsbw805glpo=0xCCCAAAA6
# Mid
mcslr5gmpo=0
mcsbw205gmpo=0x88866662
mcsbw405gmpo=0xAAA88884
mcsbw805gmpo=0xCCCAAAA6
# High
mcslr5ghpo=0
mcsbw205ghpo=0x88866662
mcsbw405ghpo=0xAAA88884
mcsbw805ghpo=0xCCCAAAA6
#20MHz High Rate
sb20in40hrpo=0x0
sb20in80and160hr5glpo=0x0
sb20in80and160hr5gmpo=0x0
sb20in80and160hr5ghpo=0x0
#40MHz High Rate
sb40and80hr5glpo=0x0
sb40and80hr5gmpo=0x0
sb40and80hr5ghpo=0x0
#20MHz Low Rate
sb20in40lrpo=0x0
sb20in80and160lr5glpo=0x0
sb20in80and160lr5gmpo=0x0
sb20in80and160lr5ghpo=0x0
#40MHz Low Rate
sb40and80lr5glpo=0x0
sb40and80lr5gmpo=0x0
sb40and80lr5ghpo=0x0
dot11agduphrpo=0x0
dot11agduplrpo=0x0
tssifloor2g=80
tssifloor5g=160,190,240,260
#rpcal:use with 171.17 or later, compensates filter ripple
rpcal2g=0x0
rpcal5gb0=0x0
#cckdigfilttype[0-7] 0:default
cckdigfilttype=2
phycal_tempdelta=25
#GPIO 0 for SDIO HW OOB interruption
muxenab=0x10
#sd_gpout=0
#sd_oobonly=1
rssicorrnorm_c0=-3,-2
rssicorrnorm5g_c0=-1,0,-3,-1,0,-3,-3,-2,-4,-3,-2,-4
#txidxcap2g and txidxcap5g modified by Murata
#txidxcap2g=32
#txidxcap5g=44
txidxcap2g=36
txidxcap5g=36
paparambwver=1
EOF

 

sudo rmmod brcmfmac_wcc brcmfmac brcmutil
modprobe brcmfmac

 

Topic description:

This topic aims to demonstrate the path taken to the Armibian EMMC solution.
In our path we create a lot of ready-to-use ROM files, some users burn an use this images without learning with the Linux compilation process.

the name of the topic is efforts but that's no effort at all, you should try compile your own images.


Device Capability Test: Using Rockchip SoCs NPU.
Drivers: https://github.com/rockchip-linux/rknpu2
User Guide: https://github.com/rockchip-linux/rknpu2/blob/master/doc/Rockchip_RKNPU_User_Guide_RKNN_API_V1.4.0_EN.pdf
OpenCV: https://opencv.org/blog/2022/11/29/working-with-neural-processing-units-npus-using-opencv/
A discussion on Reddit: https://www.reddit.com/r/OrangePI/comments/12b3jmj/accessing_the_npu_on_the_orange_pi/

Transformers models: https://github.com/usefulsensors/useful-transformers
Usage: https://www.crowdsupply.com/useful-sensors/ai-in-a-box/
Usage: https://youtu.be/pN8mKZ5wpdQ



d0533304-bac1-4e4b-b135-c1cfb661583b.jpg

 

 

 

 

 

Edited by Hqnicolas
Link to comment
Share on other sites

moved

 

The images mentioned above are provided by a 3rd party that is not affiliated with the Armbian project. As with all downloads on the internet special precaution should be taken when using unofficial stuff.

Link to comment
Share on other sites

decompile DTS Files 
 

Quote

/dts-v1/;

/ {
    compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566";
    interrupt-parent = <0x1>;
    #address-cells = <0x2>;
    #size-cells = <0x2>;
    model = "Rockchip RK3566 EVB3 DDR3 V10 Board";

    ddr_timing {
        compatible = "rockchip,ddr-timing";
        ddr2_speed_bin = <0x0>;
        ddr3_speed_bin = <0x15>;
        ddr4_speed_bin = <0xc>;
        pd_idle = <0xd>;
        sr_idle = <0x5d>;
        sr_mc_gate_idle = <0x0>;
        srpd_lite_idle = <0x0>;
        standby_idle = <0x0>;
        auto_pd_dis_freq = <0x42a>;
        auto_sr_dis_freq = <0x320>;
        ddr2_dll_dis_freq = <0x12c>;
        ddr3_dll_dis_freq = <0x12c>;
        ddr4_dll_dis_freq = <0x271>;
        phy_dll_dis_freq = <0x190>;
        ddr2_odt_dis_freq = <0x64>;
        phy_ddr2_odt_dis_freq = <0x64>;
        ddr2_drv = <0x2>;
        ddr2_odt = <0x40>;
        phy_ddr2_ca_drv = <0x0>;
        phy_ddr2_ck_drv = <0x0>;
        phy_ddr2_dq_drv = <0x0>;
        phy_ddr2_odt = <0x0>;
        ddr3_odt_dis_freq = <0x14d>;
        phy_ddr3_odt_dis_freq = <0x14d>;
        ddr3_drv = <0x2>;
        ddr3_odt = <0x40>;
        phy_ddr3_ca_drv = <0x0>;
        phy_ddr3_ck_drv = <0x0>;
        phy_ddr3_dq_drv = <0x0>;
        phy_ddr3_odt = <0x0>;
        phy_lpddr2_odt_dis_freq = <0x14d>;
        lpddr2_drv = <0x2>;
        phy_lpddr2_ca_drv = <0x0>;
        phy_lpddr2_ck_drv = <0x0>;
        phy_lpddr2_dq_drv = <0x0>;
        phy_lpddr2_odt = <0x0>;
        lpddr3_odt_dis_freq = <0x14d>;
        phy_lpddr3_odt_dis_freq = <0x14d>;
        lpddr3_drv = <0x1>;
        lpddr3_odt = <0x2>;
        phy_lpddr3_ca_drv = <0x0>;
        phy_lpddr3_ck_drv = <0x0>;
        phy_lpddr3_dq_drv = <0x0>;
        phy_lpddr3_odt = <0x0>;
        lpddr4_odt_dis_freq = <0x14d>;
        phy_lpddr4_odt_dis_freq = <0x14d>;
        lpddr4_drv = <0x30>;
        lpddr4_dq_odt = <0x1>;
        lpddr4_ca_odt = <0x0>;
        phy_lpddr4_ca_drv = <0x0>;
        phy_lpddr4_ck_cs_drv = <0x0>;
        phy_lpddr4_dq_drv = <0x0>;
        phy_lpddr4_odt = <0x0>;
        ddr4_odt_dis_freq = <0x271>;
        phy_ddr4_odt_dis_freq = <0x271>;
        ddr4_drv = <0x0>;
        ddr4_odt = <0x200>;
        phy_ddr4_ca_drv = <0x0>;
        phy_ddr4_ck_drv = <0x0>;
        phy_ddr4_dq_drv = <0x0>;
        phy_ddr4_odt = <0x0>;
        phandle = <0xa8>;
    };

    aliases {
        csi2dphy0 = "/csi2-dphy0";
        csi2dphy1 = "/csi2-dphy1";
        csi2dphy2 = "/csi2-dphy2";
        dsi0 = "/dsi@fe060000";
        dsi1 = "/dsi@fe070000";
        ethernet1 = "/ethernet@fe010000";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        i2c0 = "/i2c@fdd40000";
        i2c1 = "/i2c@fe5a0000";
        i2c2 = "/i2c@fe5b0000";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mmc0 = "/dwmmc@fe2b0000";
        mmc1 = "/dwmmc@fe2c0000";
        mmc2 = "/sdhci@fe310000";
        mmc3 = "/dwmmc@fe000000";
        serial0 = "/serial@fdd50000";
        serial1 = "/serial@fe650000";
        serial2 = "/serial@fe660000";
        serial3 = "/serial@fe670000";
        serial4 = "/serial@fe680000";
        serial5 = "/serial@fe690000";
        serial6 = "/serial@fe6a0000";
        serial7 = "/serial@fe6b0000";
        serial8 = "/serial@fe6c0000";
        serial9 = "/serial@fe6d0000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
    };

    cpus {
        #address-cells = <0x2>;
        #size-cells = <0x0>;

        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x0>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            #cooling-cells = <0x2>;
            dynamic-power-coefficient = <0xbb>;
            cpu-supply = <0x5>;
            phandle = <0x9>;

            power-model {
                compatible = "simple-power-model";
                leakage-range = <0xa 0x28>;
                ls = <0xffffdc14 0x18d8 0x0>;
                static-coefficient = <0x186a0>;
                ts = <0x1476e 0x3263d 0xffffef34 0x47>;
                thermal-zone = "soc-thermal";
            };
        };

        cpu@100 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x100>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            phandle = <0xa>;
        };

        cpu@200 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x200>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            phandle = <0xb>;
        };

        cpu@300 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x300>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            phandle = <0xc>;
        };

        idle-states {
            entry-method = "psci";

            cpu-sleep {
                compatible = "arm,idle-state";
                local-timer-stop;
                arm,psci-suspend-param = <0x10000>;
                entry-latency-us = <0x64>;
                exit-latency-us = <0x78>;
                min-residency-us = <0x3e8>;
                phandle = <0x4>;
            };
        };
    };

    cpu0-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0x6 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,pvtm-voltage-sel = <0x0 0x14050 0x0 0x14051 0x16b48 0x1 0x16b49 0x186a0 0x2>;
        rockchip,pvtm-freq = <0x639c0>;
        rockchip,pvtm-volt = <0xdbba0>;
        rockchip,pvtm-ch = <0x0 0x5>;
        rockchip,pvtm-sample-time = <0x3e8>;
        rockchip,pvtm-number = <0xa>;
        rockchip,pvtm-error = <0x3e8>;
        rockchip,pvtm-ref-temp = <0x28>;
        rockchip,pvtm-temp-prop = <0x1a 0x1a>;
        rockchip,thermal-zone = "soc-thermal";
        rockchip,temp-hysteresis = <0x1388>;
        rockchip,low-temp = <0x0>;
        rockchip,low-temp-adjust-volt = <0x0 0x648 0x124f8>;
        phandle = <0x3>;

        opp-408000000 {
            opp-hz = <0x0 0x18519600>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            status = "disabled";
        };

        opp-600000000 {
            opp-hz = <0x0 0x23c34600>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            status = "disabled";
        };

        opp-816000000 {
            opp-hz = <0x0 0x30a32c00>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            opp-suspend;
            status = "disabled";
        };

        opp-1104000000 {
            opp-hz = <0x0 0x41cdb400>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            status = "disabled";
        };

        opp-1416000000 {
            opp-hz = <0x0 0x54667200>;
            opp-microvolt = <0xe1d48 0xe1d48 0x118c30>;
            clock-latency-ns = <0x9c40>;
        };

        opp-1608000000 {
            opp-hz = <0x0 0x5fd82200>;
            opp-microvolt = <0xf4240 0xf4240 0x118c30>;
            clock-latency-ns = <0x9c40>;
        };

        opp-1800000000 {
            opp-hz = <0x0 0x6b49d200>;
            opp-microvolt = <0x100590 0x100590 0x118c30>;
            clock-latency-ns = <0x9c40>;
        };
    };

    arm-pmu {
        compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
        interrupts = <0x0 0xe4 0x4 0x0 0xe5 0x4 0x0 0xe6 0x4 0x0 0xe7 0x4>;
        interrupt-affinity = <0x9 0xa 0xb 0xc>;
    };

    cpuinfo {
        compatible = "rockchip,cpuinfo";
        nvmem-cells = <0xd 0xe 0xf>;
        nvmem-cell-names = "id", "cpu-version", "cpu-code";
    };

    display-subsystem {
        compatible = "rockchip,display-subsystem";
        memory-region = <0x10 0x11>;
        memory-region-names = "drm-logo", "drm-cubic-lut";
        ports = <0x12>;
        devfreq = <0x13>;
        phandle = <0x134>;

        route {

            route-dsi0 {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x14>;
                phandle = <0x135>;
            };

            route-dsi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x15>;
                phandle = <0x136>;
            };

            route-edp {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x16>;
                phandle = <0x137>;
            };

            route-hdmi {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x17>;
                phandle = <0x138>;
            };

            route-lvds {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x18>;
                phandle = <0x139>;
            };

            route-rgb {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x19>;
                phandle = <0x13a>;
            };
        };
    };

    firmware {

        optee {
            compatible = "linaro,optee-tz";
            method = "smc";
            phandle = <0x13b>;
        };

        scmi {
            compatible = "arm,scmi-smc";
            shmem = <0x1a>;
            arm,smc-id = <0x82000010>;
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            phandle = <0x13c>;

            protocol@14 {
                reg = <0x14>;
                #clock-cells = <0x1>;
                rockchip,clk-init = "Tfr";
                phandle = <0x2>;
            };
        };

        sdei {
            compatible = "arm,sdei-1.0";
            method = "smc";
            phandle = <0x13d>;
        };
    };

    mpp-srv {
        compatible = "rockchip,mpp-service";
        rockchip,taskqueue-count = <0x6>;
        rockchip,resetgroup-count = <0x6>;
        status = "okay";
        phandle = <0x67>;
    };

    psci {
        compatible = "arm,psci-1.0";
        method = "smc";
    };

    reserved-memory {
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        phandle = <0x13e>;

        drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x0 0x0 0x0 0x0>;
            phandle = <0x10>;
        };

        drm-cubic-lut@00000000 {
            compatible = "rockchip,drm-cubic-lut";
            reg = <0x0 0x0 0x0 0x0>;
            phandle = <0x11>;
        };

        linux,cma {
            compatible = "shared-dma-pool";
            inactive;
            reusable;
            reg = <0x0 0x10000000 0x0 0x800000>;
            linux,cma-default;
        };

        ramoops@110000 {
            compatible = "ramoops";
            reg = <0x0 0x110000 0x0 0xf0000>;
            record-size = <0x20000>;
            console-size = <0x80000>;
            ftrace-size = <0x0>;
            pmsg-size = <0x50000>;
            phandle = <0x13f>;
        };
    };

    rockchip-suspend {
        compatible = "rockchip,pm-rk3568";
        status = "okay";
        rockchip,sleep-debug-en = <0x1>;
        rockchip,sleep-mode-config = <0x4e4>;
        rockchip,wakeup-config = <0x2001>;
        rockchip,virtual-poweroff = <0x1>;
        phandle = <0x140>;
    };

    rockchip-system-monitor {
        compatible = "rockchip,system-monitor";
        rockchip,thermal-zone = "soc-thermal";
        phandle = <0x141>;
    };

    thermal-zones {
        phandle = <0x142>;

        soc-thermal {
            polling-delay-passive = <0x14>;
            polling-delay = <0x3e8>;
            sustainable-power = <0x5c3>;
            thermal-sensors = <0x1b 0x0>;
            phandle = <0x143>;

            trips {

                trip-point-0 {
                    temperature = <0x11170>;
                    hysteresis = <0x7d0>;
                    type = "passive";
                    phandle = <0x144>;
                };

                trip-point-1 {
                    temperature = <0x14c08>;
                    hysteresis = <0x7d0>;
                    type = "passive";
                    phandle = <0x1c>;
                };

                soc-crit {
                    temperature = <0x1c138>;
                    hysteresis = <0x7d0>;
                    type = "critical";
                    phandle = <0x145>;
                };
            };

            cooling-maps {

                map0 {
                    trip = <0x1c>;
                    cooling-device = <0x9 0xffffffff 0xffffffff>;
                    contribution = <0x400>;
                };

                map1 {
                    trip = <0x1c>;
                    cooling-device = <0x1d 0xffffffff 0xffffffff>;
                    contribution = <0x400>;
                };
            };
        };

        gpu-thermal {
            polling-delay-passive = <0x14>;
            polling-delay = <0x3e8>;
            thermal-sensors = <0x1b 0x1>;
            phandle = <0x146>;
        };
    };

    timer {
        compatible = "arm,armv8-timer";
        interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
        arm,no-tick-in-suspend;
    };

    external-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x7735940>;
        clock-output-names = "gmac1_clkin";
        #clock-cells = <0x0>;
        phandle = <0x147>;
    };

    xpcs-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x7735940>;
        clock-output-names = "clk_gmac1_xpcs_mii";
        #clock-cells = <0x0>;
        phandle = <0x148>;
    };

    i2s1-mclkin-rx {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s1_mclkin_rx";
        phandle = <0x149>;
    };

    i2s1-mclkin-tx {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s1_mclkin_tx";
        phandle = <0x14a>;
    };

    i2s2-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s2_mclkin";
        phandle = <0x14b>;
    };

    i2s3-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s3_mclkin";
        phandle = <0x14c>;
    };

    mpll {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0x2faf0800>;
        clock-output-names = "mpll";
        phandle = <0x14d>;
    };

    xin24m {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0x16e3600>;
        clock-output-names = "xin24m";
        phandle = <0x14e>;
    };

    xin32k {
        compatible = "fixed-clock";
        clock-frequency = <0x8000>;
        clock-output-names = "xin32k";
        #clock-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x1e>;
        phandle = <0x14f>;
    };

    scmi-shmem@10f000 {
        compatible = "arm,scmi-shmem";
        reg = <0x0 0x10f000 0x0 0x100>;
        phandle = <0x1a>;
    };

    sata@fc400000 {
        compatible = "snps,dwc-ahci";
        reg = <0x0 0xfc400000 0x0 0x1000>;
        clocks = <0x1f 0x9b 0x1f 0x9c 0x1f 0x9d>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x0 0x5f 0x4>;
        interrupt-names = "hostc";
        phys = <0x20 0x1>;
        phy-names = "sata-phy";
        ports-implemented = <0x1>;
        power-domains = <0x21 0xf>;
        status = "disabled";
        phandle = <0x150>;
    };

    sata@fc800000 {
        compatible = "snps,dwc-ahci";
        reg = <0x0 0xfc800000 0x0 0x1000>;
        clocks = <0x1f 0xa0 0x1f 0xa1 0x1f 0xa2>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x0 0x60 0x4>;
        interrupt-names = "hostc";
        phys = <0x22 0x1>;
        phy-names = "sata-phy";
        ports-implemented = <0x1>;
        power-domains = <0x21 0xf>;
        status = "disabled";
        phandle = <0x151>;
    };

    usbdrd {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x1f 0xa6 0x1f 0xa7 0x1f 0xa5 0x1f 0x7f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        status = "okay";
        phandle = <0x152>;

        dwc3@fcc00000 {
            compatible = "snps,dwc3";
            reg = <0x0 0xfcc00000 0x0 0x400000>;
            interrupts = <0x0 0xa9 0x4>;
            dr_mode = "host";
            phys = <0x23>;
            phy-names = "usb2-phy";
            phy_type = "utmi_wide";
            power-domains = <0x21 0xf>;
            resets = <0x1f 0x94>;
            reset-names = "usb3-otg";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            extcon = <0x24>;
            maximum-speed = "high-speed";
            snps,dis_u2_susphy_quirk;
            phandle = <0x153>;
        };
    };

    usbhost {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x1f 0xa9 0x1f 0xaa 0x1f 0xa8 0x1f 0x7f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        status = "okay";
        phandle = <0x154>;

        dwc3@fd000000 {
            compatible = "snps,dwc3";
            reg = <0x0 0xfd000000 0x0 0x400000>;
            interrupts = <0x0 0xaa 0x4>;
            dr_mode = "host";
            phys = <0x25 0x20 0x4>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            power-domains = <0x21 0xf>;
            resets = <0x1f 0x95>;
            reset-names = "usb3-host";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            phandle = <0x155>;
        };
    };

    interrupt-controller@fd400000 {
        compatible = "arm,gic-v3";
        #interrupt-cells = <0x3>;
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        interrupt-controller;
        reg = <0x0 0xfd400000 0x0 0x10000 0x0 0xfd460000 0x0 0xc0000>;
        interrupts = <0x1 0x9 0x4>;
        phandle = <0x1>;

        interrupt-controller@fd440000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x1>;
            reg = <0x0 0xfd440000 0x0 0x20000>;
            phandle = <0xab>;
        };
    };

    usb@fd800000 {
        compatible = "generic-ehci";
        reg = <0x0 0xfd800000 0x0 0x40000>;
        interrupts = <0x0 0x82 0x4>;
        clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x27>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x156>;
    };

    usb@fd840000 {
        compatible = "generic-ohci";
        reg = <0x0 0xfd840000 0x0 0x40000>;
        interrupts = <0x0 0x83 0x4>;
        clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x27>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x157>;
    };

    usb@fd880000 {
        compatible = "generic-ehci";
        reg = <0x0 0xfd880000 0x0 0x40000>;
        interrupts = <0x0 0x85 0x4>;
        clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x28>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x158>;
    };

    usb@fd8c0000 {
        compatible = "generic-ohci";
        reg = <0x0 0xfd8c0000 0x0 0x40000>;
        interrupts = <0x0 0x86 0x4>;
        clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x28>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x159>;
    };

    syscon@fda00000 {
        compatible = "rockchip,rk3568-xpcs", "syscon";
        reg = <0x0 0xfda00000 0x0 0x200000>;
        status = "disabled";
        phandle = <0x15a>;
    };

    syscon@fdc20000 {
        compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
        reg = <0x0 0xfdc20000 0x0 0x10000>;
        phandle = <0x33>;

        io-domains {
            compatible = "rockchip,rk3568-pmu-io-voltage-domain";
            status = "okay";
            pmuio1-supply = <0x29>;
            pmuio2-supply = <0x29>;
            vccio1-supply = <0x2a>;
            vccio3-supply = <0x2b>;
            vccio4-supply = <0x2c>;
            vccio5-supply = <0x2d>;
            vccio6-supply = <0x2c>;
            vccio7-supply = <0x2d>;
            phandle = <0x15b>;
        };

        reboot-mode {
            compatible = "syscon-reboot-mode";
            offset = <0x200>;
            mode-bootloader = <0x5242c301>;
            mode-charge = <0x5242c30b>;
            mode-fastboot = <0x5242c309>;
            mode-loader = <0x5242c301>;
            mode-normal = <0x5242c300>;
            mode-recovery = <0x5242c303>;
            mode-ums = <0x5242c30c>;
            mode-panic = <0x5242c307>;
            mode-watchdog = <0x5242c308>;
            phandle = <0x15c>;
        };
    };

    syscon@fdc50000 {
        compatible = "rockchip,rk3568-pipegrf", "syscon";
        reg = <0x0 0xfdc50000 0x0 0x1000>;
        phandle = <0x104>;
    };

    syscon@fdc60000 {
        compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
        reg = <0x0 0xfdc60000 0x0 0x10000>;
        phandle = <0x32>;

        io-domains {
            compatible = "rockchip,rk3568-io-voltage-domain";
            status = "disabled";
            phandle = <0x15d>;
        };

        lvds {
            compatible = "rockchip,rk3568-lvds";
            phys = <0x2e>;
            phy-names = "phy";
            status = "disabled";
            phandle = <0x15e>;

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;
                    #address-cells = <0x1>;
                    #size-cells = <0x0>;

                    endpoint@1 {
                        reg = <0x1>;
                        remote-endpoint = <0x18>;
                        status = "disabled";
                        phandle = <0x8b>;
                    };

                    endpoint@2 {
                        reg = <0x2>;
                        remote-endpoint = <0x2f>;
                        status = "disabled";
                        phandle = <0x8c>;
                    };
                };
            };
        };

        rgb {
            compatible = "rockchip,rk3568-rgb";
            pinctrl-names = "default";
            pinctrl-0 = <0x30>;
            status = "disabled";
            phandle = <0x15f>;

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;
                    #address-cells = <0x1>;
                    #size-cells = <0x0>;

                    endpoint@2 {
                        reg = <0x2>;
                        remote-endpoint = <0x19>;
                        status = "disabled";
                        phandle = <0x8d>;
                    };
                };
            };
        };
    };

    syscon@fdc70000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x0 0xfdc70000 0x0 0x1000>;
        phandle = <0x160>;
    };

    syscon@fdc80000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x0 0xfdc80000 0x0 0x1000>;
        phandle = <0x105>;
    };

    syscon@fdc90000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x0 0xfdc90000 0x0 0x1000>;
        phandle = <0x106>;
    };

    syscon@fdca0000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x0 0xfdca0000 0x0 0x8000>;
        phandle = <0x10b>;
    };

    syscon@fdca8000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x0 0xfdca8000 0x0 0x8000>;
        phandle = <0x10e>;
    };

    edp-phy@fdcb0000 {
        compatible = "rockchip,rk3568-edp-phy";
        reg = <0x0 0xfdcb0000 0x0 0x8000>;
        clocks = <0x31 0x29 0x1f 0x192>;
        clock-names = "refclk", "pclk";
        resets = <0x1f 0x1d6>;
        reset-names = "apb";
        #phy-cells = <0x0>;
        status = "okay";
        phandle = <0xa4>;
    };

    sram@fdcc0000 {
        compatible = "mmio-sram";
        reg = <0x0 0xfdcc0000 0x0 0xb000>;
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        ranges = <0x0 0x0 0xfdcc0000 0xb000>;
        phandle = <0x161>;

        rkvdec-sram@0 {
            reg = <0x0 0xb000>;
            phandle = <0x6f>;
        };
    };

    clock-controller@fdd00000 {
        compatible = "rockchip,rk3568-pmucru";
        reg = <0x0 0xfdd00000 0x0 0x1000>;
        rockchip,grf = <0x32>;
        rockchip,pmugrf = <0x33>;
        #clock-cells = <0x1>;
        #reset-cells = <0x1>;
        assigned-clocks = <0x31 0x32>;
        assigned-clock-parents = <0x31 0x5>;
        phandle = <0x31>;
    };

    clock-controller@fdd20000 {
        compatible = "rockchip,rk3568-cru";
        reg = <0x0 0xfdd20000 0x0 0x1000>;
        rockchip,grf = <0x32>;
        #clock-cells = <0x1>;
        #reset-cells = <0x1>;
        assigned-clocks = <0x31 0x5 0x1f 0x106 0x1f 0x10b 0x31 0x1 0x31 0x2b 0x1f 0x3 0x1f 0x19b 0x1f 0x9 0x1f 0x19c 0x1f 0x19d 0x1f 0x1a1 0x1f 0x19e 0x1f 0x19f 0x1f 0x1a0 0x1f 0x4 0x1f 0x10d 0x1f 0x10e 0x1f 0x173 0x1f 0x174 0x1f 0x175 0x1f 0x176 0x1f 0xc9 0x1f 0xca 0x1f 0x6 0x1f 0x7e 0x1f 0x7f 0x1f 0x3d 0x1f 0x41 0x1f 0x45 0x1f 0x49 0x1f 0x4d 0x1f 0x4d 0x1f 0x55 0x1f 0x51 0x1f 0x5d 0x1f 0xdd>;
        assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
        assigned-clock-parents = <0x31 0x8 0x1f 0x4 0x1f 0x4>;
        phandle = <0x1f>;
    };

    i2c@fdd40000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfdd40000 0x0 0x1000>;
        clocks = <0x31 0x7 0x31 0x2d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x2e 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0x34>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x162>;

        pmic@20 {
            compatible = "rockchip,rk809";
            reg = <0x20>;
            interrupt-parent = <0x35>;
            interrupts = <0x3 0x8>;
            pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
            pinctrl-0 = <0x36>;
            pinctrl-1 = <0x37 0x38>;
            pinctrl-2 = <0x39 0x3a>;
            pinctrl-3 = <0x39 0x3b>;
            rockchip,system-power-controller;
            wakeup-source;
            #clock-cells = <0x1>;
            clock-output-names = "rk808-clkout1", "rk808-clkout2";
            pmic-reset-func = <0x0>;
            not-save-power-en = <0x1>;
            vcc1-supply = <0x3c>;
            vcc2-supply = <0x3c>;
            vcc3-supply = <0x3c>;
            vcc4-supply = <0x3c>;
            vcc5-supply = <0x3c>;
            vcc6-supply = <0x3c>;
            vcc7-supply = <0x3c>;
            vcc8-supply = <0x3c>;
            vcc9-supply = <0x3c>;
            phandle = <0x12c>;

            pwrkey {
                status = "okay";
            };

            pinctrl_rk8xx {
                gpio-controller;
                #gpio-cells = <0x2>;
                phandle = <0x163>;

                rk817_slppin_null {
                    pins = "gpio_slp";
                    function = "pin_fun0";
                    phandle = <0x164>;
                };

                rk817_slppin_slp {
                    pins = "gpio_slp";
                    function = "pin_fun1";
                    phandle = <0x38>;
                };

                rk817_slppin_pwrdn {
                    pins = "gpio_slp";
                    function = "pin_fun2";
                    phandle = <0x3a>;
                };

                rk817_slppin_rst {
                    pins = "gpio_slp";
                    function = "pin_fun3";
                    phandle = <0x3b>;
                };
            };

            regulators {

                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x7a120>;
                    regulator-max-microvolt = <0x149970>;
                    regulator-init-microvolt = <0xdbba0>;
                    regulator-ramp-delay = <0x1771>;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vdd_logic";
                    phandle = <0x62>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x7a120>;
                    regulator-max-microvolt = <0x149970>;
                    regulator-init-microvolt = <0xdbba0>;
                    regulator-ramp-delay = <0x1771>;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vdd_gpu";
                    phandle = <0x64>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vcc_ddr";
                    phandle = <0x165>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                    };
                };

                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x7a120>;
                    regulator-max-microvolt = <0x149970>;
                    regulator-init-microvolt = <0xdbba0>;
                    regulator-ramp-delay = <0x1771>;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vdd_npu";
                    phandle = <0x5f>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG1 {
                    regulator-boot-on;
                    regulator-always-on;
                    regulator-min-microvolt = <0xdbba0>;
                    regulator-max-microvolt = <0xdbba0>;
                    regulator-name = "vdda0v9_image";
                    phandle = <0x166>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0xdbba0>;
                    regulator-max-microvolt = <0xdbba0>;
                    regulator-name = "vdda_0v9";
                    phandle = <0x167>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0xdbba0>;
                    regulator-max-microvolt = <0xdbba0>;
                    regulator-name = "vdda0v9_pmu";
                    phandle = <0x168>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0xdbba0>;
                    };
                };

                LDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x325aa0>;
                    regulator-max-microvolt = <0x325aa0>;
                    regulator-name = "vccio_acodec";
                    phandle = <0x2a>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x325aa0>;
                    regulator-name = "vccio_sd";
                    phandle = <0x2b>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x325aa0>;
                    regulator-max-microvolt = <0x325aa0>;
                    regulator-name = "vcc3v3_pmu";
                    phandle = <0x29>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x325aa0>;
                    };
                };

                LDO_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcca_1v8";
                    phandle = <0x103>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcca1v8_pmu";
                    phandle = <0x169>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x1b7740>;
                    };
                };

                LDO_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcca1v8_image";
                    phandle = <0x16a>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcc_1v8";
                    phandle = <0x2c>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                SWITCH_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc_3v3";
                    phandle = <0x2d>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                SWITCH_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc3v3_sd";
                    phandle = <0xac>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };

            codec {
                #sound-dai-cells = <0x0>;
                compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
                clocks = <0x1f 0x1a4>;
                clock-names = "mclk";
                assigned-clocks = <0x1f 0x1a4 0x1f 0x1a8>;
                assigned-clock-rates = <0xbb8000>;
                assigned-clock-parents = <0x1f 0x54 0x1f 0x1a4>;
                pinctrl-names = "default";
                pinctrl-0 = <0x3d>;
                hp-volume = <0x14>;
                spk-volume = <0x3>;
                mic-in-differential;
                status = "okay";
                phandle = <0x125>;
            };
        };

        tcs4526@10 {
            compatible = "tcs,tcs452x";
            reg = <0x10>;
            vin-supply = <0x3e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x100590>;
            regulator-max-microvolt = <0x1535b0>;
            regulator-ramp-delay = <0x8fc>;
            fcs,suspend-voltage-selector = <0x1>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x5>;

            regulator-state-mem {
                regulator-off-in-suspend;
            };
        };
    };

    serial@fdd50000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfdd50000 0x0 0x100>;
        interrupts = <0x0 0x74 0x4>;
        clocks = <0x31 0xb 0x31 0x2c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x0 0x3f 0x1>;
        pinctrl-names = "default";
        pinctrl-0 = <0x40>;
        status = "disabled";
        phandle = <0x16b>;
    };

    pwm@fdd70000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfdd70000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x41>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x16c>;
    };

    pwm@fdd70010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfdd70010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x42>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x16d>;
    };

    pwm@fdd70020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfdd70020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x43>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x16e>;
    };

    pwm@fdd70030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x0 0xfdd70030 0x0 0x10>;
        interrupts = <0x0 0x52 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "default";
        pinctrl-0 = <0x44>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "okay";
        remote_pwm_id = <0x3>;
        handle_cpu_id = <0x1>;
        remote_support_psci = <0x0>;
        phandle = <0x16f>;

        ir_key1 {
            rockchip,usercode = <0x4040>;
            rockchip,key_table = <0xf2 0xe8 0xbd 0x9e 0xf4 0x67 0xf1 0x6c 0xef 0x69 0xee 0x6a 0xe5 0x66 0xe7 0x73 0xe8 0x72 0xb2 0x74 0xbc 0x71 0xec 0x8b 0xbf 0x190 0xe0 0x191 0xe1 0x192 0xe9 0xb7 0xe6 0xf8 0xe8 0xb9 0xe7 0xba 0xf0 0x184 0xbe 0x175>;
        };

        ir_key2 {
            rockchip,usercode = <0xff00>;
            rockchip,key_table = <0xf9 0x66 0xbf 0x9e 0xfb 0x8b 0xaa 0xe8 0xb9 0x67 0xe9 0x6c 0xb8 0x69 0xea 0x6a 0xeb 0x72 0xef 0x73 0xf7 0x71 0xe7 0x74 0xfc 0x74 0xa9 0x72 0xa8 0xa4 0xe0 0x72 0xa5 0x72 0xab 0xb7 0xb7 0x184 0xe8 0x184 0xf8 0xb8 0xaf 0xb9 0xed 0x72 0xee 0xba 0xb3 0x72 0xf1 0x72 0xf2 0x72 0xf3 0xd9 0xb4 0x72 0xa4 0x8d 0xbe 0xd9>;
        };

        ir_key3 {
            rockchip,usercode = <0x1dcc>;
            rockchip,key_table = <0xee 0xe8 0xf0 0x9e 0xf8 0x67 0xbb 0x6c 0xef 0x69 0xed 0x6a 0xfc 0x66 0xf1 0x73 0xfd 0x72 0xb7 0xd9 0xff 0x74 0xf3 0x71 0xbf 0x8b 0xf9 0x191 0xf5 0x192 0xb3 0x184 0xbe 0x2 0xba 0x3 0xb2 0x4 0xbd 0x5 0xf9 0x6 0xb1 0x7 0xfc 0x8 0xf8 0x9 0xb0 0xa 0xb6 0xb 0xb5 0xe>;
        };

        ir_key4 {
            rockchip,usercode = <0xfe01>;
            rockchip,key_table = <0xec 0xe8 0xe6 0x9e 0xe9 0x67 0xe5 0x6c 0xae 0x69 0xaf 0x6a 0xee 0x66 0xe7 0x73 0xef 0x72 0xbf 0x74 0xbe 0x71 0xb3 0x8b 0xff 0x184 0xb1 0x2 0xf2 0x3 0xf3 0x4 0xb5 0x5 0xf6 0x6 0xf7 0x7 0xb9 0x8 0xfa 0x9 0xfb 0xa 0xfe 0xb 0xbd 0xe 0xbc 0xb7 0xf0 0xba 0xb4 0x19c 0xb8 0x1e 0xb0 0x197>;
        };

        ir_key5 {
            rockchip,usercode = <0x7f80>;
            rockchip,key_table = <0xec 0xe8 0xd8 0x9e 0xc7 0x67 0xbf 0x6c 0xc8 0x69 0xc6 0x6a 0x8c 0x66 0x78 0x73 0x76 0x72 0x7e 0x74 0x7c 0x8b 0xb7 0x184>;
        };

        ir_key6 {
            rockchip,usercode = <0xfd01>;
            rockchip,key_table = <0x31 0xe8 0x2f 0x9e 0x35 0x67 0x2d 0x6c 0x66 0x69 0x3e 0x6a 0x6a 0x66 0x5e 0x73 0x47 0x72 0x23 0x74 0x3a 0x184 0xd 0x40>;
        };
    };

    power-management@fdd90000 {
        compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
        reg = <0x0 0xfdd90000 0x0 0x1000>;
        phandle = <0x170>;

        power-controller {
            compatible = "rockchip,rk3568-power-controller";
            #power-domain-cells = <0x1>;
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            status = "okay";
            phandle = <0x21>;

            pd_npu@6 {
                reg = <0x6>;
                clocks = <0x1f 0x27 0x1f 0x25 0x1f 0x26>;
                pm_qos = <0x45>;
            };

            pd_gpu@7 {
                reg = <0x7>;
                clocks = <0x1f 0x19 0x1f 0x1a>;
                pm_qos = <0x46>;
            };

            pd_vi@8 {
                reg = <0x8>;
                clocks = <0x1f 0xcc 0x1f 0xcd>;
                pm_qos = <0x47 0x48 0x49>;
            };

            pd_vo@9 {
                reg = <0x9>;
                clocks = <0x1f 0xda 0x1f 0xdb 0x1f 0xdc>;
                pm_qos = <0x4a 0x4b 0x4c>;
            };

            pd_rga@10 {
                reg = <0xa>;
                clocks = <0x1f 0xf1 0x1f 0xf2>;
                pm_qos = <0x4d 0x4e 0x4f 0x50 0x51 0x52>;
            };

            pd_vpu@11 {
                reg = <0xb>;
                clocks = <0x1f 0xed>;
                pm_qos = <0x53>;
            };

            pd_rkvdec@13 {
                clocks = <0x1f 0x107>;
                reg = <0xd>;
                pm_qos = <0x54>;
            };

            pd_rkvenc@14 {
                reg = <0xe>;
                clocks = <0x1f 0x102>;
                pm_qos = <0x55 0x56 0x57>;
            };

            pd_pipe@15 {
                reg = <0xf>;
                clocks = <0x1f 0x7f>;
                pm_qos = <0x58 0x59 0x5a 0x5b 0x5c>;
            };
        };
    };

    pvtm@fde00000 {
        compatible = "rockchip,rk3568-core-pvtm";
        reg = <0x0 0xfde00000 0x0 0x100>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;

        pvtm@0 {
            reg = <0x0>;
            clocks = <0x1f 0x13 0x1f 0x1c2>;
            clock-names = "clk", "pclk";
            resets = <0x1f 0x1a 0x1f 0x19>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };

    npu@fde40000 {
        compatible = "rockchip,rknpu";
        reg = <0x0 0xfde40000 0x0 0x10000>;
        interrupts = <0x0 0x97 0x4>;
        clocks = <0x2 0x2 0x1f 0x23 0x1f 0x28 0x1f 0x29>;
        clock-names = "scmi_clk", "clk", "aclk", "hclk";
        assigned-clocks = <0x1f 0x23>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x1f 0x2b 0x1f 0x2c>;
        reset-names = "srst_a", "srst_h";
        power-domains = <0x21 0x6>;
        operating-points-v2 = <0x5d>;
        iommus = <0x5e>;
        status = "okay";
        rknpu-supply = <0x5f>;
        phandle = <0x171>;
    };

    npu-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0x60 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x1388>;
        rockchip,low-temp = <0x0>;
        rockchip,low-temp-adjust-volt = <0x0 0x2bc 0xc350>;
        phandle = <0x5d>;

        opp-200000000 {
            opp-hz = <0x0 0xbebc200>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-300000000 {
            opp-hz = <0x0 0x11b3dc40>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-400000000 {
            opp-hz = <0x0 0x17d78400>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-600000000 {
            opp-hz = <0x0 0x23c34600>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-700000000 {
            opp-hz = <0x0 0x29b92700>;
            opp-microvolt = <0xcf850 0xcf850 0xf4240>;
        };

        opp-800000000 {
            opp-hz = <0x0 0x2faf0800>;
            opp-microvolt = <0xd59f8 0xd59f8 0xf4240>;
        };

        opp-900000000 {
            opp-hz = <0x0 0x35a4e900>;
            opp-microvolt = <0xe1d48 0xe1d48 0xf4240>;
        };

        opp-1000000000 {
            opp-hz = <0x0 0x3b9aca00>;
            opp-microvolt = <0xf4240 0xf4240 0xf4240>;
            status = "disabled";
        };
    };

    bus-npu {
        compatible = "rockchip,rk3568-bus";
        rockchip,busfreq-policy = "clkfreq";
        clocks = <0x2 0x2>;
        clock-names = "bus";
        operating-points-v2 = <0x61>;
        status = "okay";
        bus-supply = <0x62>;
        pvtm-supply = <0x5>;
        phandle = <0x172>;
    };

    bus-npu-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        nvmem-cells = <0x7>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x0 0x14050 0x0 0x14051 0x16b48 0x1 0x16b49 0x186a0 0x2>;
        rockchip,pvtm-ch = <0x0 0x5>;
        phandle = <0x61>;

        opp-1000000000 {
            opp-hz = <0x0 0x3b9aca00>;
            opp-microvolt = <0xe7ef0>;
            opp-microvolt-L0 = <0xe7ef0>;
            opp-microvolt-L1 = <0xe1d48>;
            opp-microvolt-L2 = <0x0>;
        };

        opp-900000000 {
            opp-hz = <0x0 0x35a4e900>;
            opp-microvolt = <0x0>;
        };
    };

    iommu@fde4b000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfde4b000 0x0 0x40>;
        interrupts = <0x0 0x97 0x4>;
        interrupt-names = "rknpu_mmu";
        clocks = <0x1f 0x28 0x1f 0x29>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0x6>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x5e>;
    };

    gpu@fde60000 {
        compatible = "arm,mali-bifrost";
        reg = <0x0 0xfde60000 0x0 0x4000>;
        interrupts = <0x0 0x27 0x4 0x0 0x29 0x4 0x0 0x28 0x4>;
        interrupt-names = "GPU", "MMU", "JOB";
        upthreshold = <0x28>;
        downdifferential = <0xa>;
        clocks = <0x2 0x1 0x1f 0x1b>;
        clock-names = "clk_mali", "clk_gpu";
        power-domains = <0x21 0x7>;
        #cooling-cells = <0x2>;
        operating-points-v2 = <0x63>;
        status = "okay";
        mali-supply = <0x64>;
        phandle = <0x1d>;

        power-model {
            compatible = "simple-power-model";
            leakage-range = <0x5 0xf>;
            ls = <0xffffa23e 0x5927 0x0>;
            static-coefficient = <0x186a0>;
            dynamic-coefficient = <0x3b9>;
            ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>;
            thermal-zone = "gpu-thermal";
            phandle = <0x173>;
        };
    };

    opp-table2 {
        compatible = "operating-points-v2";
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0x65 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        phandle = <0x63>;

        opp-200000000 {
            opp-hz = <0x0 0xbebc200>;
            opp-microvolt = <0xc96a8>;
        };

        opp-300000000 {
            opp-hz = <0x0 0x11e1a300>;
            opp-microvolt = <0xc96a8>;
        };

        opp-400000000 {
            opp-hz = <0x0 0x17d78400>;
            opp-microvolt = <0xc96a8>;
        };

        opp-600000000 {
            opp-hz = <0x0 0x23c34600>;
            opp-microvolt = <0xc96a8>;
        };

        opp-700000000 {
            opp-hz = <0x0 0x29b92700>;
            opp-microvolt = <0xdbba0>;
        };

        opp-800000000 {
            opp-hz = <0x0 0x2faf0800>;
            opp-microvolt = <0xe7ef0>;
        };
    };

    pvtm@fde80000 {
        compatible = "rockchip,rk3568-gpu-pvtm";
        reg = <0x0 0xfde80000 0x0 0x100>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;

        pvtm@1 {
            reg = <0x1>;
            clocks = <0x1f 0x1e 0x1f 0x1d>;
            clock-names = "clk", "pclk";
            resets = <0x1f 0x24 0x1f 0x23>;
            reset-names = "rts", "rst-p";
            thermal-zone = "gpu-thermal";
        };
    };

    pvtm@fde90000 {
        compatible = "rockchip,rk3568-npu-pvtm";
        reg = <0x0 0xfde90000 0x0 0x100>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;

        pvtm@2 {
            reg = <0x2>;
            clocks = <0x1f 0x2b 0x1f 0x2a 0x1f 0x25>;
            clock-names = "clk", "pclk", "hclk";
            resets = <0x1f 0x2e 0x1f 0x2d>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };

    vdpu@fdea0400 {
        compatible = "rockchip,vpu-decoder-v2";
        reg = <0x0 0xfdea0400 0x0 0x400>;
        interrupts = <0x0 0x8b 0x4>;
        interrupt-names = "irq_dec";
        clocks = <0x1f 0xee 0x1f 0xef>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        resets = <0x1f 0x11a 0x1f 0x11b>;
        reset-names = "video_a", "video_h";
        iommus = <0x66>;
        power-domains = <0x21 0xb>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x0>;
        rockchip,resetgroup-node = <0x0>;
        status = "okay";
        phandle = <0x174>;
    };

    iommu@fdea0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdea0800 0x0 0x40>;
        interrupts = <0x0 0x8a 0x4>;
        interrupt-names = "vdpu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x1f 0xee 0x1f 0xef>;
        power-domains = <0x21 0xb>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x66>;
    };

    rk_rga@fdeb0000 {
        compatible = "rockchip,rga2";
        reg = <0x0 0xfdeb0000 0x0 0x1000>;
        interrupts = <0x0 0x5a 0x4>;
        clocks = <0x1f 0xf3 0x1f 0xf4 0x1f 0xf5>;
        clock-names = "aclk_rga", "hclk_rga", "clk_rga";
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x175>;
    };

    ebc@fdec0000 {
        compatible = "rockchip,rk3568-ebc-tcon";
        reg = <0x0 0xfdec0000 0x0 0x5000>;
        interrupts = <0x0 0x11 0x4>;
        clocks = <0x1f 0xf9 0x1f 0xfa>;
        clock-names = "hclk", "dclk";
        power-domains = <0x21 0xa>;
        rockchip,grf = <0x32>;
        pinctrl-names = "default";
        pinctrl-0 = <0x68>;
        status = "disabled";
        phandle = <0x176>;
    };

    jpegd@fded0000 {
        compatible = "rockchip,rkv-jpeg-decoder-v1";
        reg = <0x0 0xfded0000 0x0 0x400>;
        interrupts = <0x0 0x3e 0x4>;
        clocks = <0x1f 0xfb 0x1f 0xfc>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x1f 0x12c 0x1f 0x12d>;
        reset-names = "video_a", "video_h";
        iommus = <0x69>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x1>;
        rockchip,resetgroup-node = <0x1>;
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x177>;
    };

    iommu@fded0480 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfded0480 0x0 0x40>;
        interrupts = <0x0 0x3d 0x4>;
        interrupt-names = "jpegd_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x1f 0xfb 0x1f 0xfc>;
        power-domains = <0x21 0xa>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x69>;
    };

    vepu@fdee0000 {
        compatible = "rockchip,vpu-encoder-v2";
        reg = <0x0 0xfdee0000 0x0 0x400>;
        interrupts = <0x0 0x40 0x4>;
        clocks = <0x1f 0xfd 0x1f 0xfe>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x1f 0x12e 0x1f 0x12f>;
        reset-names = "video_a", "video_h";
        iommus = <0x6a>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x2>;
        rockchip,resetgroup-node = <0x2>;
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x178>;
    };

    iommu@fdee0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdee0800 0x0 0x40>;
        interrupts = <0x0 0x3f 0x4>;
        interrupt-names = "vepu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x1f 0xfd 0x1f 0xfe>;
        power-domains = <0x21 0xa>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x6a>;
    };

    iep@fdef0000 {
        compatible = "rockchip,iep-v2";
        reg = <0x0 0xfdef0000 0x0 0x500>;
        interrupts = <0x0 0x38 0x4>;
        clocks = <0x1f 0xf6 0x1f 0xf7 0x1f 0xf8>;
        clock-names = "aclk", "hclk", "sclk";
        resets = <0x1f 0x127 0x1f 0x128 0x1f 0x129>;
        reset-names = "rst_a", "rst_h", "rst_s";
        power-domains = <0x21 0xa>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x5>;
        rockchip,resetgroup-node = <0x5>;
        iommus = <0x6b>;
        status = "okay";
        phandle = <0x179>;
    };

    iommu@fdef0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdef0800 0x0 0x100>;
        interrupts = <0x0 0x38 0x4>;
        interrupt-names = "iep_mmu";
        clocks = <0x1f 0xf6 0x1f 0xf7>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x0>;
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x6b>;
    };

    eink@fdf00000 {
        compatible = "rockchip,rk3568-eink-tcon";
        reg = <0x0 0xfdf00000 0x0 0x74>;
        interrupts = <0x0 0xb2 0x4>;
        clocks = <0x1f 0xff 0x1f 0x100>;
        clock-names = "pclk", "hclk";
        status = "disabled";
        phandle = <0x17a>;
    };

    rkvenc@fdf40000 {
        compatible = "rockchip,rkv-encoder-v1";
        reg = <0x0 0xfdf40000 0x0 0x400>;
        interrupts = <0x0 0x8c 0x4>;
        interrupt-names = "irq_enc";
        clocks = <0x1f 0x103 0x1f 0x104 0x1f 0x105>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x11b3dc40 0x0 0x11b3dc40>;
        resets = <0x1f 0x133 0x1f 0x134 0x1f 0x135>;
        reset-names = "video_a", "video_h", "video_core";
        assigned-clocks = <0x1f 0x103 0x1f 0x105>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40>;
        iommus = <0x6c>;
        node-name = "rkvenc";
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x3>;
        rockchip,resetgroup-node = <0x3>;
        power-domains = <0x21 0xe>;
        operating-points-v2 = <0x6d>;
        status = "okay";
        venc-supply = <0x62>;
        phandle = <0x17b>;
    };

    rkvenc-opp-table {
        compatible = "operating-points-v2";
        nvmem-cells = <0x7>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x0 0x14050 0x0 0x14051 0x16b48 0x1 0x16b49 0x186a0 0x2>;
        rockchip,pvtm-ch = <0x0 0x5>;
        phandle = <0x6d>;

        opp-297000000 {
            opp-hz = <0x0 0x11b3dc40>;
            opp-microvolt = <0x0>;
        };

        opp-400000000 {
            opp-hz = <0x0 0x17d78400>;
            opp-microvolt = <0xe7ef0>;
            opp-microvolt-L0 = <0xe7ef0>;
            opp-microvolt-L1 = <0xe1d48>;
            opp-microvolt-L2 = <0x0>;
        };
    };

    iommu@fdf40f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdf40f00 0x0 0x40 0x0 0xfdf40f40 0x0 0x40>;
        interrupts = <0x0 0x8d 0x4 0x0 0x8e 0x4>;
        interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
        clocks = <0x1f 0x103 0x1f 0x104>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        #iommu-cells = <0x0>;
        power-domains = <0x21 0xe>;
        status = "okay";
        phandle = <0x6c>;
    };

    rkvdec@fdf80200 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x0 0xfdf80200 0x0 0x400>;
        interrupts = <0x0 0x5b 0x4>;
        interrupt-names = "irq_dec";
        clocks = <0x1f 0x108 0x1f 0x109 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core", "clk_hevc_cabac";
        rockchip,normal-rates = <0x11b3dc40 0x0 0x11b3dc40 0x11b3dc40 0x23c34600>;
        rockchip,advanced-rates = <0x179a7b00 0x0 0x179a7b00 0x179a7b00 0x23c34600>;
        rockchip,default-max-load = <0x1fe000>;
        resets = <0x1f 0x142 0x1f 0x143 0x1f 0x144 0x1f 0x145 0x1f 0x146>;
        assigned-clocks = <0x1f 0x108 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>;
        reset-names = "video_a", "video_h", "video_cabac", "video_core", "video_hevc_cabac";
        power-domains = <0x21 0xd>;
        iommus = <0x6e>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x4>;
        rockchip,resetgroup-node = <0x4>;
        rockchip,sram = <0x6f>;
        rockchip,rcb-iova = <0x10000000 0x10000>;
        rockchip,rcb-min-width = <0x200>;
        status = "okay";
        phandle = <0x17c>;
    };

    iommu@fdf80800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdf80800 0x0 0x40 0x0 0xfdf80840 0x0 0x40>;
        interrupts = <0x0 0x5c 0x4>;
        interrupt-names = "rkvdec_mmu";
        clocks = <0x1f 0x108 0x1f 0x109>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0xd>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x6e>;
    };

    mipi-csi2@fdfb0000 {
        compatible = "rockchip,rk3568-mipi-csi2";
        reg = <0x0 0xfdfb0000 0x0 0x10000>;
        reg-names = "csihost_regs";
        interrupts = <0x0 0x8 0x4 0x0 0x9 0x4>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x1f 0xd5>;
        clock-names = "pclk_csi2host";
        resets = <0x1f 0xff>;
        reset-names = "srst_csihost_p";
        status = "disabled";
        phandle = <0x17d>;
    };

    rkcif@fdfe0000 {
        compatible = "rockchip,rk3568-cif";
        reg = <0x0 0xfdfe0000 0x0 0x8000>;
        reg-names = "cif_regs";
        interrupts = <0x0 0x92 0x4>;
        interrupt-names = "cif-intr";
        clocks = <0x1f 0xce 0x1f 0xcf 0x1f 0xd0 0x1f 0xd1>;
        clock-names = "aclk_cif", "hclk_cif", "dclk_cif", "iclk_cif_g";
        resets = <0x1f 0xf7 0x1f 0xf8 0x1f 0xf9 0x1f 0xfb 0x1f 0xfa>;
        reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_p", "rst_cif_i";
        assigned-clocks = <0x1f 0xd0>;
        assigned-clock-rates = <0x11e1a300>;
        power-domains = <0x21 0x8>;
        rockchip,grf = <0x32>;
        iommus = <0x70>;
        status = "okay";
        phandle = <0x71>;
    };

    iommu@fdfe0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdfe0800 0x0 0x100>;
        interrupts = <0x0 0x92 0x4>;
        interrupt-names = "cif_mmu";
        clocks = <0x1f 0xce 0x1f 0xcf>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0x8>;
        rockchip,disable-mmu-reset;
        #iommu-cells = <0x0>;
        status = "disabled";
        phandle = <0x70>;
    };

    rkcif_dvp {
        compatible = "rockchip,rkcif-dvp";
        rockchip,hw = <0x71>;
        status = "okay";
        phandle = <0x73>;

        port {

            endpoint {
                remote-endpoint = <0x72>;
                bus-width = <0x8>;
                vsync-active = <0x0>;
                hsync-active = <0x1>;
                phandle = <0xd3>;
            };
        };
    };

    rkcif_dvp_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x73>;
        status = "disabled";
        phandle = <0x17e>;
    };

    rkcif_mipi_lvds {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x71>;
        status = "disabled";
        phandle = <0x74>;
    };

    rkcif_mipi_lvds_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x74>;
        status = "disabled";
        phandle = <0x17f>;
    };

    rkisp@fdff0000 {
        compatible = "rockchip,rk3568-rkisp";
        reg = <0x0 0xfdff0000 0x0 0x10000>;
        interrupts = <0x0 0x39 0x4 0x0 0x3a 0x4 0x0 0x3c 0x4>;
        interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
        clocks = <0x1f 0xd2 0x1f 0xd3 0x1f 0xd4>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp";
        resets = <0x1f 0xfd 0x1f 0xfc>;
        reset-names = "isp", "isp-h";
        rockchip,grf = <0x32>;
        power-domains = <0x21 0x8>;
        iommus = <0x75>;
        rockchip,iq-feature = <0x3fb 0xf7fe67ff>;
        status = "okay";
        phandle = <0x76>;
    };

    iommu@fdff1a00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdff1a00 0x0 0x100>;
        interrupts = <0x0 0x3b 0x4>;
        interrupt-names = "isp_mmu";
        clocks = <0x1f 0xd2 0x1f 0xd3>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0x8>;
        #iommu-cells = <0x0>;
        rockchip,disable-mmu-reset;
        status = "okay";
        phandle = <0x75>;
    };

    rkisp-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x76>;
        status = "okay";
        phandle = <0x180>;

        port {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            endpoint@0 {
                reg = <0x0>;
                remote-endpoint = <0x77>;
                phandle = <0x10a>;
            };
        };
    };

    rkisp-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x76>;
        status = "disabled";
        phandle = <0x181>;
    };

    ethernet@fe010000 {
        compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
        reg = <0x0 0xfe010000 0x0 0x10000>;
        interrupts = <0x0 0x20 0x4 0x0 0x1d 0x4>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x32>;
        clocks = <0x1f 0x186 0x1f 0x189 0x1f 0x189 0x1f 0xc7 0x1f 0xc3 0x1f 0xc4 0x1f 0x189 0x1f 0xc8 0x1f 0xac>;
        clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref", "pclk_xpcs";
        resets = <0x1f 0xec>;
        reset-names = "stmmaceth";
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x78>;
        snps,mtl-rx-config = <0x79>;
        snps,mtl-tx-config = <0x7a>;
        status = "okay";
        phy-mode = "rgmii";
        clock_in_out = "output";
        snps,reset-gpio = <0x7b 0x1 0x1>;
        snps,reset-active-low;
        snps,reset-delays-us = <0x0 0x4e20 0x186a0>;
        assigned-clocks = <0x1f 0x189 0x1f 0x186>;
        assigned-clock-parents = <0x1f 0x187 0x1f 0xc5>;
        assigned-clock-rates = <0x0 0x7735940>;
        pinctrl-names = "default";
        pinctrl-0 = <0x7c 0x7d 0x7e 0x7f 0x80>;
        tx_delay = <0x41>;
        rx_delay = <0x2e>;
        phy-handle = <0x81>;
        phandle = <0x182>;

        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            phandle = <0x183>;

            phy@0 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <0x0>;
                phandle = <0x81>;
            };
        };

        stmmac-axi-config {
            snps,wr_osr_lmt = <0x4>;
            snps,rd_osr_lmt = <0x8>;
            snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>;
            phandle = <0x78>;
        };

        rx-queues-config {
            snps,rx-queues-to-use = <0x1>;
            phandle = <0x79>;

            queue0 {
            };
        };

        tx-queues-config {
            snps,tx-queues-to-use = <0x1>;
            phandle = <0x7a>;

            queue0 {
            };
        };
    };

    vop@fe040000 {
        compatible = "rockchip,rk3568-vop";
        reg = <0x0 0xfe040000 0x0 0x3000 0x0 0xfe044000 0x0 0x1000>;
        reg-names = "regs", "gamma_lut";
        rockchip,grf = <0x32>;
        interrupts = <0x0 0x94 0x4>;
        clocks = <0x1f 0xdd 0x1f 0xde 0x1f 0xdf 0x1f 0xe0 0x1f 0xe1>;
        clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
        iommus = <0x82>;
        power-domains = <0x21 0x9>;
        status = "okay";
        assigned-clocks = <0x1f 0xdf 0x1f 0xe0>;
        assigned-clock-parents = <0x31 0x2 0x1f 0x5>;
        support-multi-area;
        phandle = <0x184>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            phandle = <0x12>;

            port@0 {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                reg = <0x0>;
                phandle = <0x185>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x83>;
                    phandle = <0x8f>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x84>;
                    phandle = <0x15>;
                };

                endpoint@2 {
                    reg = <0x2>;
                    remote-endpoint = <0x85>;
                    phandle = <0x16>;
                };

                endpoint@3 {
                    reg = <0x3>;
                    remote-endpoint = <0x86>;
                    phandle = <0x17>;
                };
            };

            port@1 {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                reg = <0x1>;
                phandle = <0x186>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x87>;
                    phandle = <0x14>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x88>;
                    phandle = <0x98>;
                };

                endpoint@2 {
                    reg = <0x2>;
                    remote-endpoint = <0x89>;
                    phandle = <0xa5>;
                };

                endpoint@3 {
                    reg = <0x3>;
                    remote-endpoint = <0x8a>;
                    phandle = <0xa3>;
                };

                endpoint@4 {
                    reg = <0x4>;
                    remote-endpoint = <0x8b>;
                    phandle = <0x18>;
                };
            };

            port@2 {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                reg = <0x2>;
                phandle = <0x187>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x8c>;
                    phandle = <0x2f>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x8d>;
                    phandle = <0x19>;
                };
            };
        };
    };

    iommu@fe043e00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfe043e00 0x0 0x100 0x0 0xfe043f00 0x0 0x100>;
        interrupts = <0x0 0x94 0x4>;
        interrupt-names = "vop_mmu";
        clocks = <0x1f 0xdd 0x1f 0xde>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x82>;
    };

    dsi@fe060000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x0 0xfe060000 0x0 0x10000>;
        interrupts = <0x0 0x44 0x4>;
        clocks = <0x1f 0xe8 0x1f 0xda 0x8e>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x1f 0x110>;
        reset-names = "apb";
        phys = <0x8e>;
        phy-names = "mipi_dphy";
        power-domains = <0x21 0x9>;
        rockchip,grf = <0x32>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x188>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x189>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x8f>;
                    status = "disabled";
                    phandle = <0x83>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x14>;
                    status = "okay";
                    phandle = <0x87>;
                };
            };

            port@1 {
                reg = <0x1>;

                endpoint {
                    remote-endpoint = <0x90>;
                    phandle = <0x96>;
                };
            };
        };

        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x0>;
            backlight = <0x91>;
            reset-delay-ms = <0x3c>;
            enable-delay-ms = <0x3c>;
            prepare-delay-ms = <0x3c>;
            unprepare-delay-ms = <0x3c>;
            disable-delay-ms = <0x3c>;
            dsi,flags = <0xa03>;
            dsi,format = <0x0>;
            dsi,lanes = <0x4>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x5000128 0x5000110>;
            power-supply = <0x92>;
            reset-gpios = <0x93 0x5 0x1>;
            pinctrl-names = "default";
            pinctrl-0 = <0x94>;
            phandle = <0x18a>;

            display-timings {
                native-mode = <0x95>;
                phandle = <0x18b>;

                timing0 {
                    clock-frequency = <0x7de2900>;
                    hactive = <0x438>;
                    vactive = <0x780>;
                    hfront-porch = <0xf>;
                    hsync-len = <0x2>;
                    hback-porch = <0x1e>;
                    vfront-porch = <0xf>;
                    vsync-len = <0x2>;
                    vback-porch = <0xf>;
                    hsync-active = <0x0>;
                    vsync-active = <0x0>;
                    de-active = <0x0>;
                    pixelclk-active = <0x1>;
                    phandle = <0x95>;
                };
            };

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;

                    endpoint {
                        remote-endpoint = <0x96>;
                        phandle = <0x90>;
                    };
                };
            };
        };
    };

    dsi@fe070000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x0 0xfe070000 0x0 0x10000>;
        interrupts = <0x0 0x45 0x4>;
        clocks = <0x1f 0xe9 0x1f 0xda 0x97>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x1f 0x111>;
        reset-names = "apb";
        phys = <0x97>;
        phy-names = "mipi_dphy";
        power-domains = <0x21 0x9>;
        rockchip,grf = <0x32>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x18c>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x18d>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x15>;
                    status = "disabled";
                    phandle = <0x84>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x98>;
                    status = "disabled";
                    phandle = <0x88>;
                };
            };

            port@1 {
                reg = <0x1>;

                endpoint {
                    remote-endpoint = <0x99>;
                    phandle = <0x9f>;
                };
            };
        };

        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x0>;
            backlight = <0x9a>;
            reset-delay-ms = <0x3c>;
            enable-delay-ms = <0x3c>;
            prepare-delay-ms = <0x3c>;
            unprepare-delay-ms = <0x3c>;
            disable-delay-ms = <0x3c>;
            dsi,flags = <0xa03>;
            dsi,format = <0x0>;
            dsi,lanes = <0x4>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x5000128 0x5000110>;
            power-supply = <0x9b>;
            reset-gpios = <0x9c 0x16 0x1>;
            pinctrl-names = "default";
            pinctrl-0 = <0x9d>;
            phandle = <0x18e>;

            display-timings {
                native-mode = <0x9e>;
                phandle = <0x18f>;

                timing0 {
                    clock-frequency = <0x7de2900>;
                    hactive = <0x438>;
                    vactive = <0x780>;
                    hfront-porch = <0xf>;
                    hsync-len = <0x2>;
                    hback-porch = <0x1e>;
                    vfront-porch = <0xf>;
                    vsync-len = <0x2>;
                    vback-porch = <0xf>;
                    hsync-active = <0x0>;
                    vsync-active = <0x0>;
                    de-active = <0x0>;
                    pixelclk-active = <0x1>;
                    phandle = <0x9e>;
                };
            };

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;

                    endpoint {
                        remote-endpoint = <0x9f>;
                        phandle = <0x99>;
                    };
                };
            };
        };
    };

    hdmi@fe0a0000 {
        compatible = "rockchip,rk3568-dw-hdmi";
        reg = <0x0 0xfe0a0000 0x0 0x20000>;
        interrupts = <0x0 0x2d 0x4>;
        clocks = <0x1f 0xe6 0x1f 0xe7 0x1f 0x193 0x31 0x2 0x1f 0xde>;
        clock-names = "iahb", "isfr", "cec", "ref", "hclk";
        power-domains = <0x21 0x9>;
        reg-io-width = <0x4>;
        rockchip,grf = <0x32>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xa0 0xa1 0xa2>;
        status = "okay";
        rockchip,phy-table = <0x58834d4 0x8009 0x0 0x270 0x9d5b340 0x800b 0x0 0x26d 0xb1069a8 0x800b 0x0 0x1ed 0x11b3dc40 0x800b 0x0 0x1ad 0x2367b880 0x8029 0x0 0x88 0x0 0x0 0x0 0x0>;
        phandle = <0x122>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x190>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x17>;
                    status = "okay";
                    phandle = <0x86>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0xa3>;
                    status = "disabled";
                    phandle = <0x8a>;
                };
            };
        };
    };

    edp@fe0c0000 {
        compatible = "rockchip,rk3568-edp";
        reg = <0x0 0xfe0c0000 0x0 0x10000>;
        interrupts = <0x0 0x12 0x4>;
        clocks = <0x31 0x29 0x1f 0xea 0x1f 0xeb 0x1f 0xda>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x1f 0x113 0x1f 0x112>;
        reset-names = "dp", "apb";
        phys = <0xa4>;
        phy-names = "dp";
        power-domains = <0x21 0x9>;
        status = "okay";
        hpd-gpios = <0x93 0x7 0x0>;
        phandle = <0x191>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x192>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x16>;
                    status = "okay";
                    phandle = <0x85>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0xa5>;
                    status = "disabled";
                    phandle = <0x89>;
                };
            };
        };
    };

    qos@fe128000 {
        compatible = "syscon";
        reg = <0x0 0xfe128000 0x0 0x20>;
        phandle = <0x46>;
    };

    qos@fe138080 {
        compatible = "syscon";
        reg = <0x0 0xfe138080 0x0 0x20>;
        phandle = <0x55>;
    };

    qos@fe138100 {
        compatible = "syscon";
        reg = <0x0 0xfe138100 0x0 0x20>;
        phandle = <0x56>;
    };

    qos@fe138180 {
        compatible = "syscon";
        reg = <0x0 0xfe138180 0x0 0x20>;
        phandle = <0x57>;
    };

    qos@fe148000 {
        compatible = "syscon";
        reg = <0x0 0xfe148000 0x0 0x20>;
        phandle = <0x47>;
    };

    qos@fe148080 {
        compatible = "syscon";
        reg = <0x0 0xfe148080 0x0 0x20>;
        phandle = <0x48>;
    };

    qos@fe148100 {
        compatible = "syscon";
        reg = <0x0 0xfe148100 0x0 0x20>;
        phandle = <0x49>;
    };

    qos@fe150000 {
        compatible = "syscon";
        reg = <0x0 0xfe150000 0x0 0x20>;
        phandle = <0x53>;
    };

    qos@fe158000 {
        compatible = "syscon";
        reg = <0x0 0xfe158000 0x0 0x20>;
        phandle = <0x4d>;
    };

    qos@fe158100 {
        compatible = "syscon";
        reg = <0x0 0xfe158100 0x0 0x20>;
        phandle = <0x4e>;
    };

    qos@fe158180 {
        compatible = "syscon";
        reg = <0x0 0xfe158180 0x0 0x20>;
        phandle = <0x4f>;
    };

    qos@fe158200 {
        compatible = "syscon";
        reg = <0x0 0xfe158200 0x0 0x20>;
        phandle = <0x50>;
    };

    qos@fe158280 {
        compatible = "syscon";
        reg = <0x0 0xfe158280 0x0 0x20>;
        phandle = <0x51>;
    };

    qos@fe158300 {
        compatible = "syscon";
        reg = <0x0 0xfe158300 0x0 0x20>;
        phandle = <0x52>;
    };

    qos@fe180000 {
        compatible = "syscon";
        reg = <0x0 0xfe180000 0x0 0x20>;
        phandle = <0x45>;
    };

    qos@fe190000 {
        compatible = "syscon";
        reg = <0x0 0xfe190000 0x0 0x20>;
        phandle = <0x58>;
    };

    qos@fe190280 {
        compatible = "syscon";
        reg = <0x0 0xfe190280 0x0 0x20>;
        phandle = <0x59>;
    };

    qos@fe190300 {
        compatible = "syscon";
        reg = <0x0 0xfe190300 0x0 0x20>;
        phandle = <0x5a>;
    };

    qos@fe190380 {
        compatible = "syscon";
        reg = <0x0 0xfe190380 0x0 0x20>;
        phandle = <0x5b>;
    };

    qos@fe190400 {
        compatible = "syscon";
        reg = <0x0 0xfe190400 0x0 0x20>;
        phandle = <0x5c>;
    };

    qos@fe198000 {
        compatible = "syscon";
        reg = <0x0 0xfe198000 0x0 0x20>;
        phandle = <0x54>;
    };

    qos@fe1a8000 {
        compatible = "syscon";
        reg = <0x0 0xfe1a8000 0x0 0x20>;
        phandle = <0x4a>;
    };

    qos@fe1a8080 {
        compatible = "syscon";
        reg = <0x0 0xfe1a8080 0x0 0x20>;
        phandle = <0x4b>;
    };

    qos@fe1a8100 {
        compatible = "syscon";
        reg = <0x0 0xfe1a8100 0x0 0x20>;
        phandle = <0x4c>;
    };

    dwmmc@fe000000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x0 0xfe000000 0x0 0x4000>;
        interrupts = <0x0 0x64 0x4>;
        max-frequency = <0x8f0d180>;
        clocks = <0x1f 0xc1 0x1f 0xc2 0x1f 0x18e 0x1f 0x18f>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x100>;
        resets = <0x1f 0xeb>;
        reset-names = "reset";
        status = "disabled";
        phandle = <0x193>;
    };

    dfi@fe230000 {
        reg = <0x0 0xfe230000 0x0 0x400>;
        compatible = "rockchip,rk3568-dfi";
        rockchip,pmugrf = <0x33>;
        status = "disabled";
        phandle = <0xa6>;
    };

    dmc {
        compatible = "rockchip,rk3568-dmc";
        interrupts = <0x0 0xa 0x4>;
        interrupt-names = "complete";
        devfreq-events = <0xa6>;
        clocks = <0x1f 0x1a2>;
        clock-names = "dmc_clk";
        operating-points-v2 = <0xa7>;
        ddr_timing = <0xa8>;
        vop-bw-dmc-freq = <0x0 0x1f9 0x4f1a0 0x1fa 0x1869f 0x80e80>;
        upthreshold = <0x28>;
        downdifferential = <0x14>;
        system-status-freq = <0x1 0xbe6e0 0x8 0xbe6e0 0x2 0xbe6e0 0x10 0xbe6e0 0x10000 0xbe6e0 0x1000 0xbe6e0 0x4000 0xbe6e0 0x2000 0xbe6e0 0xc00 0xbe6e0>;
        auto-min-freq = <0x4f1a0>;
        auto-freq-en = <0x1>;
        #cooling-cells = <0x2>;
        status = "disabled";
        center-supply = <0x62>;
        phandle = <0x13>;
    };

    dmc-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0xa9 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x1388>;
        rockchip,low-temp = <0x0>;
        rockchip,low-temp-adjust-volt = <0x0 0x618 0x61a8>;
        rockchip,leakage-voltage-sel = <0x1 0x50 0x0 0x51 0xfe 0x1>;
        phandle = <0xa7>;

        opp-324000000 {
            opp-hz = <0x0 0x134fd900>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };

        opp-528000000 {
            opp-hz = <0x0 0x1f78a400>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };

        opp-780000000 {
            opp-hz = <0x0 0x2e7ddb00>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };

        opp-920000000 {
            opp-hz = <0x0 0x36d61600>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
            status = "disabled";
        };

        opp-1056000000 {
            opp-hz = <0x0 0x3ef14800>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };
    };

    pcie@fe260000 {
        compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
        #address-cells = <0x3>;
        #size-cells = <0x2>;
        bus-range = <0x0 0xf>;
        clocks = <0x1f 0x81 0x1f 0x82 0x1f 0x83 0x1f 0x84 0x1f 0x85>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
        device_type = "pci";
        interrupts = <0x0 0x4b 0x4 0x0 0x4a 0x4 0x0 0x49 0x4 0x0 0x48 0x4 0x0 0x47 0x4>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x1>;
        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
        interrupt-map = <0x0 0x0 0x0 0x1 0xaa 0x0 0x0 0x0 0x0 0x2 0xaa 0x1 0x0 0x0 0x0 0x3 0xaa 0x2 0x0 0x0 0x0 0x4 0xaa 0x3>;
        linux,pci-domain = <0x0>;
        num-ib-windows = <0x6>;
        num-ob-windows = <0x2>;
        max-link-speed = <0x2>;
        msi-map = <0x0 0xab 0x0 0x1000>;
        num-lanes = <0x1>;
        phys = <0x22 0x2>;
        phy-names = "pcie-phy";
        power-domains = <0x21 0xf>;
        ranges = <0x800 0x0 0x0 0x3 0x0 0x0 0x800000 0x81000000 0x0 0x800000 0x3 0x800000 0x0 0x100000 0x83000000 0x0 0x900000 0x3 0x900000 0x0 0x3f700000>;
        reg = <0x3 0xc0000000 0x0 0x400000 0x0 0xfe260000 0x0 0x10000>;
        reg-names = "pcie-dbi", "pcie-apb";
        resets = <0x1f 0xa1>;
        reset-names = "pipe";
        status = "disabled";
        phandle = <0x194>;

        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x0>;
            #interrupt-cells = <0x1>;
            interrupt-parent = <0x1>;
            interrupts = <0x0 0x48 0x1>;
            phandle = <0xaa>;
        };
    };

    dwmmc@fe2b0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x0 0xfe2b0000 0x0 0x4000>;
        interrupts = <0x0 0x62 0x4>;
        max-frequency = <0x8f0d180>;
        clocks = <0x1f 0xb0 0x1f 0xb1 0x1f 0x18a 0x1f 0x18b>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x100>;
        resets = <0x1f 0xd4>;
        reset-names = "reset";
        status = "okay";
        supports-sd;
        bus-width = <0x4>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        disable-wp;
        sd-uhs-sdr104;
        vmmc-supply = <0xac>;
        vqmmc-supply = <0x2b>;
        pinctrl-names = "default";
        pinctrl-0 = <0xad 0xae 0xaf 0xb0>;
        phandle = <0x195>;
    };

    dwmmc@fe2c0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x0 0xfe2c0000 0x0 0x4000>;
        interrupts = <0x0 0x63 0x4>;
        max-frequency = <0x8f0d180>;
        clocks = <0x1f 0xb2 0x1f 0xb3 0x1f 0x18c 0x1f 0x18d>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x100>;
        resets = <0x1f 0xd6>;
        reset-names = "reset";
        status = "okay";
        supports-sdio;
        bus-width = <0x4>;
        disable-wp;
        cap-sd-highspeed;
        cap-sdio-irq;
        keep-power-in-suspend;
        mmc-pwrseq = <0xb1>;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <0xb2 0xb3 0xb4>;
        sd-uhs-sdr104;
        phandle = <0x196>;
    };

    sfc@fe300000 {
        compatible = "rockchip,sfc";
        reg = <0x0 0xfe300000 0x0 0x4000>;
        interrupts = <0x0 0x65 0x4>;
        clocks = <0x1f 0x78 0x1f 0x76>;
        clock-names = "clk_sfc", "hclk_sfc";
        assigned-clocks = <0x1f 0x78>;
        assigned-clock-rates = <0x5f5e100>;
        status = "okay";
        phandle = <0x197>;
    };

    sdhci@fe310000 {
        compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
        reg = <0x0 0xfe310000 0x0 0x10000>;
        interrupts = <0x0 0x13 0x4>;
        assigned-clocks = <0x1f 0x7b 0x1f 0x7d>;
        assigned-clock-rates = <0xbebc200 0x16e3600>;
        clocks = <0x1f 0x7c 0x1f 0x7a 0x1f 0x79 0x1f 0x7b 0x1f 0x7d>;
        clock-names = "core", "bus", "axi", "block", "timer";
        status = "okay";
        bus-width = <0x8>;
        supports-emmc;
        non-removable;
        max-frequency = <0xbebc200>;
        phandle = <0x198>;
    };

    nandc@fe330000 {
        compatible = "rockchip,rk-nandc-v9";
        reg = <0x0 0xfe330000 0x0 0x4000>;
        interrupts = <0x0 0x46 0x4>;
        nandc_id = <0x0>;
        clocks = <0x1f 0x75 0x1f 0x74>;
        clock-names = "clk_nandc", "hclk_nandc";
        status = "okay";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        phandle = <0x199>;

        nand@0 {
            reg = <0x0>;
            nand-bus-width = <0x8>;
            nand-ecc-mode = "hw";
            nand-ecc-strength = <0x10>;
            nand-ecc-step-size = <0x400>;
        };
    };

    crypto@fe380000 {
        compatible = "rockchip,rk3568-crypto";
        reg = <0x0 0xfe380000 0x0 0x4000>;
        interrupts = <0x0 0x4 0x4>;
        clocks = <0x1f 0x6a 0x1f 0x6b 0x1f 0x6c 0x1f 0x6d>;
        clock-names = "aclk", "hclk", "sclk", "apb_pclk";
        assigned-clocks = <0x1f 0x6c>;
        assigned-clock-rates = <0xbebc200>;
        resets = <0x1f 0x69>;
        reset-names = "crypto-rst";
        status = "disabled";
        phandle = <0x19a>;
    };

    rng@fe388000 {
        compatible = "rockchip,cryptov2-rng";
        reg = <0x0 0xfe388000 0x0 0x2000>;
        clocks = <0x1f 0x70 0x1f 0x6f>;
        clock-names = "clk_trng", "hclk_trng";
        resets = <0x1f 0x6d>;
        reset-names = "reset";
        status = "okay";
        phandle = <0x19b>;
    };

    otp@fe38c000 {
        compatible = "rockchip,rk3568-otp";
        reg = <0x0 0xfe38c000 0x0 0x4000>;
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        clocks = <0x1f 0x73 0x1f 0x72 0x1f 0x71 0x1f 0x181>;
        clock-names = "usr", "sbpi", "apb", "phy";
        resets = <0x1f 0x1cf>;
        reset-names = "otp_phy";
        phandle = <0x19c>;

        cpu-code@2 {
            reg = <0x2 0x2>;
            phandle = <0xf>;
        };

        cpu-version@8 {
            reg = <0x8 0x1>;
            bits = <0x3 0x3>;
            phandle = <0xe>;
        };

        mbist-vmin@9 {
            reg = <0x9 0x1>;
            bits = <0x0 0x4>;
            phandle = <0x8>;
        };

        id@a {
            reg = <0xa 0x10>;
            phandle = <0xd>;
        };

        cpu-leakage@1a {
            reg = <0x1a 0x1>;
            phandle = <0x6>;
        };

        log-leakage@1b {
            reg = <0x1b 0x1>;
            phandle = <0xa9>;
        };

        npu-leakage@1c {
            reg = <0x1c 0x1>;
            phandle = <0x60>;
        };

        gpu-leakage@1d {
            reg = <0x1d 0x1>;
            phandle = <0x65>;
        };

        core-pvtm@2a {
            reg = <0x2a 0x2>;
            phandle = <0x7>;
        };
    };

    i2s@fe400000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe400000 0x0 0x1000>;
        interrupts = <0x0 0x34 0x4>;
        clocks = <0x1f 0x3f 0x1f 0x43 0x1f 0x39>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x0>;
        dma-names = "tx";
        resets = <0x1f 0x50 0x1f 0x51>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        rockchip,playback-only;
        #sound-dai-cells = <0x0>;
        status = "okay";
        phandle = <0x121>;
    };

    i2s@fe410000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe410000 0x0 0x1000>;
        interrupts = <0x0 0x35 0x4>;
        clocks = <0x1f 0x47 0x1f 0x4b 0x1f 0x3a>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x2 0xb5 0x3>;
        dma-names = "tx", "rx";
        resets = <0x1f 0x52 0x1f 0x53>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xb6 0xb7 0xb8 0xb9>;
        status = "disabled";
        rockchip,clk-trcm = <0x1>;
        phandle = <0xc6>;
    };

    i2s@fe420000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe420000 0x0 0x1000>;
        interrupts = <0x0 0x36 0x4>;
        clocks = <0x1f 0x4f 0x1f 0x4f 0x1f 0x3b>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x4 0xb5 0x5>;
        dma-names = "tx", "rx";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        rockchip,clk-trcm = <0x1>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xba 0xbb 0xbc 0xbd>;
        status = "disabled";
        phandle = <0x19d>;
    };

    i2s@fe430000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe430000 0x0 0x1000>;
        interrupts = <0x0 0x37 0x4>;
        clocks = <0x1f 0x53 0x1f 0x57 0x1f 0x3c>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x6 0xb5 0x7>;
        dma-names = "tx", "rx";
        resets = <0x1f 0x55 0x1f 0x56>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        rockchip,clk-trcm = <0x1>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xbe 0xbf 0xc0 0xc1>;
        status = "okay";
        phandle = <0x11d>;
    };

    pdm@fe440000 {
        compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
        reg = <0x0 0xfe440000 0x0 0x1000>;
        clocks = <0x1f 0x5a 0x1f 0x59>;
        clock-names = "pdm_clk", "pdm_hclk";
        dmas = <0xb5 0x9>;
        dma-names = "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0xc2 0xc3 0xc4 0xc5>;
        #sound-dai-cells = <0x0>;
        status = "disabled";
        phandle = <0x123>;
    };

    vad@fe450000 {
        compatible = "rockchip,rk3568-vad";
        reg = <0x0 0xfe450000 0x0 0x10000>;
        reg-names = "vad";
        clocks = <0x1f 0x5b>;
        clock-names = "hclk";
        interrupts = <0x0 0x89 0x4>;
        rockchip,audio-src = <0xc6>;
        rockchip,det-channel = <0x0>;
        rockchip,mode = <0x0>;
        #sound-dai-cells = <0x0>;
        status = "disabled";
        rockchip,buffer-time-ms = <0x80>;
        phandle = <0x128>;
    };

    spdif@fe460000 {
        compatible = "rockchip,rk3568-spdif";
        reg = <0x0 0xfe460000 0x0 0x1000>;
        interrupts = <0x0 0x66 0x4>;
        dmas = <0xb5 0x1>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x1f 0x5f 0x1f 0x5c>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xc7>;
        status = "okay";
        phandle = <0x126>;
    };

    audpwm@fe470000 {
        compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
        reg = <0x0 0xfe470000 0x0 0x1000>;
        clocks = <0x1f 0x63 0x1f 0x60>;
        clock-names = "clk", "hclk";
        dmas = <0xb5 0x8>;
        dma-names = "tx";
        #sound-dai-cells = <0x0>;
        rockchip,sample-width-bits = <0xb>;
        rockchip,interpolat-points = <0x1>;
        status = "disabled";
        phandle = <0x19e>;
    };

    codec-digital@fe478000 {
        compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
        reg = <0x0 0xfe478000 0x0 0x1000>;
        clocks = <0x1f 0x67 0x1f 0x66 0x1f 0x65 0x1f 0x64>;
        clock-names = "adc", "dac", "i2c", "pclk";
        pinctrl-names = "default";
        pinctrl-0 = <0xc8>;
        resets = <0x1f 0x5f>;
        reset-names = "reset";
        rockchip,grf = <0x32>;
        #sound-dai-cells = <0x0>;
        status = "disabled";
        phandle = <0x11e>;
    };

    dmac@fe530000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x0 0xfe530000 0x0 0x4000>;
        interrupts = <0x0 0xe 0x4 0x0 0xd 0x4>;
        clocks = <0x1f 0x10d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x1>;
        arm,pl330-periph-burst;
        phandle = <0x3f>;
    };

    dmac@fe550000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x0 0xfe550000 0x0 0x4000>;
        interrupts = <0x0 0x10 0x4 0x0 0xf 0x4>;
        clocks = <0x1f 0x10d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x1>;
        arm,pl330-periph-burst;
        phandle = <0xb5>;
    };

    rkscr@fe560000 {
        compatible = "rockchip-scr";
        reg = <0x0 0xfe560000 0x0 0x10000>;
        interrupts = <0x0 0x61 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xc9>;
        clocks = <0x1f 0x114>;
        clock-names = "g_pclk_sim_card";
        status = "disabled";
        phandle = <0x19f>;
    };

    can@fe570000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x0 0xfe570000 0x0 0x1000>;
        interrupts = <0x0 0x1 0x4>;
        clocks = <0x1f 0x141 0x1f 0x140>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x1f 0x155 0x1f 0x154>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x1>;
        rx-fifo-depth = <0x6>;
        status = "disabled";
        assigned-clocks = <0x1f 0x141>;
        assigned-clock-rates = <0x8f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0xca>;
        phandle = <0x1a0>;
    };

    can@fe580000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x0 0xfe580000 0x0 0x1000>;
        interrupts = <0x0 0x2 0x4>;
        clocks = <0x1f 0x143 0x1f 0x142>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x1f 0x157 0x1f 0x156>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x1>;
        rx-fifo-depth = <0x6>;
        status = "disabled";
        assigned-clocks = <0x1f 0x143>;
        assigned-clock-rates = <0x8f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcb>;
        phandle = <0x1a1>;
    };

    can@fe590000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x0 0xfe590000 0x0 0x1000>;
        interrupts = <0x0 0x3 0x4>;
        clocks = <0x1f 0x145 0x1f 0x144>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x1f 0x159 0x1f 0x158>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x1>;
        rx-fifo-depth = <0x6>;
        status = "disabled";
        assigned-clocks = <0x1f 0x145>;
        assigned-clock-rates = <0x8f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcc>;
        phandle = <0x1a2>;
    };

    i2c@fe5a0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5a0000 0x0 0x1000>;
        clocks = <0x1f 0x148 0x1f 0x147>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x2f 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcd>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x1a3>;

        gt1x@14 {
            compatible = "goodix,gt1x";
            reg = <0x14>;
            pinctrl-names = "default";
            pinctrl-0 = <0xce>;
            goodix,rst-gpio = <0x35 0xe 0x0>;
            goodix,irq-gpio = <0x35 0xd 0x8>;
            power-supply = <0x92>;
            status = "disabled";
            phandle = <0x1a4>;
        };
    };

    i2c@fe5b0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5b0000 0x0 0x1000>;
        clocks = <0x1f 0x14a 0x1f 0x149>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x30 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcf>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x1a5>;

        gc2145@3c {
            status = "okay";
            compatible = "galaxycore,gc2145";
            reg = <0x3c>;
            clocks = <0x1f 0xd6>;
            clock-names = "xvclk";
            power-domains = <0x21 0x8>;
            pinctrl-names = "default";
            pinctrl-0 = <0xd0 0xd1 0xd2>;
            power-gpios = <0x7b 0x1c 0x0>;
            pwdn-gpios = <0x7b 0x1a 0x0>;
            rockchip,camera-module-index = <0x1>;
            rockchip,camera-module-facing = "front";
            rockchip,camera-module-name = "CameraKing";
            rockchip,camera-module-lens-name = "Largan";
            phandle = <0x1a6>;

            port {

                endpoint {
                    remote-endpoint = <0xd3>;
                    phandle = <0x72>;
                };
            };
        };

        ov5695@36 {
            status = "okay";
            compatible = "ovti,ov5695";
            reg = <0x36>;
            clocks = <0x1f 0xd7>;
            clock-names = "xvclk";
            power-domains = <0x21 0x8>;
            pinctrl-names = "default";
            pinctrl-0 = <0xd4>;
            reset-gpios = <0x7b 0x18 0x0>;
            pwdn-gpios = <0x7b 0x16 0x0>;
            rockchip,camera-module-index = <0x0>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "TongJu";
            rockchip,camera-module-lens-name = "CHT842-MD";
            phandle = <0x1a7>;

            port {

                endpoint {
                    remote-endpoint = <0xd5>;
                    data-lanes = <0x1 0x2>;
                    phandle = <0x108>;
                };
            };
        };

        gc8034@37 {
            compatible = "galaxycore,gc8034";
            status = "okay";
            reg = <0x37>;
            clocks = <0x1f 0xd7>;
            clock-names = "xvclk";
            power-domains = <0x21 0x8>;
            pinctrl-names = "default";
            pinctrl-0 = <0xd4>;
            reset-gpios = <0x7b 0x18 0x1>;
            pwdn-gpios = <0x7b 0x16 0x1>;
            rockchip,camera-module-index = <0x0>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "RK-CMK-8M-2-v1";
            rockchip,camera-module-lens-name = "CK8401";
            phandle = <0x1a8>;

            port {

                endpoint {
                    remote-endpoint = <0xd6>;
                    data-lanes = <0x1 0x2 0x3 0x4>;
                    phandle = <0x109>;
                };
            };
        };
    };

    i2c@fe5c0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5c0000 0x0 0x1000>;
        clocks = <0x1f 0x14c 0x1f 0x14b>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x31 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xd7>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x1a9>;
    };

    i2c@fe5d0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5d0000 0x0 0x1000>;
        clocks = <0x1f 0x14e 0x1f 0x14d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x32 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xd8>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x1aa>;
    };

    i2c@fe5e0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5e0000 0x0 0x1000>;
        clocks = <0x1f 0x150 0x1f 0x14f>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x33 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xd9>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x1ab>;

        mxc6655xa@15 {
            status = "okay";
            compatible = "gs_mxc6655xa";
            pinctrl-names = "default";
            pinctrl-0 = <0xda>;
            reg = <0x15>;
            irq-gpio = <0x7b 0x11 0x8>;
            irq_enable = <0x0>;
            poll_delay_ms = <0x1e>;
            type = <0x2>;
            power-off-in-suspend = <0x1>;
            layout = <0x1>;
            phandle = <0x1ac>;
        };
    };

    timer@fe5f0000 {
        compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
        reg = <0x0 0xfe5f0000 0x0 0x1000>;
        interrupts = <0x0 0x6d 0x4>;
        clocks = <0x1f 0x16c 0x1f 0x16d>;
        clock-names = "pclk", "timer";
        phandle = <0x1ad>;
    };

    watchdog@fe600000 {
        compatible = "snps,dw-wdt";
        reg = <0x0 0xfe600000 0x0 0x100>;
        clocks = <0x1f 0x116 0x1f 0x115>;
        clock-names = "tclk", "pclk";
        interrupts = <0x0 0x95 0x4>;
        status = "okay";
        phandle = <0x1ae>;
    };

    spi@fe610000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe610000 0x0 0x1000>;
        interrupts = <0x0 0x67 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x152 0x1f 0x151>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x14 0x3f 0x15>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xdb 0xdc 0xdd>;
        pinctrl-1 = <0xdb 0xdc 0xde>;
        status = "disabled";
        phandle = <0x1af>;
    };

    spi@fe620000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe620000 0x0 0x1000>;
        interrupts = <0x0 0x68 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x154 0x1f 0x153>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x16 0x3f 0x17>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xdf 0xe0 0xe1>;
        pinctrl-1 = <0xdf 0xe0 0xe2>;
        status = "disabled";
        phandle = <0x1b0>;
    };

    spi@fe630000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe630000 0x0 0x1000>;
        interrupts = <0x0 0x69 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x156 0x1f 0x155>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x18 0x3f 0x19>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xe3 0xe4 0xe5>;
        pinctrl-1 = <0xe3 0xe4 0xe6>;
        status = "disabled";
        phandle = <0x1b1>;
    };

    spi@fe640000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe640000 0x0 0x1000>;
        interrupts = <0x0 0x6a 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x158 0x1f 0x157>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x1a 0x3f 0x1b>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xe7 0xe8 0xe9>;
        pinctrl-1 = <0xe7 0xe8 0xea>;
        status = "disabled";
        phandle = <0x1b2>;
    };

    serial@fe650000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe650000 0x0 0x100>;
        interrupts = <0x0 0x75 0x4>;
        clocks = <0x1f 0x11f 0x1f 0x11c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x2 0x3f 0x3>;
        pinctrl-names = "default";
        pinctrl-0 = <0xeb 0xec>;
        status = "okay";
        phandle = <0x1b3>;
    };

    serial@fe660000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe660000 0x0 0x100>;
        interrupts = <0x0 0x76 0x4>;
        clocks = <0x1f 0x123 0x1f 0x120>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x4 0x3f 0x5>;
        pinctrl-names = "default";
        pinctrl-0 = <0xed>;
        status = "disabled";
        phandle = <0x1b4>;
    };

    serial@fe670000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe670000 0x0 0x100>;
        interrupts = <0x0 0x77 0x4>;
        clocks = <0x1f 0x127 0x1f 0x124>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x6 0x3f 0x7>;
        pinctrl-names = "default";
        pinctrl-0 = <0xee>;
        status = "disabled";
        phandle = <0x1b5>;
    };

    serial@fe680000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe680000 0x0 0x100>;
        interrupts = <0x0 0x78 0x4>;
        clocks = <0x1f 0x12b 0x1f 0x128>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x8 0x3f 0x9>;
        pinctrl-names = "default";
        pinctrl-0 = <0xef>;
        status = "disabled";
        phandle = <0x1b6>;
    };

    serial@fe690000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe690000 0x0 0x100>;
        interrupts = <0x0 0x79 0x4>;
        clocks = <0x1f 0x12f 0x1f 0x12c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0xa 0x3f 0xb>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf0>;
        status = "disabled";
        phandle = <0x1b7>;
    };

    serial@fe6a0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6a0000 0x0 0x100>;
        interrupts = <0x0 0x7a 0x4>;
        clocks = <0x1f 0x133 0x1f 0x130>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0xc 0x3f 0xd>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf1>;
        status = "disabled";
        phandle = <0x1b8>;
    };

    serial@fe6b0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6b0000 0x0 0x100>;
        interrupts = <0x0 0x7b 0x4>;
        clocks = <0x1f 0x137 0x1f 0x134>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0xe 0x3f 0xf>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf2>;
        status = "disabled";
        phandle = <0x1b9>;
    };

    serial@fe6c0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6c0000 0x0 0x100>;
        interrupts = <0x0 0x7c 0x4>;
        clocks = <0x1f 0x13b 0x1f 0x138>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x10 0x3f 0x11>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf3>;
        status = "disabled";
        phandle = <0x1ba>;
    };

    serial@fe6d0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6d0000 0x0 0x100>;
        interrupts = <0x0 0x7d 0x4>;
        clocks = <0x1f 0x13f 0x1f 0x13c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x12 0x3f 0x13>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf4>;
        status = "disabled";
        phandle = <0x1bb>;
    };

    pwm@fe6e0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6e0000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf5>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x11f>;
    };

    pwm@fe6e0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6e0010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf6>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x120>;
    };

    pwm@fe6e0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6e0020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf7>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1bc>;
    };

    pwm@fe6e0030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x0 0xfe6e0030 0x0 0x10>;
        interrupts = <0x0 0x53 0x4 0x0 0x57 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf8>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        remote_pwm_id = <0x3>;
        handle_cpu_id = <0x1>;
        remote_support_psci = <0x0>;
        phandle = <0x1bd>;

        ir_key1 {
            rockchip,usercode = <0x4040>;
            rockchip,key_table = <0xf2 0xe8 0xba 0x9e 0xf4 0x67 0xf1 0x6c 0xef 0x69 0xee 0x6a 0xbd 0x66 0xea 0x73 0xe3 0x72 0xe2 0xd9 0xb2 0x74 0xbc 0x71 0xec 0x8b 0xbf 0x190 0xe0 0x191 0xe1 0x192 0xe9 0xb7 0xe6 0xf8 0xe8 0xb9 0xe7 0xba 0xf0 0x184 0xbe 0x175>;
        };

        ir_key2 {
            rockchip,usercode = <0xff00>;
            rockchip,key_table = <0xf9 0x66 0xbf 0x9e 0xfb 0x8b 0xaa 0xe8 0xb9 0x67 0xe9 0x6c 0xb8 0x69 0xea 0x6a 0xeb 0x72 0xef 0x73 0xf7 0x71 0xe7 0x74 0xfc 0x74 0xa9 0x72 0xa8 0x72 0xe0 0x72 0xa5 0x72 0xab 0xb7 0xb7 0x184 0xe8 0x184 0xf8 0xb8 0xaf 0xb9 0xed 0x72 0xee 0xba 0xb3 0x72 0xf1 0x72 0xf2 0x72 0xf3 0xd9 0xb4 0x72 0xbe 0xd9>;
        };

        ir_key3 {
            rockchip,usercode = <0x1dcc>;
            rockchip,key_table = <0xee 0xe8 0xf0 0x9e 0xf8 0x67 0xbb 0x6c 0xef 0x69 0xed 0x6a 0xfc 0x66 0xf1 0x73 0xfd 0x72 0xb7 0xd9 0xff 0x74 0xf3 0x71 0xbf 0x8b 0xf9 0x191 0xf5 0x192 0xb3 0x184 0xbe 0x2 0xba 0x3 0xb2 0x4 0xbd 0x5 0xf9 0x6 0xb1 0x7 0xfc 0x8 0xf8 0x9 0xb0 0xa 0xb6 0xb 0xb5 0xe>;
        };
    };

    pwm@fe6f0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf9>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1be>;
    };

    pwm@fe6f0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfa>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1bf>;
    };

    pwm@fe6f0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfb>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c0>;
    };

    pwm@fe6f0030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0030 0x0 0x10>;
        interrupts = <0x0 0x54 0x4 0x0 0x58 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfc>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c1>;
    };

    pwm@fe700000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfd>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c2>;
    };

    pwm@fe700010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfe>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c3>;
    };

    pwm@fe700020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xff>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c4>;
    };

    pwm@fe700030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700030 0x0 0x10>;
        interrupts = <0x0 0x55 0x4 0x0 0x59 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x100>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c5>;
    };

    tsadc@fe710000 {
        compatible = "rockchip,rk3568-tsadc";
        reg = <0x0 0xfe710000 0x0 0x100>;
        interrupts = <0x0 0x73 0x4>;
        rockchip,grf = <0x32>;
        clocks = <0x1f 0x111 0x1f 0x10f>;
        clock-names = "tsadc", "apb_pclk";
        assigned-clocks = <0x1f 0x110 0x1f 0x111>;
        assigned-clock-rates = <0x1036640 0xaae60>;
        resets = <0x1f 0x182 0x1f 0x181 0x1f 0x1d7>;
        reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
        #thermal-sensor-cells = <0x1>;
        rockchip,hw-tshut-temp = <0x1d4c0>;
        rockchip,hw-tshut-mode = <0x0>;
        rockchip,hw-tshut-polarity = <0x0>;
        pinctrl-names = "gpio", "otpout";
        pinctrl-0 = <0x101>;
        pinctrl-1 = <0x102>;
        status = "okay";
        phandle = <0x1b>;
    };

    saradc@fe720000 {
        compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
        reg = <0x0 0xfe720000 0x0 0x100>;
        interrupts = <0x0 0x5d 0x4>;
        #io-channel-cells = <0x1>;
        clocks = <0x1f 0x113 0x1f 0x112>;
        clock-names = "saradc", "apb_pclk";
        resets = <0x1f 0x180>;
        reset-names = "saradc-apb";
        status = "okay";
        vref-supply = <0x103>;
        phandle = <0x11b>;
    };

    mailbox@fe780000 {
        compatible = "rockchip,rk3568-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x0 0xfe780000 0x0 0x1000>;
        interrupts = <0x0 0xb7 0x4 0x0 0xb8 0x4 0x0 0xb9 0x4 0x0 0xba 0x4>;
        clocks = <0x1f 0x11b>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x1>;
        status = "disabled";
        phandle = <0x1c6>;
    };

    phy@fe830000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x0 0xfe830000 0x0 0x100>;
        #phy-cells = <0x1>;
        clocks = <0x31 0x22 0x1f 0x17d 0x1f 0x7f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x31 0x22>;
        assigned-clock-rates = <0x5f5e100>;
        resets = <0x1f 0x1c6 0x1f 0x1c7>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x104>;
        rockchip,pipe-phy-grf = <0x105>;
        status = "okay";
        phandle = <0x20>;
    };

    phy@fe840000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x0 0xfe840000 0x0 0x100>;
        #phy-cells = <0x1>;
        clocks = <0x31 0x25 0x1f 0x17e 0x1f 0x7f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x31 0x25>;
        assigned-clock-rates = <0x5f5e100>;
        resets = <0x1f 0x1c8 0x1f 0x1c9>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x104>;
        rockchip,pipe-phy-grf = <0x106>;
        status = "disabled";
        phandle = <0x22>;
    };

    mipi-dphy@fe850000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x0 0xfe850000 0x0 0x10000>;
        clocks = <0x31 0x17 0x1f 0x17a>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy_pll";
        #clock-cells = <0x0>;
        resets = <0x1f 0x1bb>;
        reset-names = "apb";
        power-domains = <0x21 0x9>;
        #phy-cells = <0x0>;
        rockchip,grf = <0x32>;
        status = "okay";
        phandle = <0x8e>;
    };

    video-phy@fe850000 {
        compatible = "rockchip,rk3568-video-phy";
        reg = <0x0 0xfe850000 0x0 0x10000 0x0 0xfe060000 0x0 0x10000>;
        clocks = <0x31 0x17 0x1f 0x17a 0x1f 0xe8>;
        clock-names = "ref", "pclk_phy", "pclk_host";
        #clock-cells = <0x0>;
        resets = <0x1f 0x1bb>;
        reset-names = "rst";
        power-domains = <0x21 0x9>;
        #phy-cells = <0x0>;
        status = "disabled";
        phandle = <0x2e>;
    };

    mipi-dphy@fe860000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x0 0xfe860000 0x0 0x10000>;
        clocks = <0x31 0x19 0x1f 0x17b>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy1_pll";
        #clock-cells = <0x0>;
        resets = <0x1f 0x1bc>;
        reset-names = "apb";
        power-domains = <0x21 0x9>;
        #phy-cells = <0x0>;
        rockchip,grf = <0x32>;
        status = "disabled";
        phandle = <0x97>;
    };

    csi2-dphy-hw@fe870000 {
        compatible = "rockchip,rk3568-csi2-dphy-hw";
        reg = <0x0 0xfe870000 0x0 0x1000>;
        clocks = <0x1f 0x179>;
        clock-names = "pclk";
        rockchip,grf = <0x32>;
        status = "okay";
        phandle = <0x107>;
    };

    csi2-dphy0 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x107>;
        status = "okay";
        phandle = <0x1c7>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x108>;
                    data-lanes = <0x1 0x2>;
                    phandle = <0xd5>;
                };

                endpoint@2 {
                    reg = <0x2>;
                    remote-endpoint = <0x109>;
                    data-lanes = <0x1 0x2 0x3 0x4>;
                    phandle = <0xd6>;
                };
            };

            port@1 {
                reg = <0x1>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x10a>;
                    phandle = <0x77>;
                };
            };
        };
    };

    csi2-dphy1 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x107>;
        status = "disabled";
        phandle = <0x1c8>;
    };

    csi2-dphy2 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x107>;
        status = "disabled";
        phandle = <0x1c9>;
    };

    usb2-phy@fe8a0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x0 0xfe8a0000 0x0 0x10000>;
        interrupts = <0x0 0x87 0x4>;
        clocks = <0x31 0x13>;
        clock-names = "phyclk";
        #clock-cells = <0x0>;
        assigned-clocks = <0x1f 0xb>;
        assigned-clock-parents = <0x24>;
        clock-output-names = "usb480m_phy";
        rockchip,usbgrf = <0x10b>;
        status = "okay";
        phandle = <0x24>;

        host-port {
            #phy-cells = <0x0>;
            status = "okay";
            phy-supply = <0x10c>;
            phandle = <0x25>;
        };

        otg-port {
            #phy-cells = <0x0>;
            status = "okay";
            vbus-supply = <0x10d>;
            phandle = <0x23>;
        };
    };

    usb2-phy@fe8b0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x0 0xfe8b0000 0x0 0x10000>;
        interrupts = <0x0 0x88 0x4>;
        clocks = <0x31 0x15>;
        clock-names = "phyclk";
        #clock-cells = <0x0>;
        rockchip,usbgrf = <0x10e>;
        status = "okay";
        phandle = <0x26>;

        host-port {
            #phy-cells = <0x0>;
            status = "okay";
            phy-supply = <0x10c>;
            phandle = <0x28>;
        };

        otg-port {
            #phy-cells = <0x0>;
            status = "okay";
            phy-supply = <0x10c>;
            phandle = <0x27>;
        };
    };

    pinctrl {
        compatible = "rockchip,rk3568-pinctrl";
        rockchip,grf = <0x32>;
        rockchip,pmu = <0x33>;
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        pinctrl-names = "default";
        pinctrl-0 = <0x10f>;
        phandle = <0x110>;

        gpio@fdd60000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfdd60000 0x0 0x100>;
            interrupts = <0x0 0x21 0x4>;
            clocks = <0x31 0x2e 0x31 0xc>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x0 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x35>;
        };

        gpio@fe740000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe740000 0x0 0x100>;
            interrupts = <0x0 0x22 0x4>;
            clocks = <0x1f 0x163 0x1f 0x164>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x20 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x93>;
        };

        gpio@fe750000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe750000 0x0 0x100>;
            interrupts = <0x0 0x23 0x4>;
            clocks = <0x1f 0x165 0x1f 0x166>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x40 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x12e>;
        };

        gpio@fe760000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe760000 0x0 0x100>;
            interrupts = <0x0 0x24 0x4>;
            clocks = <0x1f 0x167 0x1f 0x168>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x60 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x7b>;
        };

        gpio@fe770000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe770000 0x0 0x100>;
            interrupts = <0x0 0x25 0x4>;
            clocks = <0x1f 0x169 0x1f 0x16a>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x80 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x9c>;
        };

        pcfg-pull-up {
            bias-pull-up;
            phandle = <0x113>;
        };

        pcfg-pull-down {
            bias-pull-down;
            phandle = <0x11a>;
        };

        pcfg-pull-none {
            bias-disable;
            phandle = <0x111>;
        };

        pcfg-pull-none-drv-level-1 {
            bias-disable;
            drive-strength = <0x1>;
            phandle = <0x115>;
        };

        pcfg-pull-none-drv-level-2 {
            bias-disable;
            drive-strength = <0x2>;
            phandle = <0x114>;
        };

        pcfg-pull-none-drv-level-3 {
            bias-disable;
            drive-strength = <0x3>;
            phandle = <0x119>;
        };

        pcfg-pull-up-drv-level-1 {
            bias-pull-up;
            drive-strength = <0x1>;
            phandle = <0x118>;
        };

        pcfg-pull-up-drv-level-2 {
            bias-pull-up;
            drive-strength = <0x2>;
            phandle = <0x112>;
        };

        pcfg-pull-none-smt {
            bias-disable;
            input-schmitt-enable;
            phandle = <0x116>;
        };

        pcfg-output-low {
            output-low;
            phandle = <0x117>;
        };

        acodec {

            acodec-pins {
                rockchip,pins = <0x1 0x9 0x5 0x111 0x1 0x1 0x5 0x111 0x1 0x0 0x5 0x111 0x1 0x7 0x5 0x111 0x1 0x8 0x5 0x111 0x1 0x3 0x5 0x111 0x1 0x5 0x5 0x111>;
                phandle = <0xc8>;
            };
        };

        cam {

            cam-clkout0 {
                rockchip,pins = <0x4 0x7 0x1 0x111>;
                phandle = <0xd4>;
            };

            camera-pwr {
                rockchip,pins = <0x0 0x11 0x0 0x111>;
                phandle = <0x133>;
            };
        };

        can0 {

            can0m1-pins {
                rockchip,pins = <0x2 0x2 0x4 0x111 0x2 0x1 0x4 0x111>;
                phandle = <0xca>;
            };
        };

        can1 {

            can1m1-pins {
                rockchip,pins = <0x4 0x12 0x3 0x111 0x4 0x13 0x3 0x111>;
                phandle = <0xcb>;
            };
        };

        can2 {

            can2m1-pins {
                rockchip,pins = <0x2 0x9 0x4 0x111 0x2 0xa 0x4 0x111>;
                phandle = <0xcc>;
            };
        };

        cif {

            cif-clk {
                rockchip,pins = <0x4 0x10 0x1 0x111>;
                phandle = <0xd0>;
            };

            cif-dvp-clk {
                rockchip,pins = <0x4 0x11 0x1 0x111 0x4 0xe 0x1 0x111 0x4 0xf 0x1 0x111>;
                phandle = <0xd1>;
            };

            cif-dvp-bus16 {
                rockchip,pins = <0x3 0x1e 0x1 0x111 0x3 0x1f 0x1 0x111 0x4 0x0 0x1 0x111 0x4 0x1 0x1 0x111 0x4 0x2 0x1 0x111 0x4 0x3 0x1 0x111 0x4 0x4 0x1 0x111 0x4 0x5 0x1 0x111>;
                phandle = <0xd2>;
            };
        };

        clk32k {

            clk32k-out0 {
                rockchip,pins = <0x0 0x8 0x2 0x111>;
                phandle = <0x1e>;
            };
        };

        ebc {

            ebc-pins {
                rockchip,pins = <0x4 0x10 0x2 0x111 0x4 0xb 0x2 0x111 0x4 0xc 0x2 0x111 0x4 0x6 0x2 0x111 0x4 0x11 0x2 0x111 0x3 0x16 0x2 0x111 0x3 0x17 0x2 0x111 0x3 0x18 0x2 0x111 0x3 0x19 0x2 0x111 0x3 0x1a 0x2 0x111 0x3 0x1b 0x2 0x111 0x3 0x1c 0x2 0x111 0x3 0x1d 0x2 0x111 0x3 0x1e 0x2 0x111 0x3 0x1f 0x2 0x111 0x4 0x0 0x2 0x111 0x4 0x1 0x2 0x111 0x4 0x2 0x2 0x111 0x4 0x3 0x2 0x111 0x4 0x4 0x2 0x111 0x4 0x5 0x2 0x111 0x4 0xe 0x2 0x111 0x4 0xf 0x2 0x111>;
                phandle = <0x68>;
            };
        };

        gmac1 {

            gmac1m0-miim {
                rockchip,pins = <0x3 0x14 0x3 0x111 0x3 0x15 0x3 0x111>;
                phandle = <0x7c>;
            };

            gmac1m0-rx-bus2 {
                rockchip,pins = <0x3 0x9 0x3 0x111 0x3 0xa 0x3 0x111 0x3 0xb 0x3 0x111>;
                phandle = <0x7e>;
            };
        };

        hdmitx {

            hdmitxm0-cec {
                rockchip,pins = <0x4 0x19 0x1 0x111>;
                phandle = <0xa2>;
            };

            hdmitx-scl {
                rockchip,pins = <0x4 0x17 0x1 0x111>;
                phandle = <0xa0>;
            };

            hdmitx-sda {
                rockchip,pins = <0x4 0x18 0x1 0x111>;
                phandle = <0xa1>;
            };
        };

        i2c0 {

            i2c0-xfer {
                rockchip,pins = <0x0 0x9 0x1 0x116 0x0 0xa 0x1 0x116>;
                phandle = <0x34>;
            };
        };

        i2c1 {

            i2c1-xfer {
                rockchip,pins = <0x0 0xb 0x1 0x116 0x0 0xc 0x1 0x116>;
                phandle = <0xcd>;
            };
        };

        i2c2 {

            i2c2m1-xfer {
                rockchip,pins = <0x4 0xd 0x1 0x116 0x4 0xc 0x1 0x116>;
                phandle = <0xcf>;
            };
        };

        i2c3 {

            i2c3m0-xfer {
                rockchip,pins = <0x1 0x1 0x1 0x116 0x1 0x0 0x1 0x116>;
                phandle = <0xd7>;
            };
        };

        i2c4 {

            i2c4m0-xfer {
                rockchip,pins = <0x4 0xb 0x1 0x116 0x4 0xa 0x1 0x116>;
                phandle = <0xd8>;
            };
        };

        i2c5 {

            i2c5m0-xfer {
                rockchip,pins = <0x3 0xb 0x4 0x116 0x3 0xc 0x4 0x116>;
                phandle = <0xd9>;
            };
        };

        i2s1 {

            i2s1m0-lrcktx {
                rockchip,pins = <0x1 0x5 0x1 0x111>;
                phandle = <0xb7>;
            };

            i2s1m0-sclktx {
                rockchip,pins = <0x1 0x3 0x1 0x111>;
                phandle = <0xb6>;
            };

            i2s1m0-sdi0 {
                rockchip,pins = <0x1 0xb 0x1 0x111>;
                phandle = <0xb8>;
            };

            i2s1m0-sdo0 {
                rockchip,pins = <0x1 0x7 0x1 0x111>;
                phandle = <0xb9>;
            };
        };

        i2s2 {

            i2s2m0-lrcktx {
                rockchip,pins = <0x2 0x13 0x1 0x111>;
                phandle = <0xbb>;
            };

            i2s2m0-sclktx {
                rockchip,pins = <0x2 0x12 0x1 0x111>;
                phandle = <0xba>;
            };

            i2s2m0-sdi {
                rockchip,pins = <0x2 0x15 0x1 0x111>;
                phandle = <0xbc>;
            };

            i2s2m0-sdo {
                rockchip,pins = <0x2 0x14 0x1 0x111>;
                phandle = <0xbd>;
            };
        };

        i2s3 {

            i2s3m1-lrck {
                rockchip,pins = <0x4 0x14 0x5 0x111>;
                phandle = <0xbf>;
            };

            i2s3m1-mclk {
                rockchip,pins = <0x4 0x12 0x5 0x111>;
                phandle = <0x3d>;
            };

            i2s3m1-sclk {
                rockchip,pins = <0x4 0x13 0x5 0x111>;
                phandle = <0xbe>;
            };

            i2s3m1-sdi {
                rockchip,pins = <0x4 0x16 0x5 0x111>;
                phandle = <0xc0>;
            };

            i2s3m1-sdo {
                rockchip,pins = <0x4 0x15 0x5 0x111>;
                phandle = <0xc1>;
            };
        };

        lcdc {

            lcdc-ctl {
                rockchip,pins = <0x3 0x0 0x1 0x111 0x2 0x18 0x1 0x111 0x2 0x19 0x1 0x111 0x2 0x1a 0x1 0x111 0x2 0x1b 0x1 0x111 0x2 0x1c 0x1 0x111 0x2 0x1d 0x1 0x111 0x2 0x1e 0x1 0x111 0x2 0x1f 0x1 0x111 0x3 0x1 0x1 0x111 0x3 0x2 0x1 0x111 0x3 0x3 0x1 0x111 0x3 0x4 0x1 0x111 0x3 0x5 0x1 0x111 0x3 0x6 0x1 0x111 0x3 0x7 0x1 0x111 0x3 0x8 0x1 0x111 0x3 0x9 0x1 0x111 0x3 0xa 0x1 0x111 0x3 0xb 0x1 0x111 0x3 0xc 0x1 0x111 0x3 0xd 0x1 0x111 0x3 0xe 0x1 0x111 0x3 0xf 0x1 0x111 0x3 0x10 0x1 0x111 0x3 0x13 0x1 0x111 0x3 0x11 0x1 0x111 0x3 0x12 0x1 0x111>;
                phandle = <0x30>;
            };
        };

        pdm {

            pdmm1-clk1 {
                rockchip,pins = <0x4 0x0 0x4 0x111>;
                phandle = <0xc2>;
            };

            pdmm1-sdi1 {
                rockchip,pins = <0x4 0x1 0x4 0x111>;
                phandle = <0xc3>;
            };

            pdmm1-sdi2 {
                rockchip,pins = <0x4 0x2 0x5 0x111>;
                phandle = <0xc4>;
            };

            pdmm1-sdi3 {
                rockchip,pins = <0x4 0x3 0x5 0x111>;
                phandle = <0xc5>;
            };
        };

        pmic {

            pmic_int {
                rockchip,pins = <0x0 0x3 0x0 0x113>;
                phandle = <0x36>;
            };

            soc_slppin_gpio {
                rockchip,pins = <0x0 0x2 0x0 0x117>;
                phandle = <0x39>;
            };

            soc_slppin_slp {
                rockchip,pins = <0x0 0x2 0x1 0x111>;
                phandle = <0x37>;
            };

            soc_slppin_rst {
                rockchip,pins = <0x0 0x2 0x2 0x111>;
                phandle = <0x1ca>;
            };
        };

        pwm0 {

            pwm0m0-pins {
                rockchip,pins = <0x0 0xf 0x1 0x111>;
                phandle = <0x41>;
            };
        };

        pwm1 {

            pwm1m0-pins {
                rockchip,pins = <0x0 0x10 0x1 0x111>;
                phandle = <0x42>;
            };
        };

        pwm2 {

            pwm2m0-pins {
                rockchip,pins = <0x0 0x11 0x1 0x111>;
                phandle = <0x43>;
            };
        };

        pwm3 {

            pwm3-pins {
                rockchip,pins = <0x0 0x12 0x1 0x111>;
                phandle = <0x44>;
            };
        };

        pwm4 {

            pwm4-pins {
                rockchip,pins = <0x0 0x13 0x1 0x111>;
                phandle = <0xf5>;
            };
        };

        pwm5 {

            pwm5-pins {
                rockchip,pins = <0x0 0x14 0x1 0x111>;
                phandle = <0xf6>;
            };
        };

        pwm6 {

            pwm6-pins {
                rockchip,pins = <0x0 0x15 0x1 0x111>;
                phandle = <0xf7>;
            };
        };

        pwm7 {

            pwm7-pins {
                rockchip,pins = <0x0 0x16 0x1 0x111>;
                phandle = <0xf8>;
            };
        };

        pwm8 {

            pwm8m0-pins {
                rockchip,pins = <0x3 0x9 0x5 0x111>;
                phandle = <0xf9>;
            };
        };

        pwm9 {

            pwm9m0-pins {
                rockchip,pins = <0x3 0xa 0x5 0x111>;
                phandle = <0xfa>;
            };
        };

        pwm10 {

            pwm10m0-pins {
                rockchip,pins = <0x3 0xd 0x5 0x111>;
                phandle = <0xfb>;
            };
        };

        pwm11 {

            pwm11m0-pins {
                rockchip,pins = <0x3 0xe 0x5 0x111>;
                phandle = <0xfc>;
            };
        };

        pwm12 {

            pwm12m0-pins {
                rockchip,pins = <0x3 0xf 0x2 0x111>;
                phandle = <0xfd>;
            };
        };

        pwm13 {

            pwm13m0-pins {
                rockchip,pins = <0x3 0x10 0x2 0x111>;
                phandle = <0xfe>;
            };
        };

        pwm14 {

            pwm14m0-pins {
                rockchip,pins = <0x3 0x14 0x1 0x111>;
                phandle = <0xff>;
            };
        };

        pwm15 {

            pwm15m0-pins {
                rockchip,pins = <0x3 0x15 0x1 0x111>;
                phandle = <0x100>;
            };
        };

        scr {

            scr-pins {
                rockchip,pins = <0x1 0x2 0x3 0x111 0x1 0x7 0x3 0x113 0x1 0x3 0x3 0x113 0x1 0x5 0x3 0x111>;
                phandle = <0xc9>;
            };
        };

        sdmmc0 {

            sdmmc0-bus4 {
                rockchip,pins = <0x1 0x1d 0x1 0x112 0x1 0x1e 0x1 0x112 0x1 0x1f 0x1 0x112 0x2 0x0 0x1 0x112>;
                phandle = <0xad>;
            };

            sdmmc0-clk {
                rockchip,pins = <0x2 0x2 0x1 0x112>;
                phandle = <0xae>;
            };

            sdmmc0-cmd {
                rockchip,pins = <0x2 0x1 0x1 0x112>;
                phandle = <0xaf>;
            };

            sdmmc0-det {
                rockchip,pins = <0x0 0x4 0x1 0x113>;
                phandle = <0xb0>;
            };
        };

        sdmmc1 {

            sdmmc1-bus4 {
                rockchip,pins = <0x2 0x3 0x1 0x112 0x2 0x4 0x1 0x112 0x2 0x5 0x1 0x112 0x2 0x6 0x1 0x112>;
                phandle = <0xb2>;
            };

            sdmmc1-clk {
                rockchip,pins = <0x2 0x8 0x1 0x112>;
                phandle = <0xb4>;
            };

            sdmmc1-cmd {
                rockchip,pins = <0x2 0x7 0x1 0x112>;
                phandle = <0xb3>;
            };
        };

        spdif {

            spdifm0-tx {
                rockchip,pins = <0x1 0x4 0x4 0x111>;
                phandle = <0xc7>;
            };
        };

        spi0 {

            spi0m0-pins {
                rockchip,pins = <0x0 0xd 0x2 0x111 0x0 0x15 0x2 0x111 0x0 0xe 0x2 0x111>;
                phandle = <0xdd>;
            };

            spi0m0-cs0 {
                rockchip,pins = <0x0 0x16 0x2 0x111>;
                phandle = <0xdb>;
            };

            spi0m0-cs1 {
                rockchip,pins = <0x0 0x14 0x2 0x111>;
                phandle = <0xdc>;
            };
        };

        spi1 {

            spi1m0-pins {
                rockchip,pins = <0x2 0xd 0x3 0x111 0x2 0xe 0x3 0x111 0x2 0xf 0x4 0x111>;
                phandle = <0xe1>;
            };

            spi1m0-cs0 {
                rockchip,pins = <0x2 0x10 0x4 0x111>;
                phandle = <0xdf>;
            };

            spi1m0-cs1 {
                rockchip,pins = <0x2 0x16 0x3 0x111>;
                phandle = <0xe0>;
            };
        };

        spi2 {

            spi2m0-pins {
                rockchip,pins = <0x2 0x11 0x4 0x111 0x2 0x12 0x4 0x111 0x2 0x13 0x4 0x111>;
                phandle = <0xe5>;
            };

            spi2m0-cs0 {
                rockchip,pins = <0x2 0x14 0x4 0x111>;
                phandle = <0xe3>;
            };

            spi2m0-cs1 {
                rockchip,pins = <0x2 0x15 0x4 0x111>;
                phandle = <0xe4>;
            };
        };

        spi3 {

            spi3m0-pins {
                rockchip,pins = <0x4 0xb 0x4 0x111 0x4 0x8 0x4 0x111 0x4 0xa 0x4 0x111>;
                phandle = <0xe9>;
            };

            spi3m0-cs0 {
                rockchip,pins = <0x4 0x6 0x4 0x111>;
                phandle = <0xe7>;
            };

            spi3m0-cs1 {
                rockchip,pins = <0x4 0x7 0x4 0x111>;
                phandle = <0xe8>;
            };
        };

        tsadc {

            tsadc-shutorg {
                rockchip,pins = <0x0 0x1 0x2 0x111>;
                phandle = <0x102>;
            };
        };

        uart0 {

            uart0-xfer {
                rockchip,pins = <0x0 0x10 0x3 0x113 0x0 0x11 0x3 0x113>;
                phandle = <0x40>;
            };
        };

        uart1 {

            uart1m0-xfer {
                rockchip,pins = <0x2 0xb 0x2 0x113 0x2 0xc 0x2 0x113>;
                phandle = <0xeb>;
            };

            uart1m0-ctsn {
                rockchip,pins = <0x2 0xe 0x2 0x111>;
                phandle = <0xec>;
            };

            uart1m0-rtsn {
                rockchip,pins = <0x2 0xd 0x2 0x111>;
                phandle = <0x130>;
            };
        };

        uart2 {

            uart2m0-xfer {
                rockchip,pins = <0x0 0x18 0x1 0x113 0x0 0x19 0x1 0x113>;
                phandle = <0xed>;
            };
        };

        uart3 {

            uart3m0-xfer {
                rockchip,pins = <0x1 0x0 0x2 0x113 0x1 0x1 0x2 0x113>;
                phandle = <0xee>;
            };
        };

        uart4 {

            uart4m0-xfer {
                rockchip,pins = <0x1 0x4 0x2 0x113 0x1 0x6 0x2 0x113>;
                phandle = <0xef>;
            };
        };

        uart5 {

            uart5m0-xfer {
                rockchip,pins = <0x2 0x1 0x3 0x113 0x2 0x2 0x3 0x113>;
                phandle = <0xf0>;
            };
        };

        uart6 {

            uart6m0-xfer {
                rockchip,pins = <0x2 0x3 0x3 0x113 0x2 0x4 0x3 0x113>;
                phandle = <0xf1>;
            };
        };

        uart7 {

            uart7m0-xfer {
                rockchip,pins = <0x2 0x5 0x3 0x113 0x2 0x6 0x3 0x113>;
                phandle = <0xf2>;
            };
        };

        uart8 {

            uart8m0-xfer {
                rockchip,pins = <0x2 0x16 0x2 0x113 0x2 0x15 0x3 0x113>;
                phandle = <0xf3>;
            };
        };

        uart9 {

            uart9m0-xfer {
                rockchip,pins = <0x2 0x7 0x3 0x113 0x2 0x8 0x3 0x113>;
                phandle = <0xf4>;
            };
        };

        spi0-hs {

            spi0m0-pins {
                rockchip,pins = <0x0 0xd 0x2 0x118 0x0 0x15 0x2 0x118 0x0 0xe 0x2 0x118>;
                phandle = <0xde>;
            };
        };

        spi1-hs {

            spi1m0-pins {
                rockchip,pins = <0x2 0xd 0x3 0x118 0x2 0xe 0x3 0x118 0x2 0xf 0x4 0x118>;
                phandle = <0xe2>;
            };
        };

        spi2-hs {

            spi2m0-pins {
                rockchip,pins = <0x2 0x11 0x4 0x118 0x2 0x12 0x4 0x118 0x2 0x13 0x4 0x118>;
                phandle = <0xe6>;
            };
        };

        spi3-hs {

            spi3m0-pins {
                rockchip,pins = <0x4 0xb 0x4 0x118 0x4 0x8 0x4 0x118 0x4 0xa 0x4 0x118>;
                phandle = <0xea>;
            };
        };

        gmac-txd-level3 {

            gmac1m0-tx-bus2-level3 {
                rockchip,pins = <0x3 0xd 0x3 0x119 0x3 0xe 0x3 0x119 0x3 0xf 0x3 0x111>;
                phandle = <0x7d>;
            };

            gmac1m0-rgmii-bus-level3 {
                rockchip,pins = <0x3 0x4 0x3 0x111 0x3 0x5 0x3 0x111 0x3 0x2 0x3 0x119 0x3 0x3 0x3 0x119>;
                phandle = <0x80>;
            };
        };

        gmac-txc-level2 {

            gmac1m0-rgmii-clk-level2 {
                rockchip,pins = <0x3 0x7 0x3 0x111 0x3 0x6 0x3 0x114>;
                phandle = <0x7f>;
            };
        };

        gpio-func {

            tsadc-gpio-func {
                rockchip,pins = <0x0 0x1 0x0 0x111>;
                phandle = <0x101>;
            };
        };

        mxc6655xa {

            mxc6655xa_irq_gpio {
                rockchip,pins = <0x3 0x11 0x0 0x111>;
                phandle = <0xda>;
            };
        };

        touch {

            touch-gpio {
                rockchip,pins = <0x0 0xd 0x0 0x113 0x0 0xe 0x0 0x111>;
                phandle = <0xce>;
            };
        };

        sdio-pwrseq {

            wifi-enable-h {
                rockchip,pins = <0x2 0x9 0x0 0x111>;
                phandle = <0x12d>;
            };
        };

        usb {

            vcc5v0-host-en {
                rockchip,pins = <0x0 0x6 0x0 0x111>;
                phandle = <0x12a>;
            };

            vcc5v0-otg-en {
                rockchip,pins = <0x0 0x5 0x0 0x111>;
                phandle = <0x12b>;
            };
        };

        wireless-bluetooth {

            uart8-gpios {
                rockchip,pins = <0x2 0x9 0x0 0x111>;
                phandle = <0x1cb>;
            };

            uart1-gpios {
                rockchip,pins = <0x2 0xd 0x0 0x111>;
                phandle = <0x131>;
            };
        };

        headphone {

            hp-det {
                rockchip,pins = <0x4 0xb 0x0 0x11a>;
                phandle = <0x132>;
            };
        };

        lcd0 {

            lcd-rst-gpio {
                rockchip,pins = <0x1 0x5 0x0 0x111>;
                phandle = <0x94>;
            };
        };

        lcd1 {

            lcd1-rst-gpio {
                rockchip,pins = <0x4 0x16 0x0 0x111>;
                phandle = <0x9d>;
            };
        };

        wireless-wlan {

            wifi-host-wake-irq {
                rockchip,pins = <0x2 0xa 0x0 0x11a>;
                phandle = <0x12f>;
            };
        };

        fddis_ctr {

            dis-ctl {
                rockchip,pins = <0x0 0xb 0x0 0x113 0x0 0xc 0x0 0x113>;
                phandle = <0x10f>;
            };
        };
    };

    adc-keys {
        compatible = "adc-keys";
        io-channels = <0x11b 0x0>;
        io-channel-names = "buttons";
        keyup-threshold-microvolt = <0x1b7740>;
        poll-interval = <0x64>;
        phandle = <0x1cc>;

        vol-up-key {
            label = "volume up";
            linux,code = <0x73>;
            press-threshold-microvolt = <0x6d6>;
        };

        vol-down-key {
            label = "volume down";
            linux,code = <0x72>;
            press-threshold-microvolt = <0x48a1c>;
        };

        menu-key {
            label = "menu";
            linux,code = <0x8b>;
            press-threshold-microvolt = <0xef420>;
        };

        back-key {
            label = "back";
            linux,code = <0x9e>;
            press-threshold-microvolt = <0x13eb9c>;
        };
    };

    audiopwmout-diff {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,audiopwmout-diff";
        simple-audio-card,mclk-fs = <0x100>;
        simple-audio-card,bitclock-master = <0x11c>;
        simple-audio-card,frame-master = <0x11c>;
        phandle = <0x1cd>;

        simple-audio-card,cpu {
            sound-dai = <0x11d>;
        };

        simple-audio-card,codec {
            sound-dai = <0x11e>;
            phandle = <0x11c>;
        };
    };

    backlight {
        compatible = "pwm-backlight";
        pwms = <0x11f 0x0 0x61a8 0x0>;
        brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
        default-brightness-level = <0xc8>;
        phandle = <0x91>;
    };

    backlight1 {
        compatible = "pwm-backlight";
        pwms = <0x120 0x0 0x61a8 0x0>;
        brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
        default-brightness-level = <0xc8>;
        phandle = <0x9a>;
    };

    dc-12v {
        compatible = "regulator-fixed";
        regulator-name = "dc_12v";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0xb71b00>;
        regulator-max-microvolt = <0xb71b00>;
        phandle = <0x129>;
    };

    hdmi-sound {
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <0x80>;
        simple-audio-card,name = "rockchip,hdmi";
        status = "okay";
        phandle = <0x1ce>;

        simple-audio-card,cpu {
            sound-dai = <0x121>;
        };

        simple-audio-card,codec {
            sound-dai = <0x122>;
        };
    };

    dummy-codec {
        status = "disabled";
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0x0>;
        phandle = <0x124>;
    };

    pdm-mic-array {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,name = "rockchip,pdm-mic-array";
        phandle = <0x1cf>;

        simple-audio-card,cpu {
            sound-dai = <0x123>;
        };

        simple-audio-card,codec {
            sound-dai = <0x124>;
        };
    };

    rk809-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,rk809-codec";
        simple-audio-card,mclk-fs = <0x100>;
        phandle = <0x1d0>;

        simple-audio-card,cpu {
            sound-dai = <0x11d>;
        };

        simple-audio-card,codec {
            sound-dai = <0x125>;
        };
    };

    spdif-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,name = "ROCKCHIP,SPDIF";

        simple-audio-card,cpu {
            sound-dai = <0x126>;
        };

        simple-audio-card,codec {
            sound-dai = <0x127>;
        };
    };

    spdif-out {
        status = "okay";
        compatible = "linux,spdif-dit";
        #sound-dai-cells = <0x0>;
        phandle = <0x127>;
    };

    vad-sound {
        status = "disabled";
        compatible = "rockchip,multicodecs-card";
        rockchip,card-name = "rockchip,rk3568-vad";
        rockchip,cpu = <0xc6>;
        rockchip,codec = <0x125 0x128>;
        phandle = <0x1d1>;
    };

    vcc3v3-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x325aa0>;
        regulator-max-microvolt = <0x325aa0>;
        vin-supply = <0x129>;
        phandle = <0x3c>;
    };

    vcc5v0-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x4c4b40>;
        regulator-max-microvolt = <0x4c4b40>;
        vin-supply = <0x129>;
        phandle = <0x3e>;
    };

    vcc5v0-host-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x35 0x6 0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x12a>;
        regulator-name = "vcc5v0_host";
        regulator-always-on;
        phandle = <0x10c>;
    };

    vcc5v0-otg-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x35 0x5 0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x12b>;
        regulator-name = "vcc5v0_otg";
        phandle = <0x10d>;
    };

    vcc3v3-lcd0-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd0_n";
        regulator-boot-on;
        gpio = <0x35 0x10 0x0>;
        enable-active-high;
        phandle = <0x92>;

        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };

    vcc3v3-lcd1-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd1_n";
        regulator-boot-on;
        phandle = <0x9b>;

        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };

    sdio-pwrseq {
        compatible = "mmc-pwrseq-simple";
        clocks = <0x12c 0x1>;
        clock-names = "ext_clock";
        pinctrl-names = "default";
        pinctrl-0 = <0x12d>;
        post-power-on-delay-ms = <0xc8>;
        reset-gpios = <0x12e 0x9 0x1>;
        phandle = <0xb1>;
    };

    wireless-wlan {
        compatible = "wlan-platdata";
        rockchip,grf = <0x32>;
        wifi_chip_type = "ap6398s";
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x12f>;
        WIFI,host_wake_irq = <0x12e 0xa 0x0>;
        phandle = <0x1d2>;
    };

    wireless-bluetooth {
        compatible = "bluetooth-platdata";
        clocks = <0x12c 0x1>;
        clock-names = "ext_clock";
        uart_rts_gpios = <0x12e 0xd 0x1>;
        pinctrl-names = "default", "rts_gpio";
        pinctrl-0 = <0x130>;
        pinctrl-1 = <0x131>;
        BT,reset_gpio = <0x12e 0xf 0x0>;
        BT,wake_gpio = <0x12e 0x11 0x0>;
        BT,wake_host_irq = <0x12e 0x10 0x0>;
        status = "okay";
        phandle = <0x1d3>;
    };

    test-power {
        status = "okay";
    };

    rk-headset {
        compatible = "rockchip_headset";
        headset_gpio = <0x9c 0xb 0x1>;
        pinctrl-names = "default";
        pinctrl-0 = <0x132>;
        phandle = <0x1d4>;
    };

    vcc3v3-vga {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_vga";
        regulator-always-on;
        regulator-boot-on;
        gpio = <0x9c 0xa 0x0>;
        enable-active-high;
        vin-supply = <0x3c>;
        phandle = <0x1d5>;
    };

    vcc-camera-regulator {
        compatible = "regulator-fixed";
        gpio = <0x35 0x11 0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x133>;
        regulator-name = "vcc_camera";
        enable-active-high;
        regulator-always-on;
        regulator-boot-on;
        phandle = <0x1d6>;
    };

    chosen {
        bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0";
        phandle = <0x1d7>;
    };

    fiq-debugger {
        compatible = "rockchip,fiq-debugger";
        rockchip,serial-id = <0x2>;
        rockchip,wake-irq = <0x0>;
        rockchip,irq-mode-enable = <0x1>;
        rockchip,baudrate = <0x16e360>;
        interrupts = <0x0 0xfc 0x8>;
        pinctrl-names = "default";
        pinctrl-0 = <0xed>;
        status = "okay";
    };

    debug@fd904000 {
        compatible = "rockchip,debug";
        reg = <0x0 0xfd904000 0x0 0x1000 0x0 0xfd905000 0x0 0x1000 0x0 0xfd906000 0x0 0x1000 0x0 0xfd907000 0x0 0x1000>;
        phandle = <0x1d8>;
    };

    cspmu@fd90c000 {
        compatible = "rockchip,cspmu";
        reg = <0x0 0xfd90c000 0x0 0x1000 0x0 0xfd90d000 0x0 0x1000 0x0 0xfd90e000 0x0 0x1000 0x0 0xfd90f000 0x0 0x1000>;
        phandle = <0x1d9>;
    };

    leds {
        compatible = "gpio-leds";

        power-green {
            gpios = <0x35 0x1b 0x1>;
            linux,default-trigger = "none";
            default-state = "off";
        };

        power-red {
            gpios = <0x35 0x1c 0x0>;
            linux,default-trigger = "none";
            default-state = "off";
        };
    };

    fddis_dev {
        compatible = "fddis_dev";
        fddis_gpio_clk = <0x35 0xb 0x0>;
        fddis_gpio_dat = <0x35 0xc 0x0>;
        status = "okay";
    };

    resume_reboot {
        compatible = "resume_reboot";
        status = "okay";
    };

    __symbols__ {
        ddr_timing = "/ddr_timing";
        cpu0 = "/cpus/cpu@0";
        cpu1 = "/cpus/cpu@100";
        cpu2 = "/cpus/cpu@200";
        cpu3 = "/cpus/cpu@300";
        CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
        cpu0_opp_table = "/cpu0-opp-table";
        display_subsystem = "/display-subsystem";
        route_dsi0 = "/display-subsystem/route/route-dsi0";
        route_dsi1 = "/display-subsystem/route/route-dsi1";
        route_edp = "/display-subsystem/route/route-edp";
        route_hdmi = "/display-subsystem/route/route-hdmi";
        route_lvds = "/display-subsystem/route/route-lvds";
        route_rgb = "/display-subsystem/route/route-rgb";
        optee = "/firmware/optee";
        scmi = "/firmware/scmi";
        scmi_clk = "/firmware/scmi/protocol@14";
        sdei = "/firmware/sdei";
        mpp_srv = "/mpp-srv";
        reserved_memory = "/reserved-memory";
        drm_logo = "/reserved-memory/drm-logo@00000000";
        drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000";
        ramoops = "/reserved-memory/ramoops@110000";
        rockchip_suspend = "/rockchip-suspend";
        rockchip_system_monitor = "/rockchip-system-monitor";
        thermal_zones = "/thermal-zones";
        soc_thermal = "/thermal-zones/soc-thermal";
        threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
        target = "/thermal-zones/soc-thermal/trips/trip-point-1";
        soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
        gpu_thermal = "/thermal-zones/gpu-thermal";
        gmac1_clkin = "/external-gmac1-clock";
        gmac1_xpcsclk = "/xpcs-gmac1-clock";
        i2s1_mclkin_rx = "/i2s1-mclkin-rx";
        i2s1_mclkin_tx = "/i2s1-mclkin-tx";
        i2s2_mclkin = "/i2s2-mclkin";
        i2s3_mclkin = "/i2s3-mclkin";
        mpll = "/mpll";
        xin24m = "/xin24m";
        xin32k = "/xin32k";
        scmi_shmem = "/scmi-shmem@10f000";
        sata1 = "/sata@fc400000";
        sata2 = "/sata@fc800000";
        usbdrd30 = "/usbdrd";
        usbdrd_dwc3 = "/usbdrd/dwc3@fcc00000";
        usbhost30 = "/usbhost";
        usbhost_dwc3 = "/usbhost/dwc3@fd000000";
        gic = "/interrupt-controller@fd400000";
        its = "/interrupt-controller@fd400000/interrupt-controller@fd440000";
        usb_host0_ehci = "/usb@fd800000";
        usb_host0_ohci = "/usb@fd840000";
        usb_host1_ehci = "/usb@fd880000";
        usb_host1_ohci = "/usb@fd8c0000";
        xpcs = "/syscon@fda00000";
        pmugrf = "/syscon@fdc20000";
        pmu_io_domains = "/syscon@fdc20000/io-domains";
        reboot_mode = "/syscon@fdc20000/reboot-mode";
        pipegrf = "/syscon@fdc50000";
        grf = "/syscon@fdc60000";
        io_domains = "/syscon@fdc60000/io-domains";
        lvds = "/syscon@fdc60000/lvds";
        lvds_in_vp1 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@1";
        lvds_in_vp2 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@2";
        rgb = "/syscon@fdc60000/rgb";
        rgb_in_vp2 = "/syscon@fdc60000/rgb/ports/port@0/endpoint@2";
        pipe_phy_grf0 = "/syscon@fdc70000";
        pipe_phy_grf1 = "/syscon@fdc80000";
        pipe_phy_grf2 = "/syscon@fdc90000";
        usb2phy0_grf = "/syscon@fdca0000";
        usb2phy1_grf = "/syscon@fdca8000";
        edp_phy = "/edp-phy@fdcb0000";
        sram = "/sram@fdcc0000";
        rkvdec_sram = "/sram@fdcc0000/rkvdec-sram@0";
        pmucru = "/clock-controller@fdd00000";
        cru = "/clock-controller@fdd20000";
        i2c0 = "/i2c@fdd40000";
        rk809 = "/i2c@fdd40000/pmic@20";
        pinctrl_rk8xx = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx";
        rk817_slppin_null = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_null";
        rk817_slppin_slp = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_slp";
        rk817_slppin_pwrdn = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_pwrdn";
        rk817_slppin_rst = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_rst";
        vdd_logic = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG1";
        vdd_gpu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG2";
        vcc_ddr = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG3";
        vdd_npu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG4";
        vdda0v9_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG1";
        vdda_0v9 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG2";
        vdda0v9_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG3";
        vccio_acodec = "/i2c@fdd40000/pmic@20/regulators/LDO_REG4";
        vccio_sd = "/i2c@fdd40000/pmic@20/regulators/LDO_REG5";
        vcc3v3_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG6";
        vcca_1v8 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG7";
        vcca1v8_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG8";
        vcca1v8_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG9";
        vcc_1v8 = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG5";
        vcc_3v3 = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG1";
        vcc3v3_sd = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG2";
        rk809_codec = "/i2c@fdd40000/pmic@20/codec";
        vdd_cpu = "/i2c@fdd40000/tcs4526@10";
        uart0 = "/serial@fdd50000";
        pwm0 = "/pwm@fdd70000";
        pwm1 = "/pwm@fdd70010";
        pwm2 = "/pwm@fdd70020";
        pwm3 = "/pwm@fdd70030";
        pmu = "/power-management@fdd90000";
        power = "/power-management@fdd90000/power-controller";
        rknpu = "/npu@fde40000";
        npu_opp_table = "/npu-opp-table";
        bus_npu = "/bus-npu";
        bus_npu_opp_table = "/bus-npu-opp-table";
        rknpu_mmu = "/iommu@fde4b000";
        gpu = "/gpu@fde60000";
        gpu_power_model = "/gpu@fde60000/power-model";
        gpu_opp_table = "/opp-table2";
        vdpu = "/vdpu@fdea0400";
        vdpu_mmu = "/iommu@fdea0800";
        rk_rga = "/rk_rga@fdeb0000";
        ebc = "/ebc@fdec0000";
        jpegd = "/jpegd@fded0000";
        jpegd_mmu = "/iommu@fded0480";
        vepu = "/vepu@fdee0000";
        vepu_mmu = "/iommu@fdee0800";
        iep = "/iep@fdef0000";
        iep_mmu = "/iommu@fdef0800";
        eink = "/eink@fdf00000";
        rkvenc = "/rkvenc@fdf40000";
        rkvenc_opp_table = "/rkvenc-opp-table";
        rkvenc_mmu = "/iommu@fdf40f00";
        rkvdec = "/rkvdec@fdf80200";
        rkvdec_mmu = "/iommu@fdf80800";
        mipi_csi2 = "/mipi-csi2@fdfb0000";
        rkcif = "/rkcif@fdfe0000";
        rkcif_mmu = "/iommu@fdfe0800";
        rkcif_dvp = "/rkcif_dvp";
        dvp_in_bcam = "/rkcif_dvp/port/endpoint";
        rkcif_dvp_sditf = "/rkcif_dvp_sditf";
        rkcif_mipi_lvds = "/rkcif_mipi_lvds";
        rkcif_mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf";
        rkisp = "/rkisp@fdff0000";
        rkisp_mmu = "/iommu@fdff1a00";
        rkisp_vir0 = "/rkisp-vir0";
        isp0_in = "/rkisp-vir0/port/endpoint@0";
        rkisp_vir1 = "/rkisp-vir1";
        gmac1 = "/ethernet@fe010000";
        mdio1 = "/ethernet@fe010000/mdio";
        rgmii_phy1 = "/ethernet@fe010000/mdio/phy@0";
        gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config";
        gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config";
        gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config";
        vop = "/vop@fe040000";
        vop_out = "/vop@fe040000/ports";
        vp0 = "/vop@fe040000/ports/port@0";
        vp0_out_dsi0 = "/vop@fe040000/ports/port@0/endpoint@0";
        vp0_out_dsi1 = "/vop@fe040000/ports/port@0/endpoint@1";
        vp0_out_edp = "/vop@fe040000/ports/port@0/endpoint@2";
        vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@3";
        vp1 = "/vop@fe040000/ports/port@1";
        vp1_out_dsi0 = "/vop@fe040000/ports/port@1/endpoint@0";
        vp1_out_dsi1 = "/vop@fe040000/ports/port@1/endpoint@1";
        vp1_out_edp = "/vop@fe040000/ports/port@1/endpoint@2";
        vp1_out_hdmi = "/vop@fe040000/ports/port@1/endpoint@3";
        vp1_out_lvds = "/vop@fe040000/ports/port@1/endpoint@4";
        vp2 = "/vop@fe040000/ports/port@2";
        vp2_out_lvds = "/vop@fe040000/ports/port@2/endpoint@0";
        vp2_out_rgb = "/vop@fe040000/ports/port@2/endpoint@1";
        vop_mmu = "/iommu@fe043e00";
        dsi0 = "/dsi@fe060000";
        dsi0_in = "/dsi@fe060000/ports/port@0";
        dsi0_in_vp0 = "/dsi@fe060000/ports/port@0/endpoint@0";
        dsi0_in_vp1 = "/dsi@fe060000/ports/port@0/endpoint@1";
        dsi_out_panel = "/dsi@fe060000/ports/port@1/endpoint";
        dsi0_panel = "/dsi@fe060000/panel@0";
        disp_timings0 = "/dsi@fe060000/panel@0/display-timings";
        dsi0_timing0 = "/dsi@fe060000/panel@0/display-timings/timing0";
        panel_in_dsi = "/dsi@fe060000/panel@0/ports/port@0/endpoint";
        dsi1 = "/dsi@fe070000";
        dsi1_in = "/dsi@fe070000/ports/port@0";
        dsi1_in_vp0 = "/dsi@fe070000/ports/port@0/endpoint@0";
        dsi1_in_vp1 = "/dsi@fe070000/ports/port@0/endpoint@1";
        dsi1_out_panel = "/dsi@fe070000/ports/port@1/endpoint";
        dsi1_panel = "/dsi@fe070000/panel@0";
        disp_timings1 = "/dsi@fe070000/panel@0/display-timings";
        dsi1_timing0 = "/dsi@fe070000/panel@0/display-timings/timing0";
        panel_in_dsi1 = "/dsi@fe070000/panel@0/ports/port@0/endpoint";
        hdmi = "/hdmi@fe0a0000";
        hdmi_in = "/hdmi@fe0a0000/ports/port";
        hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port/endpoint@0";
        hdmi_in_vp1 = "/hdmi@fe0a0000/ports/port/endpoint@1";
        edp = "/edp@fe0c0000";
        edp_in = "/edp@fe0c0000/ports/port@0";
        edp_in_vp0 = "/edp@fe0c0000/ports/port@0/endpoint@0";
        edp_in_vp1 = "/edp@fe0c0000/ports/port@0/endpoint@1";
        qos_gpu = "/qos@fe128000";
        qos_rkvenc_rd_m0 = "/qos@fe138080";
        qos_rkvenc_rd_m1 = "/qos@fe138100";
        qos_rkvenc_wr_m0 = "/qos@fe138180";
        qos_isp = "/qos@fe148000";
        qos_vicap0 = "/qos@fe148080";
        qos_vicap1 = "/qos@fe148100";
        qos_vpu = "/qos@fe150000";
        qos_ebc = "/qos@fe158000";
        qos_iep = "/qos@fe158100";
        qos_jpeg_dec = "/qos@fe158180";
        qos_jpeg_enc = "/qos@fe158200";
        qos_rga_rd = "/qos@fe158280";
        qos_rga_wr = "/qos@fe158300";
        qos_npu = "/qos@fe180000";
        qos_pcie2x1 = "/qos@fe190000";
        qos_sata1 = "/qos@fe190280";
        qos_sata2 = "/qos@fe190300";
        qos_usb3_0 = "/qos@fe190380";
        qos_usb3_1 = "/qos@fe190400";
        qos_rkvdec = "/qos@fe198000";
        qos_hdcp = "/qos@fe1a8000";
        qos_vop_m0 = "/qos@fe1a8080";
        qos_vop_m1 = "/qos@fe1a8100";
        sdmmc2 = "/dwmmc@fe000000";
        dfi = "/dfi@fe230000";
        dmc = "/dmc";
        dmc_opp_table = "/dmc-opp-table";
        pcie2x1 = "/pcie@fe260000";
        pcie2x1_intc = "/pcie@fe260000/legacy-interrupt-controller";
        sdmmc0 = "/dwmmc@fe2b0000";
        sdmmc1 = "/dwmmc@fe2c0000";
        sfc = "/sfc@fe300000";
        sdhci = "/sdhci@fe310000";
        nandc0 = "/nandc@fe330000";
        crypto = "/crypto@fe380000";
        rng = "/rng@fe388000";
        otp = "/otp@fe38c000";
        cpu_code = "/otp@fe38c000/cpu-code@2";
        otp_cpu_version = "/otp@fe38c000/cpu-version@8";
        mbist_vmin = "/otp@fe38c000/mbist-vmin@9";
        otp_id = "/otp@fe38c000/id@a";
        cpu_leakage = "/otp@fe38c000/cpu-leakage@1a";
        log_leakage = "/otp@fe38c000/log-leakage@1b";
        npu_leakage = "/otp@fe38c000/npu-leakage@1c";
        gpu_leakage = "/otp@fe38c000/gpu-leakage@1d";
        core_pvtm = "/otp@fe38c000/core-pvtm@2a";
        i2s0_8ch = "/i2s@fe400000";
        i2s1_8ch = "/i2s@fe410000";
        i2s2_2ch = "/i2s@fe420000";
        i2s3_2ch = "/i2s@fe430000";
        pdm = "/pdm@fe440000";
        vad = "/vad@fe450000";
        spdif_8ch = "/spdif@fe460000";
        audpwm = "/audpwm@fe470000";
        dig_acodec = "/codec-digital@fe478000";
        dmac0 = "/dmac@fe530000";
        dmac1 = "/dmac@fe550000";
        scr = "/rkscr@fe560000";
        can0 = "/can@fe570000";
        can1 = "/can@fe580000";
        can2 = "/can@fe590000";
        i2c1 = "/i2c@fe5a0000";
        gt1x = "/i2c@fe5a0000/gt1x@14";
        i2c2 = "/i2c@fe5b0000";
        gc2145 = "/i2c@fe5b0000/gc2145@3c";
        gc2145_out = "/i2c@fe5b0000/gc2145@3c/port/endpoint";
        ov5695 = "/i2c@fe5b0000/ov5695@36";
        ov5695_out = "/i2c@fe5b0000/ov5695@36/port/endpoint";
        gc8034 = "/i2c@fe5b0000/gc8034@37";
        gc8034_out = "/i2c@fe5b0000/gc8034@37/port/endpoint";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mxc6655xa = "/i2c@fe5e0000/mxc6655xa@15";
        rktimer = "/timer@fe5f0000";
        wdt = "/watchdog@fe600000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
        uart1 = "/serial@fe650000";
        uart2 = "/serial@fe660000";
        uart3 = "/serial@fe670000";
        uart4 = "/serial@fe680000";
        uart5 = "/serial@fe690000";
        uart6 = "/serial@fe6a0000";
        uart7 = "/serial@fe6b0000";
        uart8 = "/serial@fe6c0000";
        uart9 = "/serial@fe6d0000";
        pwm4 = "/pwm@fe6e0000";
        pwm5 = "/pwm@fe6e0010";
        pwm6 = "/pwm@fe6e0020";
        pwm7 = "/pwm@fe6e0030";
        pwm8 = "/pwm@fe6f0000";
        pwm9 = "/pwm@fe6f0010";
        pwm10 = "/pwm@fe6f0020";
        pwm11 = "/pwm@fe6f0030";
        pwm12 = "/pwm@fe700000";
        pwm13 = "/pwm@fe700010";
        pwm14 = "/pwm@fe700020";
        pwm15 = "/pwm@fe700030";
        tsadc = "/tsadc@fe710000";
        saradc = "/saradc@fe720000";
        mailbox = "/mailbox@fe780000";
        combphy1_usq = "/phy@fe830000";
        combphy2_psq = "/phy@fe840000";
        mipi_dphy0 = "/mipi-dphy@fe850000";
        video_phy0 = "/video-phy@fe850000";
        mipi_dphy1 = "/mipi-dphy@fe860000";
        csi2_dphy_hw = "/csi2-dphy-hw@fe870000";
        csi2_dphy0 = "/csi2-dphy0";
        mipi_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1";
        mipi_in_ucam1 = "/csi2-dphy0/ports/port@0/endpoint@2";
        csidphy_out = "/csi2-dphy0/ports/port@1/endpoint@0";
        csi2_dphy1 = "/csi2-dphy1";
        csi2_dphy2 = "/csi2-dphy2";
        usb2phy0 = "/usb2-phy@fe8a0000";
        u2phy0_host = "/usb2-phy@fe8a0000/host-port";
        u2phy0_otg = "/usb2-phy@fe8a0000/otg-port";
        usb2phy1 = "/usb2-phy@fe8b0000";
        u2phy1_host = "/usb2-phy@fe8b0000/host-port";
        u2phy1_otg = "/usb2-phy@fe8b0000/otg-port";
        pinctrl = "/pinctrl";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        pcfg_pull_up = "/pinctrl/pcfg-pull-up";
        pcfg_pull_down = "/pinctrl/pcfg-pull-down";
        pcfg_pull_none = "/pinctrl/pcfg-pull-none";
        pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
        pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
        pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
        pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
        pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
        pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
        pcfg_output_low = "/pinctrl/pcfg-output-low";
        acodec_pins = "/pinctrl/acodec/acodec-pins";
        cam_clkout0 = "/pinctrl/cam/cam-clkout0";
        camera_pwr = "/pinctrl/cam/camera-pwr";
        can0m1_pins = "/pinctrl/can0/can0m1-pins";
        can1m1_pins = "/pinctrl/can1/can1m1-pins";
        can2m1_pins = "/pinctrl/can2/can2m1-pins";
        cif_clk = "/pinctrl/cif/cif-clk";
        cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
        cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
        clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
        ebc_pins = "/pinctrl/ebc/ebc-pins";
        gmac1m0_miim = "/pinctrl/gmac1/gmac1m0-miim";
        gmac1m0_rx_bus2 = "/pinctrl/gmac1/gmac1m0-rx-bus2";
        hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec";
        hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl";
        hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda";
        i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
        i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
        i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer";
        i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
        i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
        i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
        i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx";
        i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx";
        i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
        i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
        i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx";
        i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx";
        i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi";
        i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo";
        i2s3m1_lrck = "/pinctrl/i2s3/i2s3m1-lrck";
        i2s3m1_mclk = "/pinctrl/i2s3/i2s3m1-mclk";
        i2s3m1_sclk = "/pinctrl/i2s3/i2s3m1-sclk";
        i2s3m1_sdi = "/pinctrl/i2s3/i2s3m1-sdi";
        i2s3m1_sdo = "/pinctrl/i2s3/i2s3m1-sdo";
        lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl";
        pdmm1_clk1 = "/pinctrl/pdm/pdmm1-clk1";
        pdmm1_sdi1 = "/pinctrl/pdm/pdmm1-sdi1";
        pdmm1_sdi2 = "/pinctrl/pdm/pdmm1-sdi2";
        pdmm1_sdi3 = "/pinctrl/pdm/pdmm1-sdi3";
        pmic_int = "/pinctrl/pmic/pmic_int";
        soc_slppin_gpio = "/pinctrl/pmic/soc_slppin_gpio";
        soc_slppin_slp = "/pinctrl/pmic/soc_slppin_slp";
        soc_slppin_rst = "/pinctrl/pmic/soc_slppin_rst";
        pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
        pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
        pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
        pwm3_pins = "/pinctrl/pwm3/pwm3-pins";
        pwm4_pins = "/pinctrl/pwm4/pwm4-pins";
        pwm5_pins = "/pinctrl/pwm5/pwm5-pins";
        pwm6_pins = "/pinctrl/pwm6/pwm6-pins";
        pwm7_pins = "/pinctrl/pwm7/pwm7-pins";
        pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
        pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
        pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
        pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
        pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
        pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
        pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
        pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
        scr_pins = "/pinctrl/scr/scr-pins";
        sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4";
        sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk";
        sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd";
        sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det";
        sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4";
        sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk";
        sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd";
        spdifm0_tx = "/pinctrl/spdif/spdifm0-tx";
        spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
        spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
        spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
        spi1m0_pins = "/pinctrl/spi1/spi1m0-pins";
        spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0";
        spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1";
        spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
        spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
        spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
        spi3m0_pins = "/pinctrl/spi3/spi3m0-pins";
        spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0";
        spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1";
        tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg";
        uart0_xfer = "/pinctrl/uart0/uart0-xfer";
        uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer";
        uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn";
        uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn";
        uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
        uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
        uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
        uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
        uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer";
        uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer";
        uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
        uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer";
        spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins";
        spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins";
        spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins";
        spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins";
        gmac1m0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-tx-bus2-level3";
        gmac1m0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-rgmii-bus-level3";
        gmac1m0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m0-rgmii-clk-level2";
        tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func";
        mxc6655xa_irq_gpio = "/pinctrl/mxc6655xa/mxc6655xa_irq_gpio";
        touch_gpio = "/pinctrl/touch/touch-gpio";
        wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h";
        vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en";
        vcc5v0_otg_en = "/pinctrl/usb/vcc5v0-otg-en";
        uart8_gpios = "/pinctrl/wireless-bluetooth/uart8-gpios";
        uart1_gpios = "/pinctrl/wireless-bluetooth/uart1-gpios";
        hp_det = "/pinctrl/headphone/hp-det";
        lcd0_rst_gpio = "/pinctrl/lcd0/lcd-rst-gpio";
        lcd1_rst_gpio = "/pinctrl/lcd1/lcd1-rst-gpio";
        wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq";
        dis_ctl = "/pinctrl/fddis_ctr/dis-ctl";
        adc_keys = "/adc-keys";
        audiopwmout_diff = "/audiopwmout-diff";
        master = "/audiopwmout-diff/simple-audio-card,codec";
        backlight = "/backlight";
        backlight1 = "/backlight1";
        dc_12v = "/dc-12v";
        hdmi_sound = "/hdmi-sound";
        pdmics = "/dummy-codec";
        pdm_mic_array = "/pdm-mic-array";
        rk809_sound = "/rk809-sound";
        spdif_out = "/spdif-out";
        vad_sound = "/vad-sound";
        vcc3v3_sys = "/vcc3v3-sys";
        vcc5v0_sys = "/vcc5v0-sys";
        vcc5v0_host = "/vcc5v0-host-regulator";
        vcc5v0_otg = "/vcc5v0-otg-regulator";
        vcc3v3_lcd0_n = "/vcc3v3-lcd0-n";
        vcc3v3_lcd1_n = "/vcc3v3-lcd1-n";
        sdio_pwrseq = "/sdio-pwrseq";
        wireless_wlan = "/wireless-wlan";
        wireless_bluetooth = "/wireless-bluetooth";
        rk_headset = "/rk-headset";
        vcc3v3_vga = "/vcc3v3-vga";
        vcc_camera = "/vcc-camera-regulator";
        chosen = "/chosen";
        debug = "/debug@fd904000";
        cspmu = "/cspmu@fd90c000";
    };
};

 

Edited by hotnikq
Link to comment
Share on other sites

Quote

pmuio1-supply = <&vcc3v3_pmu>; not asked
pmuio2-supply = <&vcc_3v3>;
vccio1-supply = <&vccio_acodec>; 3,3
vccio2-supply = <&vcc_1v8>; not asked
vccio3-supply = <&vccio_sd>; 3,3
vccio4-supply = <&vcca1v8_pmu>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc1v8_dvp>;
vccio7-supply = <&vcc_3v3>;

 
When Compile VCCio

Link to comment
Share on other sites

to compile Armbian build 4,19 M2 Station image.
change files to corresponding DTS file 


BOARD_TYPE_1.dts

Quote

/dts-v1/;
// magic:        0xd00dfeed
// totalsize:        0x1eb87 (125831)
// off_dt_struct:    0x38
// off_dt_strings:    0x1bc6c
// off_mem_rsvmap:    0x28
// version:        17
// last_comp_version:    16
// boot_cpuid_phys:    0x0
// size_dt_strings:    0x2f1b
// size_dt_struct:    0x1bc34

/ {
    compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566";
    interrupt-parent = <0x00000001>;
    #address-cells = <0x00000002>;
    #size-cells = <0x00000002>;
    model = "Rockchip RK3566 EVB3 DDR3 V10 Board";
    ddr_timing {
        compatible = "rockchip,ddr-timing";
        ddr2_speed_bin = <0x00000000>;
        ddr3_speed_bin = <0x00000015>;
        ddr4_speed_bin = <0x0000000c>;
        pd_idle = <0x0000000d>;
        sr_idle = <0x0000005d>;
        sr_mc_gate_idle = <0x00000000>;
        srpd_lite_idle = <0x00000000>;
        standby_idle = <0x00000000>;
        auto_pd_dis_freq = <0x0000042a>;
        auto_sr_dis_freq = <0x00000320>;
        ddr2_dll_dis_freq = <0x0000012c>;
        ddr3_dll_dis_freq = <0x0000012c>;
        ddr4_dll_dis_freq = <0x00000271>;
        phy_dll_dis_freq = <0x00000190>;
        ddr2_odt_dis_freq = <0x00000064>;
        phy_ddr2_odt_dis_freq = <0x00000064>;
        ddr2_drv = <0x00000002>;
        ddr2_odt = <0x00000040>;
        phy_ddr2_ca_drv = <0x00000000>;
        phy_ddr2_ck_drv = <0x00000000>;
        phy_ddr2_dq_drv = <0x00000000>;
        phy_ddr2_odt = <0x00000000>;
        ddr3_odt_dis_freq = <0x0000014d>;
        phy_ddr3_odt_dis_freq = <0x0000014d>;
        ddr3_drv = <0x00000002>;
        ddr3_odt = <0x00000040>;
        phy_ddr3_ca_drv = <0x00000000>;
        phy_ddr3_ck_drv = <0x00000000>;
        phy_ddr3_dq_drv = <0x00000000>;
        phy_ddr3_odt = <0x00000000>;
        phy_lpddr2_odt_dis_freq = <0x0000014d>;
        lpddr2_drv = <0x00000002>;
        phy_lpddr2_ca_drv = <0x00000000>;
        phy_lpddr2_ck_drv = <0x00000000>;
        phy_lpddr2_dq_drv = <0x00000000>;
        phy_lpddr2_odt = <0x00000000>;
        lpddr3_odt_dis_freq = <0x0000014d>;
        phy_lpddr3_odt_dis_freq = <0x0000014d>;
        lpddr3_drv = <0x00000001>;
        lpddr3_odt = <0x00000002>;
        phy_lpddr3_ca_drv = <0x00000000>;
        phy_lpddr3_ck_drv = <0x00000000>;
        phy_lpddr3_dq_drv = <0x00000000>;
        phy_lpddr3_odt = <0x00000000>;
        lpddr4_odt_dis_freq = <0x0000014d>;
        phy_lpddr4_odt_dis_freq = <0x0000014d>;
        lpddr4_drv = <0x00000030>;
        lpddr4_dq_odt = <0x00000001>;
        lpddr4_ca_odt = <0x00000000>;
        phy_lpddr4_ca_drv = <0x00000000>;
        phy_lpddr4_ck_cs_drv = <0x00000000>;
        phy_lpddr4_dq_drv = <0x00000000>;
        phy_lpddr4_odt = <0x00000000>;
        ddr4_odt_dis_freq = <0x00000271>;
        phy_ddr4_odt_dis_freq = <0x00000271>;
        ddr4_drv = <0x00000000>;
        ddr4_odt = <0x00000200>;
        phy_ddr4_ca_drv = <0x00000000>;
        phy_ddr4_ck_drv = <0x00000000>;
        phy_ddr4_dq_drv = <0x00000000>;
        phy_ddr4_odt = <0x00000000>;
        phandle = <0x000000a8>;
    };
    aliases {
        csi2dphy0 = "/csi2-dphy0";
        csi2dphy1 = "/csi2-dphy1";
        csi2dphy2 = "/csi2-dphy2";
        dsi0 = "/dsi@fe060000";
        dsi1 = "/dsi@fe070000";
        ethernet1 = "/ethernet@fe010000";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        i2c0 = "/i2c@fdd40000";
        i2c1 = "/i2c@fe5a0000";
        i2c2 = "/i2c@fe5b0000";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mmc0 = "/dwmmc@fe2b0000";
        mmc1 = "/dwmmc@fe2c0000";
        mmc2 = "/sdhci@fe310000";
        mmc3 = "/dwmmc@fe000000";
        serial0 = "/serial@fdd50000";
        serial1 = "/serial@fe650000";
        serial2 = "/serial@fe660000";
        serial3 = "/serial@fe670000";
        serial4 = "/serial@fe680000";
        serial5 = "/serial@fe690000";
        serial6 = "/serial@fe6a0000";
        serial7 = "/serial@fe6b0000";
        serial8 = "/serial@fe6c0000";
        serial9 = "/serial@fe6d0000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
    };
    cpus {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000000>;
        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000000>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            #cooling-cells = <0x00000002>;
            dynamic-power-coefficient = <0x000000bb>;
            cpu-supply = <0x00000005>;
            phandle = <0x00000009>;
            power-model {
                compatible = "simple-power-model";
                leakage-range = <0x0000000a 0x00000028>;
                ls = <0xffffdc14 0x000018d8 0x00000000>;
                static-coefficient = <0x000186a0>;
                ts = <0x0001476e 0x0003263d 0xffffef34 0x00000047>;
                thermal-zone = "soc-thermal";
            };
        };
        cpu@100 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000100>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000a>;
        };
        cpu@200 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000200>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000b>;
        };
        cpu@300 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000300>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000c>;
        };
        idle-states {
            entry-method = "psci";
            cpu-sleep {
                compatible = "arm,idle-state";
                local-timer-stop;
                arm,psci-suspend-param = <0x00010000>;
                entry-latency-us = <0x00000064>;
                exit-latency-us = <0x00000078>;
                min-residency-us = <0x000003e8>;
                phandle = <0x00000004>;
            };
        };
    };
    cpu0-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000006 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-freq = <0x000639c0>;
        rockchip,pvtm-volt = <0x000dbba0>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        rockchip,pvtm-sample-time = <0x000003e8>;
        rockchip,pvtm-number = <0x0000000a>;
        rockchip,pvtm-error = <0x000003e8>;
        rockchip,pvtm-ref-temp = <0x00000028>;
        rockchip,pvtm-temp-prop = <0x0000001a 0x0000001a>;
        rockchip,thermal-zone = "soc-thermal";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000648 0x000124f8>;
        phandle = <0x00000003>;
        opp-408000000 {
            opp-hz = <0x00000000 0x18519600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-816000000 {
            opp-hz = <0x00000000 0x30a32c00>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            opp-suspend;
            status = "disabled";
        };
        opp-1104000000 {
            opp-hz = <0x00000000 0x41cdb400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-1416000000 {
            opp-hz = <0x00000000 0x54667200>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1608000000 {
            opp-hz = <0x00000000 0x5fd82200>;
            opp-microvolt = <0x000f4240 0x000f4240 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1800000000 {
            opp-hz = <0x00000000 0x6b49d200>;
            opp-microvolt = <0x00100590 0x00100590 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
    };
    arm-pmu {
        compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
        interrupts = <0x00000000 0x000000e4 0x00000004 0x00000000 0x000000e5 0x00000004 0x00000000 0x000000e6 0x00000004 0x00000000 0x000000e7 0x00000004>;
        interrupt-affinity = <0x00000009 0x0000000a 0x0000000b 0x0000000c>;
    };
    cpuinfo {
        compatible = "rockchip,cpuinfo";
        nvmem-cells = <0x0000000d 0x0000000e 0x0000000f>;
        nvmem-cell-names = "id", "cpu-version", "cpu-code";
    };
    display-subsystem {
        compatible = "rockchip,display-subsystem";
        memory-region = <0x00000010 0x00000011>;
        memory-region-names = "drm-logo", "drm-cubic-lut";
        ports = <0x00000012>;
        devfreq = <0x00000013>;
        phandle = <0x00000134>;
        route {
            route-dsi0 {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000014>;
                phandle = <0x00000135>;
            };
            route-dsi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000015>;
                phandle = <0x00000136>;
            };
            route-edp {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000016>;
                phandle = <0x00000137>;
            };
            route-hdmi {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000017>;
                phandle = <0x00000138>;
            };
            route-lvds {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000018>;
                phandle = <0x00000139>;
            };
            route-rgb {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000019>;
                phandle = <0x0000013a>;
            };
        };
    };
    firmware {
        optee {
            compatible = "linaro,optee-tz";
            method = "smc";
            phandle = <0x0000013b>;
        };
        scmi {
            compatible = "arm,scmi-smc";
            shmem = <0x0000001a>;
            arm,smc-id = <0x82000010>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x0000013c>;
            protocol@14 {
                reg = <0x00000014>;
                #clock-cells = <0x00000001>;
                rockchip,clk-init = "Tfr";
                phandle = <0x00000002>;
            };
        };
        sdei {
            compatible = "arm,sdei-1.0";
            method = "smc";
            phandle = <0x0000013d>;
        };
    };
    mpp-srv {
        compatible = "rockchip,mpp-service";
        rockchip,taskqueue-count = <0x00000006>;
        rockchip,resetgroup-count = <0x00000006>;
        status = "okay";
        phandle = <0x00000067>;
    };
    psci {
        compatible = "arm,psci-1.0";
        method = "smc";
    };
    reserved-memory {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        phandle = <0x0000013e>;
        drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000010>;
        };
        drm-cubic-lut@00000000 {
            compatible = "rockchip,drm-cubic-lut";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000011>;
        };
        linux,cma {
            compatible = "shared-dma-pool";
            inactive;
            reusable;
            reg = <0x00000000 0x10000000 0x00000000 0x00800000>;
            linux,cma-default;
        };
        ramoops@110000 {
            compatible = "ramoops";
            reg = <0x00000000 0x00110000 0x00000000 0x000f0000>;
            record-size = <0x00020000>;
            console-size = <0x00080000>;
            ftrace-size = <0x00000000>;
            pmsg-size = <0x00050000>;
            phandle = <0x0000013f>;
        };
    };
    rockchip-suspend {
        compatible = "rockchip,pm-rk3568";
        status = "okay";
        rockchip,sleep-debug-en = <0x00000001>;
        rockchip,sleep-mode-config = <0x000004e4>;
        rockchip,wakeup-config = <0x00002001>;
        rockchip,virtual-poweroff = <0x00000001>;
        phandle = <0x00000140>;
    };
    rockchip-system-monitor {
        compatible = "rockchip,system-monitor";
        rockchip,thermal-zone = "soc-thermal";
        phandle = <0x00000141>;
    };
    thermal-zones {
        phandle = <0x00000142>;
        soc-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            sustainable-power = <0x000005c3>;
            thermal-sensors = <0x0000001b 0x00000000>;
            phandle = <0x00000143>;
            trips {
                trip-point-0 {
                    temperature = <0x00011170>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x00000144>;
                };
                trip-point-1 {
                    temperature = <0x00014c08>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x0000001c>;
                };
                soc-crit {
                    temperature = <0x0001c138>;
                    hysteresis = <0x000007d0>;
                    type = "critical";
                    phandle = <0x00000145>;
                };
            };
            cooling-maps {
                map0 {
                    trip = <0x0000001c>;
                    cooling-device = <0x00000009 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
                map1 {
                    trip = <0x0000001c>;
                    cooling-device = <0x0000001d 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
            };
        };
        gpu-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x0000001b 0x00000001>;
            phandle = <0x00000146>;
        };
    };
    timer {
        compatible = "arm,armv8-timer";
        interrupts = <0x00000001 0x0000000d 0x00000f04 0x00000001 0x0000000e 0x00000f04 0x00000001 0x0000000b 0x00000f04 0x00000001 0x0000000a 0x00000f04>;
        arm,no-tick-in-suspend;
    };
    external-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "gmac1_clkin";
        #clock-cells = <0x00000000>;
        phandle = <0x00000147>;
    };
    xpcs-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "clk_gmac1_xpcs_mii";
        #clock-cells = <0x00000000>;
        phandle = <0x00000148>;
    };
    i2s1-mclkin-rx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_rx";
        phandle = <0x00000149>;
    };
    i2s1-mclkin-tx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_tx";
        phandle = <0x0000014a>;
    };
    i2s2-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s2_mclkin";
        phandle = <0x0000014b>;
    };
    i2s3-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s3_mclkin";
        phandle = <0x0000014c>;
    };
    mpll {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x2faf0800>;
        clock-output-names = "mpll";
        phandle = <0x0000014d>;
    };
    xin24m {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x016e3600>;
        clock-output-names = "xin24m";
        phandle = <0x0000014e>;
    };
    xin32k {
        compatible = "fixed-clock";
        clock-frequency = <0x00008000>;
        clock-output-names = "xin32k";
        #clock-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000001e>;
        phandle = <0x0000014f>;
    };
    scmi-shmem@10f000 {
        compatible = "arm,scmi-shmem";
        reg = <0x00000000 0x0010f000 0x00000000 0x00000100>;
        phandle = <0x0000001a>;
    };
    sata@fc400000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc400000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000009b 0x0000001f 0x0000009c 0x0000001f 0x0000009d>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x0000005f 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000020 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000150>;
    };
    sata@fc800000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc800000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x000000a0 0x0000001f 0x000000a1 0x0000001f 0x000000a2>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x00000060 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000022 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000151>;
    };
    usbdrd {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a6 0x0000001f 0x000000a7 0x0000001f 0x000000a5 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000152>;
        dwc3@fcc00000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfcc00000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000a9 0x00000004>;
            dr_mode = "host";
            phys = <0x00000023>;
            phy-names = "usb2-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000094>;
            reset-names = "usb3-otg";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            extcon = <0x00000024>;
            maximum-speed = "high-speed";
            snps,dis_u2_susphy_quirk;
            phandle = <0x00000153>;
        };
    };
    usbhost {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a9 0x0000001f 0x000000aa 0x0000001f 0x000000a8 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000154>;
        dwc3@fd000000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfd000000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000aa 0x00000004>;
            dr_mode = "host";
            phys = <0x00000025 0x00000020 0x00000004>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000095>;
            reset-names = "usb3-host";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            phandle = <0x00000155>;
        };
    };
    interrupt-controller@fd400000 {
        compatible = "arm,gic-v3";
        #interrupt-cells = <0x00000003>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        interrupt-controller;
        reg = <0x00000000 0xfd400000 0x00000000 0x00010000 0x00000000 0xfd460000 0x00000000 0x000c0000>;
        interrupts = <0x00000001 0x00000009 0x00000004>;
        phandle = <0x00000001>;
        interrupt-controller@fd440000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x00000001>;
            reg = <0x00000000 0xfd440000 0x00000000 0x00020000>;
            phandle = <0x000000ab>;
        };
    };
    usb@fd800000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd800000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000082 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000156>;
    };
    usb@fd840000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd840000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000083 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000157>;
    };
    usb@fd880000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd880000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000085 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000158>;
    };
    usb@fd8c0000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd8c0000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000086 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000159>;
    };
    syscon@fda00000 {
        compatible = "rockchip,rk3568-xpcs", "syscon";
        reg = <0x00000000 0xfda00000 0x00000000 0x00200000>;
        status = "disabled";
        phandle = <0x0000015a>;
    };
    syscon@fdc20000 {
        compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc20000 0x00000000 0x00010000>;
        phandle = <0x00000033>;
        io-domains {
            compatible = "rockchip,rk3568-pmu-io-voltage-domain";
            status = "okay";
            pmuio1-supply = <0x00000029>;
            pmuio2-supply = <0x00000029>;
            vccio1-supply = <0x0000002a>;
            vccio3-supply = <0x0000002b>;
            vccio4-supply = <0x0000002c>;
            vccio5-supply = <0x0000002d>;
            vccio6-supply = <0x0000002c>;
            vccio7-supply = <0x0000002d>;
            phandle = <0x0000015b>;
        };
        reboot-mode {
            compatible = "syscon-reboot-mode";
            offset = <0x00000200>;
            mode-bootloader = <0x5242c301>;
            mode-charge = <0x5242c30b>;
            mode-fastboot = <0x5242c309>;
            mode-loader = <0x5242c301>;
            mode-normal = <0x5242c300>;
            mode-recovery = <0x5242c303>;
            mode-ums = <0x5242c30c>;
            mode-panic = <0x5242c307>;
            mode-watchdog = <0x5242c308>;
            phandle = <0x0000015c>;
        };
    };
    syscon@fdc50000 {
        compatible = "rockchip,rk3568-pipegrf", "syscon";
        reg = <0x00000000 0xfdc50000 0x00000000 0x00001000>;
        phandle = <0x00000104>;
    };
    syscon@fdc60000 {
        compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc60000 0x00000000 0x00010000>;
        phandle = <0x00000032>;
        io-domains {
            compatible = "rockchip,rk3568-io-voltage-domain";
            status = "disabled";
            phandle = <0x0000015d>;
        };
        lvds {
            compatible = "rockchip,rk3568-lvds";
            phys = <0x0000002e>;
            phy-names = "phy";
            status = "disabled";
            phandle = <0x0000015e>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@1 {
                        reg = <0x00000001>;
                        remote-endpoint = <0x00000018>;
                        status = "disabled";
                        phandle = <0x0000008b>;
                    };
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x0000002f>;
                        status = "disabled";
                        phandle = <0x0000008c>;
                    };
                };
            };
        };
        rgb {
            compatible = "rockchip,rk3568-rgb";
            pinctrl-names = "default";
            pinctrl-0 = <0x00000030>;
            status = "disabled";
            phandle = <0x0000015f>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x00000019>;
                        status = "disabled";
                        phandle = <0x0000008d>;
                    };
                };
            };
        };
    };
    syscon@fdc70000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc70000 0x00000000 0x00001000>;
        phandle = <0x00000160>;
    };
    syscon@fdc80000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc80000 0x00000000 0x00001000>;
        phandle = <0x00000105>;
    };
    syscon@fdc90000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc90000 0x00000000 0x00001000>;
        phandle = <0x00000106>;
    };
    syscon@fdca0000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca0000 0x00000000 0x00008000>;
        phandle = <0x0000010b>;
    };
    syscon@fdca8000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca8000 0x00000000 0x00008000>;
        phandle = <0x0000010e>;
    };
    edp-phy@fdcb0000 {
        compatible = "rockchip,rk3568-edp-phy";
        reg = <0x00000000 0xfdcb0000 0x00000000 0x00008000>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x00000192>;
        clock-names = "refclk", "pclk";
        resets = <0x0000001f 0x000001d6>;
        reset-names = "apb";
        #phy-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000000a4>;
    };
    sram@fdcc0000 {
        compatible = "mmio-sram";
        reg = <0x00000000 0xfdcc0000 0x00000000 0x0000b000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges = <0x00000000 0x00000000 0xfdcc0000 0x0000b000>;
        phandle = <0x00000161>;
        rkvdec-sram@0 {
            reg = <0x00000000 0x0000b000>;
            phandle = <0x0000006f>;
        };
    };
    clock-controller@fdd00000 {
        compatible = "rockchip,rk3568-pmucru";
        reg = <0x00000000 0xfdd00000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        rockchip,pmugrf = <0x00000033>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000032>;
        assigned-clock-parents = <0x00000031 0x00000005>;
        phandle = <0x00000031>;
    };
    clock-controller@fdd20000 {
        compatible = "rockchip,rk3568-cru";
        reg = <0x00000000 0xfdd20000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000005 0x0000001f 0x00000106 0x0000001f 0x0000010b 0x00000031 0x00000001 0x00000031 0x0000002b 0x0000001f 0x00000003 0x0000001f 0x0000019b 0x0000001f 0x00000009 0x0000001f 0x0000019c 0x0000001f 0x0000019d 0x0000001f 0x000001a1 0x0000001f 0x0000019e 0x0000001f 0x0000019f 0x0000001f 0x000001a0 0x0000001f 0x00000004 0x0000001f 0x0000010d 0x0000001f 0x0000010e 0x0000001f 0x00000173 0x0000001f 0x00000174 0x0000001f 0x00000175 0x0000001f 0x00000176 0x0000001f 0x000000c9 0x0000001f 0x000000ca 0x0000001f 0x00000006 0x0000001f 0x0000007e 0x0000001f 0x0000007f 0x0000001f 0x0000003d 0x0000001f 0x00000041 0x0000001f 0x00000045 0x0000001f 0x00000049 0x0000001f 0x0000004d 0x0000001f 0x0000004d 0x0000001f 0x00000055 0x0000001f 0x00000051 0x0000001f 0x0000005d 0x0000001f 0x000000dd>;
        assigned-clock-rates = <0x00008000 0x11e1a300 0x11e1a300 0x0bebc200 0x05f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0x0ee6b280 0x07735940 0x05f5e100 0x03b9aca0 0x02faf080 0x017d7840 0x46cf7100 0x08f0d180 0x05f5e100 0x1dcd6500 0x17d78400 0x08f0d180 0x05f5e100 0x11e1a300 0x08f0d180 0x47868c00 0x17d78400 0x05f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
        assigned-clock-parents = <0x00000031 0x00000008 0x0000001f 0x00000004 0x0000001f 0x00000004>;
        phandle = <0x0000001f>;
    };
    i2c@fdd40000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfdd40000 0x00000000 0x00001000>;
        clocks = <0x00000031 0x00000007 0x00000031 0x0000002d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002e 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000034>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000162>;
        pmic@20 {
            compatible = "rockchip,rk809";
            reg = <0x00000020>;
            interrupt-parent = <0x00000035>;
            interrupts = <0x00000003 0x00000008>;
            pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
            pinctrl-0 = <0x00000036>;
            pinctrl-1 = <0x00000037 0x00000038>;
            pinctrl-2 = <0x00000039 0x0000003a>;
            pinctrl-3 = <0x00000039 0x0000003b>;
            rockchip,system-power-controller;
            wakeup-source;
            #clock-cells = <0x00000001>;
            clock-output-names = "rk808-clkout1", "rk808-clkout2";
            pmic-reset-func = <0x00000000>;
            not-save-power-en = <0x00000001>;
            vcc1-supply = <0x0000003c>;
            vcc2-supply = <0x0000003c>;
            vcc3-supply = <0x0000003c>;
            vcc4-supply = <0x0000003c>;
            vcc5-supply = <0x0000003c>;
            vcc6-supply = <0x0000003c>;
            vcc7-supply = <0x0000003c>;
            vcc8-supply = <0x0000003c>;
            vcc9-supply = <0x0000003c>;
            phandle = <0x0000012c>;
            pwrkey {
                status = "okay";
            };
            pinctrl_rk8xx {
                gpio-controller;
                #gpio-cells = <0x00000002>;
                phandle = <0x00000163>;
                rk817_slppin_null {
                    pins = "gpio_slp";
                    function = "pin_fun0";
                    phandle = <0x00000164>;
                };
                rk817_slppin_slp {
                    pins = "gpio_slp";
                    function = "pin_fun1";
                    phandle = <0x00000038>;
                };
                rk817_slppin_pwrdn {
                    pins = "gpio_slp";
                    function = "pin_fun2";
                    phandle = <0x0000003a>;
                };
                rk817_slppin_rst {
                    pins = "gpio_slp";
                    function = "pin_fun3";
                    phandle = <0x0000003b>;
                };
            };
            regulators {
                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_logic";
                    phandle = <0x00000062>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_gpu";
                    phandle = <0x00000064>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vcc_ddr";
                    phandle = <0x00000165>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                    };
                };
                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_npu";
                    phandle = <0x0000005f>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG1 {
                    regulator-boot-on;
                    regulator-always-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_image";
                    phandle = <0x00000166>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda_0v9";
                    phandle = <0x00000167>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_pmu";
                    phandle = <0x00000168>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x000dbba0>;
                    };
                };
                LDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_acodec";
                    phandle = <0x0000002a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_sd";
                    phandle = <0x0000002b>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vcc3v3_pmu";
                    phandle = <0x00000029>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x00325aa0>;
                    };
                };
                LDO_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca_1v8";
                    phandle = <0x00000103>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_pmu";
                    phandle = <0x00000169>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001b7740>;
                    };
                };
                LDO_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_image";
                    phandle = <0x0000016a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcc_1v8";
                    phandle = <0x0000002c>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc_3v3";
                    phandle = <0x0000002d>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc3v3_sd";
                    phandle = <0x000000ac>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };
            codec {
                #sound-dai-cells = <0x00000000>;
                compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
                clocks = <0x0000001f 0x000001a4>;
                clock-names = "mclk";
                assigned-clocks = <0x0000001f 0x000001a4 0x0000001f 0x000001a8>;
                assigned-clock-rates = <0x00bb8000>;
                assigned-clock-parents = <0x0000001f 0x00000054 0x0000001f 0x000001a4>;
                pinctrl-names = "default";
                pinctrl-0 = <0x0000003d>;
                hp-volume = <0x00000014>;
                spk-volume = <0x00000003>;
                mic-in-differential;
                status = "okay";
                phandle = <0x00000125>;
            };
        };
        sti8070@40 {
            compatible = "silergy,syr827";
            reg = <0x00000040>;
            vin-supply = <0x0000003e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x00100590>;
            regulator-max-microvolt = <0x001535b0>;
            regulator-ramp-delay = <0x000008fc>;
            fcs,suspend-voltage-selector = <0x00000001>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x00000005>;
            regulator-state-mem {
                regulator-off-in-suspend;
            };
        };
    };
    serial@fdd50000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfdd50000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000074 0x00000004>;
        clocks = <0x00000031 0x0000000b 0x00000031 0x0000002c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000000 0x0000003f 0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000040>;
        status = "disabled";
        phandle = <0x0000016b>;
    };
    pwm@fdd70000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000041>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016c>;
    };
    pwm@fdd70010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000042>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016d>;
    };
    pwm@fdd70020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000043>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016e>;
    };
    pwm@fdd70030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfdd70030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000052 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000044>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "okay";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x0000016f>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000bd 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000e5 0x00000066 0x000000e7 0x00000073 0x000000e8 0x00000072 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x000000a4 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000a4 0x0000008d 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
        ir_key4 {
            rockchip,usercode = <0x0000fe01>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000e6 0x0000009e 0x000000e9 0x00000067 0x000000e5 0x0000006c 0x000000ae 0x00000069 0x000000af 0x0000006a 0x000000ee 0x00000066 0x000000e7 0x00000073 0x000000ef 0x00000072 0x000000bf 0x00000074 0x000000be 0x00000071 0x000000b3 0x0000008b 0x000000ff 0x00000184 0x000000b1 0x00000002 0x000000f2 0x00000003 0x000000f3 0x00000004 0x000000b5 0x00000005 0x000000f6 0x00000006 0x000000f7 0x00000007 0x000000b9 0x00000008 0x000000fa 0x00000009 0x000000fb 0x0000000a 0x000000fe 0x0000000b 0x000000bd 0x0000000e 0x000000bc 0x000000b7 0x000000f0 0x000000ba 0x000000b4 0x0000019c 0x000000b8 0x0000001e 0x000000b0 0x00000197>;
        };
        ir_key5 {
            rockchip,usercode = <0x00007f80>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000d8 0x0000009e 0x000000c7 0x00000067 0x000000bf 0x0000006c 0x000000c8 0x00000069 0x000000c6 0x0000006a 0x0000008c 0x00000066 0x00000078 0x00000073 0x00000076 0x00000072 0x0000007e 0x00000074 0x0000007c 0x0000008b 0x000000b7 0x00000184>;
        };
        ir_key6 {
            rockchip,usercode = <0x0000fd01>;
            rockchip,key_table = <0x00000031 0x000000e8 0x0000002f 0x0000009e 0x00000035 0x00000067 0x0000002d 0x0000006c 0x00000066 0x00000069 0x0000003e 0x0000006a 0x0000006a 0x00000066 0x0000005e 0x00000073 0x00000047 0x00000072 0x00000023 0x00000074 0x0000003a 0x00000184 0x0000000d 0x00000040>;
        };
    };
    power-management@fdd90000 {
        compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdd90000 0x00000000 0x00001000>;
        phandle = <0x00000170>;
        power-controller {
            compatible = "rockchip,rk3568-power-controller";
            #power-domain-cells = <0x00000001>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000021>;
            pd_npu@6 {
                reg = <0x00000006>;
                clocks = <0x0000001f 0x00000027 0x0000001f 0x00000025 0x0000001f 0x00000026>;
                pm_qos = <0x00000045>;
            };
            pd_gpu@7 {
                reg = <0x00000007>;
                clocks = <0x0000001f 0x00000019 0x0000001f 0x0000001a>;
                pm_qos = <0x00000046>;
            };
            pd_vi@8 {
                reg = <0x00000008>;
                clocks = <0x0000001f 0x000000cc 0x0000001f 0x000000cd>;
                pm_qos = <0x00000047 0x00000048 0x00000049>;
            };
            pd_vo@9 {
                reg = <0x00000009>;
                clocks = <0x0000001f 0x000000da 0x0000001f 0x000000db 0x0000001f 0x000000dc>;
                pm_qos = <0x0000004a 0x0000004b 0x0000004c>;
            };
            pd_rga@10 {
                reg = <0x0000000a>;
                clocks = <0x0000001f 0x000000f1 0x0000001f 0x000000f2>;
                pm_qos = <0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052>;
            };
            pd_vpu@11 {
                reg = <0x0000000b>;
                clocks = <0x0000001f 0x000000ed>;
                pm_qos = <0x00000053>;
            };
            pd_rkvdec@13 {
                clocks = <0x0000001f 0x00000107>;
                reg = <0x0000000d>;
                pm_qos = <0x00000054>;
            };
            pd_rkvenc@14 {
                reg = <0x0000000e>;
                clocks = <0x0000001f 0x00000102>;
                pm_qos = <0x00000055 0x00000056 0x00000057>;
            };
            pd_pipe@15 {
                reg = <0x0000000f>;
                clocks = <0x0000001f 0x0000007f>;
                pm_qos = <0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c>;
            };
        };
    };
    pvtm@fde00000 {
        compatible = "rockchip,rk3568-core-pvtm";
        reg = <0x00000000 0xfde00000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@0 {
            reg = <0x00000000>;
            clocks = <0x0000001f 0x00000013 0x0000001f 0x000001c2>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x0000001a 0x0000001f 0x00000019>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    npu@fde40000 {
        compatible = "rockchip,rknpu";
        reg = <0x00000000 0xfde40000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        clocks = <0x00000002 0x00000002 0x0000001f 0x00000023 0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "scmi_clk", "clk", "aclk", "hclk";
        assigned-clocks = <0x0000001f 0x00000023>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x0000001f 0x0000002b 0x0000001f 0x0000002c>;
        reset-names = "srst_a", "srst_h";
        power-domains = <0x00000021 0x00000006>;
        operating-points-v2 = <0x0000005d>;
        iommus = <0x0000005e>;
        status = "okay";
        rknpu-supply = <0x0000005f>;
        phandle = <0x00000171>;
    };
    npu-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000060 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x000002bc 0x0000c350>;
        phandle = <0x0000005d>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000cf850 0x000cf850 0x000f4240>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000d59f8 0x000d59f8 0x000f4240>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x000f4240>;
        };
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000f4240 0x000f4240 0x000f4240>;
            status = "disabled";
        };
    };
    bus-npu {
        compatible = "rockchip,rk3568-bus";
        rockchip,busfreq-policy = "clkfreq";
        clocks = <0x00000002 0x00000002>;
        clock-names = "bus";
        operating-points-v2 = <0x00000061>;
        status = "okay";
        bus-supply = <0x00000062>;
        pvtm-supply = <0x00000005>;
        phandle = <0x00000172>;
    };
    bus-npu-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x00000061>;
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x00000000>;
        };
    };
    iommu@fde4b000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfde4b000 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        interrupt-names = "rknpu_mmu";
        clocks = <0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000006>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000005e>;
    };
    gpu@fde60000 {
        compatible = "arm,mali-bifrost";
        reg = <0x00000000 0xfde60000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000027 0x00000004 0x00000000 0x00000029 0x00000004 0x00000000 0x00000028 0x00000004>;
        interrupt-names = "GPU", "MMU", "JOB";
        upthreshold = <0x00000028>;
        downdifferential = <0x0000000a>;
        clocks = <0x00000002 0x00000001 0x0000001f 0x0000001b>;
        clock-names = "clk_mali", "clk_gpu";
        power-domains = <0x00000021 0x00000007>;
        #cooling-cells = <0x00000002>;
        operating-points-v2 = <0x00000063>;
        status = "okay";
        mali-supply = <0x00000064>;
        phandle = <0x0000001d>;
        power-model {
            compatible = "simple-power-model";
            leakage-range = <0x00000005 0x0000000f>;
            ls = <0xffffa23e 0x00005927 0x00000000>;
            static-coefficient = <0x000186a0>;
            dynamic-coefficient = <0x000003b9>;
            ts = <0xfffe56a6 0x0000f87a 0xfffffab5 0x00000014>;
            thermal-zone = "gpu-thermal";
            phandle = <0x00000173>;
        };
    };
    opp-table2 {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000065 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        phandle = <0x00000063>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11e1a300>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000dbba0>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000e7ef0>;
        };
    };
    pvtm@fde80000 {
        compatible = "rockchip,rk3568-gpu-pvtm";
        reg = <0x00000000 0xfde80000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@1 {
            reg = <0x00000001>;
            clocks = <0x0000001f 0x0000001e 0x0000001f 0x0000001d>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x00000024 0x0000001f 0x00000023>;
            reset-names = "rts", "rst-p";
            thermal-zone = "gpu-thermal";
        };
    };
    pvtm@fde90000 {
        compatible = "rockchip,rk3568-npu-pvtm";
        reg = <0x00000000 0xfde90000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@2 {
            reg = <0x00000002>;
            clocks = <0x0000001f 0x0000002b 0x0000001f 0x0000002a 0x0000001f 0x00000025>;
            clock-names = "clk", "pclk", "hclk";
            resets = <0x0000001f 0x0000002e 0x0000001f 0x0000002d>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    vdpu@fdea0400 {
        compatible = "rockchip,vpu-decoder-v2";
        reg = <0x00000000 0xfdea0400 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        resets = <0x0000001f 0x0000011a 0x0000001f 0x0000011b>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000066>;
        power-domains = <0x00000021 0x0000000b>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000000>;
        rockchip,resetgroup-node = <0x00000000>;
        status = "okay";
        phandle = <0x00000174>;
    };
    iommu@fdea0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdea0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008a 0x00000004>;
        interrupt-names = "vdpu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        power-domains = <0x00000021 0x0000000b>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000066>;
    };
    rk_rga@fdeb0000 {
        compatible = "rockchip,rga2";
        reg = <0x00000000 0xfdeb0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000005a 0x00000004>;
        clocks = <0x0000001f 0x000000f3 0x0000001f 0x000000f4 0x0000001f 0x000000f5>;
        clock-names = "aclk_rga", "hclk_rga", "clk_rga";
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000175>;
    };
    ebc@fdec0000 {
        compatible = "rockchip,rk3568-ebc-tcon";
        reg = <0x00000000 0xfdec0000 0x00000000 0x00005000>;
        interrupts = <0x00000000 0x00000011 0x00000004>;
        clocks = <0x0000001f 0x000000f9 0x0000001f 0x000000fa>;
        clock-names = "hclk", "dclk";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,grf = <0x00000032>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000068>;
        status = "disabled";
        phandle = <0x00000176>;
    };
    jpegd@fded0000 {
        compatible = "rockchip,rkv-jpeg-decoder-v1";
        reg = <0x00000000 0xfded0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000003e 0x00000004>;
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012c 0x0000001f 0x0000012d>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000069>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000001>;
        rockchip,resetgroup-node = <0x00000001>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000177>;
    };
    iommu@fded0480 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfded0480 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003d 0x00000004>;
        interrupt-names = "jpegd_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000069>;
    };
    vepu@fdee0000 {
        compatible = "rockchip,vpu-encoder-v2";
        reg = <0x00000000 0xfdee0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x00000040 0x00000004>;
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012e 0x0000001f 0x0000012f>;
        reset-names = "video_a", "video_h";
        iommus = <0x0000006a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000002>;
        rockchip,resetgroup-node = <0x00000002>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000178>;
    };
    iommu@fdee0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdee0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003f 0x00000004>;
        interrupt-names = "vepu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006a>;
    };
    iep@fdef0000 {
        compatible = "rockchip,iep-v2";
        reg = <0x00000000 0xfdef0000 0x00000000 0x00000500>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7 0x0000001f 0x000000f8>;
        clock-names = "aclk", "hclk", "sclk";
        resets = <0x0000001f 0x00000127 0x0000001f 0x00000128 0x0000001f 0x00000129>;
        reset-names = "rst_a", "rst_h", "rst_s";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000005>;
        rockchip,resetgroup-node = <0x00000005>;
        iommus = <0x0000006b>;
        status = "okay";
        phandle = <0x00000179>;
    };
    iommu@fdef0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdef0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        interrupt-names = "iep_mmu";
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x0000006b>;
    };
    eink@fdf00000 {
        compatible = "rockchip,rk3568-eink-tcon";
        reg = <0x00000000 0xfdf00000 0x00000000 0x00000074>;
        interrupts = <0x00000000 0x000000b2 0x00000004>;
        clocks = <0x0000001f 0x000000ff 0x0000001f 0x00000100>;
        clock-names = "pclk", "hclk";
        status = "disabled";
        phandle = <0x0000017a>;
    };
    rkvenc@fdf40000 {
        compatible = "rockchip,rkv-encoder-v1";
        reg = <0x00000000 0xfdf40000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008c 0x00000004>;
        interrupt-names = "irq_enc";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104 0x0000001f 0x00000105>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40>;
        resets = <0x0000001f 0x00000133 0x0000001f 0x00000134 0x0000001f 0x00000135>;
        reset-names = "video_a", "video_h", "video_core";
        assigned-clocks = <0x0000001f 0x00000103 0x0000001f 0x00000105>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40>;
        iommus = <0x0000006c>;
        node-name = "rkvenc";
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000003>;
        rockchip,resetgroup-node = <0x00000003>;
        power-domains = <0x00000021 0x0000000e>;
        operating-points-v2 = <0x0000006d>;
        status = "okay";
        venc-supply = <0x00000062>;
        phandle = <0x0000017b>;
    };
    rkvenc-opp-table {
        compatible = "operating-points-v2";
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x0000006d>;
        opp-297000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x00000000>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
    };
    iommu@fdf40f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf40f00 0x00000000 0x00000040 0x00000000 0xfdf40f40 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008d 0x00000004 0x00000000 0x0000008e 0x00000004>;
        interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000e>;
        status = "okay";
        phandle = <0x0000006c>;
    };
    rkvdec@fdf80200 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x00000000 0xfdf80200 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000005b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core", "clk_hevc_cabac";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40 0x11b3dc40 0x23c34600>;
        rockchip,advanced-rates = <0x179a7b00 0x00000000 0x179a7b00 0x179a7b00 0x23c34600>;
        rockchip,default-max-load = <0x001fe000>;
        resets = <0x0000001f 0x00000142 0x0000001f 0x00000143 0x0000001f 0x00000144 0x0000001f 0x00000145 0x0000001f 0x00000146>;
        assigned-clocks = <0x0000001f 0x00000108 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>;
        reset-names = "video_a", "video_h", "video_cabac", "video_core", "video_hevc_cabac";
        power-domains = <0x00000021 0x0000000d>;
        iommus = <0x0000006e>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000004>;
        rockchip,resetgroup-node = <0x00000004>;
        rockchip,sram = <0x0000006f>;
        rockchip,rcb-iova = <0x10000000 0x00010000>;
        rockchip,rcb-min-width = <0x00000200>;
        status = "okay";
        phandle = <0x0000017c>;
    };
    iommu@fdf80800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf80800 0x00000000 0x00000040 0x00000000 0xfdf80840 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000005c 0x00000004>;
        interrupt-names = "rkvdec_mmu";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x0000000d>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006e>;
    };
    mipi-csi2@fdfb0000 {
        compatible = "rockchip,rk3568-mipi-csi2";
        reg = <0x00000000 0xfdfb0000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000008 0x00000004 0x00000000 0x00000009 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x0000001f 0x000000d5>;
        clock-names = "pclk_csi2host";
        resets = <0x0000001f 0x000000ff>;
        reset-names = "srst_csihost_p";
        status = "disabled";
        phandle = <0x0000017d>;
    };
    rkcif@fdfe0000 {
        compatible = "rockchip,rk3568-cif";
        reg = <0x00000000 0xfdfe0000 0x00000000 0x00008000>;
        reg-names = "cif_regs";
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif-intr";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf 0x0000001f 0x000000d0 0x0000001f 0x000000d1>;
        clock-names = "aclk_cif", "hclk_cif", "dclk_cif", "iclk_cif_g";
        resets = <0x0000001f 0x000000f7 0x0000001f 0x000000f8 0x0000001f 0x000000f9 0x0000001f 0x000000fb 0x0000001f 0x000000fa>;
        reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_p", "rst_cif_i";
        assigned-clocks = <0x0000001f 0x000000d0>;
        assigned-clock-rates = <0x11e1a300>;
        power-domains = <0x00000021 0x00000008>;
        rockchip,grf = <0x00000032>;
        iommus = <0x00000070>;
        status = "okay";
        phandle = <0x00000071>;
    };
    iommu@fdfe0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdfe0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif_mmu";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        rockchip,disable-mmu-reset;
        #iommu-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000070>;
    };
    rkcif_dvp {
        compatible = "rockchip,rkcif-dvp";
        rockchip,hw = <0x00000071>;
        status = "okay";
        phandle = <0x00000073>;
        port {
            endpoint {
                remote-endpoint = <0x00000072>;
                bus-width = <0x00000008>;
                vsync-active = <0x00000000>;
                hsync-active = <0x00000001>;
                phandle = <0x000000d3>;
            };
        };
    };
    rkcif_dvp_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000073>;
        status = "disabled";
        phandle = <0x0000017e>;
    };
    rkcif_mipi_lvds {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000071>;
        status = "disabled";
        phandle = <0x00000074>;
    };
    rkcif_mipi_lvds_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000074>;
        status = "disabled";
        phandle = <0x0000017f>;
    };
    rkisp@fdff0000 {
        compatible = "rockchip,rk3568-rkisp";
        reg = <0x00000000 0xfdff0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000039 0x00000004 0x00000000 0x0000003a 0x00000004 0x00000000 0x0000003c 0x00000004>;
        interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3 0x0000001f 0x000000d4>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp";
        resets = <0x0000001f 0x000000fd 0x0000001f 0x000000fc>;
        reset-names = "isp", "isp-h";
        rockchip,grf = <0x00000032>;
        power-domains = <0x00000021 0x00000008>;
        iommus = <0x00000075>;
        rockchip,iq-feature = <0x000003fb 0xf7fe67ff>;
        status = "okay";
        phandle = <0x00000076>;
    };
    iommu@fdff1a00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdff1a00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000003b 0x00000004>;
        interrupt-names = "isp_mmu";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "okay";
        phandle = <0x00000075>;
    };
    rkisp-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "okay";
        phandle = <0x00000180>;
        port {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            endpoint@0 {
                reg = <0x00000000>;
                remote-endpoint = <0x00000077>;
                phandle = <0x0000010a>;
            };
        };
    };
    rkisp-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "disabled";
        phandle = <0x00000181>;
    };
    ethernet@fe010000 {
        compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
        reg = <0x00000000 0xfe010000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000020 0x00000004 0x00000000 0x0000001d 0x00000004>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000186 0x0000001f 0x00000189 0x0000001f 0x00000189 0x0000001f 0x000000c7 0x0000001f 0x000000c3 0x0000001f 0x000000c4 0x0000001f 0x00000189 0x0000001f 0x000000c8 0x0000001f 0x000000ac>;
        clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref", "pclk_xpcs";
        resets = <0x0000001f 0x000000ec>;
        reset-names = "stmmaceth";
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x00000078>;
        snps,mtl-rx-config = <0x00000079>;
        snps,mtl-tx-config = <0x0000007a>;
        status = "okay";
        phy-mode = "rgmii";
        clock_in_out = "output";
        snps,reset-gpio = <0x0000007b 0x00000001 0x00000001>;
        snps,reset-active-low;
        snps,reset-delays-us = <0x00000000 0x00004e20 0x000186a0>;
        assigned-clocks = <0x0000001f 0x00000189 0x0000001f 0x00000186>;
        assigned-clock-parents = <0x0000001f 0x00000187 0x0000001f 0x000000c5>;
        assigned-clock-rates = <0x00000000 0x07735940>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080>;
        tx_delay = <0x00000041>;
        rx_delay = <0x0000002e>;
        phy-handle = <0x00000081>;
        phandle = <0x00000182>;
        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000183>;
            phy@0 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <0x00000000>;
                phandle = <0x00000081>;
            };
        };
        stmmac-axi-config {
            snps,wr_osr_lmt = <0x00000004>;
            snps,rd_osr_lmt = <0x00000008>;
            snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>;
            phandle = <0x00000078>;
        };
        rx-queues-config {
            snps,rx-queues-to-use = <0x00000001>;
            phandle = <0x00000079>;
            queue0 {
            };
        };
        tx-queues-config {
            snps,tx-queues-to-use = <0x00000001>;
            phandle = <0x0000007a>;
            queue0 {
            };
        };
    };
    vop@fe040000 {
        compatible = "rockchip,rk3568-vop";
        reg = <0x00000000 0xfe040000 0x00000000 0x00003000 0x00000000 0xfe044000 0x00000000 0x00001000>;
        reg-names = "regs", "gamma_lut";
        rockchip,grf = <0x00000032>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de 0x0000001f 0x000000df 0x0000001f 0x000000e0 0x0000001f 0x000000e1>;
        clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
        iommus = <0x00000082>;
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        assigned-clocks = <0x0000001f 0x000000df 0x0000001f 0x000000e0>;
        assigned-clock-parents = <0x00000031 0x00000002 0x0000001f 0x00000005>;
        support-multi-area;
        phandle = <0x00000184>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000012>;
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                phandle = <0x00000185>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000083>;
                    phandle = <0x0000008f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000084>;
                    phandle = <0x00000015>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000085>;
                    phandle = <0x00000016>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x00000086>;
                    phandle = <0x00000017>;
                };
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                phandle = <0x00000186>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000087>;
                    phandle = <0x00000014>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000088>;
                    phandle = <0x00000098>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000089>;
                    phandle = <0x000000a5>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x0000008a>;
                    phandle = <0x000000a3>;
                };
                endpoint@4 {
                    reg = <0x00000004>;
                    remote-endpoint = <0x0000008b>;
                    phandle = <0x00000018>;
                };
            };
            port@2 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000002>;
                phandle = <0x00000187>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008c>;
                    phandle = <0x0000002f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000008d>;
                    phandle = <0x00000019>;
                };
            };
        };
    };
    iommu@fe043e00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfe043e00 0x00000000 0x00000100 0x00000000 0xfe043f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        interrupt-names = "vop_mmu";
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000082>;
    };
    dsi@fe060000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe060000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000044 0x00000004>;
        clocks = <0x0000001f 0x000000e8 0x0000001f 0x000000da 0x0000008e>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000110>;
        reset-names = "apb";
        phys = <0x0000008e>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000188>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000189>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008f>;
                    status = "disabled";
                    phandle = <0x00000083>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000014>;
                    status = "okay";
                    phandle = <0x00000087>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000090>;
                    phandle = <0x00000096>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x00000091>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x00000092>;
            reset-gpios = <0x00000093 0x00000005 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x00000094>;
            phandle = <0x0000018a>;
            display-timings {
                native-mode = <0x00000095>;
                phandle = <0x0000018b>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x00000095>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x00000096>;
                        phandle = <0x00000090>;
                    };
                };
            };
        };
    };
    dsi@fe070000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe070000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000045 0x00000004>;
        clocks = <0x0000001f 0x000000e9 0x0000001f 0x000000da 0x00000097>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000111>;
        reset-names = "apb";
        phys = <0x00000097>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000018c>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x0000018d>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000015>;
                    status = "disabled";
                    phandle = <0x00000084>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000098>;
                    status = "disabled";
                    phandle = <0x00000088>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000099>;
                    phandle = <0x0000009f>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x0000009a>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x0000009b>;
            reset-gpios = <0x0000009c 0x00000016 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000009d>;
            phandle = <0x0000018e>;
            display-timings {
                native-mode = <0x0000009e>;
                phandle = <0x0000018f>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x0000009e>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x0000009f>;
                        phandle = <0x00000099>;
                    };
                };
            };
        };
    };
    hdmi@fe0a0000 {
        compatible = "rockchip,rk3568-dw-hdmi";
        reg = <0x00000000 0xfe0a0000 0x00000000 0x00020000>;
        interrupts = <0x00000000 0x0000002d 0x00000004>;
        clocks = <0x0000001f 0x000000e6 0x0000001f 0x000000e7 0x0000001f 0x00000193 0x00000031 0x00000002 0x0000001f 0x000000de>;
        clock-names = "iahb", "isfr", "cec", "ref", "hclk";
        power-domains = <0x00000021 0x00000009>;
        reg-io-width = <0x00000004>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000a0 0x000000a1 0x000000a2>;
        status = "okay";
        rockchip,phy-table = <0x058834d4 0x00008009 0x00000000 0x00000270 0x09d5b340 0x0000800b 0x00000000 0x0000026d 0x0b1069a8 0x0000800b 0x00000000 0x000001ed 0x11b3dc40 0x0000800b 0x00000000 0x000001ad 0x2367b880 0x00008029 0x00000000 0x00000088 0x00000000 0x00000000 0x00000000 0x00000000>;
        phandle = <0x00000122>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000190>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000017>;
                    status = "okay";
                    phandle = <0x00000086>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a3>;
                    status = "disabled";
                    phandle = <0x0000008a>;
                };
            };
        };
    };
    edp@fe0c0000 {
        compatible = "rockchip,rk3568-edp";
        reg = <0x00000000 0xfe0c0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000012 0x00000004>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x000000ea 0x0000001f 0x000000eb 0x0000001f 0x000000da>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        reset-names = "dp", "apb";
        phys = <0x000000a4>;
        phy-names = "dp";
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        hpd-gpios = <0x00000093 0x00000007 0x00000000>;
        phandle = <0x00000191>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000192>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000016>;
                    status = "okay";
                    phandle = <0x00000085>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a5>;
                    status = "disabled";
                    phandle = <0x00000089>;
                };
            };
        };
    };
    qos@fe128000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe128000 0x00000000 0x00000020>;
        phandle = <0x00000046>;
    };
    qos@fe138080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138080 0x00000000 0x00000020>;
        phandle = <0x00000055>;
    };
    qos@fe138100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138100 0x00000000 0x00000020>;
        phandle = <0x00000056>;
    };
    qos@fe138180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138180 0x00000000 0x00000020>;
        phandle = <0x00000057>;
    };
    qos@fe148000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148000 0x00000000 0x00000020>;
        phandle = <0x00000047>;
    };
    qos@fe148080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148080 0x00000000 0x00000020>;
        phandle = <0x00000048>;
    };
    qos@fe148100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148100 0x00000000 0x00000020>;
        phandle = <0x00000049>;
    };
    qos@fe150000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe150000 0x00000000 0x00000020>;
        phandle = <0x00000053>;
    };
    qos@fe158000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158000 0x00000000 0x00000020>;
        phandle = <0x0000004d>;
    };
    qos@fe158100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158100 0x00000000 0x00000020>;
        phandle = <0x0000004e>;
    };
    qos@fe158180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158180 0x00000000 0x00000020>;
        phandle = <0x0000004f>;
    };
    qos@fe158200 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158200 0x00000000 0x00000020>;
        phandle = <0x00000050>;
    };
    qos@fe158280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158280 0x00000000 0x00000020>;
        phandle = <0x00000051>;
    };
    qos@fe158300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158300 0x00000000 0x00000020>;
        phandle = <0x00000052>;
    };
    qos@fe180000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe180000 0x00000000 0x00000020>;
        phandle = <0x00000045>;
    };
    qos@fe190000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190000 0x00000000 0x00000020>;
        phandle = <0x00000058>;
    };
    qos@fe190280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190280 0x00000000 0x00000020>;
        phandle = <0x00000059>;
    };
    qos@fe190300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190300 0x00000000 0x00000020>;
        phandle = <0x0000005a>;
    };
    qos@fe190380 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190380 0x00000000 0x00000020>;
        phandle = <0x0000005b>;
    };
    qos@fe190400 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190400 0x00000000 0x00000020>;
        phandle = <0x0000005c>;
    };
    qos@fe198000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe198000 0x00000000 0x00000020>;
        phandle = <0x00000054>;
    };
    qos@fe1a8000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8000 0x00000000 0x00000020>;
        phandle = <0x0000004a>;
    };
    qos@fe1a8080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8080 0x00000000 0x00000020>;
        phandle = <0x0000004b>;
    };
    qos@fe1a8100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8100 0x00000000 0x00000020>;
        phandle = <0x0000004c>;
    };
    dwmmc@fe000000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe000000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000064 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000c1 0x0000001f 0x000000c2 0x0000001f 0x0000018e 0x0000001f 0x0000018f>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000eb>;
        reset-names = "reset";
        status = "disabled";
        phandle = <0x00000193>;
    };
    dfi@fe230000 {
        reg = <0x00000000 0xfe230000 0x00000000 0x00000400>;
        compatible = "rockchip,rk3568-dfi";
        rockchip,pmugrf = <0x00000033>;
        status = "disabled";
        phandle = <0x000000a6>;
    };
    dmc {
        compatible = "rockchip,rk3568-dmc";
        interrupts = <0x00000000 0x0000000a 0x00000004>;
        interrupt-names = "complete";
        devfreq-events = <0x000000a6>;
        clocks = <0x0000001f 0x000001a2>;
        clock-names = "dmc_clk";
        operating-points-v2 = <0x000000a7>;
        ddr_timing = <0x000000a8>;
        vop-bw-dmc-freq = <0x00000000 0x000001f9 0x0004f1a0 0x000001fa 0x0001869f 0x00080e80>;
        upthreshold = <0x00000028>;
        downdifferential = <0x00000014>;
        system-status-freq = <0x00000001 0x000be6e0 0x00000008 0x000be6e0 0x00000002 0x000be6e0 0x00000010 0x000be6e0 0x00010000 0x000be6e0 0x00001000 0x000be6e0 0x00004000 0x000be6e0 0x00002000 0x000be6e0 0x00000c00 0x000be6e0>;
        auto-min-freq = <0x0004f1a0>;
        auto-freq-en = <0x00000001>;
        #cooling-cells = <0x00000002>;
        status = "disabled";
        center-supply = <0x00000062>;
        phandle = <0x00000013>;
    };
    dmc-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x000000a9 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000618 0x000061a8>;
        rockchip,leakage-voltage-sel = <0x00000001 0x00000050 0x00000000 0x00000051 0x000000fe 0x00000001>;
        phandle = <0x000000a7>;
        opp-324000000 {
            opp-hz = <0x00000000 0x134fd900>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-528000000 {
            opp-hz = <0x00000000 0x1f78a400>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-780000000 {
            opp-hz = <0x00000000 0x2e7ddb00>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-920000000 {
            opp-hz = <0x00000000 0x36d61600>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
            status = "disabled";
        };
        opp-1056000000 {
            opp-hz = <0x00000000 0x3ef14800>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
    };
    pcie@fe260000 {
        compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000000 0x0000000f>;
        clocks = <0x0000001f 0x00000081 0x0000001f 0x00000082 0x0000001f 0x00000083 0x0000001f 0x00000084 0x0000001f 0x00000085>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
        device_type = "pci";
        interrupts = <0x00000000 0x0000004b 0x00000004 0x00000000 0x0000004a 0x00000004 0x00000000 0x00000049 0x00000004 0x00000000 0x00000048 0x00000004 0x00000000 0x00000047 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x000000aa 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x000000aa 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x000000aa 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x000000aa 0x00000003>;
        linux,pci-domain = <0x00000000>;
        num-ib-windows = <0x00000006>;
        num-ob-windows = <0x00000002>;
        max-link-speed = <0x00000002>;
        msi-map = <0x00000000 0x000000ab 0x00000000 0x00001000>;
        num-lanes = <0x00000001>;
        phys = <0x00000022 0x00000002>;
        phy-names = "pcie-phy";
        power-domains = <0x00000021 0x0000000f>;
        ranges = <0x00000800 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00800000 0x81000000 0x00000000 0x00800000 0x00000003 0x00800000 0x00000000 0x00100000 0x83000000 0x00000000 0x00900000 0x00000003 0x00900000 0x00000000 0x3f700000>;
        reg = <0x00000003 0xc0000000 0x00000000 0x00400000 0x00000000 0xfe260000 0x00000000 0x00010000>;
        reg-names = "pcie-dbi", "pcie-apb";
        resets = <0x0000001f 0x000000a1>;
        reset-names = "pipe";
        status = "disabled";
        phandle = <0x00000194>;
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x00000048 0x00000001>;
            phandle = <0x000000aa>;
        };
    };
    dwmmc@fe2b0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2b0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000062 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b0 0x0000001f 0x000000b1 0x0000001f 0x0000018a 0x0000001f 0x0000018b>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d4>;
        reset-names = "reset";
        status = "okay";
        supports-sd;
        bus-width = <0x00000004>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        disable-wp;
        sd-uhs-sdr104;
        vmmc-supply = <0x000000ac>;
        vqmmc-supply = <0x0000002b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ad 0x000000ae 0x000000af 0x000000b0>;
        phandle = <0x00000195>;
    };
    dwmmc@fe2c0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2c0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000063 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b2 0x0000001f 0x000000b3 0x0000001f 0x0000018c 0x0000001f 0x0000018d>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d6>;
        reset-names = "reset";
        status = "okay";
        supports-sdio;
        bus-width = <0x00000004>;
        disable-wp;
        cap-sd-highspeed;
        cap-sdio-irq;
        keep-power-in-suspend;
        mmc-pwrseq = <0x000000b1>;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b2 0x000000b3 0x000000b4>;
        sd-uhs-sdr104;
        phandle = <0x00000196>;
    };
    sfc@fe300000 {
        compatible = "rockchip,sfc";
        reg = <0x00000000 0xfe300000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000065 0x00000004>;
        clocks = <0x0000001f 0x00000078 0x0000001f 0x00000076>;
        clock-names = "clk_sfc", "hclk_sfc";
        assigned-clocks = <0x0000001f 0x00000078>;
        assigned-clock-rates = <0x05f5e100>;
        status = "okay";
        phandle = <0x00000197>;
    };
    sdhci@fe310000 {
        compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
        reg = <0x00000000 0xfe310000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000013 0x00000004>;
        assigned-clocks = <0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        assigned-clock-rates = <0x0bebc200 0x016e3600>;
        clocks = <0x0000001f 0x0000007c 0x0000001f 0x0000007a 0x0000001f 0x00000079 0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        clock-names = "core", "bus", "axi", "block", "timer";
        status = "okay";
        bus-width = <0x00000008>;
        supports-emmc;
        non-removable;
        max-frequency = <0x0bebc200>;
        phandle = <0x00000198>;
    };
    nandc@fe330000 {
        compatible = "rockchip,rk-nandc-v9";
        reg = <0x00000000 0xfe330000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000046 0x00000004>;
        nandc_id = <0x00000000>;
        clocks = <0x0000001f 0x00000075 0x0000001f 0x00000074>;
        clock-names = "clk_nandc", "hclk_nandc";
        status = "okay";
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        phandle = <0x00000199>;
        nand@0 {
            reg = <0x00000000>;
            nand-bus-width = <0x00000008>;
            nand-ecc-mode = "hw";
            nand-ecc-strength = <0x00000010>;
            nand-ecc-step-size = <0x00000400>;
        };
    };
    crypto@fe380000 {
        compatible = "rockchip,rk3568-crypto";
        reg = <0x00000000 0xfe380000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000004 0x00000004>;
        clocks = <0x0000001f 0x0000006a 0x0000001f 0x0000006b 0x0000001f 0x0000006c 0x0000001f 0x0000006d>;
        clock-names = "aclk", "hclk", "sclk", "apb_pclk";
        assigned-clocks = <0x0000001f 0x0000006c>;
        assigned-clock-rates = <0x0bebc200>;
        resets = <0x0000001f 0x00000069>;
        reset-names = "crypto-rst";
        status = "disabled";
        phandle = <0x0000019a>;
    };
    rng@fe388000 {
        compatible = "rockchip,cryptov2-rng";
        reg = <0x00000000 0xfe388000 0x00000000 0x00002000>;
        clocks = <0x0000001f 0x00000070 0x0000001f 0x0000006f>;
        clock-names = "clk_trng", "hclk_trng";
        resets = <0x0000001f 0x0000006d>;
        reset-names = "reset";
        status = "okay";
        phandle = <0x0000019b>;
    };
    otp@fe38c000 {
        compatible = "rockchip,rk3568-otp";
        reg = <0x00000000 0xfe38c000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000073 0x0000001f 0x00000072 0x0000001f 0x00000071 0x0000001f 0x00000181>;
        clock-names = "usr", "sbpi", "apb", "phy";
        resets = <0x0000001f 0x000001cf>;
        reset-names = "otp_phy";
        phandle = <0x0000019c>;
        cpu-code@2 {
            reg = <0x00000002 0x00000002>;
            phandle = <0x0000000f>;
        };
        cpu-version@8 {
            reg = <0x00000008 0x00000001>;
            bits = <0x00000003 0x00000003>;
            phandle = <0x0000000e>;
        };
        mbist-vmin@9 {
            reg = <0x00000009 0x00000001>;
            bits = <0x00000000 0x00000004>;
            phandle = <0x00000008>;
        };
        id@a {
            reg = <0x0000000a 0x00000010>;
            phandle = <0x0000000d>;
        };
        cpu-leakage@1a {
            reg = <0x0000001a 0x00000001>;
            phandle = <0x00000006>;
        };
        log-leakage@1b {
            reg = <0x0000001b 0x00000001>;
            phandle = <0x000000a9>;
        };
        npu-leakage@1c {
            reg = <0x0000001c 0x00000001>;
            phandle = <0x00000060>;
        };
        gpu-leakage@1d {
            reg = <0x0000001d 0x00000001>;
            phandle = <0x00000065>;
        };
        core-pvtm@2a {
            reg = <0x0000002a 0x00000002>;
            phandle = <0x00000007>;
        };
    };
    i2s@fe400000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe400000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000034 0x00000004>;
        clocks = <0x0000001f 0x0000003f 0x0000001f 0x00000043 0x0000001f 0x00000039>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000000>;
        dma-names = "tx";
        resets = <0x0000001f 0x00000050 0x0000001f 0x00000051>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000121>;
    };
    i2s@fe410000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe410000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000035 0x00000004>;
        clocks = <0x0000001f 0x00000047 0x0000001f 0x0000004b 0x0000001f 0x0000003a>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000002 0x000000b5 0x00000003>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000052 0x0000001f 0x00000053>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b6 0x000000b7 0x000000b8 0x000000b9>;
        status = "disabled";
        rockchip,clk-trcm = <0x00000001>;
        phandle = <0x000000c6>;
    };
    i2s@fe420000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe420000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000036 0x00000004>;
        clocks = <0x0000001f 0x0000004f 0x0000001f 0x0000004f 0x0000001f 0x0000003b>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000004 0x000000b5 0x00000005>;
        dma-names = "tx", "rx";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ba 0x000000bb 0x000000bc 0x000000bd>;
        status = "disabled";
        phandle = <0x0000019d>;
    };
    i2s@fe430000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe430000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000037 0x00000004>;
        clocks = <0x0000001f 0x00000053 0x0000001f 0x00000057 0x0000001f 0x0000003c>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000006 0x000000b5 0x00000007>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000055 0x0000001f 0x00000056>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000be 0x000000bf 0x000000c0 0x000000c1>;
        status = "okay";
        phandle = <0x0000011d>;
    };
    pdm@fe440000 {
        compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
        reg = <0x00000000 0xfe440000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000005a 0x0000001f 0x00000059>;
        clock-names = "pdm_clk", "pdm_hclk";
        dmas = <0x000000b5 0x00000009>;
        dma-names = "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c2 0x000000c3 0x000000c4 0x000000c5>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000123>;
    };
    vad@fe450000 {
        compatible = "rockchip,rk3568-vad";
        reg = <0x00000000 0xfe450000 0x00000000 0x00010000>;
        reg-names = "vad";
        clocks = <0x0000001f 0x0000005b>;
        clock-names = "hclk";
        interrupts = <0x00000000 0x00000089 0x00000004>;
        rockchip,audio-src = <0x000000c6>;
        rockchip,det-channel = <0x00000000>;
        rockchip,mode = <0x00000000>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        rockchip,buffer-time-ms = <0x00000080>;
        phandle = <0x00000128>;
    };
    spdif@fe460000 {
        compatible = "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfe460000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000066 0x00000004>;
        dmas = <0x000000b5 0x00000001>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x0000001f 0x0000005f 0x0000001f 0x0000005c>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c7>;
        status = "okay";
        phandle = <0x00000126>;
    };
    audpwm@fe470000 {
        compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
        reg = <0x00000000 0xfe470000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000063 0x0000001f 0x00000060>;
        clock-names = "clk", "hclk";
        dmas = <0x000000b5 0x00000008>;
        dma-names = "tx";
        #sound-dai-cells = <0x00000000>;
        rockchip,sample-width-bits = <0x0000000b>;
        rockchip,interpolat-points = <0x00000001>;
        status = "disabled";
        phandle = <0x0000019e>;
    };
    codec-digital@fe478000 {
        compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
        reg = <0x00000000 0xfe478000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000067 0x0000001f 0x00000066 0x0000001f 0x00000065 0x0000001f 0x00000064>;
        clock-names = "adc", "dac", "i2c", "pclk";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c8>;
        resets = <0x0000001f 0x0000005f>;
        reset-names = "reset";
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000011e>;
    };
    dmac@fe530000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe530000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x0000000e 0x00000004 0x00000000 0x0000000d 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x0000003f>;
    };
    dmac@fe550000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe550000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000010 0x00000004 0x00000000 0x0000000f 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x000000b5>;
    };
    rkscr@fe560000 {
        compatible = "rockchip-scr";
        reg = <0x00000000 0xfe560000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000061 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c9>;
        clocks = <0x0000001f 0x00000114>;
        clock-names = "g_pclk_sim_card";
        status = "disabled";
        phandle = <0x0000019f>;
    };
    can@fe570000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe570000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000001 0x00000004>;
        clocks = <0x0000001f 0x00000141 0x0000001f 0x00000140>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000155 0x0000001f 0x00000154>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000141>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ca>;
        phandle = <0x000001a0>;
    };
    can@fe580000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe580000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000002 0x00000004>;
        clocks = <0x0000001f 0x00000143 0x0000001f 0x00000142>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000157 0x0000001f 0x00000156>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000143>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cb>;
        phandle = <0x000001a1>;
    };
    can@fe590000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe590000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000003 0x00000004>;
        clocks = <0x0000001f 0x00000145 0x0000001f 0x00000144>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000159 0x0000001f 0x00000158>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000145>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cc>;
        phandle = <0x000001a2>;
    };
    i2c@fe5a0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5a0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000148 0x0000001f 0x00000147>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002f 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cd>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a3>;
        gt1x@14 {
            compatible = "goodix,gt1x";
            reg = <0x00000014>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000ce>;
            goodix,rst-gpio = <0x00000035 0x0000000e 0x00000000>;
            goodix,irq-gpio = <0x00000035 0x0000000d 0x00000008>;
            power-supply = <0x00000092>;
            status = "disabled";
            phandle = <0x000001a4>;
        };
    };
    i2c@fe5b0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5b0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014a 0x0000001f 0x00000149>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000030 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cf>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001a5>;
        gc2145@3c {
            status = "okay";
            compatible = "galaxycore,gc2145";
            reg = <0x0000003c>;
            clocks = <0x0000001f 0x000000d6>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d0 0x000000d1 0x000000d2>;
            power-gpios = <0x0000007b 0x0000001c 0x00000000>;
            pwdn-gpios = <0x0000007b 0x0000001a 0x00000000>;
            rockchip,camera-module-index = <0x00000001>;
            rockchip,camera-module-facing = "front";
            rockchip,camera-module-name = "CameraKing";
            rockchip,camera-module-lens-name = "Largan";
            phandle = <0x000001a6>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d3>;
                    phandle = <0x00000072>;
                };
            };
        };
        ov5695@36 {
            status = "okay";
            compatible = "ovti,ov5695";
            reg = <0x00000036>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000000>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000000>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "TongJu";
            rockchip,camera-module-lens-name = "CHT842-MD";
            phandle = <0x000001a7>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d5>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x00000108>;
                };
            };
        };
        gc8034@37 {
            compatible = "galaxycore,gc8034";
            status = "okay";
            reg = <0x00000037>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000001>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000001>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "RK-CMK-8M-2-v1";
            rockchip,camera-module-lens-name = "CK8401";
            phandle = <0x000001a8>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d6>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x00000109>;
                };
            };
        };
    };
    i2c@fe5c0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5c0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014c 0x0000001f 0x0000014b>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000031 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d7>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a9>;
    };
    i2c@fe5d0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5d0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014e 0x0000001f 0x0000014d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000032 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d8>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001aa>;
    };
    i2c@fe5e0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5e0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000150 0x0000001f 0x0000014f>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000033 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d9>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001ab>;
        mxc6655xa@15 {
            status = "okay";
            compatible = "gs_mxc6655xa";
            pinctrl-names = "default";
            pinctrl-0 = <0x000000da>;
            reg = <0x00000015>;
            irq-gpio = <0x0000007b 0x00000011 0x00000008>;
            irq_enable = <0x00000000>;
            poll_delay_ms = <0x0000001e>;
            type = <0x00000002>;
            power-off-in-suspend = <0x00000001>;
            layout = <0x00000001>;
            phandle = <0x000001ac>;
        };
    };
    timer@fe5f0000 {
        compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
        reg = <0x00000000 0xfe5f0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006d 0x00000004>;
        clocks = <0x0000001f 0x0000016c 0x0000001f 0x0000016d>;
        clock-names = "pclk", "timer";
        phandle = <0x000001ad>;
    };
    watchdog@fe600000 {
        compatible = "snps,dw-wdt";
        reg = <0x00000000 0xfe600000 0x00000000 0x00000100>;
        clocks = <0x0000001f 0x00000116 0x0000001f 0x00000115>;
        clock-names = "tclk", "pclk";
        interrupts = <0x00000000 0x00000095 0x00000004>;
        status = "okay";
        phandle = <0x000001ae>;
    };
    spi@fe610000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe610000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000067 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000152 0x0000001f 0x00000151>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000014 0x0000003f 0x00000015>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000db 0x000000dc 0x000000dd>;
        pinctrl-1 = <0x000000db 0x000000dc 0x000000de>;
        status = "disabled";
        phandle = <0x000001af>;
    };
    spi@fe620000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe620000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000068 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000154 0x0000001f 0x00000153>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000016 0x0000003f 0x00000017>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000df 0x000000e0 0x000000e1>;
        pinctrl-1 = <0x000000df 0x000000e0 0x000000e2>;
        status = "disabled";
        phandle = <0x000001b0>;
    };
    spi@fe630000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe630000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000069 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000156 0x0000001f 0x00000155>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000018 0x0000003f 0x00000019>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e3 0x000000e4 0x000000e5>;
        pinctrl-1 = <0x000000e3 0x000000e4 0x000000e6>;
        status = "disabled";
        phandle = <0x000001b1>;
    };
    spi@fe640000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe640000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006a 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000158 0x0000001f 0x00000157>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x0000001a 0x0000003f 0x0000001b>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e7 0x000000e8 0x000000e9>;
        pinctrl-1 = <0x000000e7 0x000000e8 0x000000ea>;
        status = "disabled";
        phandle = <0x000001b2>;
    };
    serial@fe650000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe650000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000075 0x00000004>;
        clocks = <0x0000001f 0x0000011f 0x0000001f 0x0000011c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000002 0x0000003f 0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000eb 0x000000ec>;
        status = "okay";
        phandle = <0x000001b3>;
    };
    serial@fe660000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe660000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000076 0x00000004>;
        clocks = <0x0000001f 0x00000123 0x0000001f 0x00000120>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000004 0x0000003f 0x00000005>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ed>;
        status = "disabled";
        phandle = <0x000001b4>;
    };
    serial@fe670000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe670000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000077 0x00000004>;
        clocks = <0x0000001f 0x00000127 0x0000001f 0x00000124>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000006 0x0000003f 0x00000007>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ee>;
        status = "disabled";
        phandle = <0x000001b5>;
    };
    serial@fe680000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe680000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000078 0x00000004>;
        clocks = <0x0000001f 0x0000012b 0x0000001f 0x00000128>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000008 0x0000003f 0x00000009>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ef>;
        status = "disabled";
        phandle = <0x000001b6>;
    };
    serial@fe690000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe690000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000079 0x00000004>;
        clocks = <0x0000001f 0x0000012f 0x0000001f 0x0000012c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000a 0x0000003f 0x0000000b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f0>;
        status = "disabled";
        phandle = <0x000001b7>;
    };
    serial@fe6a0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6a0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007a 0x00000004>;
        clocks = <0x0000001f 0x00000133 0x0000001f 0x00000130>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000c 0x0000003f 0x0000000d>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f1>;
        status = "disabled";
        phandle = <0x000001b8>;
    };
    serial@fe6b0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6b0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007b 0x00000004>;
        clocks = <0x0000001f 0x00000137 0x0000001f 0x00000134>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000e 0x0000003f 0x0000000f>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f2>;
        status = "disabled";
        phandle = <0x000001b9>;
    };
    serial@fe6c0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6c0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007c 0x00000004>;
        clocks = <0x0000001f 0x0000013b 0x0000001f 0x00000138>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000010 0x0000003f 0x00000011>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f3>;
        status = "disabled";
        phandle = <0x000001ba>;
    };
    serial@fe6d0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6d0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007d 0x00000004>;
        clocks = <0x0000001f 0x0000013f 0x0000001f 0x0000013c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000012 0x0000003f 0x00000013>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f4>;
        status = "disabled";
        phandle = <0x000001bb>;
    };
    pwm@fe6e0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f5>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x0000011f>;
    };
    pwm@fe6e0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f6>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x00000120>;
    };
    pwm@fe6e0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f7>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bc>;
    };
    pwm@fe6e0030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfe6e0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000053 0x00000004 0x00000000 0x00000057 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f8>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x000001bd>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000ba 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000bd 0x00000066 0x000000ea 0x00000073 0x000000e3 0x00000072 0x000000e2 0x000000d9 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x00000072 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
    };
    pwm@fe6f0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f9>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001be>;
    };
    pwm@fe6f0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fa>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bf>;
    };
    pwm@fe6f0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fb>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c0>;
    };
    pwm@fe6f0030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000054 0x00000004 0x00000000 0x00000058 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fc>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c1>;
    };
    pwm@fe700000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fd>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c2>;
    };
    pwm@fe700010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fe>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c3>;
    };
    pwm@fe700020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000ff>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c4>;
    };
    pwm@fe700030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000055 0x00000004 0x00000000 0x00000059 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000100>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c5>;
    };
    tsadc@fe710000 {
        compatible = "rockchip,rk3568-tsadc";
        reg = <0x00000000 0xfe710000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000073 0x00000004>;
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000111 0x0000001f 0x0000010f>;
        clock-names = "tsadc", "apb_pclk";
        assigned-clocks = <0x0000001f 0x00000110 0x0000001f 0x00000111>;
        assigned-clock-rates = <0x01036640 0x000aae60>;
        resets = <0x0000001f 0x00000182 0x0000001f 0x00000181 0x0000001f 0x000001d7>;
        reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
        #thermal-sensor-cells = <0x00000001>;
        rockchip,hw-tshut-temp = <0x0001d4c0>;
        rockchip,hw-tshut-mode = <0x00000000>;
        rockchip,hw-tshut-polarity = <0x00000000>;
        pinctrl-names = "gpio", "otpout";
        pinctrl-0 = <0x00000101>;
        pinctrl-1 = <0x00000102>;
        status = "okay";
        phandle = <0x0000001b>;
    };
    saradc@fe720000 {
        compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
        reg = <0x00000000 0xfe720000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000005d 0x00000004>;
        #io-channel-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        clock-names = "saradc", "apb_pclk";
        resets = <0x0000001f 0x00000180>;
        reset-names = "saradc-apb";
        status = "okay";
        vref-supply = <0x00000103>;
        phandle = <0x0000011b>;
    };
    mailbox@fe780000 {
        compatible = "rockchip,rk3568-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x00000000 0xfe780000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b7 0x00000004 0x00000000 0x000000b8 0x00000004 0x00000000 0x000000b9 0x00000004 0x00000000 0x000000ba 0x00000004>;
        clocks = <0x0000001f 0x0000011b>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x00000001>;
        status = "disabled";
        phandle = <0x000001c6>;
    };
    phy@fe830000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe830000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000022 0x0000001f 0x0000017d 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000022>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c6 0x0000001f 0x000001c7>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000105>;
        status = "okay";
        phandle = <0x00000020>;
    };
    phy@fe840000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe840000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000025 0x0000001f 0x0000017e 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000025>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c8 0x0000001f 0x000001c9>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000106>;
        status = "disabled";
        phandle = <0x00000022>;
    };
    mipi-dphy@fe850000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x0000008e>;
    };
    video-phy@fe850000 {
        compatible = "rockchip,rk3568-video-phy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000 0x00000000 0xfe060000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a 0x0000001f 0x000000e8>;
        clock-names = "ref", "pclk_phy", "pclk_host";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "rst";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000002e>;
    };
    mipi-dphy@fe860000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe860000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000019 0x0000001f 0x0000017b>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy1_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bc>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "disabled";
        phandle = <0x00000097>;
    };
    csi2-dphy-hw@fe870000 {
        compatible = "rockchip,rk3568-csi2-dphy-hw";
        reg = <0x00000000 0xfe870000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000179>;
        clock-names = "pclk";
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x00000107>;
    };
    csi2-dphy0 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "okay";
        phandle = <0x000001c7>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000108>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x000000d5>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000109>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x000000d6>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000010a>;
                    phandle = <0x00000077>;
                };
            };
        };
    };
    csi2-dphy1 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c8>;
    };
    csi2-dphy2 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c9>;
    };
    usb2-phy@fe8a0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8a0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000087 0x00000004>;
        clocks = <0x00000031 0x00000013>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        assigned-clocks = <0x0000001f 0x0000000b>;
        assigned-clock-parents = <0x00000024>;
        clock-output-names = "usb480m_phy";
        rockchip,usbgrf = <0x0000010b>;
        status = "okay";
        phandle = <0x00000024>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000025>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            vbus-supply = <0x0000010d>;
            phandle = <0x00000023>;
        };
    };
    usb2-phy@fe8b0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8b0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000088 0x00000004>;
        clocks = <0x00000031 0x00000015>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        rockchip,usbgrf = <0x0000010e>;
        status = "okay";
        phandle = <0x00000026>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000028>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000027>;
        };
    };
    pinctrl {
        compatible = "rockchip,rk3568-pinctrl";
        rockchip,grf = <0x00000032>;
        rockchip,pmu = <0x00000033>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000010f>;
        phandle = <0x00000110>;
        gpio@fdd60000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfdd60000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000021 0x00000004>;
            clocks = <0x00000031 0x0000002e 0x00000031 0x0000000c>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000000 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000035>;
        };
        gpio@fe740000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe740000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000022 0x00000004>;
            clocks = <0x0000001f 0x00000163 0x0000001f 0x00000164>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000020 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000093>;
        };
        gpio@fe750000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe750000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000023 0x00000004>;
            clocks = <0x0000001f 0x00000165 0x0000001f 0x00000166>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000040 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000012e>;
        };
        gpio@fe760000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe760000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000024 0x00000004>;
            clocks = <0x0000001f 0x00000167 0x0000001f 0x00000168>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000060 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000007b>;
        };
        gpio@fe770000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe770000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000025 0x00000004>;
            clocks = <0x0000001f 0x00000169 0x0000001f 0x0000016a>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000080 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000009c>;
        };
        pcfg-pull-up {
            bias-pull-up;
            phandle = <0x00000113>;
        };
        pcfg-pull-down {
            bias-pull-down;
            phandle = <0x0000011a>;
        };
        pcfg-pull-none {
            bias-disable;
            phandle = <0x00000111>;
        };
        pcfg-pull-none-drv-level-1 {
            bias-disable;
            drive-strength = <0x00000001>;
            phandle = <0x00000115>;
        };
        pcfg-pull-none-drv-level-2 {
            bias-disable;
            drive-strength = <0x00000002>;
            phandle = <0x00000114>;
        };
        pcfg-pull-none-drv-level-3 {
            bias-disable;
            drive-strength = <0x00000003>;
            phandle = <0x00000119>;
        };
        pcfg-pull-up-drv-level-1 {
            bias-pull-up;
            drive-strength = <0x00000001>;
            phandle = <0x00000118>;
        };
        pcfg-pull-up-drv-level-2 {
            bias-pull-up;
            drive-strength = <0x00000002>;
            phandle = <0x00000112>;
        };
        pcfg-pull-none-smt {
            bias-disable;
            input-schmitt-enable;
            phandle = <0x00000116>;
        };
        pcfg-output-low {
            output-low;
            phandle = <0x00000117>;
        };
        acodec {
            acodec-pins {
                rockchip,pins = <0x00000001 0x00000009 0x00000005 0x00000111 0x00000001 0x00000001 0x00000005 0x00000111 0x00000001 0x00000000 0x00000005 0x00000111 0x00000001 0x00000007 0x00000005 0x00000111 0x00000001 0x00000008 0x00000005 0x00000111 0x00000001 0x00000003 0x00000005 0x00000111 0x00000001 0x00000005 0x00000005 0x00000111>;
                phandle = <0x000000c8>;
            };
        };
        cam {
            cam-clkout0 {
                rockchip,pins = <0x00000004 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000d4>;
            };
            camera-pwr {
                rockchip,pins = <0x00000000 0x00000011 0x00000000 0x00000111>;
                phandle = <0x00000133>;
            };
        };
        can0 {
            can0m1-pins {
                rockchip,pins = <0x00000002 0x00000002 0x00000004 0x00000111 0x00000002 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000ca>;
            };
        };
        can1 {
            can1m1-pins {
                rockchip,pins = <0x00000004 0x00000012 0x00000003 0x00000111 0x00000004 0x00000013 0x00000003 0x00000111>;
                phandle = <0x000000cb>;
            };
        };
        can2 {
            can2m1-pins {
                rockchip,pins = <0x00000002 0x00000009 0x00000004 0x00000111 0x00000002 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000cc>;
            };
        };
        cif {
            cif-clk {
                rockchip,pins = <0x00000004 0x00000010 0x00000001 0x00000111>;
                phandle = <0x000000d0>;
            };
            cif-dvp-clk {
                rockchip,pins = <0x00000004 0x00000011 0x00000001 0x00000111 0x00000004 0x0000000e 0x00000001 0x00000111 0x00000004 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x000000d1>;
            };
            cif-dvp-bus16 {
                rockchip,pins = <0x00000003 0x0000001e 0x00000001 0x00000111 0x00000003 0x0000001f 0x00000001 0x00000111 0x00000004 0x00000000 0x00000001 0x00000111 0x00000004 0x00000001 0x00000001 0x00000111 0x00000004 0x00000002 0x00000001 0x00000111 0x00000004 0x00000003 0x00000001 0x00000111 0x00000004 0x00000004 0x00000001 0x00000111 0x00000004 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000d2>;
            };
        };
        clk32k {
            clk32k-out0 {
                rockchip,pins = <0x00000000 0x00000008 0x00000002 0x00000111>;
                phandle = <0x0000001e>;
            };
        };
        ebc {
            ebc-pins {
                rockchip,pins = <0x00000004 0x00000010 0x00000002 0x00000111 0x00000004 0x0000000b 0x00000002 0x00000111 0x00000004 0x0000000c 0x00000002 0x00000111 0x00000004 0x00000006 0x00000002 0x00000111 0x00000004 0x00000011 0x00000002 0x00000111 0x00000003 0x00000016 0x00000002 0x00000111 0x00000003 0x00000017 0x00000002 0x00000111 0x00000003 0x00000018 0x00000002 0x00000111 0x00000003 0x00000019 0x00000002 0x00000111 0x00000003 0x0000001a 0x00000002 0x00000111 0x00000003 0x0000001b 0x00000002 0x00000111 0x00000003 0x0000001c 0x00000002 0x00000111 0x00000003 0x0000001d 0x00000002 0x00000111 0x00000003 0x0000001e 0x00000002 0x00000111 0x00000003 0x0000001f 0x00000002 0x00000111 0x00000004 0x00000000 0x00000002 0x00000111 0x00000004 0x00000001 0x00000002 0x00000111 0x00000004 0x00000002 0x00000002 0x00000111 0x00000004 0x00000003 0x00000002 0x00000111 0x00000004 0x00000004 0x00000002 0x00000111 0x00000004 0x00000005 0x00000002 0x00000111 0x00000004 0x0000000e 0x00000002 0x00000111 0x00000004 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x00000068>;
            };
        };
        gmac1 {
            gmac1m0-miim {
                rockchip,pins = <0x00000003 0x00000014 0x00000003 0x00000111 0x00000003 0x00000015 0x00000003 0x00000111>;
                phandle = <0x0000007c>;
            };
            gmac1m0-rx-bus2 {
                rockchip,pins = <0x00000003 0x00000009 0x00000003 0x00000111 0x00000003 0x0000000a 0x00000003 0x00000111 0x00000003 0x0000000b 0x00000003 0x00000111>;
                phandle = <0x0000007e>;
            };
        };
        hdmitx {
            hdmitxm0-cec {
                rockchip,pins = <0x00000004 0x00000019 0x00000001 0x00000111>;
                phandle = <0x000000a2>;
            };
            hdmitx-scl {
                rockchip,pins = <0x00000004 0x00000017 0x00000001 0x00000111>;
                phandle = <0x000000a0>;
            };
            hdmitx-sda {
                rockchip,pins = <0x00000004 0x00000018 0x00000001 0x00000111>;
                phandle = <0x000000a1>;
            };
        };
        i2c0 {
            i2c0-xfer {
                rockchip,pins = <0x00000000 0x00000009 0x00000001 0x00000116 0x00000000 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x00000034>;
            };
        };
        i2c1 {
            i2c1-xfer {
                rockchip,pins = <0x00000000 0x0000000b 0x00000001 0x00000116 0x00000000 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cd>;
            };
        };
        i2c2 {
            i2c2m1-xfer {
                rockchip,pins = <0x00000004 0x0000000d 0x00000001 0x00000116 0x00000004 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cf>;
            };
        };
        i2c3 {
            i2c3m0-xfer {
                rockchip,pins = <0x00000001 0x00000001 0x00000001 0x00000116 0x00000001 0x00000000 0x00000001 0x00000116>;
                phandle = <0x000000d7>;
            };
        };
        i2c4 {
            i2c4m0-xfer {
                rockchip,pins = <0x00000004 0x0000000b 0x00000001 0x00000116 0x00000004 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x000000d8>;
            };
        };
        i2c5 {
            i2c5m0-xfer {
                rockchip,pins = <0x00000003 0x0000000b 0x00000004 0x00000116 0x00000003 0x0000000c 0x00000004 0x00000116>;
                phandle = <0x000000d9>;
            };
        };
        i2s1 {
            i2s1m0-lrcktx {
                rockchip,pins = <0x00000001 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000b7>;
            };
            i2s1m0-sclktx {
                rockchip,pins = <0x00000001 0x00000003 0x00000001 0x00000111>;
                phandle = <0x000000b6>;
            };
            i2s1m0-sdi0 {
                rockchip,pins = <0x00000001 0x0000000b 0x00000001 0x00000111>;
                phandle = <0x000000b8>;
            };
            i2s1m0-sdo0 {
                rockchip,pins = <0x00000001 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000b9>;
            };
        };
        i2s2 {
            i2s2m0-lrcktx {
                rockchip,pins = <0x00000002 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000bb>;
            };
            i2s2m0-sclktx {
                rockchip,pins = <0x00000002 0x00000012 0x00000001 0x00000111>;
                phandle = <0x000000ba>;
            };
            i2s2m0-sdi {
                rockchip,pins = <0x00000002 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000bc>;
            };
            i2s2m0-sdo {
                rockchip,pins = <0x00000002 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000bd>;
            };
        };
        i2s3 {
            i2s3m1-lrck {
                rockchip,pins = <0x00000004 0x00000014 0x00000005 0x00000111>;
                phandle = <0x000000bf>;
            };
            i2s3m1-mclk {
                rockchip,pins = <0x00000004 0x00000012 0x00000005 0x00000111>;
                phandle = <0x0000003d>;
            };
            i2s3m1-sclk {
                rockchip,pins = <0x00000004 0x00000013 0x00000005 0x00000111>;
                phandle = <0x000000be>;
            };
            i2s3m1-sdi {
                rockchip,pins = <0x00000004 0x00000016 0x00000005 0x00000111>;
                phandle = <0x000000c0>;
            };
            i2s3m1-sdo {
                rockchip,pins = <0x00000004 0x00000015 0x00000005 0x00000111>;
                phandle = <0x000000c1>;
            };
        };
        lcdc {
            lcdc-ctl {
                rockchip,pins = <0x00000003 0x00000000 0x00000001 0x00000111 0x00000002 0x00000018 0x00000001 0x00000111 0x00000002 0x00000019 0x00000001 0x00000111 0x00000002 0x0000001a 0x00000001 0x00000111 0x00000002 0x0000001b 0x00000001 0x00000111 0x00000002 0x0000001c 0x00000001 0x00000111 0x00000002 0x0000001d 0x00000001 0x00000111 0x00000002 0x0000001e 0x00000001 0x00000111 0x00000002 0x0000001f 0x00000001 0x00000111 0x00000003 0x00000001 0x00000001 0x00000111 0x00000003 0x00000002 0x00000001 0x00000111 0x00000003 0x00000003 0x00000001 0x00000111 0x00000003 0x00000004 0x00000001 0x00000111 0x00000003 0x00000005 0x00000001 0x00000111 0x00000003 0x00000006 0x00000001 0x00000111 0x00000003 0x00000007 0x00000001 0x00000111 0x00000003 0x00000008 0x00000001 0x00000111 0x00000003 0x00000009 0x00000001 0x00000111 0x00000003 0x0000000a 0x00000001 0x00000111 0x00000003 0x0000000b 0x00000001 0x00000111 0x00000003 0x0000000c 0x00000001 0x00000111 0x00000003 0x0000000d 0x00000001 0x00000111 0x00000003 0x0000000e 0x00000001 0x00000111 0x00000003 0x0000000f 0x00000001 0x00000111 0x00000003 0x00000010 0x00000001 0x00000111 0x00000003 0x00000013 0x00000001 0x00000111 0x00000003 0x00000011 0x00000001 0x00000111 0x00000003 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000030>;
            };
        };
        pdm {
            pdmm1-clk1 {
                rockchip,pins = <0x00000004 0x00000000 0x00000004 0x00000111>;
                phandle = <0x000000c2>;
            };
            pdmm1-sdi1 {
                rockchip,pins = <0x00000004 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000c3>;
            };
            pdmm1-sdi2 {
                rockchip,pins = <0x00000004 0x00000002 0x00000005 0x00000111>;
                phandle = <0x000000c4>;
            };
            pdmm1-sdi3 {
                rockchip,pins = <0x00000004 0x00000003 0x00000005 0x00000111>;
                phandle = <0x000000c5>;
            };
        };
        pmic {
            pmic_int {
                rockchip,pins = <0x00000000 0x00000003 0x00000000 0x00000113>;
                phandle = <0x00000036>;
            };
            soc_slppin_gpio {
                rockchip,pins = <0x00000000 0x00000002 0x00000000 0x00000117>;
                phandle = <0x00000039>;
            };
            soc_slppin_slp {
                rockchip,pins = <0x00000000 0x00000002 0x00000001 0x00000111>;
                phandle = <0x00000037>;
            };
            soc_slppin_rst {
                rockchip,pins = <0x00000000 0x00000002 0x00000002 0x00000111>;
                phandle = <0x000001ca>;
            };
        };
        pwm0 {
            pwm0m0-pins {
                rockchip,pins = <0x00000000 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x00000041>;
            };
        };
        pwm1 {
            pwm1m0-pins {
                rockchip,pins = <0x00000000 0x00000010 0x00000001 0x00000111>;
                phandle = <0x00000042>;
            };
        };
        pwm2 {
            pwm2m0-pins {
                rockchip,pins = <0x00000000 0x00000011 0x00000001 0x00000111>;
                phandle = <0x00000043>;
            };
        };
        pwm3 {
            pwm3-pins {
                rockchip,pins = <0x00000000 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000044>;
            };
        };
        pwm4 {
            pwm4-pins {
                rockchip,pins = <0x00000000 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000f5>;
            };
        };
        pwm5 {
            pwm5-pins {
                rockchip,pins = <0x00000000 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000f6>;
            };
        };
        pwm6 {
            pwm6-pins {
                rockchip,pins = <0x00000000 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000f7>;
            };
        };
        pwm7 {
            pwm7-pins {
                rockchip,pins = <0x00000000 0x00000016 0x00000001 0x00000111>;
                phandle = <0x000000f8>;
            };
        };
        pwm8 {
            pwm8m0-pins {
                rockchip,pins = <0x00000003 0x00000009 0x00000005 0x00000111>;
                phandle = <0x000000f9>;
            };
        };
        pwm9 {
            pwm9m0-pins {
                rockchip,pins = <0x00000003 0x0000000a 0x00000005 0x00000111>;
                phandle = <0x000000fa>;
            };
        };
        pwm10 {
            pwm10m0-pins {
                rockchip,pins = <0x00000003 0x0000000d 0x00000005 0x00000111>;
                phandle = <0x000000fb>;
            };
        };
        pwm11 {
            pwm11m0-pins {
                rockchip,pins = <0x00000003 0x0000000e 0x00000005 0x00000111>;
                phandle = <0x000000fc>;
            };
        };
        pwm12 {
            pwm12m0-pins {
                rockchip,pins = <0x00000003 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x000000fd>;
            };
        };
        pwm13 {
            pwm13m0-pins {
                rockchip,pins = <0x00000003 0x00000010 0x00000002 0x00000111>;
                phandle = <0x000000fe>;
            };
        };
        pwm14 {
            pwm14m0-pins {
                rockchip,pins = <0x00000003 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000ff>;
            };
        };
        pwm15 {
            pwm15m0-pins {
                rockchip,pins = <0x00000003 0x00000015 0x00000001 0x00000111>;
                phandle = <0x00000100>;
            };
        };
        scr {
            scr-pins {
                rockchip,pins = <0x00000001 0x00000002 0x00000003 0x00000111 0x00000001 0x00000007 0x00000003 0x00000113 0x00000001 0x00000003 0x00000003 0x00000113 0x00000001 0x00000005 0x00000003 0x00000111>;
                phandle = <0x000000c9>;
            };
        };
        sdmmc0 {
            sdmmc0-bus4 {
                rockchip,pins = <0x00000001 0x0000001d 0x00000001 0x00000112 0x00000001 0x0000001e 0x00000001 0x00000112 0x00000001 0x0000001f 0x00000001 0x00000112 0x00000002 0x00000000 0x00000001 0x00000112>;
                phandle = <0x000000ad>;
            };
            sdmmc0-clk {
                rockchip,pins = <0x00000002 0x00000002 0x00000001 0x00000112>;
                phandle = <0x000000ae>;
            };
            sdmmc0-cmd {
                rockchip,pins = <0x00000002 0x00000001 0x00000001 0x00000112>;
                phandle = <0x000000af>;
            };
            sdmmc0-det {
                rockchip,pins = <0x00000000 0x00000004 0x00000001 0x00000113>;
                phandle = <0x000000b0>;
            };
        };
        sdmmc1 {
            sdmmc1-bus4 {
                rockchip,pins = <0x00000002 0x00000003 0x00000001 0x00000112 0x00000002 0x00000004 0x00000001 0x00000112 0x00000002 0x00000005 0x00000001 0x00000112 0x00000002 0x00000006 0x00000001 0x00000112>;
                phandle = <0x000000b2>;
            };
            sdmmc1-clk {
                rockchip,pins = <0x00000002 0x00000008 0x00000001 0x00000112>;
                phandle = <0x000000b4>;
            };
            sdmmc1-cmd {
                rockchip,pins = <0x00000002 0x00000007 0x00000001 0x00000112>;
                phandle = <0x000000b3>;
            };
        };
        spdif {
            spdifm0-tx {
                rockchip,pins = <0x00000001 0x00000004 0x00000004 0x00000111>;
                phandle = <0x000000c7>;
            };
        };
        spi0 {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000111 0x00000000 0x00000015 0x00000002 0x00000111 0x00000000 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000dd>;
            };
            spi0m0-cs0 {
                rockchip,pins = <0x00000000 0x00000016 0x00000002 0x00000111>;
                phandle = <0x000000db>;
            };
            spi0m0-cs1 {
                rockchip,pins = <0x00000000 0x00000014 0x00000002 0x00000111>;
                phandle = <0x000000dc>;
            };
        };
        spi1 {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000111 0x00000002 0x0000000e 0x00000003 0x00000111 0x00000002 0x0000000f 0x00000004 0x00000111>;
                phandle = <0x000000e1>;
            };
            spi1m0-cs0 {
                rockchip,pins = <0x00000002 0x00000010 0x00000004 0x00000111>;
                phandle = <0x000000df>;
            };
            spi1m0-cs1 {
                rockchip,pins = <0x00000002 0x00000016 0x00000003 0x00000111>;
                phandle = <0x000000e0>;
            };
        };
        spi2 {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000111 0x00000002 0x00000012 0x00000004 0x00000111 0x00000002 0x00000013 0x00000004 0x00000111>;
                phandle = <0x000000e5>;
            };
            spi2m0-cs0 {
                rockchip,pins = <0x00000002 0x00000014 0x00000004 0x00000111>;
                phandle = <0x000000e3>;
            };
            spi2m0-cs1 {
                rockchip,pins = <0x00000002 0x00000015 0x00000004 0x00000111>;
                phandle = <0x000000e4>;
            };
        };
        spi3 {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000111 0x00000004 0x00000008 0x00000004 0x00000111 0x00000004 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000e9>;
            };
            spi3m0-cs0 {
                rockchip,pins = <0x00000004 0x00000006 0x00000004 0x00000111>;
                phandle = <0x000000e7>;
            };
            spi3m0-cs1 {
                rockchip,pins = <0x00000004 0x00000007 0x00000004 0x00000111>;
                phandle = <0x000000e8>;
            };
        };
        tsadc {
            tsadc-shutorg {
                rockchip,pins = <0x00000000 0x00000001 0x00000002 0x00000111>;
                phandle = <0x00000102>;
            };
        };
        uart0 {
            uart0-xfer {
                rockchip,pins = <0x00000000 0x00000010 0x00000003 0x00000113 0x00000000 0x00000011 0x00000003 0x00000113>;
                phandle = <0x00000040>;
            };
        };
        uart1 {
            uart1m0-xfer {
                rockchip,pins = <0x00000002 0x0000000b 0x00000002 0x00000113 0x00000002 0x0000000c 0x00000002 0x00000113>;
                phandle = <0x000000eb>;
            };
            uart1m0-ctsn {
                rockchip,pins = <0x00000002 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000ec>;
            };
            uart1m0-rtsn {
                rockchip,pins = <0x00000002 0x0000000d 0x00000002 0x00000111>;
                phandle = <0x00000130>;
            };
        };
        uart2 {
            uart2m0-xfer {
                rockchip,pins = <0x00000000 0x00000018 0x00000001 0x00000113 0x00000000 0x00000019 0x00000001 0x00000113>;
                phandle = <0x000000ed>;
            };
        };
        uart3 {
            uart3m0-xfer {
                rockchip,pins = <0x00000001 0x00000000 0x00000002 0x00000113 0x00000001 0x00000001 0x00000002 0x00000113>;
                phandle = <0x000000ee>;
            };
        };
        uart4 {
            uart4m0-xfer {
                rockchip,pins = <0x00000001 0x00000004 0x00000002 0x00000113 0x00000001 0x00000006 0x00000002 0x00000113>;
                phandle = <0x000000ef>;
            };
        };
        uart5 {
            uart5m0-xfer {
                rockchip,pins = <0x00000002 0x00000001 0x00000003 0x00000113 0x00000002 0x00000002 0x00000003 0x00000113>;
                phandle = <0x000000f0>;
            };
        };
        uart6 {
            uart6m0-xfer {
                rockchip,pins = <0x00000002 0x00000003 0x00000003 0x00000113 0x00000002 0x00000004 0x00000003 0x00000113>;
                phandle = <0x000000f1>;
            };
        };
        uart7 {
            uart7m0-xfer {
                rockchip,pins = <0x00000002 0x00000005 0x00000003 0x00000113 0x00000002 0x00000006 0x00000003 0x00000113>;
                phandle = <0x000000f2>;
            };
        };
        uart8 {
            uart8m0-xfer {
                rockchip,pins = <0x00000002 0x00000016 0x00000002 0x00000113 0x00000002 0x00000015 0x00000003 0x00000113>;
                phandle = <0x000000f3>;
            };
        };
        uart9 {
            uart9m0-xfer {
                rockchip,pins = <0x00000002 0x00000007 0x00000003 0x00000113 0x00000002 0x00000008 0x00000003 0x00000113>;
                phandle = <0x000000f4>;
            };
        };
        spi0-hs {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000118 0x00000000 0x00000015 0x00000002 0x00000118 0x00000000 0x0000000e 0x00000002 0x00000118>;
                phandle = <0x000000de>;
            };
        };
        spi1-hs {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000118 0x00000002 0x0000000e 0x00000003 0x00000118 0x00000002 0x0000000f 0x00000004 0x00000118>;
                phandle = <0x000000e2>;
            };
        };
        spi2-hs {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000118 0x00000002 0x00000012 0x00000004 0x00000118 0x00000002 0x00000013 0x00000004 0x00000118>;
                phandle = <0x000000e6>;
            };
        };
        spi3-hs {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000118 0x00000004 0x00000008 0x00000004 0x00000118 0x00000004 0x0000000a 0x00000004 0x00000118>;
                phandle = <0x000000ea>;
            };
        };
        gmac-txd-level3 {
            gmac1m0-tx-bus2-level3 {
                rockchip,pins = <0x00000003 0x0000000d 0x00000003 0x00000119 0x00000003 0x0000000e 0x00000003 0x00000119 0x00000003 0x0000000f 0x00000003 0x00000111>;
                phandle = <0x0000007d>;
            };
            gmac1m0-rgmii-bus-level3 {
                rockchip,pins = <0x00000003 0x00000004 0x00000003 0x00000111 0x00000003 0x00000005 0x00000003 0x00000111 0x00000003 0x00000002 0x00000003 0x00000119 0x00000003 0x00000003 0x00000003 0x00000119>;
                phandle = <0x00000080>;
            };
        };
        gmac-txc-level2 {
            gmac1m0-rgmii-clk-level2 {
                rockchip,pins = <0x00000003 0x00000007 0x00000003 0x00000111 0x00000003 0x00000006 0x00000003 0x00000114>;
                phandle = <0x0000007f>;
            };
        };
        gpio-func {
            tsadc-gpio-func {
                rockchip,pins = <0x00000000 0x00000001 0x00000000 0x00000111>;
                phandle = <0x00000101>;
            };
        };
        mxc6655xa {
            mxc6655xa_irq_gpio {
                rockchip,pins = <0x00000003 0x00000011 0x00000000 0x00000111>;
                phandle = <0x000000da>;
            };
        };
        touch {
            touch-gpio {
                rockchip,pins = <0x00000000 0x0000000d 0x00000000 0x00000113 0x00000000 0x0000000e 0x00000000 0x00000111>;
                phandle = <0x000000ce>;
            };
        };
        sdio-pwrseq {
            wifi-enable-h {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x0000012d>;
            };
        };
        usb {
            vcc5v0-host-en {
                rockchip,pins = <0x00000000 0x00000006 0x00000000 0x00000111>;
                phandle = <0x0000012a>;
            };
            vcc5v0-otg-en {
                rockchip,pins = <0x00000000 0x00000005 0x00000000 0x00000111>;
                phandle = <0x0000012b>;
            };
        };
        wireless-bluetooth {
            uart8-gpios {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x000001cb>;
            };
            uart1-gpios {
                rockchip,pins = <0x00000002 0x0000000d 0x00000000 0x00000111>;
                phandle = <0x00000131>;
            };
        };
        headphone {
            hp-det {
                rockchip,pins = <0x00000004 0x0000000b 0x00000000 0x0000011a>;
                phandle = <0x00000132>;
            };
        };
        lcd0 {
            lcd-rst-gpio {
                rockchip,pins = <0x00000001 0x00000005 0x00000000 0x00000111>;
                phandle = <0x00000094>;
            };
        };
        lcd1 {
            lcd1-rst-gpio {
                rockchip,pins = <0x00000004 0x00000016 0x00000000 0x00000111>;
                phandle = <0x0000009d>;
            };
        };
        wireless-wlan {
            wifi-host-wake-irq {
                rockchip,pins = <0x00000002 0x0000000a 0x00000000 0x0000011a>;
                phandle = <0x0000012f>;
            };
        };
        fddis_ctr {
            dis-ctl {
                rockchip,pins = <0x00000000 0x0000000b 0x00000000 0x00000113 0x00000000 0x0000000c 0x00000000 0x00000113>;
                phandle = <0x0000010f>;
            };
        };
    };
    adc-keys {
        compatible = "adc-keys";
        io-channels = <0x0000011b 0x00000000>;
        io-channel-names = "buttons";
        keyup-threshold-microvolt = <0x001b7740>;
        poll-interval = <0x00000064>;
        phandle = <0x000001cc>;
        vol-up-key {
            label = "volume up";
            linux,code = <0x00000073>;
            press-threshold-microvolt = <0x000006d6>;
        };
        vol-down-key {
            label = "volume down";
            linux,code = <0x00000072>;
            press-threshold-microvolt = <0x00048a1c>;
        };
        menu-key {
            label = "menu";
            linux,code = <0x0000008b>;
            press-threshold-microvolt = <0x000ef420>;
        };
        back-key {
            label = "back";
            linux,code = <0x0000009e>;
            press-threshold-microvolt = <0x0013eb9c>;
        };
    };
    audiopwmout-diff {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,audiopwmout-diff";
        simple-audio-card,mclk-fs = <0x00000100>;
        simple-audio-card,bitclock-master = <0x0000011c>;
        simple-audio-card,frame-master = <0x0000011c>;
        phandle = <0x000001cd>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x0000011e>;
            phandle = <0x0000011c>;
        };
    };
    backlight {
        compatible = "pwm-backlight";
        pwms = <0x0000011f 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x00000091>;
    };
    backlight1 {
        compatible = "pwm-backlight";
        pwms = <0x00000120 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x0000009a>;
    };
    dc-12v {
        compatible = "regulator-fixed";
        regulator-name = "dc_12v";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00b71b00>;
        regulator-max-microvolt = <0x00b71b00>;
        phandle = <0x00000129>;
    };
    hdmi-sound {
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <0x00000080>;
        simple-audio-card,name = "rockchip,hdmi";
        status = "okay";
        phandle = <0x000001ce>;
        simple-audio-card,cpu {
            sound-dai = <0x00000121>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000122>;
        };
    };
    dummy-codec {
        status = "disabled";
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000124>;
    };
    pdm-mic-array {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,name = "rockchip,pdm-mic-array";
        phandle = <0x000001cf>;
        simple-audio-card,cpu {
            sound-dai = <0x00000123>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000124>;
        };
    };
    rk809-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,rk809-codec";
        simple-audio-card,mclk-fs = <0x00000100>;
        phandle = <0x000001d0>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000125>;
        };
    };
    spdif-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,name = "ROCKCHIP,SPDIF";
        simple-audio-card,cpu {
            sound-dai = <0x00000126>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000127>;
        };
    };
    spdif-out {
        status = "okay";
        compatible = "linux,spdif-dit";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000127>;
    };
    vad-sound {
        status = "disabled";
        compatible = "rockchip,multicodecs-card";
        rockchip,card-name = "rockchip,rk3568-vad";
        rockchip,cpu = <0x000000c6>;
        rockchip,codec = <0x00000125 0x00000128>;
        phandle = <0x000001d1>;
    };
    vcc3v3-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00325aa0>;
        regulator-max-microvolt = <0x00325aa0>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003c>;
    };
    vcc5v0-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003e>;
    };
    vcc5v0-host-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000006 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012a>;
        regulator-name = "vcc5v0_host";
        regulator-always-on;
        phandle = <0x0000010c>;
    };
    vcc5v0-otg-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000005 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012b>;
        regulator-name = "vcc5v0_otg";
        phandle = <0x0000010d>;
    };
    vcc3v3-lcd0-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd0_n";
        regulator-boot-on;
        gpio = <0x00000035 0x00000010 0x00000000>;
        enable-active-high;
        phandle = <0x00000092>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    vcc3v3-lcd1-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd1_n";
        regulator-boot-on;
        phandle = <0x0000009b>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    sdio-pwrseq {
        compatible = "mmc-pwrseq-simple";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012d>;
        post-power-on-delay-ms = <0x000000c8>;
        reset-gpios = <0x0000012e 0x00000009 0x00000001>;
        phandle = <0x000000b1>;
    };
    wireless-wlan {
        compatible = "wlan-platdata";
        rockchip,grf = <0x00000032>;
        wifi_chip_type = "ap6398s";
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012f>;
        WIFI,host_wake_irq = <0x0000012e 0x0000000a 0x00000000>;
        phandle = <0x000001d2>;
    };
    wireless-bluetooth {
        compatible = "bluetooth-platdata";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        uart_rts_gpios = <0x0000012e 0x0000000d 0x00000001>;
        pinctrl-names = "default", "rts_gpio";
        pinctrl-0 = <0x00000130>;
        pinctrl-1 = <0x00000131>;
        BT,reset_gpio = <0x0000012e 0x0000000f 0x00000000>;
        BT,wake_gpio = <0x0000012e 0x00000011 0x00000000>;
        BT,wake_host_irq = <0x0000012e 0x00000010 0x00000000>;
        status = "okay";
        phandle = <0x000001d3>;
    };
    test-power {
        status = "okay";
    };
    rk-headset {
        compatible = "rockchip_headset";
        headset_gpio = <0x0000009c 0x0000000b 0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000132>;
        phandle = <0x000001d4>;
    };
    vcc3v3-vga {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_vga";
        regulator-always-on;
        regulator-boot-on;
        gpio = <0x0000009c 0x0000000a 0x00000000>;
        enable-active-high;
        vin-supply = <0x0000003c>;
        phandle = <0x000001d5>;
    };
    vcc-camera-regulator {
        compatible = "regulator-fixed";
        gpio = <0x00000035 0x00000011 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000133>;
        regulator-name = "vcc_camera";
        enable-active-high;
        regulator-always-on;
        regulator-boot-on;
        phandle = <0x000001d6>;
    };
    chosen {
        bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0";
        phandle = <0x000001d7>;
    };
    fiq-debugger {
        compatible = "rockchip,fiq-debugger";
        rockchip,serial-id = <0x00000002>;
        rockchip,wake-irq = <0x00000000>;
        rockchip,irq-mode-enable = <0x00000001>;
        rockchip,baudrate = <0x0016e360>;
        interrupts = <0x00000000 0x000000fc 0x00000008>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ed>;
        status = "okay";
    };
    debug@fd904000 {
        compatible = "rockchip,debug";
        reg = <0x00000000 0xfd904000 0x00000000 0x00001000 0x00000000 0xfd905000 0x00000000 0x00001000 0x00000000 0xfd906000 0x00000000 0x00001000 0x00000000 0xfd907000 0x00000000 0x00001000>;
        phandle = <0x000001d8>;
    };
    cspmu@fd90c000 {
        compatible = "rockchip,cspmu";
        reg = <0x00000000 0xfd90c000 0x00000000 0x00001000 0x00000000 0xfd90d000 0x00000000 0x00001000 0x00000000 0xfd90e000 0x00000000 0x00001000 0x00000000 0xfd90f000 0x00000000 0x00001000>;
        phandle = <0x000001d9>;
    };
    leds {
        compatible = "gpio-leds";
        power-green {
            gpios = <0x00000035 0x0000001b 0x00000001>;
            linux,default-trigger = "none";
            default-state = "off";
        };
        power-red {
            gpios = <0x00000035 0x0000001c 0x00000000>;
            linux,default-trigger = "none";
            default-state = "off";
        };
    };
    fddis_dev {
        compatible = "fddis_dev";
        fddis_gpio_clk = <0x00000035 0x0000000b 0x00000000>;
        fddis_gpio_dat = <0x00000035 0x0000000c 0x00000000>;
        status = "okay";
    };
    resume_reboot {
        compatible = "resume_reboot";
        status = "okay";
    };
    __symbols__ {
        ddr_timing = "/ddr_timing";
        cpu0 = "/cpus/cpu@0";
        cpu1 = "/cpus/cpu@100";
        cpu2 = "/cpus/cpu@200";
        cpu3 = "/cpus/cpu@300";
        CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
        cpu0_opp_table = "/cpu0-opp-table";
        display_subsystem = "/display-subsystem";
        route_dsi0 = "/display-subsystem/route/route-dsi0";
        route_dsi1 = "/display-subsystem/route/route-dsi1";
        route_edp = "/display-subsystem/route/route-edp";
        route_hdmi = "/display-subsystem/route/route-hdmi";
        route_lvds = "/display-subsystem/route/route-lvds";
        route_rgb = "/display-subsystem/route/route-rgb";
        optee = "/firmware/optee";
        scmi = "/firmware/scmi";
        scmi_clk = "/firmware/scmi/protocol@14";
        sdei = "/firmware/sdei";
        mpp_srv = "/mpp-srv";
        reserved_memory = "/reserved-memory";
        drm_logo = "/reserved-memory/drm-logo@00000000";
        drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000";
        ramoops = "/reserved-memory/ramoops@110000";
        rockchip_suspend = "/rockchip-suspend";
        rockchip_system_monitor = "/rockchip-system-monitor";
        thermal_zones = "/thermal-zones";
        soc_thermal = "/thermal-zones/soc-thermal";
        threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
        target = "/thermal-zones/soc-thermal/trips/trip-point-1";
        soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
        gpu_thermal = "/thermal-zones/gpu-thermal";
        gmac1_clkin = "/external-gmac1-clock";
        gmac1_xpcsclk = "/xpcs-gmac1-clock";
        i2s1_mclkin_rx = "/i2s1-mclkin-rx";
        i2s1_mclkin_tx = "/i2s1-mclkin-tx";
        i2s2_mclkin = "/i2s2-mclkin";
        i2s3_mclkin = "/i2s3-mclkin";
        mpll = "/mpll";
        xin24m = "/xin24m";
        xin32k = "/xin32k";
        scmi_shmem = "/scmi-shmem@10f000";
        sata1 = "/sata@fc400000";
        sata2 = "/sata@fc800000";
        usbdrd30 = "/usbdrd";
        usbdrd_dwc3 = "/usbdrd/dwc3@fcc00000";
        usbhost30 = "/usbhost";
        usbhost_dwc3 = "/usbhost/dwc3@fd000000";
        gic = "/interrupt-controller@fd400000";
        its = "/interrupt-controller@fd400000/interrupt-controller@fd440000";
        usb_host0_ehci = "/usb@fd800000";
        usb_host0_ohci = "/usb@fd840000";
        usb_host1_ehci = "/usb@fd880000";
        usb_host1_ohci = "/usb@fd8c0000";
        xpcs = "/syscon@fda00000";
        pmugrf = "/syscon@fdc20000";
        pmu_io_domains = "/syscon@fdc20000/io-domains";
        reboot_mode = "/syscon@fdc20000/reboot-mode";
        pipegrf = "/syscon@fdc50000";
        grf = "/syscon@fdc60000";
        io_domains = "/syscon@fdc60000/io-domains";
        lvds = "/syscon@fdc60000/lvds";
        lvds_in_vp1 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@1";
        lvds_in_vp2 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@2";
        rgb = "/syscon@fdc60000/rgb";
        rgb_in_vp2 = "/syscon@fdc60000/rgb/ports/port@0/endpoint@2";
        pipe_phy_grf0 = "/syscon@fdc70000";
        pipe_phy_grf1 = "/syscon@fdc80000";
        pipe_phy_grf2 = "/syscon@fdc90000";
        usb2phy0_grf = "/syscon@fdca0000";
        usb2phy1_grf = "/syscon@fdca8000";
        edp_phy = "/edp-phy@fdcb0000";
        sram = "/sram@fdcc0000";
        rkvdec_sram = "/sram@fdcc0000/rkvdec-sram@0";
        pmucru = "/clock-controller@fdd00000";
        cru = "/clock-controller@fdd20000";
        i2c0 = "/i2c@fdd40000";
        rk809 = "/i2c@fdd40000/pmic@20";
        pinctrl_rk8xx = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx";
        rk817_slppin_null = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_null";
        rk817_slppin_slp = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_slp";
        rk817_slppin_pwrdn = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_pwrdn";
        rk817_slppin_rst = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_rst";
        vdd_logic = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG1";
        vdd_gpu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG2";
        vcc_ddr = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG3";
        vdd_npu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG4";
        vdda0v9_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG1";
        vdda_0v9 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG2";
        vdda0v9_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG3";
        vccio_acodec = "/i2c@fdd40000/pmic@20/regulators/LDO_REG4";
        vccio_sd = "/i2c@fdd40000/pmic@20/regulators/LDO_REG5";
        vcc3v3_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG6";
        vcca_1v8 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG7";
        vcca1v8_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG8";
        vcca1v8_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG9";
        vcc_1v8 = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG5";
        vcc_3v3 = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG1";
        vcc3v3_sd = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG2";
        rk809_codec = "/i2c@fdd40000/pmic@20/codec";
        vdd_cpu = "/i2c@fdd40000/sti8070@40";
        uart0 = "/serial@fdd50000";
        pwm0 = "/pwm@fdd70000";
        pwm1 = "/pwm@fdd70010";
        pwm2 = "/pwm@fdd70020";
        pwm3 = "/pwm@fdd70030";
        pmu = "/power-management@fdd90000";
        power = "/power-management@fdd90000/power-controller";
        rknpu = "/npu@fde40000";
        npu_opp_table = "/npu-opp-table";
        bus_npu = "/bus-npu";
        bus_npu_opp_table = "/bus-npu-opp-table";
        rknpu_mmu = "/iommu@fde4b000";
        gpu = "/gpu@fde60000";
        gpu_power_model = "/gpu@fde60000/power-model";
        gpu_opp_table = "/opp-table2";
        vdpu = "/vdpu@fdea0400";
        vdpu_mmu = "/iommu@fdea0800";
        rk_rga = "/rk_rga@fdeb0000";
        ebc = "/ebc@fdec0000";
        jpegd = "/jpegd@fded0000";
        jpegd_mmu = "/iommu@fded0480";
        vepu = "/vepu@fdee0000";
        vepu_mmu = "/iommu@fdee0800";
        iep = "/iep@fdef0000";
        iep_mmu = "/iommu@fdef0800";
        eink = "/eink@fdf00000";
        rkvenc = "/rkvenc@fdf40000";
        rkvenc_opp_table = "/rkvenc-opp-table";
        rkvenc_mmu = "/iommu@fdf40f00";
        rkvdec = "/rkvdec@fdf80200";
        rkvdec_mmu = "/iommu@fdf80800";
        mipi_csi2 = "/mipi-csi2@fdfb0000";
        rkcif = "/rkcif@fdfe0000";
        rkcif_mmu = "/iommu@fdfe0800";
        rkcif_dvp = "/rkcif_dvp";
        dvp_in_bcam = "/rkcif_dvp/port/endpoint";
        rkcif_dvp_sditf = "/rkcif_dvp_sditf";
        rkcif_mipi_lvds = "/rkcif_mipi_lvds";
        rkcif_mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf";
        rkisp = "/rkisp@fdff0000";
        rkisp_mmu = "/iommu@fdff1a00";
        rkisp_vir0 = "/rkisp-vir0";
        isp0_in = "/rkisp-vir0/port/endpoint@0";
        rkisp_vir1 = "/rkisp-vir1";
        gmac1 = "/ethernet@fe010000";
        mdio1 = "/ethernet@fe010000/mdio";
        rgmii_phy1 = "/ethernet@fe010000/mdio/phy@0";
        gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config";
        gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config";
        gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config";
        vop = "/vop@fe040000";
        vop_out = "/vop@fe040000/ports";
        vp0 = "/vop@fe040000/ports/port@0";
        vp0_out_dsi0 = "/vop@fe040000/ports/port@0/endpoint@0";
        vp0_out_dsi1 = "/vop@fe040000/ports/port@0/endpoint@1";
        vp0_out_edp = "/vop@fe040000/ports/port@0/endpoint@2";
        vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@3";
        vp1 = "/vop@fe040000/ports/port@1";
        vp1_out_dsi0 = "/vop@fe040000/ports/port@1/endpoint@0";
        vp1_out_dsi1 = "/vop@fe040000/ports/port@1/endpoint@1";
        vp1_out_edp = "/vop@fe040000/ports/port@1/endpoint@2";
        vp1_out_hdmi = "/vop@fe040000/ports/port@1/endpoint@3";
        vp1_out_lvds = "/vop@fe040000/ports/port@1/endpoint@4";
        vp2 = "/vop@fe040000/ports/port@2";
        vp2_out_lvds = "/vop@fe040000/ports/port@2/endpoint@0";
        vp2_out_rgb = "/vop@fe040000/ports/port@2/endpoint@1";
        vop_mmu = "/iommu@fe043e00";
        dsi0 = "/dsi@fe060000";
        dsi0_in = "/dsi@fe060000/ports/port@0";
        dsi0_in_vp0 = "/dsi@fe060000/ports/port@0/endpoint@0";
        dsi0_in_vp1 = "/dsi@fe060000/ports/port@0/endpoint@1";
        dsi_out_panel = "/dsi@fe060000/ports/port@1/endpoint";
        dsi0_panel = "/dsi@fe060000/panel@0";
        disp_timings0 = "/dsi@fe060000/panel@0/display-timings";
        dsi0_timing0 = "/dsi@fe060000/panel@0/display-timings/timing0";
        panel_in_dsi = "/dsi@fe060000/panel@0/ports/port@0/endpoint";
        dsi1 = "/dsi@fe070000";
        dsi1_in = "/dsi@fe070000/ports/port@0";
        dsi1_in_vp0 = "/dsi@fe070000/ports/port@0/endpoint@0";
        dsi1_in_vp1 = "/dsi@fe070000/ports/port@0/endpoint@1";
        dsi1_out_panel = "/dsi@fe070000/ports/port@1/endpoint";
        dsi1_panel = "/dsi@fe070000/panel@0";
        disp_timings1 = "/dsi@fe070000/panel@0/display-timings";
        dsi1_timing0 = "/dsi@fe070000/panel@0/display-timings/timing0";
        panel_in_dsi1 = "/dsi@fe070000/panel@0/ports/port@0/endpoint";
        hdmi = "/hdmi@fe0a0000";
        hdmi_in = "/hdmi@fe0a0000/ports/port";
        hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port/endpoint@0";
        hdmi_in_vp1 = "/hdmi@fe0a0000/ports/port/endpoint@1";
        edp = "/edp@fe0c0000";
        edp_in = "/edp@fe0c0000/ports/port@0";
        edp_in_vp0 = "/edp@fe0c0000/ports/port@0/endpoint@0";
        edp_in_vp1 = "/edp@fe0c0000/ports/port@0/endpoint@1";
        qos_gpu = "/qos@fe128000";
        qos_rkvenc_rd_m0 = "/qos@fe138080";
        qos_rkvenc_rd_m1 = "/qos@fe138100";
        qos_rkvenc_wr_m0 = "/qos@fe138180";
        qos_isp = "/qos@fe148000";
        qos_vicap0 = "/qos@fe148080";
        qos_vicap1 = "/qos@fe148100";
        qos_vpu = "/qos@fe150000";
        qos_ebc = "/qos@fe158000";
        qos_iep = "/qos@fe158100";
        qos_jpeg_dec = "/qos@fe158180";
        qos_jpeg_enc = "/qos@fe158200";
        qos_rga_rd = "/qos@fe158280";
        qos_rga_wr = "/qos@fe158300";
        qos_npu = "/qos@fe180000";
        qos_pcie2x1 = "/qos@fe190000";
        qos_sata1 = "/qos@fe190280";
        qos_sata2 = "/qos@fe190300";
        qos_usb3_0 = "/qos@fe190380";
        qos_usb3_1 = "/qos@fe190400";
        qos_rkvdec = "/qos@fe198000";
        qos_hdcp = "/qos@fe1a8000";
        qos_vop_m0 = "/qos@fe1a8080";
        qos_vop_m1 = "/qos@fe1a8100";
        sdmmc2 = "/dwmmc@fe000000";
        dfi = "/dfi@fe230000";
        dmc = "/dmc";
        dmc_opp_table = "/dmc-opp-table";
        pcie2x1 = "/pcie@fe260000";
        pcie2x1_intc = "/pcie@fe260000/legacy-interrupt-controller";
        sdmmc0 = "/dwmmc@fe2b0000";
        sdmmc1 = "/dwmmc@fe2c0000";
        sfc = "/sfc@fe300000";
        sdhci = "/sdhci@fe310000";
        nandc0 = "/nandc@fe330000";
        crypto = "/crypto@fe380000";
        rng = "/rng@fe388000";
        otp = "/otp@fe38c000";
        cpu_code = "/otp@fe38c000/cpu-code@2";
        otp_cpu_version = "/otp@fe38c000/cpu-version@8";
        mbist_vmin = "/otp@fe38c000/mbist-vmin@9";
        otp_id = "/otp@fe38c000/id@a";
        cpu_leakage = "/otp@fe38c000/cpu-leakage@1a";
        log_leakage = "/otp@fe38c000/log-leakage@1b";
        npu_leakage = "/otp@fe38c000/npu-leakage@1c";
        gpu_leakage = "/otp@fe38c000/gpu-leakage@1d";
        core_pvtm = "/otp@fe38c000/core-pvtm@2a";
        i2s0_8ch = "/i2s@fe400000";
        i2s1_8ch = "/i2s@fe410000";
        i2s2_2ch = "/i2s@fe420000";
        i2s3_2ch = "/i2s@fe430000";
        pdm = "/pdm@fe440000";
        vad = "/vad@fe450000";
        spdif_8ch = "/spdif@fe460000";
        audpwm = "/audpwm@fe470000";
        dig_acodec = "/codec-digital@fe478000";
        dmac0 = "/dmac@fe530000";
        dmac1 = "/dmac@fe550000";
        scr = "/rkscr@fe560000";
        can0 = "/can@fe570000";
        can1 = "/can@fe580000";
        can2 = "/can@fe590000";
        i2c1 = "/i2c@fe5a0000";
        gt1x = "/i2c@fe5a0000/gt1x@14";
        i2c2 = "/i2c@fe5b0000";
        gc2145 = "/i2c@fe5b0000/gc2145@3c";
        gc2145_out = "/i2c@fe5b0000/gc2145@3c/port/endpoint";
        ov5695 = "/i2c@fe5b0000/ov5695@36";
        ov5695_out = "/i2c@fe5b0000/ov5695@36/port/endpoint";
        gc8034 = "/i2c@fe5b0000/gc8034@37";
        gc8034_out = "/i2c@fe5b0000/gc8034@37/port/endpoint";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mxc6655xa = "/i2c@fe5e0000/mxc6655xa@15";
        rktimer = "/timer@fe5f0000";
        wdt = "/watchdog@fe600000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
        uart1 = "/serial@fe650000";
        uart2 = "/serial@fe660000";
        uart3 = "/serial@fe670000";
        uart4 = "/serial@fe680000";
        uart5 = "/serial@fe690000";
        uart6 = "/serial@fe6a0000";
        uart7 = "/serial@fe6b0000";
        uart8 = "/serial@fe6c0000";
        uart9 = "/serial@fe6d0000";
        pwm4 = "/pwm@fe6e0000";
        pwm5 = "/pwm@fe6e0010";
        pwm6 = "/pwm@fe6e0020";
        pwm7 = "/pwm@fe6e0030";
        pwm8 = "/pwm@fe6f0000";
        pwm9 = "/pwm@fe6f0010";
        pwm10 = "/pwm@fe6f0020";
        pwm11 = "/pwm@fe6f0030";
        pwm12 = "/pwm@fe700000";
        pwm13 = "/pwm@fe700010";
        pwm14 = "/pwm@fe700020";
        pwm15 = "/pwm@fe700030";
        tsadc = "/tsadc@fe710000";
        saradc = "/saradc@fe720000";
        mailbox = "/mailbox@fe780000";
        combphy1_usq = "/phy@fe830000";
        combphy2_psq = "/phy@fe840000";
        mipi_dphy0 = "/mipi-dphy@fe850000";
        video_phy0 = "/video-phy@fe850000";
        mipi_dphy1 = "/mipi-dphy@fe860000";
        csi2_dphy_hw = "/csi2-dphy-hw@fe870000";
        csi2_dphy0 = "/csi2-dphy0";
        mipi_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1";
        mipi_in_ucam1 = "/csi2-dphy0/ports/port@0/endpoint@2";
        csidphy_out = "/csi2-dphy0/ports/port@1/endpoint@0";
        csi2_dphy1 = "/csi2-dphy1";
        csi2_dphy2 = "/csi2-dphy2";
        usb2phy0 = "/usb2-phy@fe8a0000";
        u2phy0_host = "/usb2-phy@fe8a0000/host-port";
        u2phy0_otg = "/usb2-phy@fe8a0000/otg-port";
        usb2phy1 = "/usb2-phy@fe8b0000";
        u2phy1_host = "/usb2-phy@fe8b0000/host-port";
        u2phy1_otg = "/usb2-phy@fe8b0000/otg-port";
        pinctrl = "/pinctrl";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        pcfg_pull_up = "/pinctrl/pcfg-pull-up";
        pcfg_pull_down = "/pinctrl/pcfg-pull-down";
        pcfg_pull_none = "/pinctrl/pcfg-pull-none";
        pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
        pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
        pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
        pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
        pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
        pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
        pcfg_output_low = "/pinctrl/pcfg-output-low";
        acodec_pins = "/pinctrl/acodec/acodec-pins";
        cam_clkout0 = "/pinctrl/cam/cam-clkout0";
        camera_pwr = "/pinctrl/cam/camera-pwr";
        can0m1_pins = "/pinctrl/can0/can0m1-pins";
        can1m1_pins = "/pinctrl/can1/can1m1-pins";
        can2m1_pins = "/pinctrl/can2/can2m1-pins";
        cif_clk = "/pinctrl/cif/cif-clk";
        cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
        cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
        clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
        ebc_pins = "/pinctrl/ebc/ebc-pins";
        gmac1m0_miim = "/pinctrl/gmac1/gmac1m0-miim";
        gmac1m0_rx_bus2 = "/pinctrl/gmac1/gmac1m0-rx-bus2";
        hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec";
        hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl";
        hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda";
        i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
        i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
        i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer";
        i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
        i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
        i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
        i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx";
        i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx";
        i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
        i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
        i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx";
        i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx";
        i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi";
        i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo";
        i2s3m1_lrck = "/pinctrl/i2s3/i2s3m1-lrck";
        i2s3m1_mclk = "/pinctrl/i2s3/i2s3m1-mclk";
        i2s3m1_sclk = "/pinctrl/i2s3/i2s3m1-sclk";
        i2s3m1_sdi = "/pinctrl/i2s3/i2s3m1-sdi";
        i2s3m1_sdo = "/pinctrl/i2s3/i2s3m1-sdo";
        lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl";
        pdmm1_clk1 = "/pinctrl/pdm/pdmm1-clk1";
        pdmm1_sdi1 = "/pinctrl/pdm/pdmm1-sdi1";
        pdmm1_sdi2 = "/pinctrl/pdm/pdmm1-sdi2";
        pdmm1_sdi3 = "/pinctrl/pdm/pdmm1-sdi3";
        pmic_int = "/pinctrl/pmic/pmic_int";
        soc_slppin_gpio = "/pinctrl/pmic/soc_slppin_gpio";
        soc_slppin_slp = "/pinctrl/pmic/soc_slppin_slp";
        soc_slppin_rst = "/pinctrl/pmic/soc_slppin_rst";
        pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
        pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
        pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
        pwm3_pins = "/pinctrl/pwm3/pwm3-pins";
        pwm4_pins = "/pinctrl/pwm4/pwm4-pins";
        pwm5_pins = "/pinctrl/pwm5/pwm5-pins";
        pwm6_pins = "/pinctrl/pwm6/pwm6-pins";
        pwm7_pins = "/pinctrl/pwm7/pwm7-pins";
        pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
        pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
        pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
        pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
        pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
        pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
        pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
        pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
        scr_pins = "/pinctrl/scr/scr-pins";
        sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4";
        sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk";
        sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd";
        sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det";
        sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4";
        sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk";
        sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd";
        spdifm0_tx = "/pinctrl/spdif/spdifm0-tx";
        spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
        spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
        spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
        spi1m0_pins = "/pinctrl/spi1/spi1m0-pins";
        spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0";
        spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1";
        spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
        spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
        spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
        spi3m0_pins = "/pinctrl/spi3/spi3m0-pins";
        spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0";
        spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1";
        tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg";
        uart0_xfer = "/pinctrl/uart0/uart0-xfer";
        uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer";
        uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn";
        uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn";
        uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
        uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
        uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
        uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
        uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer";
        uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer";
        uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
        uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer";
        spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins";
        spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins";
        spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins";
        spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins";
        gmac1m0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-tx-bus2-level3";
        gmac1m0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-rgmii-bus-level3";
        gmac1m0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m0-rgmii-clk-level2";
        tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func";
        mxc6655xa_irq_gpio = "/pinctrl/mxc6655xa/mxc6655xa_irq_gpio";
        touch_gpio = "/pinctrl/touch/touch-gpio";
        wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h";
        vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en";
        vcc5v0_otg_en = "/pinctrl/usb/vcc5v0-otg-en";
        uart8_gpios = "/pinctrl/wireless-bluetooth/uart8-gpios";
        uart1_gpios = "/pinctrl/wireless-bluetooth/uart1-gpios";
        hp_det = "/pinctrl/headphone/hp-det";
        lcd0_rst_gpio = "/pinctrl/lcd0/lcd-rst-gpio";
        lcd1_rst_gpio = "/pinctrl/lcd1/lcd1-rst-gpio";
        wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq";
        dis_ctl = "/pinctrl/fddis_ctr/dis-ctl";
        adc_keys = "/adc-keys";
        audiopwmout_diff = "/audiopwmout-diff";
        master = "/audiopwmout-diff/simple-audio-card,codec";
        backlight = "/backlight";
        backlight1 = "/backlight1";
        dc_12v = "/dc-12v";
        hdmi_sound = "/hdmi-sound";
        pdmics = "/dummy-codec";
        pdm_mic_array = "/pdm-mic-array";
        rk809_sound = "/rk809-sound";
        spdif_out = "/spdif-out";
        vad_sound = "/vad-sound";
        vcc3v3_sys = "/vcc3v3-sys";
        vcc5v0_sys = "/vcc5v0-sys";
        vcc5v0_host = "/vcc5v0-host-regulator";
        vcc5v0_otg = "/vcc5v0-otg-regulator";
        vcc3v3_lcd0_n = "/vcc3v3-lcd0-n";
        vcc3v3_lcd1_n = "/vcc3v3-lcd1-n";
        sdio_pwrseq = "/sdio-pwrseq";
        wireless_wlan = "/wireless-wlan";
        wireless_bluetooth = "/wireless-bluetooth";
        rk_headset = "/rk-headset";
        vcc3v3_vga = "/vcc3v3-vga";
        vcc_camera = "/vcc-camera-regulator";
        chosen = "/chosen";
        debug = "/debug@fd904000";
        cspmu = "/cspmu@fd90c000";
    };
};
 



BOARD_TYPE_2.dts

Quote

/dts-v1/;
// magic:        0xd00dfeed
// totalsize:        0x1eb83 (125827)
// off_dt_struct:    0x38
// off_dt_strings:    0x1bc68
// off_mem_rsvmap:    0x28
// version:        17
// last_comp_version:    16
// boot_cpuid_phys:    0x0
// size_dt_strings:    0x2f1b
// size_dt_struct:    0x1bc30

/ {
    compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566";
    interrupt-parent = <0x00000001>;
    #address-cells = <0x00000002>;
    #size-cells = <0x00000002>;
    model = "Rockchip RK3566 EVB3 DDR3 V10 Board";
    ddr_timing {
        compatible = "rockchip,ddr-timing";
        ddr2_speed_bin = <0x00000000>;
        ddr3_speed_bin = <0x00000015>;
        ddr4_speed_bin = <0x0000000c>;
        pd_idle = <0x0000000d>;
        sr_idle = <0x0000005d>;
        sr_mc_gate_idle = <0x00000000>;
        srpd_lite_idle = <0x00000000>;
        standby_idle = <0x00000000>;
        auto_pd_dis_freq = <0x0000042a>;
        auto_sr_dis_freq = <0x00000320>;
        ddr2_dll_dis_freq = <0x0000012c>;
        ddr3_dll_dis_freq = <0x0000012c>;
        ddr4_dll_dis_freq = <0x00000271>;
        phy_dll_dis_freq = <0x00000190>;
        ddr2_odt_dis_freq = <0x00000064>;
        phy_ddr2_odt_dis_freq = <0x00000064>;
        ddr2_drv = <0x00000002>;
        ddr2_odt = <0x00000040>;
        phy_ddr2_ca_drv = <0x00000000>;
        phy_ddr2_ck_drv = <0x00000000>;
        phy_ddr2_dq_drv = <0x00000000>;
        phy_ddr2_odt = <0x00000000>;
        ddr3_odt_dis_freq = <0x0000014d>;
        phy_ddr3_odt_dis_freq = <0x0000014d>;
        ddr3_drv = <0x00000002>;
        ddr3_odt = <0x00000040>;
        phy_ddr3_ca_drv = <0x00000000>;
        phy_ddr3_ck_drv = <0x00000000>;
        phy_ddr3_dq_drv = <0x00000000>;
        phy_ddr3_odt = <0x00000000>;
        phy_lpddr2_odt_dis_freq = <0x0000014d>;
        lpddr2_drv = <0x00000002>;
        phy_lpddr2_ca_drv = <0x00000000>;
        phy_lpddr2_ck_drv = <0x00000000>;
        phy_lpddr2_dq_drv = <0x00000000>;
        phy_lpddr2_odt = <0x00000000>;
        lpddr3_odt_dis_freq = <0x0000014d>;
        phy_lpddr3_odt_dis_freq = <0x0000014d>;
        lpddr3_drv = <0x00000001>;
        lpddr3_odt = <0x00000002>;
        phy_lpddr3_ca_drv = <0x00000000>;
        phy_lpddr3_ck_drv = <0x00000000>;
        phy_lpddr3_dq_drv = <0x00000000>;
        phy_lpddr3_odt = <0x00000000>;
        lpddr4_odt_dis_freq = <0x0000014d>;
        phy_lpddr4_odt_dis_freq = <0x0000014d>;
        lpddr4_drv = <0x00000030>;
        lpddr4_dq_odt = <0x00000001>;
        lpddr4_ca_odt = <0x00000000>;
        phy_lpddr4_ca_drv = <0x00000000>;
        phy_lpddr4_ck_cs_drv = <0x00000000>;
        phy_lpddr4_dq_drv = <0x00000000>;
        phy_lpddr4_odt = <0x00000000>;
        ddr4_odt_dis_freq = <0x00000271>;
        phy_ddr4_odt_dis_freq = <0x00000271>;
        ddr4_drv = <0x00000000>;
        ddr4_odt = <0x00000200>;
        phy_ddr4_ca_drv = <0x00000000>;
        phy_ddr4_ck_drv = <0x00000000>;
        phy_ddr4_dq_drv = <0x00000000>;
        phy_ddr4_odt = <0x00000000>;
        phandle = <0x000000a8>;
    };
    aliases {
        csi2dphy0 = "/csi2-dphy0";
        csi2dphy1 = "/csi2-dphy1";
        csi2dphy2 = "/csi2-dphy2";
        dsi0 = "/dsi@fe060000";
        dsi1 = "/dsi@fe070000";
        ethernet1 = "/ethernet@fe010000";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        i2c0 = "/i2c@fdd40000";
        i2c1 = "/i2c@fe5a0000";
        i2c2 = "/i2c@fe5b0000";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mmc0 = "/dwmmc@fe2b0000";
        mmc1 = "/dwmmc@fe2c0000";
        mmc2 = "/sdhci@fe310000";
        mmc3 = "/dwmmc@fe000000";
        serial0 = "/serial@fdd50000";
        serial1 = "/serial@fe650000";
        serial2 = "/serial@fe660000";
        serial3 = "/serial@fe670000";
        serial4 = "/serial@fe680000";
        serial5 = "/serial@fe690000";
        serial6 = "/serial@fe6a0000";
        serial7 = "/serial@fe6b0000";
        serial8 = "/serial@fe6c0000";
        serial9 = "/serial@fe6d0000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
    };
    cpus {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000000>;
        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000000>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            #cooling-cells = <0x00000002>;
            dynamic-power-coefficient = <0x000000bb>;
            cpu-supply = <0x00000005>;
            phandle = <0x00000009>;
            power-model {
                compatible = "simple-power-model";
                leakage-range = <0x0000000a 0x00000028>;
                ls = <0xffffdc14 0x000018d8 0x00000000>;
                static-coefficient = <0x000186a0>;
                ts = <0x0001476e 0x0003263d 0xffffef34 0x00000047>;
                thermal-zone = "soc-thermal";
            };
        };
        cpu@100 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000100>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000a>;
        };
        cpu@200 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000200>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000b>;
        };
        cpu@300 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000300>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000c>;
        };
        idle-states {
            entry-method = "psci";
            cpu-sleep {
                compatible = "arm,idle-state";
                local-timer-stop;
                arm,psci-suspend-param = <0x00010000>;
                entry-latency-us = <0x00000064>;
                exit-latency-us = <0x00000078>;
                min-residency-us = <0x000003e8>;
                phandle = <0x00000004>;
            };
        };
    };
    cpu0-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000006 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-freq = <0x000639c0>;
        rockchip,pvtm-volt = <0x000dbba0>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        rockchip,pvtm-sample-time = <0x000003e8>;
        rockchip,pvtm-number = <0x0000000a>;
        rockchip,pvtm-error = <0x000003e8>;
        rockchip,pvtm-ref-temp = <0x00000028>;
        rockchip,pvtm-temp-prop = <0x0000001a 0x0000001a>;
        rockchip,thermal-zone = "soc-thermal";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000648 0x000124f8>;
        phandle = <0x00000003>;
        opp-408000000 {
            opp-hz = <0x00000000 0x18519600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-816000000 {
            opp-hz = <0x00000000 0x30a32c00>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            opp-suspend;
            status = "disabled";
        };
        opp-1104000000 {
            opp-hz = <0x00000000 0x41cdb400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-1416000000 {
            opp-hz = <0x00000000 0x54667200>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1608000000 {
            opp-hz = <0x00000000 0x5fd82200>;
            opp-microvolt = <0x000f4240 0x000f4240 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1800000000 {
            opp-hz = <0x00000000 0x6b49d200>;
            opp-microvolt = <0x00100590 0x00100590 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
    };
    arm-pmu {
        compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
        interrupts = <0x00000000 0x000000e4 0x00000004 0x00000000 0x000000e5 0x00000004 0x00000000 0x000000e6 0x00000004 0x00000000 0x000000e7 0x00000004>;
        interrupt-affinity = <0x00000009 0x0000000a 0x0000000b 0x0000000c>;
    };
    cpuinfo {
        compatible = "rockchip,cpuinfo";
        nvmem-cells = <0x0000000d 0x0000000e 0x0000000f>;
        nvmem-cell-names = "id", "cpu-version", "cpu-code";
    };
    display-subsystem {
        compatible = "rockchip,display-subsystem";
        memory-region = <0x00000010 0x00000011>;
        memory-region-names = "drm-logo", "drm-cubic-lut";
        ports = <0x00000012>;
        devfreq = <0x00000013>;
        phandle = <0x00000134>;
        route {
            route-dsi0 {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000014>;
                phandle = <0x00000135>;
            };
            route-dsi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000015>;
                phandle = <0x00000136>;
            };
            route-edp {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000016>;
                phandle = <0x00000137>;
            };
            route-hdmi {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000017>;
                phandle = <0x00000138>;
            };
            route-lvds {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000018>;
                phandle = <0x00000139>;
            };
            route-rgb {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000019>;
                phandle = <0x0000013a>;
            };
        };
    };
    firmware {
        optee {
            compatible = "linaro,optee-tz";
            method = "smc";
            phandle = <0x0000013b>;
        };
        scmi {
            compatible = "arm,scmi-smc";
            shmem = <0x0000001a>;
            arm,smc-id = <0x82000010>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x0000013c>;
            protocol@14 {
                reg = <0x00000014>;
                #clock-cells = <0x00000001>;
                rockchip,clk-init = "Tfr";
                phandle = <0x00000002>;
            };
        };
        sdei {
            compatible = "arm,sdei-1.0";
            method = "smc";
            phandle = <0x0000013d>;
        };
    };
    mpp-srv {
        compatible = "rockchip,mpp-service";
        rockchip,taskqueue-count = <0x00000006>;
        rockchip,resetgroup-count = <0x00000006>;
        status = "okay";
        phandle = <0x00000067>;
    };
    psci {
        compatible = "arm,psci-1.0";
        method = "smc";
    };
    reserved-memory {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        phandle = <0x0000013e>;
        drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000010>;
        };
        drm-cubic-lut@00000000 {
            compatible = "rockchip,drm-cubic-lut";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000011>;
        };
        linux,cma {
            compatible = "shared-dma-pool";
            inactive;
            reusable;
            reg = <0x00000000 0x10000000 0x00000000 0x00800000>;
            linux,cma-default;
        };
        ramoops@110000 {
            compatible = "ramoops";
            reg = <0x00000000 0x00110000 0x00000000 0x000f0000>;
            record-size = <0x00020000>;
            console-size = <0x00080000>;
            ftrace-size = <0x00000000>;
            pmsg-size = <0x00050000>;
            phandle = <0x0000013f>;
        };
    };
    rockchip-suspend {
        compatible = "rockchip,pm-rk3568";
        status = "okay";
        rockchip,sleep-debug-en = <0x00000001>;
        rockchip,sleep-mode-config = <0x000004e4>;
        rockchip,wakeup-config = <0x00002001>;
        rockchip,virtual-poweroff = <0x00000001>;
        phandle = <0x00000140>;
    };
    rockchip-system-monitor {
        compatible = "rockchip,system-monitor";
        rockchip,thermal-zone = "soc-thermal";
        phandle = <0x00000141>;
    };
    thermal-zones {
        phandle = <0x00000142>;
        soc-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            sustainable-power = <0x000005c3>;
            thermal-sensors = <0x0000001b 0x00000000>;
            phandle = <0x00000143>;
            trips {
                trip-point-0 {
                    temperature = <0x00011170>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x00000144>;
                };
                trip-point-1 {
                    temperature = <0x00014c08>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x0000001c>;
                };
                soc-crit {
                    temperature = <0x0001c138>;
                    hysteresis = <0x000007d0>;
                    type = "critical";
                    phandle = <0x00000145>;
                };
            };
            cooling-maps {
                map0 {
                    trip = <0x0000001c>;
                    cooling-device = <0x00000009 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
                map1 {
                    trip = <0x0000001c>;
                    cooling-device = <0x0000001d 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
            };
        };
        gpu-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x0000001b 0x00000001>;
            phandle = <0x00000146>;
        };
    };
    timer {
        compatible = "arm,armv8-timer";
        interrupts = <0x00000001 0x0000000d 0x00000f04 0x00000001 0x0000000e 0x00000f04 0x00000001 0x0000000b 0x00000f04 0x00000001 0x0000000a 0x00000f04>;
        arm,no-tick-in-suspend;
    };
    external-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "gmac1_clkin";
        #clock-cells = <0x00000000>;
        phandle = <0x00000147>;
    };
    xpcs-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "clk_gmac1_xpcs_mii";
        #clock-cells = <0x00000000>;
        phandle = <0x00000148>;
    };
    i2s1-mclkin-rx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_rx";
        phandle = <0x00000149>;
    };
    i2s1-mclkin-tx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_tx";
        phandle = <0x0000014a>;
    };
    i2s2-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s2_mclkin";
        phandle = <0x0000014b>;
    };
    i2s3-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s3_mclkin";
        phandle = <0x0000014c>;
    };
    mpll {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x2faf0800>;
        clock-output-names = "mpll";
        phandle = <0x0000014d>;
    };
    xin24m {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x016e3600>;
        clock-output-names = "xin24m";
        phandle = <0x0000014e>;
    };
    xin32k {
        compatible = "fixed-clock";
        clock-frequency = <0x00008000>;
        clock-output-names = "xin32k";
        #clock-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000001e>;
        phandle = <0x0000014f>;
    };
    scmi-shmem@10f000 {
        compatible = "arm,scmi-shmem";
        reg = <0x00000000 0x0010f000 0x00000000 0x00000100>;
        phandle = <0x0000001a>;
    };
    sata@fc400000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc400000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000009b 0x0000001f 0x0000009c 0x0000001f 0x0000009d>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x0000005f 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000020 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000150>;
    };
    sata@fc800000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc800000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x000000a0 0x0000001f 0x000000a1 0x0000001f 0x000000a2>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x00000060 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000022 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000151>;
    };
    usbdrd {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a6 0x0000001f 0x000000a7 0x0000001f 0x000000a5 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000152>;
        dwc3@fcc00000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfcc00000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000a9 0x00000004>;
            dr_mode = "host";
            phys = <0x00000023>;
            phy-names = "usb2-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000094>;
            reset-names = "usb3-otg";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            extcon = <0x00000024>;
            maximum-speed = "high-speed";
            snps,dis_u2_susphy_quirk;
            phandle = <0x00000153>;
        };
    };
    usbhost {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a9 0x0000001f 0x000000aa 0x0000001f 0x000000a8 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000154>;
        dwc3@fd000000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfd000000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000aa 0x00000004>;
            dr_mode = "host";
            phys = <0x00000025 0x00000020 0x00000004>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000095>;
            reset-names = "usb3-host";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            phandle = <0x00000155>;
        };
    };
    interrupt-controller@fd400000 {
        compatible = "arm,gic-v3";
        #interrupt-cells = <0x00000003>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        interrupt-controller;
        reg = <0x00000000 0xfd400000 0x00000000 0x00010000 0x00000000 0xfd460000 0x00000000 0x000c0000>;
        interrupts = <0x00000001 0x00000009 0x00000004>;
        phandle = <0x00000001>;
        interrupt-controller@fd440000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x00000001>;
            reg = <0x00000000 0xfd440000 0x00000000 0x00020000>;
            phandle = <0x000000ab>;
        };
    };
    usb@fd800000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd800000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000082 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000156>;
    };
    usb@fd840000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd840000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000083 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000157>;
    };
    usb@fd880000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd880000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000085 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000158>;
    };
    usb@fd8c0000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd8c0000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000086 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000159>;
    };
    syscon@fda00000 {
        compatible = "rockchip,rk3568-xpcs", "syscon";
        reg = <0x00000000 0xfda00000 0x00000000 0x00200000>;
        status = "disabled";
        phandle = <0x0000015a>;
    };
    syscon@fdc20000 {
        compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc20000 0x00000000 0x00010000>;
        phandle = <0x00000033>;
        io-domains {
            compatible = "rockchip,rk3568-pmu-io-voltage-domain";
            status = "okay";
            pmuio1-supply = <0x00000029>;
            pmuio2-supply = <0x00000029>;
            vccio1-supply = <0x0000002a>;
            vccio3-supply = <0x0000002b>;
            vccio4-supply = <0x0000002c>;
            vccio5-supply = <0x0000002d>;
            vccio6-supply = <0x0000002c>;
            vccio7-supply = <0x0000002d>;
            phandle = <0x0000015b>;
        };
        reboot-mode {
            compatible = "syscon-reboot-mode";
            offset = <0x00000200>;
            mode-bootloader = <0x5242c301>;
            mode-charge = <0x5242c30b>;
            mode-fastboot = <0x5242c309>;
            mode-loader = <0x5242c301>;
            mode-normal = <0x5242c300>;
            mode-recovery = <0x5242c303>;
            mode-ums = <0x5242c30c>;
            mode-panic = <0x5242c307>;
            mode-watchdog = <0x5242c308>;
            phandle = <0x0000015c>;
        };
    };
    syscon@fdc50000 {
        compatible = "rockchip,rk3568-pipegrf", "syscon";
        reg = <0x00000000 0xfdc50000 0x00000000 0x00001000>;
        phandle = <0x00000104>;
    };
    syscon@fdc60000 {
        compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc60000 0x00000000 0x00010000>;
        phandle = <0x00000032>;
        io-domains {
            compatible = "rockchip,rk3568-io-voltage-domain";
            status = "disabled";
            phandle = <0x0000015d>;
        };
        lvds {
            compatible = "rockchip,rk3568-lvds";
            phys = <0x0000002e>;
            phy-names = "phy";
            status = "disabled";
            phandle = <0x0000015e>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@1 {
                        reg = <0x00000001>;
                        remote-endpoint = <0x00000018>;
                        status = "disabled";
                        phandle = <0x0000008b>;
                    };
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x0000002f>;
                        status = "disabled";
                        phandle = <0x0000008c>;
                    };
                };
            };
        };
        rgb {
            compatible = "rockchip,rk3568-rgb";
            pinctrl-names = "default";
            pinctrl-0 = <0x00000030>;
            status = "disabled";
            phandle = <0x0000015f>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x00000019>;
                        status = "disabled";
                        phandle = <0x0000008d>;
                    };
                };
            };
        };
    };
    syscon@fdc70000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc70000 0x00000000 0x00001000>;
        phandle = <0x00000160>;
    };
    syscon@fdc80000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc80000 0x00000000 0x00001000>;
        phandle = <0x00000105>;
    };
    syscon@fdc90000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc90000 0x00000000 0x00001000>;
        phandle = <0x00000106>;
    };
    syscon@fdca0000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca0000 0x00000000 0x00008000>;
        phandle = <0x0000010b>;
    };
    syscon@fdca8000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca8000 0x00000000 0x00008000>;
        phandle = <0x0000010e>;
    };
    edp-phy@fdcb0000 {
        compatible = "rockchip,rk3568-edp-phy";
        reg = <0x00000000 0xfdcb0000 0x00000000 0x00008000>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x00000192>;
        clock-names = "refclk", "pclk";
        resets = <0x0000001f 0x000001d6>;
        reset-names = "apb";
        #phy-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000000a4>;
    };
    sram@fdcc0000 {
        compatible = "mmio-sram";
        reg = <0x00000000 0xfdcc0000 0x00000000 0x0000b000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges = <0x00000000 0x00000000 0xfdcc0000 0x0000b000>;
        phandle = <0x00000161>;
        rkvdec-sram@0 {
            reg = <0x00000000 0x0000b000>;
            phandle = <0x0000006f>;
        };
    };
    clock-controller@fdd00000 {
        compatible = "rockchip,rk3568-pmucru";
        reg = <0x00000000 0xfdd00000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        rockchip,pmugrf = <0x00000033>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000032>;
        assigned-clock-parents = <0x00000031 0x00000005>;
        phandle = <0x00000031>;
    };
    clock-controller@fdd20000 {
        compatible = "rockchip,rk3568-cru";
        reg = <0x00000000 0xfdd20000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000005 0x0000001f 0x00000106 0x0000001f 0x0000010b 0x00000031 0x00000001 0x00000031 0x0000002b 0x0000001f 0x00000003 0x0000001f 0x0000019b 0x0000001f 0x00000009 0x0000001f 0x0000019c 0x0000001f 0x0000019d 0x0000001f 0x000001a1 0x0000001f 0x0000019e 0x0000001f 0x0000019f 0x0000001f 0x000001a0 0x0000001f 0x00000004 0x0000001f 0x0000010d 0x0000001f 0x0000010e 0x0000001f 0x00000173 0x0000001f 0x00000174 0x0000001f 0x00000175 0x0000001f 0x00000176 0x0000001f 0x000000c9 0x0000001f 0x000000ca 0x0000001f 0x00000006 0x0000001f 0x0000007e 0x0000001f 0x0000007f 0x0000001f 0x0000003d 0x0000001f 0x00000041 0x0000001f 0x00000045 0x0000001f 0x00000049 0x0000001f 0x0000004d 0x0000001f 0x0000004d 0x0000001f 0x00000055 0x0000001f 0x00000051 0x0000001f 0x0000005d 0x0000001f 0x000000dd>;
        assigned-clock-rates = <0x00008000 0x11e1a300 0x11e1a300 0x0bebc200 0x05f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0x0ee6b280 0x07735940 0x05f5e100 0x03b9aca0 0x02faf080 0x017d7840 0x46cf7100 0x08f0d180 0x05f5e100 0x1dcd6500 0x17d78400 0x08f0d180 0x05f5e100 0x11e1a300 0x08f0d180 0x47868c00 0x17d78400 0x05f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
        assigned-clock-parents = <0x00000031 0x00000008 0x0000001f 0x00000004 0x0000001f 0x00000004>;
        phandle = <0x0000001f>;
    };
    i2c@fdd40000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfdd40000 0x00000000 0x00001000>;
        clocks = <0x00000031 0x00000007 0x00000031 0x0000002d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002e 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000034>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000162>;
        pmic@20 {
            compatible = "rockchip,rk809";
            reg = <0x00000020>;
            interrupt-parent = <0x00000035>;
            interrupts = <0x00000003 0x00000008>;
            pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
            pinctrl-0 = <0x00000036>;
            pinctrl-1 = <0x00000037 0x00000038>;
            pinctrl-2 = <0x00000039 0x0000003a>;
            pinctrl-3 = <0x00000039 0x0000003b>;
            rockchip,system-power-controller;
            wakeup-source;
            #clock-cells = <0x00000001>;
            clock-output-names = "rk808-clkout1", "rk808-clkout2";
            pmic-reset-func = <0x00000000>;
            not-save-power-en = <0x00000001>;
            vcc1-supply = <0x0000003c>;
            vcc2-supply = <0x0000003c>;
            vcc3-supply = <0x0000003c>;
            vcc4-supply = <0x0000003c>;
            vcc5-supply = <0x0000003c>;
            vcc6-supply = <0x0000003c>;
            vcc7-supply = <0x0000003c>;
            vcc8-supply = <0x0000003c>;
            vcc9-supply = <0x0000003c>;
            phandle = <0x0000012c>;
            pwrkey {
                status = "okay";
            };
            pinctrl_rk8xx {
                gpio-controller;
                #gpio-cells = <0x00000002>;
                phandle = <0x00000163>;
                rk817_slppin_null {
                    pins = "gpio_slp";
                    function = "pin_fun0";
                    phandle = <0x00000164>;
                };
                rk817_slppin_slp {
                    pins = "gpio_slp";
                    function = "pin_fun1";
                    phandle = <0x00000038>;
                };
                rk817_slppin_pwrdn {
                    pins = "gpio_slp";
                    function = "pin_fun2";
                    phandle = <0x0000003a>;
                };
                rk817_slppin_rst {
                    pins = "gpio_slp";
                    function = "pin_fun3";
                    phandle = <0x0000003b>;
                };
            };
            regulators {
                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_logic";
                    phandle = <0x00000062>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_gpu";
                    phandle = <0x00000064>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vcc_ddr";
                    phandle = <0x00000165>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                    };
                };
                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_npu";
                    phandle = <0x0000005f>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG1 {
                    regulator-boot-on;
                    regulator-always-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_image";
                    phandle = <0x00000166>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda_0v9";
                    phandle = <0x00000167>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_pmu";
                    phandle = <0x00000168>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x000dbba0>;
                    };
                };
                LDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_acodec";
                    phandle = <0x0000002a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_sd";
                    phandle = <0x0000002b>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vcc3v3_pmu";
                    phandle = <0x00000029>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x00325aa0>;
                    };
                };
                LDO_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca_1v8";
                    phandle = <0x00000103>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_pmu";
                    phandle = <0x00000169>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001b7740>;
                    };
                };
                LDO_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_image";
                    phandle = <0x0000016a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcc_1v8";
                    phandle = <0x0000002c>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc_3v3";
                    phandle = <0x0000002d>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc3v3_sd";
                    phandle = <0x000000ac>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };
            codec {
                #sound-dai-cells = <0x00000000>;
                compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
                clocks = <0x0000001f 0x000001a4>;
                clock-names = "mclk";
                assigned-clocks = <0x0000001f 0x000001a4 0x0000001f 0x000001a8>;
                assigned-clock-rates = <0x00bb8000>;
                assigned-clock-parents = <0x0000001f 0x00000054 0x0000001f 0x000001a4>;
                pinctrl-names = "default";
                pinctrl-0 = <0x0000003d>;
                hp-volume = <0x00000014>;
                spk-volume = <0x00000003>;
                mic-in-differential;
                status = "okay";
                phandle = <0x00000125>;
            };
        };
        tcs4526@10 {
            compatible = "tcs,tcs452x";
            reg = <0x00000010>;
            vin-supply = <0x0000003e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x00100590>;
            regulator-max-microvolt = <0x001535b0>;
            regulator-ramp-delay = <0x000008fc>;
            fcs,suspend-voltage-selector = <0x00000001>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x00000005>;
            regulator-state-mem {
                regulator-off-in-suspend;
            };
        };
    };
    serial@fdd50000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfdd50000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000074 0x00000004>;
        clocks = <0x00000031 0x0000000b 0x00000031 0x0000002c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000000 0x0000003f 0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000040>;
        status = "disabled";
        phandle = <0x0000016b>;
    };
    pwm@fdd70000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000041>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016c>;
    };
    pwm@fdd70010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000042>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016d>;
    };
    pwm@fdd70020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000043>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016e>;
    };
    pwm@fdd70030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfdd70030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000052 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000044>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "okay";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x0000016f>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000bd 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000e5 0x00000066 0x000000e7 0x00000073 0x000000e8 0x00000072 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x000000a4 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000a4 0x0000008d 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
        ir_key4 {
            rockchip,usercode = <0x0000fe01>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000e6 0x0000009e 0x000000e9 0x00000067 0x000000e5 0x0000006c 0x000000ae 0x00000069 0x000000af 0x0000006a 0x000000ee 0x00000066 0x000000e7 0x00000073 0x000000ef 0x00000072 0x000000bf 0x00000074 0x000000be 0x00000071 0x000000b3 0x0000008b 0x000000ff 0x00000184 0x000000b1 0x00000002 0x000000f2 0x00000003 0x000000f3 0x00000004 0x000000b5 0x00000005 0x000000f6 0x00000006 0x000000f7 0x00000007 0x000000b9 0x00000008 0x000000fa 0x00000009 0x000000fb 0x0000000a 0x000000fe 0x0000000b 0x000000bd 0x0000000e 0x000000bc 0x000000b7 0x000000f0 0x000000ba 0x000000b4 0x0000019c 0x000000b8 0x0000001e 0x000000b0 0x00000197>;
        };
        ir_key5 {
            rockchip,usercode = <0x00007f80>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000d8 0x0000009e 0x000000c7 0x00000067 0x000000bf 0x0000006c 0x000000c8 0x00000069 0x000000c6 0x0000006a 0x0000008c 0x00000066 0x00000078 0x00000073 0x00000076 0x00000072 0x0000007e 0x00000074 0x0000007c 0x0000008b 0x000000b7 0x00000184>;
        };
        ir_key6 {
            rockchip,usercode = <0x0000fd01>;
            rockchip,key_table = <0x00000031 0x000000e8 0x0000002f 0x0000009e 0x00000035 0x00000067 0x0000002d 0x0000006c 0x00000066 0x00000069 0x0000003e 0x0000006a 0x0000006a 0x00000066 0x0000005e 0x00000073 0x00000047 0x00000072 0x00000023 0x00000074 0x0000003a 0x00000184 0x0000000d 0x00000040>;
        };
    };
    power-management@fdd90000 {
        compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdd90000 0x00000000 0x00001000>;
        phandle = <0x00000170>;
        power-controller {
            compatible = "rockchip,rk3568-power-controller";
            #power-domain-cells = <0x00000001>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000021>;
            pd_npu@6 {
                reg = <0x00000006>;
                clocks = <0x0000001f 0x00000027 0x0000001f 0x00000025 0x0000001f 0x00000026>;
                pm_qos = <0x00000045>;
            };
            pd_gpu@7 {
                reg = <0x00000007>;
                clocks = <0x0000001f 0x00000019 0x0000001f 0x0000001a>;
                pm_qos = <0x00000046>;
            };
            pd_vi@8 {
                reg = <0x00000008>;
                clocks = <0x0000001f 0x000000cc 0x0000001f 0x000000cd>;
                pm_qos = <0x00000047 0x00000048 0x00000049>;
            };
            pd_vo@9 {
                reg = <0x00000009>;
                clocks = <0x0000001f 0x000000da 0x0000001f 0x000000db 0x0000001f 0x000000dc>;
                pm_qos = <0x0000004a 0x0000004b 0x0000004c>;
            };
            pd_rga@10 {
                reg = <0x0000000a>;
                clocks = <0x0000001f 0x000000f1 0x0000001f 0x000000f2>;
                pm_qos = <0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052>;
            };
            pd_vpu@11 {
                reg = <0x0000000b>;
                clocks = <0x0000001f 0x000000ed>;
                pm_qos = <0x00000053>;
            };
            pd_rkvdec@13 {
                clocks = <0x0000001f 0x00000107>;
                reg = <0x0000000d>;
                pm_qos = <0x00000054>;
            };
            pd_rkvenc@14 {
                reg = <0x0000000e>;
                clocks = <0x0000001f 0x00000102>;
                pm_qos = <0x00000055 0x00000056 0x00000057>;
            };
            pd_pipe@15 {
                reg = <0x0000000f>;
                clocks = <0x0000001f 0x0000007f>;
                pm_qos = <0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c>;
            };
        };
    };
    pvtm@fde00000 {
        compatible = "rockchip,rk3568-core-pvtm";
        reg = <0x00000000 0xfde00000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@0 {
            reg = <0x00000000>;
            clocks = <0x0000001f 0x00000013 0x0000001f 0x000001c2>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x0000001a 0x0000001f 0x00000019>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    npu@fde40000 {
        compatible = "rockchip,rknpu";
        reg = <0x00000000 0xfde40000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        clocks = <0x00000002 0x00000002 0x0000001f 0x00000023 0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "scmi_clk", "clk", "aclk", "hclk";
        assigned-clocks = <0x0000001f 0x00000023>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x0000001f 0x0000002b 0x0000001f 0x0000002c>;
        reset-names = "srst_a", "srst_h";
        power-domains = <0x00000021 0x00000006>;
        operating-points-v2 = <0x0000005d>;
        iommus = <0x0000005e>;
        status = "okay";
        rknpu-supply = <0x0000005f>;
        phandle = <0x00000171>;
    };
    npu-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000060 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x000002bc 0x0000c350>;
        phandle = <0x0000005d>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000cf850 0x000cf850 0x000f4240>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000d59f8 0x000d59f8 0x000f4240>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x000f4240>;
        };
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000f4240 0x000f4240 0x000f4240>;
            status = "disabled";
        };
    };
    bus-npu {
        compatible = "rockchip,rk3568-bus";
        rockchip,busfreq-policy = "clkfreq";
        clocks = <0x00000002 0x00000002>;
        clock-names = "bus";
        operating-points-v2 = <0x00000061>;
        status = "okay";
        bus-supply = <0x00000062>;
        pvtm-supply = <0x00000005>;
        phandle = <0x00000172>;
    };
    bus-npu-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x00000061>;
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x00000000>;
        };
    };
    iommu@fde4b000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfde4b000 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        interrupt-names = "rknpu_mmu";
        clocks = <0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000006>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000005e>;
    };
    gpu@fde60000 {
        compatible = "arm,mali-bifrost";
        reg = <0x00000000 0xfde60000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000027 0x00000004 0x00000000 0x00000029 0x00000004 0x00000000 0x00000028 0x00000004>;
        interrupt-names = "GPU", "MMU", "JOB";
        upthreshold = <0x00000028>;
        downdifferential = <0x0000000a>;
        clocks = <0x00000002 0x00000001 0x0000001f 0x0000001b>;
        clock-names = "clk_mali", "clk_gpu";
        power-domains = <0x00000021 0x00000007>;
        #cooling-cells = <0x00000002>;
        operating-points-v2 = <0x00000063>;
        status = "okay";
        mali-supply = <0x00000064>;
        phandle = <0x0000001d>;
        power-model {
            compatible = "simple-power-model";
            leakage-range = <0x00000005 0x0000000f>;
            ls = <0xffffa23e 0x00005927 0x00000000>;
            static-coefficient = <0x000186a0>;
            dynamic-coefficient = <0x000003b9>;
            ts = <0xfffe56a6 0x0000f87a 0xfffffab5 0x00000014>;
            thermal-zone = "gpu-thermal";
            phandle = <0x00000173>;
        };
    };
    opp-table2 {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000065 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        phandle = <0x00000063>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11e1a300>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000dbba0>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000e7ef0>;
        };
    };
    pvtm@fde80000 {
        compatible = "rockchip,rk3568-gpu-pvtm";
        reg = <0x00000000 0xfde80000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@1 {
            reg = <0x00000001>;
            clocks = <0x0000001f 0x0000001e 0x0000001f 0x0000001d>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x00000024 0x0000001f 0x00000023>;
            reset-names = "rts", "rst-p";
            thermal-zone = "gpu-thermal";
        };
    };
    pvtm@fde90000 {
        compatible = "rockchip,rk3568-npu-pvtm";
        reg = <0x00000000 0xfde90000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@2 {
            reg = <0x00000002>;
            clocks = <0x0000001f 0x0000002b 0x0000001f 0x0000002a 0x0000001f 0x00000025>;
            clock-names = "clk", "pclk", "hclk";
            resets = <0x0000001f 0x0000002e 0x0000001f 0x0000002d>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    vdpu@fdea0400 {
        compatible = "rockchip,vpu-decoder-v2";
        reg = <0x00000000 0xfdea0400 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        resets = <0x0000001f 0x0000011a 0x0000001f 0x0000011b>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000066>;
        power-domains = <0x00000021 0x0000000b>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000000>;
        rockchip,resetgroup-node = <0x00000000>;
        status = "okay";
        phandle = <0x00000174>;
    };
    iommu@fdea0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdea0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008a 0x00000004>;
        interrupt-names = "vdpu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        power-domains = <0x00000021 0x0000000b>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000066>;
    };
    rk_rga@fdeb0000 {
        compatible = "rockchip,rga2";
        reg = <0x00000000 0xfdeb0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000005a 0x00000004>;
        clocks = <0x0000001f 0x000000f3 0x0000001f 0x000000f4 0x0000001f 0x000000f5>;
        clock-names = "aclk_rga", "hclk_rga", "clk_rga";
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000175>;
    };
    ebc@fdec0000 {
        compatible = "rockchip,rk3568-ebc-tcon";
        reg = <0x00000000 0xfdec0000 0x00000000 0x00005000>;
        interrupts = <0x00000000 0x00000011 0x00000004>;
        clocks = <0x0000001f 0x000000f9 0x0000001f 0x000000fa>;
        clock-names = "hclk", "dclk";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,grf = <0x00000032>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000068>;
        status = "disabled";
        phandle = <0x00000176>;
    };
    jpegd@fded0000 {
        compatible = "rockchip,rkv-jpeg-decoder-v1";
        reg = <0x00000000 0xfded0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000003e 0x00000004>;
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012c 0x0000001f 0x0000012d>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000069>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000001>;
        rockchip,resetgroup-node = <0x00000001>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000177>;
    };
    iommu@fded0480 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfded0480 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003d 0x00000004>;
        interrupt-names = "jpegd_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000069>;
    };
    vepu@fdee0000 {
        compatible = "rockchip,vpu-encoder-v2";
        reg = <0x00000000 0xfdee0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x00000040 0x00000004>;
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012e 0x0000001f 0x0000012f>;
        reset-names = "video_a", "video_h";
        iommus = <0x0000006a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000002>;
        rockchip,resetgroup-node = <0x00000002>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000178>;
    };
    iommu@fdee0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdee0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003f 0x00000004>;
        interrupt-names = "vepu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006a>;
    };
    iep@fdef0000 {
        compatible = "rockchip,iep-v2";
        reg = <0x00000000 0xfdef0000 0x00000000 0x00000500>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7 0x0000001f 0x000000f8>;
        clock-names = "aclk", "hclk", "sclk";
        resets = <0x0000001f 0x00000127 0x0000001f 0x00000128 0x0000001f 0x00000129>;
        reset-names = "rst_a", "rst_h", "rst_s";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000005>;
        rockchip,resetgroup-node = <0x00000005>;
        iommus = <0x0000006b>;
        status = "okay";
        phandle = <0x00000179>;
    };
    iommu@fdef0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdef0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        interrupt-names = "iep_mmu";
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x0000006b>;
    };
    eink@fdf00000 {
        compatible = "rockchip,rk3568-eink-tcon";
        reg = <0x00000000 0xfdf00000 0x00000000 0x00000074>;
        interrupts = <0x00000000 0x000000b2 0x00000004>;
        clocks = <0x0000001f 0x000000ff 0x0000001f 0x00000100>;
        clock-names = "pclk", "hclk";
        status = "disabled";
        phandle = <0x0000017a>;
    };
    rkvenc@fdf40000 {
        compatible = "rockchip,rkv-encoder-v1";
        reg = <0x00000000 0xfdf40000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008c 0x00000004>;
        interrupt-names = "irq_enc";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104 0x0000001f 0x00000105>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40>;
        resets = <0x0000001f 0x00000133 0x0000001f 0x00000134 0x0000001f 0x00000135>;
        reset-names = "video_a", "video_h", "video_core";
        assigned-clocks = <0x0000001f 0x00000103 0x0000001f 0x00000105>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40>;
        iommus = <0x0000006c>;
        node-name = "rkvenc";
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000003>;
        rockchip,resetgroup-node = <0x00000003>;
        power-domains = <0x00000021 0x0000000e>;
        operating-points-v2 = <0x0000006d>;
        status = "okay";
        venc-supply = <0x00000062>;
        phandle = <0x0000017b>;
    };
    rkvenc-opp-table {
        compatible = "operating-points-v2";
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x0000006d>;
        opp-297000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x00000000>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
    };
    iommu@fdf40f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf40f00 0x00000000 0x00000040 0x00000000 0xfdf40f40 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008d 0x00000004 0x00000000 0x0000008e 0x00000004>;
        interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000e>;
        status = "okay";
        phandle = <0x0000006c>;
    };
    rkvdec@fdf80200 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x00000000 0xfdf80200 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000005b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core", "clk_hevc_cabac";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40 0x11b3dc40 0x23c34600>;
        rockchip,advanced-rates = <0x179a7b00 0x00000000 0x179a7b00 0x179a7b00 0x23c34600>;
        rockchip,default-max-load = <0x001fe000>;
        resets = <0x0000001f 0x00000142 0x0000001f 0x00000143 0x0000001f 0x00000144 0x0000001f 0x00000145 0x0000001f 0x00000146>;
        assigned-clocks = <0x0000001f 0x00000108 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>;
        reset-names = "video_a", "video_h", "video_cabac", "video_core", "video_hevc_cabac";
        power-domains = <0x00000021 0x0000000d>;
        iommus = <0x0000006e>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000004>;
        rockchip,resetgroup-node = <0x00000004>;
        rockchip,sram = <0x0000006f>;
        rockchip,rcb-iova = <0x10000000 0x00010000>;
        rockchip,rcb-min-width = <0x00000200>;
        status = "okay";
        phandle = <0x0000017c>;
    };
    iommu@fdf80800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf80800 0x00000000 0x00000040 0x00000000 0xfdf80840 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000005c 0x00000004>;
        interrupt-names = "rkvdec_mmu";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x0000000d>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006e>;
    };
    mipi-csi2@fdfb0000 {
        compatible = "rockchip,rk3568-mipi-csi2";
        reg = <0x00000000 0xfdfb0000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000008 0x00000004 0x00000000 0x00000009 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x0000001f 0x000000d5>;
        clock-names = "pclk_csi2host";
        resets = <0x0000001f 0x000000ff>;
        reset-names = "srst_csihost_p";
        status = "disabled";
        phandle = <0x0000017d>;
    };
    rkcif@fdfe0000 {
        compatible = "rockchip,rk3568-cif";
        reg = <0x00000000 0xfdfe0000 0x00000000 0x00008000>;
        reg-names = "cif_regs";
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif-intr";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf 0x0000001f 0x000000d0 0x0000001f 0x000000d1>;
        clock-names = "aclk_cif", "hclk_cif", "dclk_cif", "iclk_cif_g";
        resets = <0x0000001f 0x000000f7 0x0000001f 0x000000f8 0x0000001f 0x000000f9 0x0000001f 0x000000fb 0x0000001f 0x000000fa>;
        reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_p", "rst_cif_i";
        assigned-clocks = <0x0000001f 0x000000d0>;
        assigned-clock-rates = <0x11e1a300>;
        power-domains = <0x00000021 0x00000008>;
        rockchip,grf = <0x00000032>;
        iommus = <0x00000070>;
        status = "okay";
        phandle = <0x00000071>;
    };
    iommu@fdfe0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdfe0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif_mmu";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        rockchip,disable-mmu-reset;
        #iommu-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000070>;
    };
    rkcif_dvp {
        compatible = "rockchip,rkcif-dvp";
        rockchip,hw = <0x00000071>;
        status = "okay";
        phandle = <0x00000073>;
        port {
            endpoint {
                remote-endpoint = <0x00000072>;
                bus-width = <0x00000008>;
                vsync-active = <0x00000000>;
                hsync-active = <0x00000001>;
                phandle = <0x000000d3>;
            };
        };
    };
    rkcif_dvp_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000073>;
        status = "disabled";
        phandle = <0x0000017e>;
    };
    rkcif_mipi_lvds {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000071>;
        status = "disabled";
        phandle = <0x00000074>;
    };
    rkcif_mipi_lvds_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000074>;
        status = "disabled";
        phandle = <0x0000017f>;
    };
    rkisp@fdff0000 {
        compatible = "rockchip,rk3568-rkisp";
        reg = <0x00000000 0xfdff0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000039 0x00000004 0x00000000 0x0000003a 0x00000004 0x00000000 0x0000003c 0x00000004>;
        interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3 0x0000001f 0x000000d4>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp";
        resets = <0x0000001f 0x000000fd 0x0000001f 0x000000fc>;
        reset-names = "isp", "isp-h";
        rockchip,grf = <0x00000032>;
        power-domains = <0x00000021 0x00000008>;
        iommus = <0x00000075>;
        rockchip,iq-feature = <0x000003fb 0xf7fe67ff>;
        status = "okay";
        phandle = <0x00000076>;
    };
    iommu@fdff1a00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdff1a00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000003b 0x00000004>;
        interrupt-names = "isp_mmu";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "okay";
        phandle = <0x00000075>;
    };
    rkisp-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "okay";
        phandle = <0x00000180>;
        port {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            endpoint@0 {
                reg = <0x00000000>;
                remote-endpoint = <0x00000077>;
                phandle = <0x0000010a>;
            };
        };
    };
    rkisp-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "disabled";
        phandle = <0x00000181>;
    };
    ethernet@fe010000 {
        compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
        reg = <0x00000000 0xfe010000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000020 0x00000004 0x00000000 0x0000001d 0x00000004>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000186 0x0000001f 0x00000189 0x0000001f 0x00000189 0x0000001f 0x000000c7 0x0000001f 0x000000c3 0x0000001f 0x000000c4 0x0000001f 0x00000189 0x0000001f 0x000000c8 0x0000001f 0x000000ac>;
        clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref", "pclk_xpcs";
        resets = <0x0000001f 0x000000ec>;
        reset-names = "stmmaceth";
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x00000078>;
        snps,mtl-rx-config = <0x00000079>;
        snps,mtl-tx-config = <0x0000007a>;
        status = "okay";
        phy-mode = "rgmii";
        clock_in_out = "output";
        snps,reset-gpio = <0x0000007b 0x00000001 0x00000001>;
        snps,reset-active-low;
        snps,reset-delays-us = <0x00000000 0x00004e20 0x000186a0>;
        assigned-clocks = <0x0000001f 0x00000189 0x0000001f 0x00000186>;
        assigned-clock-parents = <0x0000001f 0x00000187 0x0000001f 0x000000c5>;
        assigned-clock-rates = <0x00000000 0x07735940>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080>;
        tx_delay = <0x00000041>;
        rx_delay = <0x0000002e>;
        phy-handle = <0x00000081>;
        phandle = <0x00000182>;
        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000183>;
            phy@0 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <0x00000000>;
                phandle = <0x00000081>;
            };
        };
        stmmac-axi-config {
            snps,wr_osr_lmt = <0x00000004>;
            snps,rd_osr_lmt = <0x00000008>;
            snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>;
            phandle = <0x00000078>;
        };
        rx-queues-config {
            snps,rx-queues-to-use = <0x00000001>;
            phandle = <0x00000079>;
            queue0 {
            };
        };
        tx-queues-config {
            snps,tx-queues-to-use = <0x00000001>;
            phandle = <0x0000007a>;
            queue0 {
            };
        };
    };
    vop@fe040000 {
        compatible = "rockchip,rk3568-vop";
        reg = <0x00000000 0xfe040000 0x00000000 0x00003000 0x00000000 0xfe044000 0x00000000 0x00001000>;
        reg-names = "regs", "gamma_lut";
        rockchip,grf = <0x00000032>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de 0x0000001f 0x000000df 0x0000001f 0x000000e0 0x0000001f 0x000000e1>;
        clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
        iommus = <0x00000082>;
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        assigned-clocks = <0x0000001f 0x000000df 0x0000001f 0x000000e0>;
        assigned-clock-parents = <0x00000031 0x00000002 0x0000001f 0x00000005>;
        support-multi-area;
        phandle = <0x00000184>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000012>;
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                phandle = <0x00000185>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000083>;
                    phandle = <0x0000008f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000084>;
                    phandle = <0x00000015>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000085>;
                    phandle = <0x00000016>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x00000086>;
                    phandle = <0x00000017>;
                };
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                phandle = <0x00000186>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000087>;
                    phandle = <0x00000014>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000088>;
                    phandle = <0x00000098>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000089>;
                    phandle = <0x000000a5>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x0000008a>;
                    phandle = <0x000000a3>;
                };
                endpoint@4 {
                    reg = <0x00000004>;
                    remote-endpoint = <0x0000008b>;
                    phandle = <0x00000018>;
                };
            };
            port@2 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000002>;
                phandle = <0x00000187>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008c>;
                    phandle = <0x0000002f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000008d>;
                    phandle = <0x00000019>;
                };
            };
        };
    };
    iommu@fe043e00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfe043e00 0x00000000 0x00000100 0x00000000 0xfe043f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        interrupt-names = "vop_mmu";
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000082>;
    };
    dsi@fe060000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe060000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000044 0x00000004>;
        clocks = <0x0000001f 0x000000e8 0x0000001f 0x000000da 0x0000008e>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000110>;
        reset-names = "apb";
        phys = <0x0000008e>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000188>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000189>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008f>;
                    status = "disabled";
                    phandle = <0x00000083>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000014>;
                    status = "okay";
                    phandle = <0x00000087>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000090>;
                    phandle = <0x00000096>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x00000091>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x00000092>;
            reset-gpios = <0x00000093 0x00000005 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x00000094>;
            phandle = <0x0000018a>;
            display-timings {
                native-mode = <0x00000095>;
                phandle = <0x0000018b>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x00000095>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x00000096>;
                        phandle = <0x00000090>;
                    };
                };
            };
        };
    };
    dsi@fe070000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe070000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000045 0x00000004>;
        clocks = <0x0000001f 0x000000e9 0x0000001f 0x000000da 0x00000097>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000111>;
        reset-names = "apb";
        phys = <0x00000097>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000018c>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x0000018d>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000015>;
                    status = "disabled";
                    phandle = <0x00000084>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000098>;
                    status = "disabled";
                    phandle = <0x00000088>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000099>;
                    phandle = <0x0000009f>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x0000009a>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x0000009b>;
            reset-gpios = <0x0000009c 0x00000016 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000009d>;
            phandle = <0x0000018e>;
            display-timings {
                native-mode = <0x0000009e>;
                phandle = <0x0000018f>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x0000009e>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x0000009f>;
                        phandle = <0x00000099>;
                    };
                };
            };
        };
    };
    hdmi@fe0a0000 {
        compatible = "rockchip,rk3568-dw-hdmi";
        reg = <0x00000000 0xfe0a0000 0x00000000 0x00020000>;
        interrupts = <0x00000000 0x0000002d 0x00000004>;
        clocks = <0x0000001f 0x000000e6 0x0000001f 0x000000e7 0x0000001f 0x00000193 0x00000031 0x00000002 0x0000001f 0x000000de>;
        clock-names = "iahb", "isfr", "cec", "ref", "hclk";
        power-domains = <0x00000021 0x00000009>;
        reg-io-width = <0x00000004>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000a0 0x000000a1 0x000000a2>;
        status = "okay";
        rockchip,phy-table = <0x058834d4 0x00008009 0x00000000 0x00000270 0x09d5b340 0x0000800b 0x00000000 0x0000026d 0x0b1069a8 0x0000800b 0x00000000 0x000001ed 0x11b3dc40 0x0000800b 0x00000000 0x000001ad 0x2367b880 0x00008029 0x00000000 0x00000088 0x00000000 0x00000000 0x00000000 0x00000000>;
        phandle = <0x00000122>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000190>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000017>;
                    status = "okay";
                    phandle = <0x00000086>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a3>;
                    status = "disabled";
                    phandle = <0x0000008a>;
                };
            };
        };
    };
    edp@fe0c0000 {
        compatible = "rockchip,rk3568-edp";
        reg = <0x00000000 0xfe0c0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000012 0x00000004>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x000000ea 0x0000001f 0x000000eb 0x0000001f 0x000000da>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        reset-names = "dp", "apb";
        phys = <0x000000a4>;
        phy-names = "dp";
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        hpd-gpios = <0x00000093 0x00000007 0x00000000>;
        phandle = <0x00000191>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000192>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000016>;
                    status = "okay";
                    phandle = <0x00000085>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a5>;
                    status = "disabled";
                    phandle = <0x00000089>;
                };
            };
        };
    };
    qos@fe128000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe128000 0x00000000 0x00000020>;
        phandle = <0x00000046>;
    };
    qos@fe138080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138080 0x00000000 0x00000020>;
        phandle = <0x00000055>;
    };
    qos@fe138100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138100 0x00000000 0x00000020>;
        phandle = <0x00000056>;
    };
    qos@fe138180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138180 0x00000000 0x00000020>;
        phandle = <0x00000057>;
    };
    qos@fe148000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148000 0x00000000 0x00000020>;
        phandle = <0x00000047>;
    };
    qos@fe148080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148080 0x00000000 0x00000020>;
        phandle = <0x00000048>;
    };
    qos@fe148100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148100 0x00000000 0x00000020>;
        phandle = <0x00000049>;
    };
    qos@fe150000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe150000 0x00000000 0x00000020>;
        phandle = <0x00000053>;
    };
    qos@fe158000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158000 0x00000000 0x00000020>;
        phandle = <0x0000004d>;
    };
    qos@fe158100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158100 0x00000000 0x00000020>;
        phandle = <0x0000004e>;
    };
    qos@fe158180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158180 0x00000000 0x00000020>;
        phandle = <0x0000004f>;
    };
    qos@fe158200 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158200 0x00000000 0x00000020>;
        phandle = <0x00000050>;
    };
    qos@fe158280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158280 0x00000000 0x00000020>;
        phandle = <0x00000051>;
    };
    qos@fe158300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158300 0x00000000 0x00000020>;
        phandle = <0x00000052>;
    };
    qos@fe180000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe180000 0x00000000 0x00000020>;
        phandle = <0x00000045>;
    };
    qos@fe190000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190000 0x00000000 0x00000020>;
        phandle = <0x00000058>;
    };
    qos@fe190280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190280 0x00000000 0x00000020>;
        phandle = <0x00000059>;
    };
    qos@fe190300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190300 0x00000000 0x00000020>;
        phandle = <0x0000005a>;
    };
    qos@fe190380 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190380 0x00000000 0x00000020>;
        phandle = <0x0000005b>;
    };
    qos@fe190400 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190400 0x00000000 0x00000020>;
        phandle = <0x0000005c>;
    };
    qos@fe198000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe198000 0x00000000 0x00000020>;
        phandle = <0x00000054>;
    };
    qos@fe1a8000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8000 0x00000000 0x00000020>;
        phandle = <0x0000004a>;
    };
    qos@fe1a8080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8080 0x00000000 0x00000020>;
        phandle = <0x0000004b>;
    };
    qos@fe1a8100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8100 0x00000000 0x00000020>;
        phandle = <0x0000004c>;
    };
    dwmmc@fe000000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe000000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000064 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000c1 0x0000001f 0x000000c2 0x0000001f 0x0000018e 0x0000001f 0x0000018f>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000eb>;
        reset-names = "reset";
        status = "disabled";
        phandle = <0x00000193>;
    };
    dfi@fe230000 {
        reg = <0x00000000 0xfe230000 0x00000000 0x00000400>;
        compatible = "rockchip,rk3568-dfi";
        rockchip,pmugrf = <0x00000033>;
        status = "disabled";
        phandle = <0x000000a6>;
    };
    dmc {
        compatible = "rockchip,rk3568-dmc";
        interrupts = <0x00000000 0x0000000a 0x00000004>;
        interrupt-names = "complete";
        devfreq-events = <0x000000a6>;
        clocks = <0x0000001f 0x000001a2>;
        clock-names = "dmc_clk";
        operating-points-v2 = <0x000000a7>;
        ddr_timing = <0x000000a8>;
        vop-bw-dmc-freq = <0x00000000 0x000001f9 0x0004f1a0 0x000001fa 0x0001869f 0x00080e80>;
        upthreshold = <0x00000028>;
        downdifferential = <0x00000014>;
        system-status-freq = <0x00000001 0x000be6e0 0x00000008 0x000be6e0 0x00000002 0x000be6e0 0x00000010 0x000be6e0 0x00010000 0x000be6e0 0x00001000 0x000be6e0 0x00004000 0x000be6e0 0x00002000 0x000be6e0 0x00000c00 0x000be6e0>;
        auto-min-freq = <0x0004f1a0>;
        auto-freq-en = <0x00000001>;
        #cooling-cells = <0x00000002>;
        status = "disabled";
        center-supply = <0x00000062>;
        phandle = <0x00000013>;
    };
    dmc-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x000000a9 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000618 0x000061a8>;
        rockchip,leakage-voltage-sel = <0x00000001 0x00000050 0x00000000 0x00000051 0x000000fe 0x00000001>;
        phandle = <0x000000a7>;
        opp-324000000 {
            opp-hz = <0x00000000 0x134fd900>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-528000000 {
            opp-hz = <0x00000000 0x1f78a400>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-780000000 {
            opp-hz = <0x00000000 0x2e7ddb00>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-920000000 {
            opp-hz = <0x00000000 0x36d61600>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
            status = "disabled";
        };
        opp-1056000000 {
            opp-hz = <0x00000000 0x3ef14800>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
    };
    pcie@fe260000 {
        compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000000 0x0000000f>;
        clocks = <0x0000001f 0x00000081 0x0000001f 0x00000082 0x0000001f 0x00000083 0x0000001f 0x00000084 0x0000001f 0x00000085>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
        device_type = "pci";
        interrupts = <0x00000000 0x0000004b 0x00000004 0x00000000 0x0000004a 0x00000004 0x00000000 0x00000049 0x00000004 0x00000000 0x00000048 0x00000004 0x00000000 0x00000047 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x000000aa 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x000000aa 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x000000aa 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x000000aa 0x00000003>;
        linux,pci-domain = <0x00000000>;
        num-ib-windows = <0x00000006>;
        num-ob-windows = <0x00000002>;
        max-link-speed = <0x00000002>;
        msi-map = <0x00000000 0x000000ab 0x00000000 0x00001000>;
        num-lanes = <0x00000001>;
        phys = <0x00000022 0x00000002>;
        phy-names = "pcie-phy";
        power-domains = <0x00000021 0x0000000f>;
        ranges = <0x00000800 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00800000 0x81000000 0x00000000 0x00800000 0x00000003 0x00800000 0x00000000 0x00100000 0x83000000 0x00000000 0x00900000 0x00000003 0x00900000 0x00000000 0x3f700000>;
        reg = <0x00000003 0xc0000000 0x00000000 0x00400000 0x00000000 0xfe260000 0x00000000 0x00010000>;
        reg-names = "pcie-dbi", "pcie-apb";
        resets = <0x0000001f 0x000000a1>;
        reset-names = "pipe";
        status = "disabled";
        phandle = <0x00000194>;
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x00000048 0x00000001>;
            phandle = <0x000000aa>;
        };
    };
    dwmmc@fe2b0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2b0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000062 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b0 0x0000001f 0x000000b1 0x0000001f 0x0000018a 0x0000001f 0x0000018b>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d4>;
        reset-names = "reset";
        status = "okay";
        supports-sd;
        bus-width = <0x00000004>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        disable-wp;
        sd-uhs-sdr104;
        vmmc-supply = <0x000000ac>;
        vqmmc-supply = <0x0000002b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ad 0x000000ae 0x000000af 0x000000b0>;
        phandle = <0x00000195>;
    };
    dwmmc@fe2c0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2c0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000063 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b2 0x0000001f 0x000000b3 0x0000001f 0x0000018c 0x0000001f 0x0000018d>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d6>;
        reset-names = "reset";
        status = "okay";
        supports-sdio;
        bus-width = <0x00000004>;
        disable-wp;
        cap-sd-highspeed;
        cap-sdio-irq;
        keep-power-in-suspend;
        mmc-pwrseq = <0x000000b1>;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b2 0x000000b3 0x000000b4>;
        sd-uhs-sdr104;
        phandle = <0x00000196>;
    };
    sfc@fe300000 {
        compatible = "rockchip,sfc";
        reg = <0x00000000 0xfe300000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000065 0x00000004>;
        clocks = <0x0000001f 0x00000078 0x0000001f 0x00000076>;
        clock-names = "clk_sfc", "hclk_sfc";
        assigned-clocks = <0x0000001f 0x00000078>;
        assigned-clock-rates = <0x05f5e100>;
        status = "okay";
        phandle = <0x00000197>;
    };
    sdhci@fe310000 {
        compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
        reg = <0x00000000 0xfe310000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000013 0x00000004>;
        assigned-clocks = <0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        assigned-clock-rates = <0x0bebc200 0x016e3600>;
        clocks = <0x0000001f 0x0000007c 0x0000001f 0x0000007a 0x0000001f 0x00000079 0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        clock-names = "core", "bus", "axi", "block", "timer";
        status = "okay";
        bus-width = <0x00000008>;
        supports-emmc;
        non-removable;
        max-frequency = <0x0bebc200>;
        phandle = <0x00000198>;
    };
    nandc@fe330000 {
        compatible = "rockchip,rk-nandc-v9";
        reg = <0x00000000 0xfe330000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000046 0x00000004>;
        nandc_id = <0x00000000>;
        clocks = <0x0000001f 0x00000075 0x0000001f 0x00000074>;
        clock-names = "clk_nandc", "hclk_nandc";
        status = "okay";
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        phandle = <0x00000199>;
        nand@0 {
            reg = <0x00000000>;
            nand-bus-width = <0x00000008>;
            nand-ecc-mode = "hw";
            nand-ecc-strength = <0x00000010>;
            nand-ecc-step-size = <0x00000400>;
        };
    };
    crypto@fe380000 {
        compatible = "rockchip,rk3568-crypto";
        reg = <0x00000000 0xfe380000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000004 0x00000004>;
        clocks = <0x0000001f 0x0000006a 0x0000001f 0x0000006b 0x0000001f 0x0000006c 0x0000001f 0x0000006d>;
        clock-names = "aclk", "hclk", "sclk", "apb_pclk";
        assigned-clocks = <0x0000001f 0x0000006c>;
        assigned-clock-rates = <0x0bebc200>;
        resets = <0x0000001f 0x00000069>;
        reset-names = "crypto-rst";
        status = "disabled";
        phandle = <0x0000019a>;
    };
    rng@fe388000 {
        compatible = "rockchip,cryptov2-rng";
        reg = <0x00000000 0xfe388000 0x00000000 0x00002000>;
        clocks = <0x0000001f 0x00000070 0x0000001f 0x0000006f>;
        clock-names = "clk_trng", "hclk_trng";
        resets = <0x0000001f 0x0000006d>;
        reset-names = "reset";
        status = "okay";
        phandle = <0x0000019b>;
    };
    otp@fe38c000 {
        compatible = "rockchip,rk3568-otp";
        reg = <0x00000000 0xfe38c000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000073 0x0000001f 0x00000072 0x0000001f 0x00000071 0x0000001f 0x00000181>;
        clock-names = "usr", "sbpi", "apb", "phy";
        resets = <0x0000001f 0x000001cf>;
        reset-names = "otp_phy";
        phandle = <0x0000019c>;
        cpu-code@2 {
            reg = <0x00000002 0x00000002>;
            phandle = <0x0000000f>;
        };
        cpu-version@8 {
            reg = <0x00000008 0x00000001>;
            bits = <0x00000003 0x00000003>;
            phandle = <0x0000000e>;
        };
        mbist-vmin@9 {
            reg = <0x00000009 0x00000001>;
            bits = <0x00000000 0x00000004>;
            phandle = <0x00000008>;
        };
        id@a {
            reg = <0x0000000a 0x00000010>;
            phandle = <0x0000000d>;
        };
        cpu-leakage@1a {
            reg = <0x0000001a 0x00000001>;
            phandle = <0x00000006>;
        };
        log-leakage@1b {
            reg = <0x0000001b 0x00000001>;
            phandle = <0x000000a9>;
        };
        npu-leakage@1c {
            reg = <0x0000001c 0x00000001>;
            phandle = <0x00000060>;
        };
        gpu-leakage@1d {
            reg = <0x0000001d 0x00000001>;
            phandle = <0x00000065>;
        };
        core-pvtm@2a {
            reg = <0x0000002a 0x00000002>;
            phandle = <0x00000007>;
        };
    };
    i2s@fe400000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe400000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000034 0x00000004>;
        clocks = <0x0000001f 0x0000003f 0x0000001f 0x00000043 0x0000001f 0x00000039>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000000>;
        dma-names = "tx";
        resets = <0x0000001f 0x00000050 0x0000001f 0x00000051>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000121>;
    };
    i2s@fe410000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe410000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000035 0x00000004>;
        clocks = <0x0000001f 0x00000047 0x0000001f 0x0000004b 0x0000001f 0x0000003a>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000002 0x000000b5 0x00000003>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000052 0x0000001f 0x00000053>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b6 0x000000b7 0x000000b8 0x000000b9>;
        status = "disabled";
        rockchip,clk-trcm = <0x00000001>;
        phandle = <0x000000c6>;
    };
    i2s@fe420000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe420000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000036 0x00000004>;
        clocks = <0x0000001f 0x0000004f 0x0000001f 0x0000004f 0x0000001f 0x0000003b>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000004 0x000000b5 0x00000005>;
        dma-names = "tx", "rx";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ba 0x000000bb 0x000000bc 0x000000bd>;
        status = "disabled";
        phandle = <0x0000019d>;
    };
    i2s@fe430000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe430000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000037 0x00000004>;
        clocks = <0x0000001f 0x00000053 0x0000001f 0x00000057 0x0000001f 0x0000003c>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000006 0x000000b5 0x00000007>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000055 0x0000001f 0x00000056>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000be 0x000000bf 0x000000c0 0x000000c1>;
        status = "okay";
        phandle = <0x0000011d>;
    };
    pdm@fe440000 {
        compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
        reg = <0x00000000 0xfe440000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000005a 0x0000001f 0x00000059>;
        clock-names = "pdm_clk", "pdm_hclk";
        dmas = <0x000000b5 0x00000009>;
        dma-names = "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c2 0x000000c3 0x000000c4 0x000000c5>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000123>;
    };
    vad@fe450000 {
        compatible = "rockchip,rk3568-vad";
        reg = <0x00000000 0xfe450000 0x00000000 0x00010000>;
        reg-names = "vad";
        clocks = <0x0000001f 0x0000005b>;
        clock-names = "hclk";
        interrupts = <0x00000000 0x00000089 0x00000004>;
        rockchip,audio-src = <0x000000c6>;
        rockchip,det-channel = <0x00000000>;
        rockchip,mode = <0x00000000>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        rockchip,buffer-time-ms = <0x00000080>;
        phandle = <0x00000128>;
    };
    spdif@fe460000 {
        compatible = "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfe460000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000066 0x00000004>;
        dmas = <0x000000b5 0x00000001>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x0000001f 0x0000005f 0x0000001f 0x0000005c>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c7>;
        status = "okay";
        phandle = <0x00000126>;
    };
    audpwm@fe470000 {
        compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
        reg = <0x00000000 0xfe470000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000063 0x0000001f 0x00000060>;
        clock-names = "clk", "hclk";
        dmas = <0x000000b5 0x00000008>;
        dma-names = "tx";
        #sound-dai-cells = <0x00000000>;
        rockchip,sample-width-bits = <0x0000000b>;
        rockchip,interpolat-points = <0x00000001>;
        status = "disabled";
        phandle = <0x0000019e>;
    };
    codec-digital@fe478000 {
        compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
        reg = <0x00000000 0xfe478000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000067 0x0000001f 0x00000066 0x0000001f 0x00000065 0x0000001f 0x00000064>;
        clock-names = "adc", "dac", "i2c", "pclk";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c8>;
        resets = <0x0000001f 0x0000005f>;
        reset-names = "reset";
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000011e>;
    };
    dmac@fe530000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe530000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x0000000e 0x00000004 0x00000000 0x0000000d 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x0000003f>;
    };
    dmac@fe550000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe550000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000010 0x00000004 0x00000000 0x0000000f 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x000000b5>;
    };
    rkscr@fe560000 {
        compatible = "rockchip-scr";
        reg = <0x00000000 0xfe560000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000061 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c9>;
        clocks = <0x0000001f 0x00000114>;
        clock-names = "g_pclk_sim_card";
        status = "disabled";
        phandle = <0x0000019f>;
    };
    can@fe570000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe570000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000001 0x00000004>;
        clocks = <0x0000001f 0x00000141 0x0000001f 0x00000140>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000155 0x0000001f 0x00000154>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000141>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ca>;
        phandle = <0x000001a0>;
    };
    can@fe580000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe580000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000002 0x00000004>;
        clocks = <0x0000001f 0x00000143 0x0000001f 0x00000142>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000157 0x0000001f 0x00000156>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000143>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cb>;
        phandle = <0x000001a1>;
    };
    can@fe590000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe590000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000003 0x00000004>;
        clocks = <0x0000001f 0x00000145 0x0000001f 0x00000144>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000159 0x0000001f 0x00000158>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000145>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cc>;
        phandle = <0x000001a2>;
    };
    i2c@fe5a0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5a0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000148 0x0000001f 0x00000147>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002f 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cd>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a3>;
        gt1x@14 {
            compatible = "goodix,gt1x";
            reg = <0x00000014>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000ce>;
            goodix,rst-gpio = <0x00000035 0x0000000e 0x00000000>;
            goodix,irq-gpio = <0x00000035 0x0000000d 0x00000008>;
            power-supply = <0x00000092>;
            status = "disabled";
            phandle = <0x000001a4>;
        };
    };
    i2c@fe5b0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5b0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014a 0x0000001f 0x00000149>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000030 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cf>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001a5>;
        gc2145@3c {
            status = "okay";
            compatible = "galaxycore,gc2145";
            reg = <0x0000003c>;
            clocks = <0x0000001f 0x000000d6>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d0 0x000000d1 0x000000d2>;
            power-gpios = <0x0000007b 0x0000001c 0x00000000>;
            pwdn-gpios = <0x0000007b 0x0000001a 0x00000000>;
            rockchip,camera-module-index = <0x00000001>;
            rockchip,camera-module-facing = "front";
            rockchip,camera-module-name = "CameraKing";
            rockchip,camera-module-lens-name = "Largan";
            phandle = <0x000001a6>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d3>;
                    phandle = <0x00000072>;
                };
            };
        };
        ov5695@36 {
            status = "okay";
            compatible = "ovti,ov5695";
            reg = <0x00000036>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000000>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000000>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "TongJu";
            rockchip,camera-module-lens-name = "CHT842-MD";
            phandle = <0x000001a7>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d5>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x00000108>;
                };
            };
        };
        gc8034@37 {
            compatible = "galaxycore,gc8034";
            status = "okay";
            reg = <0x00000037>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000001>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000001>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "RK-CMK-8M-2-v1";
            rockchip,camera-module-lens-name = "CK8401";
            phandle = <0x000001a8>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d6>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x00000109>;
                };
            };
        };
    };
    i2c@fe5c0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5c0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014c 0x0000001f 0x0000014b>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000031 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d7>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a9>;
    };
    i2c@fe5d0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5d0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014e 0x0000001f 0x0000014d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000032 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d8>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001aa>;
    };
    i2c@fe5e0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5e0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000150 0x0000001f 0x0000014f>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000033 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d9>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001ab>;
        mxc6655xa@15 {
            status = "okay";
            compatible = "gs_mxc6655xa";
            pinctrl-names = "default";
            pinctrl-0 = <0x000000da>;
            reg = <0x00000015>;
            irq-gpio = <0x0000007b 0x00000011 0x00000008>;
            irq_enable = <0x00000000>;
            poll_delay_ms = <0x0000001e>;
            type = <0x00000002>;
            power-off-in-suspend = <0x00000001>;
            layout = <0x00000001>;
            phandle = <0x000001ac>;
        };
    };
    timer@fe5f0000 {
        compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
        reg = <0x00000000 0xfe5f0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006d 0x00000004>;
        clocks = <0x0000001f 0x0000016c 0x0000001f 0x0000016d>;
        clock-names = "pclk", "timer";
        phandle = <0x000001ad>;
    };
    watchdog@fe600000 {
        compatible = "snps,dw-wdt";
        reg = <0x00000000 0xfe600000 0x00000000 0x00000100>;
        clocks = <0x0000001f 0x00000116 0x0000001f 0x00000115>;
        clock-names = "tclk", "pclk";
        interrupts = <0x00000000 0x00000095 0x00000004>;
        status = "okay";
        phandle = <0x000001ae>;
    };
    spi@fe610000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe610000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000067 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000152 0x0000001f 0x00000151>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000014 0x0000003f 0x00000015>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000db 0x000000dc 0x000000dd>;
        pinctrl-1 = <0x000000db 0x000000dc 0x000000de>;
        status = "disabled";
        phandle = <0x000001af>;
    };
    spi@fe620000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe620000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000068 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000154 0x0000001f 0x00000153>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000016 0x0000003f 0x00000017>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000df 0x000000e0 0x000000e1>;
        pinctrl-1 = <0x000000df 0x000000e0 0x000000e2>;
        status = "disabled";
        phandle = <0x000001b0>;
    };
    spi@fe630000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe630000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000069 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000156 0x0000001f 0x00000155>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000018 0x0000003f 0x00000019>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e3 0x000000e4 0x000000e5>;
        pinctrl-1 = <0x000000e3 0x000000e4 0x000000e6>;
        status = "disabled";
        phandle = <0x000001b1>;
    };
    spi@fe640000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe640000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006a 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000158 0x0000001f 0x00000157>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x0000001a 0x0000003f 0x0000001b>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e7 0x000000e8 0x000000e9>;
        pinctrl-1 = <0x000000e7 0x000000e8 0x000000ea>;
        status = "disabled";
        phandle = <0x000001b2>;
    };
    serial@fe650000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe650000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000075 0x00000004>;
        clocks = <0x0000001f 0x0000011f 0x0000001f 0x0000011c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000002 0x0000003f 0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000eb 0x000000ec>;
        status = "okay";
        phandle = <0x000001b3>;
    };
    serial@fe660000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe660000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000076 0x00000004>;
        clocks = <0x0000001f 0x00000123 0x0000001f 0x00000120>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000004 0x0000003f 0x00000005>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ed>;
        status = "disabled";
        phandle = <0x000001b4>;
    };
    serial@fe670000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe670000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000077 0x00000004>;
        clocks = <0x0000001f 0x00000127 0x0000001f 0x00000124>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000006 0x0000003f 0x00000007>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ee>;
        status = "disabled";
        phandle = <0x000001b5>;
    };
    serial@fe680000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe680000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000078 0x00000004>;
        clocks = <0x0000001f 0x0000012b 0x0000001f 0x00000128>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000008 0x0000003f 0x00000009>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ef>;
        status = "disabled";
        phandle = <0x000001b6>;
    };
    serial@fe690000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe690000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000079 0x00000004>;
        clocks = <0x0000001f 0x0000012f 0x0000001f 0x0000012c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000a 0x0000003f 0x0000000b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f0>;
        status = "disabled";
        phandle = <0x000001b7>;
    };
    serial@fe6a0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6a0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007a 0x00000004>;
        clocks = <0x0000001f 0x00000133 0x0000001f 0x00000130>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000c 0x0000003f 0x0000000d>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f1>;
        status = "disabled";
        phandle = <0x000001b8>;
    };
    serial@fe6b0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6b0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007b 0x00000004>;
        clocks = <0x0000001f 0x00000137 0x0000001f 0x00000134>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000e 0x0000003f 0x0000000f>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f2>;
        status = "disabled";
        phandle = <0x000001b9>;
    };
    serial@fe6c0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6c0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007c 0x00000004>;
        clocks = <0x0000001f 0x0000013b 0x0000001f 0x00000138>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000010 0x0000003f 0x00000011>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f3>;
        status = "disabled";
        phandle = <0x000001ba>;
    };
    serial@fe6d0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6d0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007d 0x00000004>;
        clocks = <0x0000001f 0x0000013f 0x0000001f 0x0000013c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000012 0x0000003f 0x00000013>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f4>;
        status = "disabled";
        phandle = <0x000001bb>;
    };
    pwm@fe6e0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f5>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x0000011f>;
    };
    pwm@fe6e0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f6>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x00000120>;
    };
    pwm@fe6e0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f7>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bc>;
    };
    pwm@fe6e0030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfe6e0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000053 0x00000004 0x00000000 0x00000057 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f8>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x000001bd>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000ba 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000bd 0x00000066 0x000000ea 0x00000073 0x000000e3 0x00000072 0x000000e2 0x000000d9 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x00000072 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
    };
    pwm@fe6f0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f9>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001be>;
    };
    pwm@fe6f0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fa>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bf>;
    };
    pwm@fe6f0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fb>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c0>;
    };
    pwm@fe6f0030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000054 0x00000004 0x00000000 0x00000058 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fc>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c1>;
    };
    pwm@fe700000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fd>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c2>;
    };
    pwm@fe700010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fe>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c3>;
    };
    pwm@fe700020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000ff>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c4>;
    };
    pwm@fe700030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000055 0x00000004 0x00000000 0x00000059 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000100>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c5>;
    };
    tsadc@fe710000 {
        compatible = "rockchip,rk3568-tsadc";
        reg = <0x00000000 0xfe710000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000073 0x00000004>;
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000111 0x0000001f 0x0000010f>;
        clock-names = "tsadc", "apb_pclk";
        assigned-clocks = <0x0000001f 0x00000110 0x0000001f 0x00000111>;
        assigned-clock-rates = <0x01036640 0x000aae60>;
        resets = <0x0000001f 0x00000182 0x0000001f 0x00000181 0x0000001f 0x000001d7>;
        reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
        #thermal-sensor-cells = <0x00000001>;
        rockchip,hw-tshut-temp = <0x0001d4c0>;
        rockchip,hw-tshut-mode = <0x00000000>;
        rockchip,hw-tshut-polarity = <0x00000000>;
        pinctrl-names = "gpio", "otpout";
        pinctrl-0 = <0x00000101>;
        pinctrl-1 = <0x00000102>;
        status = "okay";
        phandle = <0x0000001b>;
    };
    saradc@fe720000 {
        compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
        reg = <0x00000000 0xfe720000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000005d 0x00000004>;
        #io-channel-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        clock-names = "saradc", "apb_pclk";
        resets = <0x0000001f 0x00000180>;
        reset-names = "saradc-apb";
        status = "okay";
        vref-supply = <0x00000103>;
        phandle = <0x0000011b>;
    };
    mailbox@fe780000 {
        compatible = "rockchip,rk3568-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x00000000 0xfe780000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b7 0x00000004 0x00000000 0x000000b8 0x00000004 0x00000000 0x000000b9 0x00000004 0x00000000 0x000000ba 0x00000004>;
        clocks = <0x0000001f 0x0000011b>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x00000001>;
        status = "disabled";
        phandle = <0x000001c6>;
    };
    phy@fe830000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe830000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000022 0x0000001f 0x0000017d 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000022>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c6 0x0000001f 0x000001c7>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000105>;
        status = "okay";
        phandle = <0x00000020>;
    };
    phy@fe840000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe840000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000025 0x0000001f 0x0000017e 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000025>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c8 0x0000001f 0x000001c9>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000106>;
        status = "disabled";
        phandle = <0x00000022>;
    };
    mipi-dphy@fe850000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x0000008e>;
    };
    video-phy@fe850000 {
        compatible = "rockchip,rk3568-video-phy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000 0x00000000 0xfe060000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a 0x0000001f 0x000000e8>;
        clock-names = "ref", "pclk_phy", "pclk_host";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "rst";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000002e>;
    };
    mipi-dphy@fe860000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe860000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000019 0x0000001f 0x0000017b>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy1_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bc>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "disabled";
        phandle = <0x00000097>;
    };
    csi2-dphy-hw@fe870000 {
        compatible = "rockchip,rk3568-csi2-dphy-hw";
        reg = <0x00000000 0xfe870000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000179>;
        clock-names = "pclk";
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x00000107>;
    };
    csi2-dphy0 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "okay";
        phandle = <0x000001c7>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000108>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x000000d5>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000109>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x000000d6>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000010a>;
                    phandle = <0x00000077>;
                };
            };
        };
    };
    csi2-dphy1 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c8>;
    };
    csi2-dphy2 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c9>;
    };
    usb2-phy@fe8a0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8a0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000087 0x00000004>;
        clocks = <0x00000031 0x00000013>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        assigned-clocks = <0x0000001f 0x0000000b>;
        assigned-clock-parents = <0x00000024>;
        clock-output-names = "usb480m_phy";
        rockchip,usbgrf = <0x0000010b>;
        status = "okay";
        phandle = <0x00000024>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000025>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            vbus-supply = <0x0000010d>;
            phandle = <0x00000023>;
        };
    };
    usb2-phy@fe8b0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8b0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000088 0x00000004>;
        clocks = <0x00000031 0x00000015>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        rockchip,usbgrf = <0x0000010e>;
        status = "okay";
        phandle = <0x00000026>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000028>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000027>;
        };
    };
    pinctrl {
        compatible = "rockchip,rk3568-pinctrl";
        rockchip,grf = <0x00000032>;
        rockchip,pmu = <0x00000033>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000010f>;
        phandle = <0x00000110>;
        gpio@fdd60000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfdd60000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000021 0x00000004>;
            clocks = <0x00000031 0x0000002e 0x00000031 0x0000000c>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000000 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000035>;
        };
        gpio@fe740000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe740000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000022 0x00000004>;
            clocks = <0x0000001f 0x00000163 0x0000001f 0x00000164>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000020 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000093>;
        };
        gpio@fe750000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe750000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000023 0x00000004>;
            clocks = <0x0000001f 0x00000165 0x0000001f 0x00000166>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000040 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000012e>;
        };
        gpio@fe760000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe760000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000024 0x00000004>;
            clocks = <0x0000001f 0x00000167 0x0000001f 0x00000168>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000060 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000007b>;
        };
        gpio@fe770000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe770000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000025 0x00000004>;
            clocks = <0x0000001f 0x00000169 0x0000001f 0x0000016a>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000080 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000009c>;
        };
        pcfg-pull-up {
            bias-pull-up;
            phandle = <0x00000113>;
        };
        pcfg-pull-down {
            bias-pull-down;
            phandle = <0x0000011a>;
        };
        pcfg-pull-none {
            bias-disable;
            phandle = <0x00000111>;
        };
        pcfg-pull-none-drv-level-1 {
            bias-disable;
            drive-strength = <0x00000001>;
            phandle = <0x00000115>;
        };
        pcfg-pull-none-drv-level-2 {
            bias-disable;
            drive-strength = <0x00000002>;
            phandle = <0x00000114>;
        };
        pcfg-pull-none-drv-level-3 {
            bias-disable;
            drive-strength = <0x00000003>;
            phandle = <0x00000119>;
        };
        pcfg-pull-up-drv-level-1 {
            bias-pull-up;
            drive-strength = <0x00000001>;
            phandle = <0x00000118>;
        };
        pcfg-pull-up-drv-level-2 {
            bias-pull-up;
            drive-strength = <0x00000002>;
            phandle = <0x00000112>;
        };
        pcfg-pull-none-smt {
            bias-disable;
            input-schmitt-enable;
            phandle = <0x00000116>;
        };
        pcfg-output-low {
            output-low;
            phandle = <0x00000117>;
        };
        acodec {
            acodec-pins {
                rockchip,pins = <0x00000001 0x00000009 0x00000005 0x00000111 0x00000001 0x00000001 0x00000005 0x00000111 0x00000001 0x00000000 0x00000005 0x00000111 0x00000001 0x00000007 0x00000005 0x00000111 0x00000001 0x00000008 0x00000005 0x00000111 0x00000001 0x00000003 0x00000005 0x00000111 0x00000001 0x00000005 0x00000005 0x00000111>;
                phandle = <0x000000c8>;
            };
        };
        cam {
            cam-clkout0 {
                rockchip,pins = <0x00000004 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000d4>;
            };
            camera-pwr {
                rockchip,pins = <0x00000000 0x00000011 0x00000000 0x00000111>;
                phandle = <0x00000133>;
            };
        };
        can0 {
            can0m1-pins {
                rockchip,pins = <0x00000002 0x00000002 0x00000004 0x00000111 0x00000002 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000ca>;
            };
        };
        can1 {
            can1m1-pins {
                rockchip,pins = <0x00000004 0x00000012 0x00000003 0x00000111 0x00000004 0x00000013 0x00000003 0x00000111>;
                phandle = <0x000000cb>;
            };
        };
        can2 {
            can2m1-pins {
                rockchip,pins = <0x00000002 0x00000009 0x00000004 0x00000111 0x00000002 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000cc>;
            };
        };
        cif {
            cif-clk {
                rockchip,pins = <0x00000004 0x00000010 0x00000001 0x00000111>;
                phandle = <0x000000d0>;
            };
            cif-dvp-clk {
                rockchip,pins = <0x00000004 0x00000011 0x00000001 0x00000111 0x00000004 0x0000000e 0x00000001 0x00000111 0x00000004 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x000000d1>;
            };
            cif-dvp-bus16 {
                rockchip,pins = <0x00000003 0x0000001e 0x00000001 0x00000111 0x00000003 0x0000001f 0x00000001 0x00000111 0x00000004 0x00000000 0x00000001 0x00000111 0x00000004 0x00000001 0x00000001 0x00000111 0x00000004 0x00000002 0x00000001 0x00000111 0x00000004 0x00000003 0x00000001 0x00000111 0x00000004 0x00000004 0x00000001 0x00000111 0x00000004 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000d2>;
            };
        };
        clk32k {
            clk32k-out0 {
                rockchip,pins = <0x00000000 0x00000008 0x00000002 0x00000111>;
                phandle = <0x0000001e>;
            };
        };
        ebc {
            ebc-pins {
                rockchip,pins = <0x00000004 0x00000010 0x00000002 0x00000111 0x00000004 0x0000000b 0x00000002 0x00000111 0x00000004 0x0000000c 0x00000002 0x00000111 0x00000004 0x00000006 0x00000002 0x00000111 0x00000004 0x00000011 0x00000002 0x00000111 0x00000003 0x00000016 0x00000002 0x00000111 0x00000003 0x00000017 0x00000002 0x00000111 0x00000003 0x00000018 0x00000002 0x00000111 0x00000003 0x00000019 0x00000002 0x00000111 0x00000003 0x0000001a 0x00000002 0x00000111 0x00000003 0x0000001b 0x00000002 0x00000111 0x00000003 0x0000001c 0x00000002 0x00000111 0x00000003 0x0000001d 0x00000002 0x00000111 0x00000003 0x0000001e 0x00000002 0x00000111 0x00000003 0x0000001f 0x00000002 0x00000111 0x00000004 0x00000000 0x00000002 0x00000111 0x00000004 0x00000001 0x00000002 0x00000111 0x00000004 0x00000002 0x00000002 0x00000111 0x00000004 0x00000003 0x00000002 0x00000111 0x00000004 0x00000004 0x00000002 0x00000111 0x00000004 0x00000005 0x00000002 0x00000111 0x00000004 0x0000000e 0x00000002 0x00000111 0x00000004 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x00000068>;
            };
        };
        gmac1 {
            gmac1m0-miim {
                rockchip,pins = <0x00000003 0x00000014 0x00000003 0x00000111 0x00000003 0x00000015 0x00000003 0x00000111>;
                phandle = <0x0000007c>;
            };
            gmac1m0-rx-bus2 {
                rockchip,pins = <0x00000003 0x00000009 0x00000003 0x00000111 0x00000003 0x0000000a 0x00000003 0x00000111 0x00000003 0x0000000b 0x00000003 0x00000111>;
                phandle = <0x0000007e>;
            };
        };
        hdmitx {
            hdmitxm0-cec {
                rockchip,pins = <0x00000004 0x00000019 0x00000001 0x00000111>;
                phandle = <0x000000a2>;
            };
            hdmitx-scl {
                rockchip,pins = <0x00000004 0x00000017 0x00000001 0x00000111>;
                phandle = <0x000000a0>;
            };
            hdmitx-sda {
                rockchip,pins = <0x00000004 0x00000018 0x00000001 0x00000111>;
                phandle = <0x000000a1>;
            };
        };
        i2c0 {
            i2c0-xfer {
                rockchip,pins = <0x00000000 0x00000009 0x00000001 0x00000116 0x00000000 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x00000034>;
            };
        };
        i2c1 {
            i2c1-xfer {
                rockchip,pins = <0x00000000 0x0000000b 0x00000001 0x00000116 0x00000000 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cd>;
            };
        };
        i2c2 {
            i2c2m1-xfer {
                rockchip,pins = <0x00000004 0x0000000d 0x00000001 0x00000116 0x00000004 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cf>;
            };
        };
        i2c3 {
            i2c3m0-xfer {
                rockchip,pins = <0x00000001 0x00000001 0x00000001 0x00000116 0x00000001 0x00000000 0x00000001 0x00000116>;
                phandle = <0x000000d7>;
            };
        };
        i2c4 {
            i2c4m0-xfer {
                rockchip,pins = <0x00000004 0x0000000b 0x00000001 0x00000116 0x00000004 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x000000d8>;
            };
        };
        i2c5 {
            i2c5m0-xfer {
                rockchip,pins = <0x00000003 0x0000000b 0x00000004 0x00000116 0x00000003 0x0000000c 0x00000004 0x00000116>;
                phandle = <0x000000d9>;
            };
        };
        i2s1 {
            i2s1m0-lrcktx {
                rockchip,pins = <0x00000001 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000b7>;
            };
            i2s1m0-sclktx {
                rockchip,pins = <0x00000001 0x00000003 0x00000001 0x00000111>;
                phandle = <0x000000b6>;
            };
            i2s1m0-sdi0 {
                rockchip,pins = <0x00000001 0x0000000b 0x00000001 0x00000111>;
                phandle = <0x000000b8>;
            };
            i2s1m0-sdo0 {
                rockchip,pins = <0x00000001 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000b9>;
            };
        };
        i2s2 {
            i2s2m0-lrcktx {
                rockchip,pins = <0x00000002 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000bb>;
            };
            i2s2m0-sclktx {
                rockchip,pins = <0x00000002 0x00000012 0x00000001 0x00000111>;
                phandle = <0x000000ba>;
            };
            i2s2m0-sdi {
                rockchip,pins = <0x00000002 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000bc>;
            };
            i2s2m0-sdo {
                rockchip,pins = <0x00000002 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000bd>;
            };
        };
        i2s3 {
            i2s3m1-lrck {
                rockchip,pins = <0x00000004 0x00000014 0x00000005 0x00000111>;
                phandle = <0x000000bf>;
            };
            i2s3m1-mclk {
                rockchip,pins = <0x00000004 0x00000012 0x00000005 0x00000111>;
                phandle = <0x0000003d>;
            };
            i2s3m1-sclk {
                rockchip,pins = <0x00000004 0x00000013 0x00000005 0x00000111>;
                phandle = <0x000000be>;
            };
            i2s3m1-sdi {
                rockchip,pins = <0x00000004 0x00000016 0x00000005 0x00000111>;
                phandle = <0x000000c0>;
            };
            i2s3m1-sdo {
                rockchip,pins = <0x00000004 0x00000015 0x00000005 0x00000111>;
                phandle = <0x000000c1>;
            };
        };
        lcdc {
            lcdc-ctl {
                rockchip,pins = <0x00000003 0x00000000 0x00000001 0x00000111 0x00000002 0x00000018 0x00000001 0x00000111 0x00000002 0x00000019 0x00000001 0x00000111 0x00000002 0x0000001a 0x00000001 0x00000111 0x00000002 0x0000001b 0x00000001 0x00000111 0x00000002 0x0000001c 0x00000001 0x00000111 0x00000002 0x0000001d 0x00000001 0x00000111 0x00000002 0x0000001e 0x00000001 0x00000111 0x00000002 0x0000001f 0x00000001 0x00000111 0x00000003 0x00000001 0x00000001 0x00000111 0x00000003 0x00000002 0x00000001 0x00000111 0x00000003 0x00000003 0x00000001 0x00000111 0x00000003 0x00000004 0x00000001 0x00000111 0x00000003 0x00000005 0x00000001 0x00000111 0x00000003 0x00000006 0x00000001 0x00000111 0x00000003 0x00000007 0x00000001 0x00000111 0x00000003 0x00000008 0x00000001 0x00000111 0x00000003 0x00000009 0x00000001 0x00000111 0x00000003 0x0000000a 0x00000001 0x00000111 0x00000003 0x0000000b 0x00000001 0x00000111 0x00000003 0x0000000c 0x00000001 0x00000111 0x00000003 0x0000000d 0x00000001 0x00000111 0x00000003 0x0000000e 0x00000001 0x00000111 0x00000003 0x0000000f 0x00000001 0x00000111 0x00000003 0x00000010 0x00000001 0x00000111 0x00000003 0x00000013 0x00000001 0x00000111 0x00000003 0x00000011 0x00000001 0x00000111 0x00000003 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000030>;
            };
        };
        pdm {
            pdmm1-clk1 {
                rockchip,pins = <0x00000004 0x00000000 0x00000004 0x00000111>;
                phandle = <0x000000c2>;
            };
            pdmm1-sdi1 {
                rockchip,pins = <0x00000004 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000c3>;
            };
            pdmm1-sdi2 {
                rockchip,pins = <0x00000004 0x00000002 0x00000005 0x00000111>;
                phandle = <0x000000c4>;
            };
            pdmm1-sdi3 {
                rockchip,pins = <0x00000004 0x00000003 0x00000005 0x00000111>;
                phandle = <0x000000c5>;
            };
        };
        pmic {
            pmic_int {
                rockchip,pins = <0x00000000 0x00000003 0x00000000 0x00000113>;
                phandle = <0x00000036>;
            };
            soc_slppin_gpio {
                rockchip,pins = <0x00000000 0x00000002 0x00000000 0x00000117>;
                phandle = <0x00000039>;
            };
            soc_slppin_slp {
                rockchip,pins = <0x00000000 0x00000002 0x00000001 0x00000111>;
                phandle = <0x00000037>;
            };
            soc_slppin_rst {
                rockchip,pins = <0x00000000 0x00000002 0x00000002 0x00000111>;
                phandle = <0x000001ca>;
            };
        };
        pwm0 {
            pwm0m0-pins {
                rockchip,pins = <0x00000000 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x00000041>;
            };
        };
        pwm1 {
            pwm1m0-pins {
                rockchip,pins = <0x00000000 0x00000010 0x00000001 0x00000111>;
                phandle = <0x00000042>;
            };
        };
        pwm2 {
            pwm2m0-pins {
                rockchip,pins = <0x00000000 0x00000011 0x00000001 0x00000111>;
                phandle = <0x00000043>;
            };
        };
        pwm3 {
            pwm3-pins {
                rockchip,pins = <0x00000000 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000044>;
            };
        };
        pwm4 {
            pwm4-pins {
                rockchip,pins = <0x00000000 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000f5>;
            };
        };
        pwm5 {
            pwm5-pins {
                rockchip,pins = <0x00000000 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000f6>;
            };
        };
        pwm6 {
            pwm6-pins {
                rockchip,pins = <0x00000000 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000f7>;
            };
        };
        pwm7 {
            pwm7-pins {
                rockchip,pins = <0x00000000 0x00000016 0x00000001 0x00000111>;
                phandle = <0x000000f8>;
            };
        };
        pwm8 {
            pwm8m0-pins {
                rockchip,pins = <0x00000003 0x00000009 0x00000005 0x00000111>;
                phandle = <0x000000f9>;
            };
        };
        pwm9 {
            pwm9m0-pins {
                rockchip,pins = <0x00000003 0x0000000a 0x00000005 0x00000111>;
                phandle = <0x000000fa>;
            };
        };
        pwm10 {
            pwm10m0-pins {
                rockchip,pins = <0x00000003 0x0000000d 0x00000005 0x00000111>;
                phandle = <0x000000fb>;
            };
        };
        pwm11 {
            pwm11m0-pins {
                rockchip,pins = <0x00000003 0x0000000e 0x00000005 0x00000111>;
                phandle = <0x000000fc>;
            };
        };
        pwm12 {
            pwm12m0-pins {
                rockchip,pins = <0x00000003 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x000000fd>;
            };
        };
        pwm13 {
            pwm13m0-pins {
                rockchip,pins = <0x00000003 0x00000010 0x00000002 0x00000111>;
                phandle = <0x000000fe>;
            };
        };
        pwm14 {
            pwm14m0-pins {
                rockchip,pins = <0x00000003 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000ff>;
            };
        };
        pwm15 {
            pwm15m0-pins {
                rockchip,pins = <0x00000003 0x00000015 0x00000001 0x00000111>;
                phandle = <0x00000100>;
            };
        };
        scr {
            scr-pins {
                rockchip,pins = <0x00000001 0x00000002 0x00000003 0x00000111 0x00000001 0x00000007 0x00000003 0x00000113 0x00000001 0x00000003 0x00000003 0x00000113 0x00000001 0x00000005 0x00000003 0x00000111>;
                phandle = <0x000000c9>;
            };
        };
        sdmmc0 {
            sdmmc0-bus4 {
                rockchip,pins = <0x00000001 0x0000001d 0x00000001 0x00000112 0x00000001 0x0000001e 0x00000001 0x00000112 0x00000001 0x0000001f 0x00000001 0x00000112 0x00000002 0x00000000 0x00000001 0x00000112>;
                phandle = <0x000000ad>;
            };
            sdmmc0-clk {
                rockchip,pins = <0x00000002 0x00000002 0x00000001 0x00000112>;
                phandle = <0x000000ae>;
            };
            sdmmc0-cmd {
                rockchip,pins = <0x00000002 0x00000001 0x00000001 0x00000112>;
                phandle = <0x000000af>;
            };
            sdmmc0-det {
                rockchip,pins = <0x00000000 0x00000004 0x00000001 0x00000113>;
                phandle = <0x000000b0>;
            };
        };
        sdmmc1 {
            sdmmc1-bus4 {
                rockchip,pins = <0x00000002 0x00000003 0x00000001 0x00000112 0x00000002 0x00000004 0x00000001 0x00000112 0x00000002 0x00000005 0x00000001 0x00000112 0x00000002 0x00000006 0x00000001 0x00000112>;
                phandle = <0x000000b2>;
            };
            sdmmc1-clk {
                rockchip,pins = <0x00000002 0x00000008 0x00000001 0x00000112>;
                phandle = <0x000000b4>;
            };
            sdmmc1-cmd {
                rockchip,pins = <0x00000002 0x00000007 0x00000001 0x00000112>;
                phandle = <0x000000b3>;
            };
        };
        spdif {
            spdifm0-tx {
                rockchip,pins = <0x00000001 0x00000004 0x00000004 0x00000111>;
                phandle = <0x000000c7>;
            };
        };
        spi0 {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000111 0x00000000 0x00000015 0x00000002 0x00000111 0x00000000 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000dd>;
            };
            spi0m0-cs0 {
                rockchip,pins = <0x00000000 0x00000016 0x00000002 0x00000111>;
                phandle = <0x000000db>;
            };
            spi0m0-cs1 {
                rockchip,pins = <0x00000000 0x00000014 0x00000002 0x00000111>;
                phandle = <0x000000dc>;
            };
        };
        spi1 {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000111 0x00000002 0x0000000e 0x00000003 0x00000111 0x00000002 0x0000000f 0x00000004 0x00000111>;
                phandle = <0x000000e1>;
            };
            spi1m0-cs0 {
                rockchip,pins = <0x00000002 0x00000010 0x00000004 0x00000111>;
                phandle = <0x000000df>;
            };
            spi1m0-cs1 {
                rockchip,pins = <0x00000002 0x00000016 0x00000003 0x00000111>;
                phandle = <0x000000e0>;
            };
        };
        spi2 {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000111 0x00000002 0x00000012 0x00000004 0x00000111 0x00000002 0x00000013 0x00000004 0x00000111>;
                phandle = <0x000000e5>;
            };
            spi2m0-cs0 {
                rockchip,pins = <0x00000002 0x00000014 0x00000004 0x00000111>;
                phandle = <0x000000e3>;
            };
            spi2m0-cs1 {
                rockchip,pins = <0x00000002 0x00000015 0x00000004 0x00000111>;
                phandle = <0x000000e4>;
            };
        };
        spi3 {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000111 0x00000004 0x00000008 0x00000004 0x00000111 0x00000004 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000e9>;
            };
            spi3m0-cs0 {
                rockchip,pins = <0x00000004 0x00000006 0x00000004 0x00000111>;
                phandle = <0x000000e7>;
            };
            spi3m0-cs1 {
                rockchip,pins = <0x00000004 0x00000007 0x00000004 0x00000111>;
                phandle = <0x000000e8>;
            };
        };
        tsadc {
            tsadc-shutorg {
                rockchip,pins = <0x00000000 0x00000001 0x00000002 0x00000111>;
                phandle = <0x00000102>;
            };
        };
        uart0 {
            uart0-xfer {
                rockchip,pins = <0x00000000 0x00000010 0x00000003 0x00000113 0x00000000 0x00000011 0x00000003 0x00000113>;
                phandle = <0x00000040>;
            };
        };
        uart1 {
            uart1m0-xfer {
                rockchip,pins = <0x00000002 0x0000000b 0x00000002 0x00000113 0x00000002 0x0000000c 0x00000002 0x00000113>;
                phandle = <0x000000eb>;
            };
            uart1m0-ctsn {
                rockchip,pins = <0x00000002 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000ec>;
            };
            uart1m0-rtsn {
                rockchip,pins = <0x00000002 0x0000000d 0x00000002 0x00000111>;
                phandle = <0x00000130>;
            };
        };
        uart2 {
            uart2m0-xfer {
                rockchip,pins = <0x00000000 0x00000018 0x00000001 0x00000113 0x00000000 0x00000019 0x00000001 0x00000113>;
                phandle = <0x000000ed>;
            };
        };
        uart3 {
            uart3m0-xfer {
                rockchip,pins = <0x00000001 0x00000000 0x00000002 0x00000113 0x00000001 0x00000001 0x00000002 0x00000113>;
                phandle = <0x000000ee>;
            };
        };
        uart4 {
            uart4m0-xfer {
                rockchip,pins = <0x00000001 0x00000004 0x00000002 0x00000113 0x00000001 0x00000006 0x00000002 0x00000113>;
                phandle = <0x000000ef>;
            };
        };
        uart5 {
            uart5m0-xfer {
                rockchip,pins = <0x00000002 0x00000001 0x00000003 0x00000113 0x00000002 0x00000002 0x00000003 0x00000113>;
                phandle = <0x000000f0>;
            };
        };
        uart6 {
            uart6m0-xfer {
                rockchip,pins = <0x00000002 0x00000003 0x00000003 0x00000113 0x00000002 0x00000004 0x00000003 0x00000113>;
                phandle = <0x000000f1>;
            };
        };
        uart7 {
            uart7m0-xfer {
                rockchip,pins = <0x00000002 0x00000005 0x00000003 0x00000113 0x00000002 0x00000006 0x00000003 0x00000113>;
                phandle = <0x000000f2>;
            };
        };
        uart8 {
            uart8m0-xfer {
                rockchip,pins = <0x00000002 0x00000016 0x00000002 0x00000113 0x00000002 0x00000015 0x00000003 0x00000113>;
                phandle = <0x000000f3>;
            };
        };
        uart9 {
            uart9m0-xfer {
                rockchip,pins = <0x00000002 0x00000007 0x00000003 0x00000113 0x00000002 0x00000008 0x00000003 0x00000113>;
                phandle = <0x000000f4>;
            };
        };
        spi0-hs {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000118 0x00000000 0x00000015 0x00000002 0x00000118 0x00000000 0x0000000e 0x00000002 0x00000118>;
                phandle = <0x000000de>;
            };
        };
        spi1-hs {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000118 0x00000002 0x0000000e 0x00000003 0x00000118 0x00000002 0x0000000f 0x00000004 0x00000118>;
                phandle = <0x000000e2>;
            };
        };
        spi2-hs {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000118 0x00000002 0x00000012 0x00000004 0x00000118 0x00000002 0x00000013 0x00000004 0x00000118>;
                phandle = <0x000000e6>;
            };
        };
        spi3-hs {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000118 0x00000004 0x00000008 0x00000004 0x00000118 0x00000004 0x0000000a 0x00000004 0x00000118>;
                phandle = <0x000000ea>;
            };
        };
        gmac-txd-level3 {
            gmac1m0-tx-bus2-level3 {
                rockchip,pins = <0x00000003 0x0000000d 0x00000003 0x00000119 0x00000003 0x0000000e 0x00000003 0x00000119 0x00000003 0x0000000f 0x00000003 0x00000111>;
                phandle = <0x0000007d>;
            };
            gmac1m0-rgmii-bus-level3 {
                rockchip,pins = <0x00000003 0x00000004 0x00000003 0x00000111 0x00000003 0x00000005 0x00000003 0x00000111 0x00000003 0x00000002 0x00000003 0x00000119 0x00000003 0x00000003 0x00000003 0x00000119>;
                phandle = <0x00000080>;
            };
        };
        gmac-txc-level2 {
            gmac1m0-rgmii-clk-level2 {
                rockchip,pins = <0x00000003 0x00000007 0x00000003 0x00000111 0x00000003 0x00000006 0x00000003 0x00000114>;
                phandle = <0x0000007f>;
            };
        };
        gpio-func {
            tsadc-gpio-func {
                rockchip,pins = <0x00000000 0x00000001 0x00000000 0x00000111>;
                phandle = <0x00000101>;
            };
        };
        mxc6655xa {
            mxc6655xa_irq_gpio {
                rockchip,pins = <0x00000003 0x00000011 0x00000000 0x00000111>;
                phandle = <0x000000da>;
            };
        };
        touch {
            touch-gpio {
                rockchip,pins = <0x00000000 0x0000000d 0x00000000 0x00000113 0x00000000 0x0000000e 0x00000000 0x00000111>;
                phandle = <0x000000ce>;
            };
        };
        sdio-pwrseq {
            wifi-enable-h {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x0000012d>;
            };
        };
        usb {
            vcc5v0-host-en {
                rockchip,pins = <0x00000000 0x00000006 0x00000000 0x00000111>;
                phandle = <0x0000012a>;
            };
            vcc5v0-otg-en {
                rockchip,pins = <0x00000000 0x00000005 0x00000000 0x00000111>;
                phandle = <0x0000012b>;
            };
        };
        wireless-bluetooth {
            uart8-gpios {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x000001cb>;
            };
            uart1-gpios {
                rockchip,pins = <0x00000002 0x0000000d 0x00000000 0x00000111>;
                phandle = <0x00000131>;
            };
        };
        headphone {
            hp-det {
                rockchip,pins = <0x00000004 0x0000000b 0x00000000 0x0000011a>;
                phandle = <0x00000132>;
            };
        };
        lcd0 {
            lcd-rst-gpio {
                rockchip,pins = <0x00000001 0x00000005 0x00000000 0x00000111>;
                phandle = <0x00000094>;
            };
        };
        lcd1 {
            lcd1-rst-gpio {
                rockchip,pins = <0x00000004 0x00000016 0x00000000 0x00000111>;
                phandle = <0x0000009d>;
            };
        };
        wireless-wlan {
            wifi-host-wake-irq {
                rockchip,pins = <0x00000002 0x0000000a 0x00000000 0x0000011a>;
                phandle = <0x0000012f>;
            };
        };
        fddis_ctr {
            dis-ctl {
                rockchip,pins = <0x00000000 0x0000000b 0x00000000 0x00000113 0x00000000 0x0000000c 0x00000000 0x00000113>;
                phandle = <0x0000010f>;
            };
        };
    };
    adc-keys {
        compatible = "adc-keys";
        io-channels = <0x0000011b 0x00000000>;
        io-channel-names = "buttons";
        keyup-threshold-microvolt = <0x001b7740>;
        poll-interval = <0x00000064>;
        phandle = <0x000001cc>;
        vol-up-key {
            label = "volume up";
            linux,code = <0x00000073>;
            press-threshold-microvolt = <0x000006d6>;
        };
        vol-down-key {
            label = "volume down";
            linux,code = <0x00000072>;
            press-threshold-microvolt = <0x00048a1c>;
        };
        menu-key {
            label = "menu";
            linux,code = <0x0000008b>;
            press-threshold-microvolt = <0x000ef420>;
        };
        back-key {
            label = "back";
            linux,code = <0x0000009e>;
            press-threshold-microvolt = <0x0013eb9c>;
        };
    };
    audiopwmout-diff {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,audiopwmout-diff";
        simple-audio-card,mclk-fs = <0x00000100>;
        simple-audio-card,bitclock-master = <0x0000011c>;
        simple-audio-card,frame-master = <0x0000011c>;
        phandle = <0x000001cd>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x0000011e>;
            phandle = <0x0000011c>;
        };
    };
    backlight {
        compatible = "pwm-backlight";
        pwms = <0x0000011f 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x00000091>;
    };
    backlight1 {
        compatible = "pwm-backlight";
        pwms = <0x00000120 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x0000009a>;
    };
    dc-12v {
        compatible = "regulator-fixed";
        regulator-name = "dc_12v";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00b71b00>;
        regulator-max-microvolt = <0x00b71b00>;
        phandle = <0x00000129>;
    };
    hdmi-sound {
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <0x00000080>;
        simple-audio-card,name = "rockchip,hdmi";
        status = "okay";
        phandle = <0x000001ce>;
        simple-audio-card,cpu {
            sound-dai = <0x00000121>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000122>;
        };
    };
    dummy-codec {
        status = "disabled";
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000124>;
    };
    pdm-mic-array {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,name = "rockchip,pdm-mic-array";
        phandle = <0x000001cf>;
        simple-audio-card,cpu {
            sound-dai = <0x00000123>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000124>;
        };
    };
    rk809-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,rk809-codec";
        simple-audio-card,mclk-fs = <0x00000100>;
        phandle = <0x000001d0>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000125>;
        };
    };
    spdif-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,name = "ROCKCHIP,SPDIF";
        simple-audio-card,cpu {
            sound-dai = <0x00000126>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000127>;
        };
    };
    spdif-out {
        status = "okay";
        compatible = "linux,spdif-dit";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000127>;
    };
    vad-sound {
        status = "disabled";
        compatible = "rockchip,multicodecs-card";
        rockchip,card-name = "rockchip,rk3568-vad";
        rockchip,cpu = <0x000000c6>;
        rockchip,codec = <0x00000125 0x00000128>;
        phandle = <0x000001d1>;
    };
    vcc3v3-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00325aa0>;
        regulator-max-microvolt = <0x00325aa0>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003c>;
    };
    vcc5v0-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003e>;
    };
    vcc5v0-host-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000006 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012a>;
        regulator-name = "vcc5v0_host";
        regulator-always-on;
        phandle = <0x0000010c>;
    };
    vcc5v0-otg-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000005 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012b>;
        regulator-name = "vcc5v0_otg";
        phandle = <0x0000010d>;
    };
    vcc3v3-lcd0-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd0_n";
        regulator-boot-on;
        gpio = <0x00000035 0x00000010 0x00000000>;
        enable-active-high;
        phandle = <0x00000092>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    vcc3v3-lcd1-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd1_n";
        regulator-boot-on;
        phandle = <0x0000009b>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    sdio-pwrseq {
        compatible = "mmc-pwrseq-simple";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012d>;
        post-power-on-delay-ms = <0x000000c8>;
        reset-gpios = <0x0000012e 0x00000009 0x00000001>;
        phandle = <0x000000b1>;
    };
    wireless-wlan {
        compatible = "wlan-platdata";
        rockchip,grf = <0x00000032>;
        wifi_chip_type = "ap6398s";
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012f>;
        WIFI,host_wake_irq = <0x0000012e 0x0000000a 0x00000000>;
        phandle = <0x000001d2>;
    };
    wireless-bluetooth {
        compatible = "bluetooth-platdata";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        uart_rts_gpios = <0x0000012e 0x0000000d 0x00000001>;
        pinctrl-names = "default", "rts_gpio";
        pinctrl-0 = <0x00000130>;
        pinctrl-1 = <0x00000131>;
        BT,reset_gpio = <0x0000012e 0x0000000f 0x00000000>;
        BT,wake_gpio = <0x0000012e 0x00000011 0x00000000>;
        BT,wake_host_irq = <0x0000012e 0x00000010 0x00000000>;
        status = "okay";
        phandle = <0x000001d3>;
    };
    test-power {
        status = "okay";
    };
    rk-headset {
        compatible = "rockchip_headset";
        headset_gpio =