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Efforts to develop firmware for H96 MAX V56 RK3566 4G/32G

Hqnicolas

By Hqnicolas
in Rockchip CPU Boxes

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Hqnicolas

Hqnicolas

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🏆 help to add other boards in armbian standart, you don't need to be a programmer to help the community,
just need a copy of the ARM BOARD and a x86 computer to compile new versions.

 

If you like what you see here and want to help: Donate Armbian, the like button only costs a few dollars.

Armbian Needs you help!


This Armbian adventure was summarized in my Public Github Repository.

 

                      

 

 

Software description:

V0.5 = @armbian The Armbian SD card image "Compiled From Armbian Project"

V0.8 = @hzdm Project with Mainline Bootloader "Boot the 64gb Emmc Armbian with Mainline Rockchip"
V0.9 = @hzdm Release Mainline Bootloader "Boot the 32gb and 64gb Emmc Armbian with Mainline Rockchip"

V1.0 = @hotnikq The Armbian SD card inside the Android Legacy Rockchip Image "Glued Image: Android boot for Linux" 

V1.2 = @ning Release Device Tree and Bootloader to longterm 6.6.27 Kernel "Boot with Mainline Rockchip"

V1.3 = @Hqnicolas Github PR Enable h96 Rk3566 TV-Box device for Kernel 6.8

V1.4 = @pocosparc Github PR Enable h96 Rk3566 TV-Box OpenVFD and IR controller

 

Video drivers:
https://developer.arm.com/downloads/-/mali-drivers/bifrost-kernel 

https://docs.mesa3d.org/download.html 

https://docs.mesa3d.org/drivers/panfrost.html 

 

Wifi Drivers:
https://drive.google.com/file/d/1B1LmAylalETcnBEWiPiJHL0MjK5xlIV4/view?usp=sharing


UEFI: https://github.com/hqnicolas/h96v56_uefi/releases/tag/v1.2.1
 

Or Just Live install Wifi Driver: 

cd /lib/firmware/brcm/
sudo wget https://github.com/LibreELEC/brcmfmac_sdio-firmware/raw/master/BCM4335A0.hcd
sudo wget https://github.com/CoreELEC/brcmfmac_sdio-firmware-aml/raw/master/firmware/brcm/fw_bcm4335b0_ag.bin
sudo ln -s fw_bcm4335b0_ag.bin brcmfmac4335-sdio.h96-TVbox,rk3566.bin
sudo reboot now

nmcli dev wifi

 

Quote

sudo cat > /lib/firmware/brcm/brcmfmac4335-sdio.txt << "EOF"
# bcm94335wlcspMS_ES50_RC171p24p23_04052013_AM_mdfy_PAparam.txt -- 4/5/2013 by Murata, based on bcm94335wlcspMS_ES50_RC171p24p20_04022013_AM.txt, changed PA parameters and txidxcap parameters and ccode.
# bcm94335wlcspMS_ES50_RC171p24p20_04022013_AM.txt -- 4/2/2013 by Broadcom Corporation
# Use with AARDVARK_REL_6_30_171_24_23 -- Murata BCM4335 WLCSP 11AC Module
# Sample variables file for Murata Type-XJ ES5.0 (0x00 0x11) -- bcm94335wlcspMS_AM_P400.txt as original
sromrev=11
boardrev=0x1500
boardtype=0x064b
boardflags=0x10401001
boardflags2=0x0
#updated boardflags3 for forcing to enable external LPO
boardflags3=0x0800c08b
macaddr=00:90:4c:c5:12:38
#ccode modified by Murata
#ccode=0
ccode=XS
regrev=0
antswitch=0
pdgain5g=1
pdgain2g=1
tworangetssi2g=0
tworangetssi5g=0
femctrl=4
vendid=0x14e4
devid=0x43ae
manfid=0x2d0
#prodid=0x052e
nocrc=1
#otpimagesize=502
xtalfreq=37400
extpagain2g=1
extpagain5g=1
rxgains2gelnagaina0=2
rxgains2gtrisoa0=6
rxgains2gtrelnabypa0=1
rxgains5gelnagaina0=3
rxgains5gtrisoa0=5
rxgains5gtrelnabypa0=1
rxchain=1
txchain=1
aa2g=1
aa5g=1
ag0=0
ag1=0
tssipos5g=1
tssipos2g=1
#PA parameters (2G20M/2G40M/5G20M/5G40M/5G80M)
#PA parameters modified by Murata
#pa2ga0=-208,6208,-764
#pa2ga1=-203,6429,-793
#pa5ga0=-167,5736,-685,-157,5669,-670,-157,5548,-665,-141,5621,-664
#pa5ga1=-101,6543,-735,-99,6452,-731,-147,5743,-695,-75,6468,-723
#pa5ga2=-172,5903,-708,-160,5868,-698,-113,6264,-722,-125,5915,-684
pa2ga0=0xff31,0x1759,0xFD1D
pa2ga1=0xff35,0x18BB,0xFCEC
pa5ga0=0xff78,0x1715,0xFD49,0xff89,0x1714,0xFD57,0xff86,0x1652,0xFD62,0xffa9,0x1760,0xFD5E
pa5ga1=0xff56,0x1596,0xFD5F,0xff88,0x1764,0xFD45,0xff89,0x1632,0xFD65,0xff69,0x160E,0xFD49
pa5ga2=0xff5a,0x1667,0xFD4E,0xff5f,0x15F7,0xFD5E,0xff5a,0x1531,0xFD68,0xff6e,0x1587,0xFD6A
# Default Target Power for 2G -- 17dBm(11)/14dBm(54)/13dBm(MCS7,MCS8)/16dBm(6,MCS0)
maxp2ga0=74
cckbw202gpo=0
cckbw20ul2gpo=0
dot11agofdmhrbw202gpo=0x6666
ofdmlrbw202gpo=0x0022
mcsbw202gpo=0x88866662
# Default Target Power for 5G -- 14dBm(54)/13dBm(HT20-MCS7,VHT20-MCS8)/12dBm(HT40-MCS7,VHT40-MCS9)/11dBm(VHT80-MCS8/MCS9)/16dBm(6,20HT-MCS0)
maxp5ga0=74,74,74,74
# Low
mcslr5glpo=0
mcsbw205glpo=0x88866662
mcsbw405glpo=0xAAA88884
mcsbw805glpo=0xCCCAAAA6
# Mid
mcslr5gmpo=0
mcsbw205gmpo=0x88866662
mcsbw405gmpo=0xAAA88884
mcsbw805gmpo=0xCCCAAAA6
# High
mcslr5ghpo=0
mcsbw205ghpo=0x88866662
mcsbw405ghpo=0xAAA88884
mcsbw805ghpo=0xCCCAAAA6
#20MHz High Rate
sb20in40hrpo=0x0
sb20in80and160hr5glpo=0x0
sb20in80and160hr5gmpo=0x0
sb20in80and160hr5ghpo=0x0
#40MHz High Rate
sb40and80hr5glpo=0x0
sb40and80hr5gmpo=0x0
sb40and80hr5ghpo=0x0
#20MHz Low Rate
sb20in40lrpo=0x0
sb20in80and160lr5glpo=0x0
sb20in80and160lr5gmpo=0x0
sb20in80and160lr5ghpo=0x0
#40MHz Low Rate
sb40and80lr5glpo=0x0
sb40and80lr5gmpo=0x0
sb40and80lr5ghpo=0x0
dot11agduphrpo=0x0
dot11agduplrpo=0x0
tssifloor2g=80
tssifloor5g=160,190,240,260
#rpcal:use with 171.17 or later, compensates filter ripple
rpcal2g=0x0
rpcal5gb0=0x0
#cckdigfilttype[0-7] 0:default
cckdigfilttype=2
phycal_tempdelta=25
#GPIO 0 for SDIO HW OOB interruption
muxenab=0x10
#sd_gpout=0
#sd_oobonly=1
rssicorrnorm_c0=-3,-2
rssicorrnorm5g_c0=-1,0,-3,-1,0,-3,-3,-2,-4,-3,-2,-4
#txidxcap2g and txidxcap5g modified by Murata
#txidxcap2g=32
#txidxcap5g=44
txidxcap2g=36
txidxcap5g=36
paparambwver=1
EOF

  

sudo rmmod brcmfmac_wcc brcmfmac brcmutil
modprobe brcmfmac

 

Topic description:

This topic aims to demonstrate the path taken to the Armibian EMMC solution.
In our path we create a lot of ready-to-use ROM files, some users burn an use this images without learning with the Linux compilation process.

the name of the topic is efforts but that's no effort at all, you should try compile your own images.


Device Capability Test: Using Rockchip SoCs NPU.
Drivers: https://github.com/rockchip-linux/rknpu2
User Guide: https://github.com/rockchip-linux/rknpu2/blob/master/doc/Rockchip_RKNPU_User_Guide_RKNN_API_V1.4.0_EN.pdf
OpenCV: https://opencv.org/blog/2022/11/29/working-with-neural-processing-units-npus-using-opencv/
A discussion on Reddit: https://www.reddit.com/r/OrangePI/comments/12b3jmj/accessing_the_npu_on_the_orange_pi/

Transformers models: https://github.com/usefulsensors/useful-transformers
Usage: https://www.crowdsupply.com/useful-sensors/ai-in-a-box/
Usage: https://youtu.be/pN8mKZ5wpdQ



d0533304-bac1-4e4b-b135-c1cfb661583b.jpg

 

 

 

 

 

Edited by Hqnicolas
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Werner

Werner

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moved

 

The images mentioned above are provided by a 3rd party that is not affiliated with the Armbian project. As with all downloads on the internet special precaution should be taken when using unofficial stuff.

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Hqnicolas

Hqnicolas

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decompile DTS Files 
 

Quote

/dts-v1/;

/ {
    compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566";
    interrupt-parent = <0x1>;
    #address-cells = <0x2>;
    #size-cells = <0x2>;
    model = "Rockchip RK3566 EVB3 DDR3 V10 Board";

    ddr_timing {
        compatible = "rockchip,ddr-timing";
        ddr2_speed_bin = <0x0>;
        ddr3_speed_bin = <0x15>;
        ddr4_speed_bin = <0xc>;
        pd_idle = <0xd>;
        sr_idle = <0x5d>;
        sr_mc_gate_idle = <0x0>;
        srpd_lite_idle = <0x0>;
        standby_idle = <0x0>;
        auto_pd_dis_freq = <0x42a>;
        auto_sr_dis_freq = <0x320>;
        ddr2_dll_dis_freq = <0x12c>;
        ddr3_dll_dis_freq = <0x12c>;
        ddr4_dll_dis_freq = <0x271>;
        phy_dll_dis_freq = <0x190>;
        ddr2_odt_dis_freq = <0x64>;
        phy_ddr2_odt_dis_freq = <0x64>;
        ddr2_drv = <0x2>;
        ddr2_odt = <0x40>;
        phy_ddr2_ca_drv = <0x0>;
        phy_ddr2_ck_drv = <0x0>;
        phy_ddr2_dq_drv = <0x0>;
        phy_ddr2_odt = <0x0>;
        ddr3_odt_dis_freq = <0x14d>;
        phy_ddr3_odt_dis_freq = <0x14d>;
        ddr3_drv = <0x2>;
        ddr3_odt = <0x40>;
        phy_ddr3_ca_drv = <0x0>;
        phy_ddr3_ck_drv = <0x0>;
        phy_ddr3_dq_drv = <0x0>;
        phy_ddr3_odt = <0x0>;
        phy_lpddr2_odt_dis_freq = <0x14d>;
        lpddr2_drv = <0x2>;
        phy_lpddr2_ca_drv = <0x0>;
        phy_lpddr2_ck_drv = <0x0>;
        phy_lpddr2_dq_drv = <0x0>;
        phy_lpddr2_odt = <0x0>;
        lpddr3_odt_dis_freq = <0x14d>;
        phy_lpddr3_odt_dis_freq = <0x14d>;
        lpddr3_drv = <0x1>;
        lpddr3_odt = <0x2>;
        phy_lpddr3_ca_drv = <0x0>;
        phy_lpddr3_ck_drv = <0x0>;
        phy_lpddr3_dq_drv = <0x0>;
        phy_lpddr3_odt = <0x0>;
        lpddr4_odt_dis_freq = <0x14d>;
        phy_lpddr4_odt_dis_freq = <0x14d>;
        lpddr4_drv = <0x30>;
        lpddr4_dq_odt = <0x1>;
        lpddr4_ca_odt = <0x0>;
        phy_lpddr4_ca_drv = <0x0>;
        phy_lpddr4_ck_cs_drv = <0x0>;
        phy_lpddr4_dq_drv = <0x0>;
        phy_lpddr4_odt = <0x0>;
        ddr4_odt_dis_freq = <0x271>;
        phy_ddr4_odt_dis_freq = <0x271>;
        ddr4_drv = <0x0>;
        ddr4_odt = <0x200>;
        phy_ddr4_ca_drv = <0x0>;
        phy_ddr4_ck_drv = <0x0>;
        phy_ddr4_dq_drv = <0x0>;
        phy_ddr4_odt = <0x0>;
        phandle = <0xa8>;
    };

    aliases {
        csi2dphy0 = "/csi2-dphy0";
        csi2dphy1 = "/csi2-dphy1";
        csi2dphy2 = "/csi2-dphy2";
        dsi0 = "/dsi@fe060000";
        dsi1 = "/dsi@fe070000";
        ethernet1 = "/ethernet@fe010000";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        i2c0 = "/i2c@fdd40000";
        i2c1 = "/i2c@fe5a0000";
        i2c2 = "/i2c@fe5b0000";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mmc0 = "/dwmmc@fe2b0000";
        mmc1 = "/dwmmc@fe2c0000";
        mmc2 = "/sdhci@fe310000";
        mmc3 = "/dwmmc@fe000000";
        serial0 = "/serial@fdd50000";
        serial1 = "/serial@fe650000";
        serial2 = "/serial@fe660000";
        serial3 = "/serial@fe670000";
        serial4 = "/serial@fe680000";
        serial5 = "/serial@fe690000";
        serial6 = "/serial@fe6a0000";
        serial7 = "/serial@fe6b0000";
        serial8 = "/serial@fe6c0000";
        serial9 = "/serial@fe6d0000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
    };

    cpus {
        #address-cells = <0x2>;
        #size-cells = <0x0>;

        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x0>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            #cooling-cells = <0x2>;
            dynamic-power-coefficient = <0xbb>;
            cpu-supply = <0x5>;
            phandle = <0x9>;

            power-model {
                compatible = "simple-power-model";
                leakage-range = <0xa 0x28>;
                ls = <0xffffdc14 0x18d8 0x0>;
                static-coefficient = <0x186a0>;
                ts = <0x1476e 0x3263d 0xffffef34 0x47>;
                thermal-zone = "soc-thermal";
            };
        };

        cpu@100 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x100>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            phandle = <0xa>;
        };

        cpu@200 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x200>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            phandle = <0xb>;
        };

        cpu@300 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x0 0x300>;
            enable-method = "psci";
            clocks = <0x2 0x0>;
            operating-points-v2 = <0x3>;
            cpu-idle-states = <0x4>;
            phandle = <0xc>;
        };

        idle-states {
            entry-method = "psci";

            cpu-sleep {
                compatible = "arm,idle-state";
                local-timer-stop;
                arm,psci-suspend-param = <0x10000>;
                entry-latency-us = <0x64>;
                exit-latency-us = <0x78>;
                min-residency-us = <0x3e8>;
                phandle = <0x4>;
            };
        };
    };

    cpu0-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0x6 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,pvtm-voltage-sel = <0x0 0x14050 0x0 0x14051 0x16b48 0x1 0x16b49 0x186a0 0x2>;
        rockchip,pvtm-freq = <0x639c0>;
        rockchip,pvtm-volt = <0xdbba0>;
        rockchip,pvtm-ch = <0x0 0x5>;
        rockchip,pvtm-sample-time = <0x3e8>;
        rockchip,pvtm-number = <0xa>;
        rockchip,pvtm-error = <0x3e8>;
        rockchip,pvtm-ref-temp = <0x28>;
        rockchip,pvtm-temp-prop = <0x1a 0x1a>;
        rockchip,thermal-zone = "soc-thermal";
        rockchip,temp-hysteresis = <0x1388>;
        rockchip,low-temp = <0x0>;
        rockchip,low-temp-adjust-volt = <0x0 0x648 0x124f8>;
        phandle = <0x3>;

        opp-408000000 {
            opp-hz = <0x0 0x18519600>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            status = "disabled";
        };

        opp-600000000 {
            opp-hz = <0x0 0x23c34600>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            status = "disabled";
        };

        opp-816000000 {
            opp-hz = <0x0 0x30a32c00>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            opp-suspend;
            status = "disabled";
        };

        opp-1104000000 {
            opp-hz = <0x0 0x41cdb400>;
            opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
            clock-latency-ns = <0x9c40>;
            status = "disabled";
        };

        opp-1416000000 {
            opp-hz = <0x0 0x54667200>;
            opp-microvolt = <0xe1d48 0xe1d48 0x118c30>;
            clock-latency-ns = <0x9c40>;
        };

        opp-1608000000 {
            opp-hz = <0x0 0x5fd82200>;
            opp-microvolt = <0xf4240 0xf4240 0x118c30>;
            clock-latency-ns = <0x9c40>;
        };

        opp-1800000000 {
            opp-hz = <0x0 0x6b49d200>;
            opp-microvolt = <0x100590 0x100590 0x118c30>;
            clock-latency-ns = <0x9c40>;
        };
    };

    arm-pmu {
        compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
        interrupts = <0x0 0xe4 0x4 0x0 0xe5 0x4 0x0 0xe6 0x4 0x0 0xe7 0x4>;
        interrupt-affinity = <0x9 0xa 0xb 0xc>;
    };

    cpuinfo {
        compatible = "rockchip,cpuinfo";
        nvmem-cells = <0xd 0xe 0xf>;
        nvmem-cell-names = "id", "cpu-version", "cpu-code";
    };

    display-subsystem {
        compatible = "rockchip,display-subsystem";
        memory-region = <0x10 0x11>;
        memory-region-names = "drm-logo", "drm-cubic-lut";
        ports = <0x12>;
        devfreq = <0x13>;
        phandle = <0x134>;

        route {

            route-dsi0 {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x14>;
                phandle = <0x135>;
            };

            route-dsi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x15>;
                phandle = <0x136>;
            };

            route-edp {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x16>;
                phandle = <0x137>;
            };

            route-hdmi {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x17>;
                phandle = <0x138>;
            };

            route-lvds {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x18>;
                phandle = <0x139>;
            };

            route-rgb {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x19>;
                phandle = <0x13a>;
            };
        };
    };

    firmware {

        optee {
            compatible = "linaro,optee-tz";
            method = "smc";
            phandle = <0x13b>;
        };

        scmi {
            compatible = "arm,scmi-smc";
            shmem = <0x1a>;
            arm,smc-id = <0x82000010>;
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            phandle = <0x13c>;

            protocol@14 {
                reg = <0x14>;
                #clock-cells = <0x1>;
                rockchip,clk-init = "Tfr";
                phandle = <0x2>;
            };
        };

        sdei {
            compatible = "arm,sdei-1.0";
            method = "smc";
            phandle = <0x13d>;
        };
    };

    mpp-srv {
        compatible = "rockchip,mpp-service";
        rockchip,taskqueue-count = <0x6>;
        rockchip,resetgroup-count = <0x6>;
        status = "okay";
        phandle = <0x67>;
    };

    psci {
        compatible = "arm,psci-1.0";
        method = "smc";
    };

    reserved-memory {
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        phandle = <0x13e>;

        drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x0 0x0 0x0 0x0>;
            phandle = <0x10>;
        };

        drm-cubic-lut@00000000 {
            compatible = "rockchip,drm-cubic-lut";
            reg = <0x0 0x0 0x0 0x0>;
            phandle = <0x11>;
        };

        linux,cma {
            compatible = "shared-dma-pool";
            inactive;
            reusable;
            reg = <0x0 0x10000000 0x0 0x800000>;
            linux,cma-default;
        };

        ramoops@110000 {
            compatible = "ramoops";
            reg = <0x0 0x110000 0x0 0xf0000>;
            record-size = <0x20000>;
            console-size = <0x80000>;
            ftrace-size = <0x0>;
            pmsg-size = <0x50000>;
            phandle = <0x13f>;
        };
    };

    rockchip-suspend {
        compatible = "rockchip,pm-rk3568";
        status = "okay";
        rockchip,sleep-debug-en = <0x1>;
        rockchip,sleep-mode-config = <0x4e4>;
        rockchip,wakeup-config = <0x2001>;
        rockchip,virtual-poweroff = <0x1>;
        phandle = <0x140>;
    };

    rockchip-system-monitor {
        compatible = "rockchip,system-monitor";
        rockchip,thermal-zone = "soc-thermal";
        phandle = <0x141>;
    };

    thermal-zones {
        phandle = <0x142>;

        soc-thermal {
            polling-delay-passive = <0x14>;
            polling-delay = <0x3e8>;
            sustainable-power = <0x5c3>;
            thermal-sensors = <0x1b 0x0>;
            phandle = <0x143>;

            trips {

                trip-point-0 {
                    temperature = <0x11170>;
                    hysteresis = <0x7d0>;
                    type = "passive";
                    phandle = <0x144>;
                };

                trip-point-1 {
                    temperature = <0x14c08>;
                    hysteresis = <0x7d0>;
                    type = "passive";
                    phandle = <0x1c>;
                };

                soc-crit {
                    temperature = <0x1c138>;
                    hysteresis = <0x7d0>;
                    type = "critical";
                    phandle = <0x145>;
                };
            };

            cooling-maps {

                map0 {
                    trip = <0x1c>;
                    cooling-device = <0x9 0xffffffff 0xffffffff>;
                    contribution = <0x400>;
                };

                map1 {
                    trip = <0x1c>;
                    cooling-device = <0x1d 0xffffffff 0xffffffff>;
                    contribution = <0x400>;
                };
            };
        };

        gpu-thermal {
            polling-delay-passive = <0x14>;
            polling-delay = <0x3e8>;
            thermal-sensors = <0x1b 0x1>;
            phandle = <0x146>;
        };
    };

    timer {
        compatible = "arm,armv8-timer";
        interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
        arm,no-tick-in-suspend;
    };

    external-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x7735940>;
        clock-output-names = "gmac1_clkin";
        #clock-cells = <0x0>;
        phandle = <0x147>;
    };

    xpcs-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x7735940>;
        clock-output-names = "clk_gmac1_xpcs_mii";
        #clock-cells = <0x0>;
        phandle = <0x148>;
    };

    i2s1-mclkin-rx {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s1_mclkin_rx";
        phandle = <0x149>;
    };

    i2s1-mclkin-tx {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s1_mclkin_tx";
        phandle = <0x14a>;
    };

    i2s2-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s2_mclkin";
        phandle = <0x14b>;
    };

    i2s3-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0xbb8000>;
        clock-output-names = "i2s3_mclkin";
        phandle = <0x14c>;
    };

    mpll {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0x2faf0800>;
        clock-output-names = "mpll";
        phandle = <0x14d>;
    };

    xin24m {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
        clock-frequency = <0x16e3600>;
        clock-output-names = "xin24m";
        phandle = <0x14e>;
    };

    xin32k {
        compatible = "fixed-clock";
        clock-frequency = <0x8000>;
        clock-output-names = "xin32k";
        #clock-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x1e>;
        phandle = <0x14f>;
    };

    scmi-shmem@10f000 {
        compatible = "arm,scmi-shmem";
        reg = <0x0 0x10f000 0x0 0x100>;
        phandle = <0x1a>;
    };

    sata@fc400000 {
        compatible = "snps,dwc-ahci";
        reg = <0x0 0xfc400000 0x0 0x1000>;
        clocks = <0x1f 0x9b 0x1f 0x9c 0x1f 0x9d>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x0 0x5f 0x4>;
        interrupt-names = "hostc";
        phys = <0x20 0x1>;
        phy-names = "sata-phy";
        ports-implemented = <0x1>;
        power-domains = <0x21 0xf>;
        status = "disabled";
        phandle = <0x150>;
    };

    sata@fc800000 {
        compatible = "snps,dwc-ahci";
        reg = <0x0 0xfc800000 0x0 0x1000>;
        clocks = <0x1f 0xa0 0x1f 0xa1 0x1f 0xa2>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x0 0x60 0x4>;
        interrupt-names = "hostc";
        phys = <0x22 0x1>;
        phy-names = "sata-phy";
        ports-implemented = <0x1>;
        power-domains = <0x21 0xf>;
        status = "disabled";
        phandle = <0x151>;
    };

    usbdrd {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x1f 0xa6 0x1f 0xa7 0x1f 0xa5 0x1f 0x7f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        status = "okay";
        phandle = <0x152>;

        dwc3@fcc00000 {
            compatible = "snps,dwc3";
            reg = <0x0 0xfcc00000 0x0 0x400000>;
            interrupts = <0x0 0xa9 0x4>;
            dr_mode = "host";
            phys = <0x23>;
            phy-names = "usb2-phy";
            phy_type = "utmi_wide";
            power-domains = <0x21 0xf>;
            resets = <0x1f 0x94>;
            reset-names = "usb3-otg";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            extcon = <0x24>;
            maximum-speed = "high-speed";
            snps,dis_u2_susphy_quirk;
            phandle = <0x153>;
        };
    };

    usbhost {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x1f 0xa9 0x1f 0xaa 0x1f 0xa8 0x1f 0x7f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        status = "okay";
        phandle = <0x154>;

        dwc3@fd000000 {
            compatible = "snps,dwc3";
            reg = <0x0 0xfd000000 0x0 0x400000>;
            interrupts = <0x0 0xaa 0x4>;
            dr_mode = "host";
            phys = <0x25 0x20 0x4>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            power-domains = <0x21 0xf>;
            resets = <0x1f 0x95>;
            reset-names = "usb3-host";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            phandle = <0x155>;
        };
    };

    interrupt-controller@fd400000 {
        compatible = "arm,gic-v3";
        #interrupt-cells = <0x3>;
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        interrupt-controller;
        reg = <0x0 0xfd400000 0x0 0x10000 0x0 0xfd460000 0x0 0xc0000>;
        interrupts = <0x1 0x9 0x4>;
        phandle = <0x1>;

        interrupt-controller@fd440000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x1>;
            reg = <0x0 0xfd440000 0x0 0x20000>;
            phandle = <0xab>;
        };
    };

    usb@fd800000 {
        compatible = "generic-ehci";
        reg = <0x0 0xfd800000 0x0 0x40000>;
        interrupts = <0x0 0x82 0x4>;
        clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x27>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x156>;
    };

    usb@fd840000 {
        compatible = "generic-ohci";
        reg = <0x0 0xfd840000 0x0 0x40000>;
        interrupts = <0x0 0x83 0x4>;
        clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x27>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x157>;
    };

    usb@fd880000 {
        compatible = "generic-ehci";
        reg = <0x0 0xfd880000 0x0 0x40000>;
        interrupts = <0x0 0x85 0x4>;
        clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x28>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x158>;
    };

    usb@fd8c0000 {
        compatible = "generic-ohci";
        reg = <0x0 0xfd8c0000 0x0 0x40000>;
        interrupts = <0x0 0x86 0x4>;
        clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x26>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x28>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x159>;
    };

    syscon@fda00000 {
        compatible = "rockchip,rk3568-xpcs", "syscon";
        reg = <0x0 0xfda00000 0x0 0x200000>;
        status = "disabled";
        phandle = <0x15a>;
    };

    syscon@fdc20000 {
        compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
        reg = <0x0 0xfdc20000 0x0 0x10000>;
        phandle = <0x33>;

        io-domains {
            compatible = "rockchip,rk3568-pmu-io-voltage-domain";
            status = "okay";
            pmuio1-supply = <0x29>;
            pmuio2-supply = <0x29>;
            vccio1-supply = <0x2a>;
            vccio3-supply = <0x2b>;
            vccio4-supply = <0x2c>;
            vccio5-supply = <0x2d>;
            vccio6-supply = <0x2c>;
            vccio7-supply = <0x2d>;
            phandle = <0x15b>;
        };

        reboot-mode {
            compatible = "syscon-reboot-mode";
            offset = <0x200>;
            mode-bootloader = <0x5242c301>;
            mode-charge = <0x5242c30b>;
            mode-fastboot = <0x5242c309>;
            mode-loader = <0x5242c301>;
            mode-normal = <0x5242c300>;
            mode-recovery = <0x5242c303>;
            mode-ums = <0x5242c30c>;
            mode-panic = <0x5242c307>;
            mode-watchdog = <0x5242c308>;
            phandle = <0x15c>;
        };
    };

    syscon@fdc50000 {
        compatible = "rockchip,rk3568-pipegrf", "syscon";
        reg = <0x0 0xfdc50000 0x0 0x1000>;
        phandle = <0x104>;
    };

    syscon@fdc60000 {
        compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
        reg = <0x0 0xfdc60000 0x0 0x10000>;
        phandle = <0x32>;

        io-domains {
            compatible = "rockchip,rk3568-io-voltage-domain";
            status = "disabled";
            phandle = <0x15d>;
        };

        lvds {
            compatible = "rockchip,rk3568-lvds";
            phys = <0x2e>;
            phy-names = "phy";
            status = "disabled";
            phandle = <0x15e>;

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;
                    #address-cells = <0x1>;
                    #size-cells = <0x0>;

                    endpoint@1 {
                        reg = <0x1>;
                        remote-endpoint = <0x18>;
                        status = "disabled";
                        phandle = <0x8b>;
                    };

                    endpoint@2 {
                        reg = <0x2>;
                        remote-endpoint = <0x2f>;
                        status = "disabled";
                        phandle = <0x8c>;
                    };
                };
            };
        };

        rgb {
            compatible = "rockchip,rk3568-rgb";
            pinctrl-names = "default";
            pinctrl-0 = <0x30>;
            status = "disabled";
            phandle = <0x15f>;

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;
                    #address-cells = <0x1>;
                    #size-cells = <0x0>;

                    endpoint@2 {
                        reg = <0x2>;
                        remote-endpoint = <0x19>;
                        status = "disabled";
                        phandle = <0x8d>;
                    };
                };
            };
        };
    };

    syscon@fdc70000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x0 0xfdc70000 0x0 0x1000>;
        phandle = <0x160>;
    };

    syscon@fdc80000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x0 0xfdc80000 0x0 0x1000>;
        phandle = <0x105>;
    };

    syscon@fdc90000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x0 0xfdc90000 0x0 0x1000>;
        phandle = <0x106>;
    };

    syscon@fdca0000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x0 0xfdca0000 0x0 0x8000>;
        phandle = <0x10b>;
    };

    syscon@fdca8000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x0 0xfdca8000 0x0 0x8000>;
        phandle = <0x10e>;
    };

    edp-phy@fdcb0000 {
        compatible = "rockchip,rk3568-edp-phy";
        reg = <0x0 0xfdcb0000 0x0 0x8000>;
        clocks = <0x31 0x29 0x1f 0x192>;
        clock-names = "refclk", "pclk";
        resets = <0x1f 0x1d6>;
        reset-names = "apb";
        #phy-cells = <0x0>;
        status = "okay";
        phandle = <0xa4>;
    };

    sram@fdcc0000 {
        compatible = "mmio-sram";
        reg = <0x0 0xfdcc0000 0x0 0xb000>;
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        ranges = <0x0 0x0 0xfdcc0000 0xb000>;
        phandle = <0x161>;

        rkvdec-sram@0 {
            reg = <0x0 0xb000>;
            phandle = <0x6f>;
        };
    };

    clock-controller@fdd00000 {
        compatible = "rockchip,rk3568-pmucru";
        reg = <0x0 0xfdd00000 0x0 0x1000>;
        rockchip,grf = <0x32>;
        rockchip,pmugrf = <0x33>;
        #clock-cells = <0x1>;
        #reset-cells = <0x1>;
        assigned-clocks = <0x31 0x32>;
        assigned-clock-parents = <0x31 0x5>;
        phandle = <0x31>;
    };

    clock-controller@fdd20000 {
        compatible = "rockchip,rk3568-cru";
        reg = <0x0 0xfdd20000 0x0 0x1000>;
        rockchip,grf = <0x32>;
        #clock-cells = <0x1>;
        #reset-cells = <0x1>;
        assigned-clocks = <0x31 0x5 0x1f 0x106 0x1f 0x10b 0x31 0x1 0x31 0x2b 0x1f 0x3 0x1f 0x19b 0x1f 0x9 0x1f 0x19c 0x1f 0x19d 0x1f 0x1a1 0x1f 0x19e 0x1f 0x19f 0x1f 0x1a0 0x1f 0x4 0x1f 0x10d 0x1f 0x10e 0x1f 0x173 0x1f 0x174 0x1f 0x175 0x1f 0x176 0x1f 0xc9 0x1f 0xca 0x1f 0x6 0x1f 0x7e 0x1f 0x7f 0x1f 0x3d 0x1f 0x41 0x1f 0x45 0x1f 0x49 0x1f 0x4d 0x1f 0x4d 0x1f 0x55 0x1f 0x51 0x1f 0x5d 0x1f 0xdd>;
        assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
        assigned-clock-parents = <0x31 0x8 0x1f 0x4 0x1f 0x4>;
        phandle = <0x1f>;
    };

    i2c@fdd40000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfdd40000 0x0 0x1000>;
        clocks = <0x31 0x7 0x31 0x2d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x2e 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0x34>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x162>;

        pmic@20 {
            compatible = "rockchip,rk809";
            reg = <0x20>;
            interrupt-parent = <0x35>;
            interrupts = <0x3 0x8>;
            pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
            pinctrl-0 = <0x36>;
            pinctrl-1 = <0x37 0x38>;
            pinctrl-2 = <0x39 0x3a>;
            pinctrl-3 = <0x39 0x3b>;
            rockchip,system-power-controller;
            wakeup-source;
            #clock-cells = <0x1>;
            clock-output-names = "rk808-clkout1", "rk808-clkout2";
            pmic-reset-func = <0x0>;
            not-save-power-en = <0x1>;
            vcc1-supply = <0x3c>;
            vcc2-supply = <0x3c>;
            vcc3-supply = <0x3c>;
            vcc4-supply = <0x3c>;
            vcc5-supply = <0x3c>;
            vcc6-supply = <0x3c>;
            vcc7-supply = <0x3c>;
            vcc8-supply = <0x3c>;
            vcc9-supply = <0x3c>;
            phandle = <0x12c>;

            pwrkey {
                status = "okay";
            };

            pinctrl_rk8xx {
                gpio-controller;
                #gpio-cells = <0x2>;
                phandle = <0x163>;

                rk817_slppin_null {
                    pins = "gpio_slp";
                    function = "pin_fun0";
                    phandle = <0x164>;
                };

                rk817_slppin_slp {
                    pins = "gpio_slp";
                    function = "pin_fun1";
                    phandle = <0x38>;
                };

                rk817_slppin_pwrdn {
                    pins = "gpio_slp";
                    function = "pin_fun2";
                    phandle = <0x3a>;
                };

                rk817_slppin_rst {
                    pins = "gpio_slp";
                    function = "pin_fun3";
                    phandle = <0x3b>;
                };
            };

            regulators {

                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x7a120>;
                    regulator-max-microvolt = <0x149970>;
                    regulator-init-microvolt = <0xdbba0>;
                    regulator-ramp-delay = <0x1771>;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vdd_logic";
                    phandle = <0x62>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x7a120>;
                    regulator-max-microvolt = <0x149970>;
                    regulator-init-microvolt = <0xdbba0>;
                    regulator-ramp-delay = <0x1771>;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vdd_gpu";
                    phandle = <0x64>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vcc_ddr";
                    phandle = <0x165>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                    };
                };

                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x7a120>;
                    regulator-max-microvolt = <0x149970>;
                    regulator-init-microvolt = <0xdbba0>;
                    regulator-ramp-delay = <0x1771>;
                    regulator-initial-mode = <0x2>;
                    regulator-name = "vdd_npu";
                    phandle = <0x5f>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG1 {
                    regulator-boot-on;
                    regulator-always-on;
                    regulator-min-microvolt = <0xdbba0>;
                    regulator-max-microvolt = <0xdbba0>;
                    regulator-name = "vdda0v9_image";
                    phandle = <0x166>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0xdbba0>;
                    regulator-max-microvolt = <0xdbba0>;
                    regulator-name = "vdda_0v9";
                    phandle = <0x167>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0xdbba0>;
                    regulator-max-microvolt = <0xdbba0>;
                    regulator-name = "vdda0v9_pmu";
                    phandle = <0x168>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0xdbba0>;
                    };
                };

                LDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x325aa0>;
                    regulator-max-microvolt = <0x325aa0>;
                    regulator-name = "vccio_acodec";
                    phandle = <0x2a>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x325aa0>;
                    regulator-name = "vccio_sd";
                    phandle = <0x2b>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x325aa0>;
                    regulator-max-microvolt = <0x325aa0>;
                    regulator-name = "vcc3v3_pmu";
                    phandle = <0x29>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x325aa0>;
                    };
                };

                LDO_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcca_1v8";
                    phandle = <0x103>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                LDO_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcca1v8_pmu";
                    phandle = <0x169>;

                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x1b7740>;
                    };
                };

                LDO_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcca1v8_image";
                    phandle = <0x16a>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x1b7740>;
                    regulator-max-microvolt = <0x1b7740>;
                    regulator-name = "vcc_1v8";
                    phandle = <0x2c>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                SWITCH_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc_3v3";
                    phandle = <0x2d>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };

                SWITCH_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc3v3_sd";
                    phandle = <0xac>;

                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };

            codec {
                #sound-dai-cells = <0x0>;
                compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
                clocks = <0x1f 0x1a4>;
                clock-names = "mclk";
                assigned-clocks = <0x1f 0x1a4 0x1f 0x1a8>;
                assigned-clock-rates = <0xbb8000>;
                assigned-clock-parents = <0x1f 0x54 0x1f 0x1a4>;
                pinctrl-names = "default";
                pinctrl-0 = <0x3d>;
                hp-volume = <0x14>;
                spk-volume = <0x3>;
                mic-in-differential;
                status = "okay";
                phandle = <0x125>;
            };
        };

        tcs4526@10 {
            compatible = "tcs,tcs452x";
            reg = <0x10>;
            vin-supply = <0x3e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x100590>;
            regulator-max-microvolt = <0x1535b0>;
            regulator-ramp-delay = <0x8fc>;
            fcs,suspend-voltage-selector = <0x1>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x5>;

            regulator-state-mem {
                regulator-off-in-suspend;
            };
        };
    };

    serial@fdd50000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfdd50000 0x0 0x100>;
        interrupts = <0x0 0x74 0x4>;
        clocks = <0x31 0xb 0x31 0x2c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x0 0x3f 0x1>;
        pinctrl-names = "default";
        pinctrl-0 = <0x40>;
        status = "disabled";
        phandle = <0x16b>;
    };

    pwm@fdd70000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfdd70000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x41>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x16c>;
    };

    pwm@fdd70010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfdd70010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x42>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x16d>;
    };

    pwm@fdd70020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfdd70020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x43>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x16e>;
    };

    pwm@fdd70030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x0 0xfdd70030 0x0 0x10>;
        interrupts = <0x0 0x52 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "default";
        pinctrl-0 = <0x44>;
        clocks = <0x31 0xd 0x31 0x30>;
        clock-names = "pwm", "pclk";
        status = "okay";
        remote_pwm_id = <0x3>;
        handle_cpu_id = <0x1>;
        remote_support_psci = <0x0>;
        phandle = <0x16f>;

        ir_key1 {
            rockchip,usercode = <0x4040>;
            rockchip,key_table = <0xf2 0xe8 0xbd 0x9e 0xf4 0x67 0xf1 0x6c 0xef 0x69 0xee 0x6a 0xe5 0x66 0xe7 0x73 0xe8 0x72 0xb2 0x74 0xbc 0x71 0xec 0x8b 0xbf 0x190 0xe0 0x191 0xe1 0x192 0xe9 0xb7 0xe6 0xf8 0xe8 0xb9 0xe7 0xba 0xf0 0x184 0xbe 0x175>;
        };

        ir_key2 {
            rockchip,usercode = <0xff00>;
            rockchip,key_table = <0xf9 0x66 0xbf 0x9e 0xfb 0x8b 0xaa 0xe8 0xb9 0x67 0xe9 0x6c 0xb8 0x69 0xea 0x6a 0xeb 0x72 0xef 0x73 0xf7 0x71 0xe7 0x74 0xfc 0x74 0xa9 0x72 0xa8 0xa4 0xe0 0x72 0xa5 0x72 0xab 0xb7 0xb7 0x184 0xe8 0x184 0xf8 0xb8 0xaf 0xb9 0xed 0x72 0xee 0xba 0xb3 0x72 0xf1 0x72 0xf2 0x72 0xf3 0xd9 0xb4 0x72 0xa4 0x8d 0xbe 0xd9>;
        };

        ir_key3 {
            rockchip,usercode = <0x1dcc>;
            rockchip,key_table = <0xee 0xe8 0xf0 0x9e 0xf8 0x67 0xbb 0x6c 0xef 0x69 0xed 0x6a 0xfc 0x66 0xf1 0x73 0xfd 0x72 0xb7 0xd9 0xff 0x74 0xf3 0x71 0xbf 0x8b 0xf9 0x191 0xf5 0x192 0xb3 0x184 0xbe 0x2 0xba 0x3 0xb2 0x4 0xbd 0x5 0xf9 0x6 0xb1 0x7 0xfc 0x8 0xf8 0x9 0xb0 0xa 0xb6 0xb 0xb5 0xe>;
        };

        ir_key4 {
            rockchip,usercode = <0xfe01>;
            rockchip,key_table = <0xec 0xe8 0xe6 0x9e 0xe9 0x67 0xe5 0x6c 0xae 0x69 0xaf 0x6a 0xee 0x66 0xe7 0x73 0xef 0x72 0xbf 0x74 0xbe 0x71 0xb3 0x8b 0xff 0x184 0xb1 0x2 0xf2 0x3 0xf3 0x4 0xb5 0x5 0xf6 0x6 0xf7 0x7 0xb9 0x8 0xfa 0x9 0xfb 0xa 0xfe 0xb 0xbd 0xe 0xbc 0xb7 0xf0 0xba 0xb4 0x19c 0xb8 0x1e 0xb0 0x197>;
        };

        ir_key5 {
            rockchip,usercode = <0x7f80>;
            rockchip,key_table = <0xec 0xe8 0xd8 0x9e 0xc7 0x67 0xbf 0x6c 0xc8 0x69 0xc6 0x6a 0x8c 0x66 0x78 0x73 0x76 0x72 0x7e 0x74 0x7c 0x8b 0xb7 0x184>;
        };

        ir_key6 {
            rockchip,usercode = <0xfd01>;
            rockchip,key_table = <0x31 0xe8 0x2f 0x9e 0x35 0x67 0x2d 0x6c 0x66 0x69 0x3e 0x6a 0x6a 0x66 0x5e 0x73 0x47 0x72 0x23 0x74 0x3a 0x184 0xd 0x40>;
        };
    };

    power-management@fdd90000 {
        compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
        reg = <0x0 0xfdd90000 0x0 0x1000>;
        phandle = <0x170>;

        power-controller {
            compatible = "rockchip,rk3568-power-controller";
            #power-domain-cells = <0x1>;
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            status = "okay";
            phandle = <0x21>;

            pd_npu@6 {
                reg = <0x6>;
                clocks = <0x1f 0x27 0x1f 0x25 0x1f 0x26>;
                pm_qos = <0x45>;
            };

            pd_gpu@7 {
                reg = <0x7>;
                clocks = <0x1f 0x19 0x1f 0x1a>;
                pm_qos = <0x46>;
            };

            pd_vi@8 {
                reg = <0x8>;
                clocks = <0x1f 0xcc 0x1f 0xcd>;
                pm_qos = <0x47 0x48 0x49>;
            };

            pd_vo@9 {
                reg = <0x9>;
                clocks = <0x1f 0xda 0x1f 0xdb 0x1f 0xdc>;
                pm_qos = <0x4a 0x4b 0x4c>;
            };

            pd_rga@10 {
                reg = <0xa>;
                clocks = <0x1f 0xf1 0x1f 0xf2>;
                pm_qos = <0x4d 0x4e 0x4f 0x50 0x51 0x52>;
            };

            pd_vpu@11 {
                reg = <0xb>;
                clocks = <0x1f 0xed>;
                pm_qos = <0x53>;
            };

            pd_rkvdec@13 {
                clocks = <0x1f 0x107>;
                reg = <0xd>;
                pm_qos = <0x54>;
            };

            pd_rkvenc@14 {
                reg = <0xe>;
                clocks = <0x1f 0x102>;
                pm_qos = <0x55 0x56 0x57>;
            };

            pd_pipe@15 {
                reg = <0xf>;
                clocks = <0x1f 0x7f>;
                pm_qos = <0x58 0x59 0x5a 0x5b 0x5c>;
            };
        };
    };

    pvtm@fde00000 {
        compatible = "rockchip,rk3568-core-pvtm";
        reg = <0x0 0xfde00000 0x0 0x100>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;

        pvtm@0 {
            reg = <0x0>;
            clocks = <0x1f 0x13 0x1f 0x1c2>;
            clock-names = "clk", "pclk";
            resets = <0x1f 0x1a 0x1f 0x19>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };

    npu@fde40000 {
        compatible = "rockchip,rknpu";
        reg = <0x0 0xfde40000 0x0 0x10000>;
        interrupts = <0x0 0x97 0x4>;
        clocks = <0x2 0x2 0x1f 0x23 0x1f 0x28 0x1f 0x29>;
        clock-names = "scmi_clk", "clk", "aclk", "hclk";
        assigned-clocks = <0x1f 0x23>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x1f 0x2b 0x1f 0x2c>;
        reset-names = "srst_a", "srst_h";
        power-domains = <0x21 0x6>;
        operating-points-v2 = <0x5d>;
        iommus = <0x5e>;
        status = "okay";
        rknpu-supply = <0x5f>;
        phandle = <0x171>;
    };

    npu-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0x60 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x1388>;
        rockchip,low-temp = <0x0>;
        rockchip,low-temp-adjust-volt = <0x0 0x2bc 0xc350>;
        phandle = <0x5d>;

        opp-200000000 {
            opp-hz = <0x0 0xbebc200>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-300000000 {
            opp-hz = <0x0 0x11b3dc40>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-400000000 {
            opp-hz = <0x0 0x17d78400>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-600000000 {
            opp-hz = <0x0 0x23c34600>;
            opp-microvolt = <0xc96a8 0xc96a8 0xf4240>;
        };

        opp-700000000 {
            opp-hz = <0x0 0x29b92700>;
            opp-microvolt = <0xcf850 0xcf850 0xf4240>;
        };

        opp-800000000 {
            opp-hz = <0x0 0x2faf0800>;
            opp-microvolt = <0xd59f8 0xd59f8 0xf4240>;
        };

        opp-900000000 {
            opp-hz = <0x0 0x35a4e900>;
            opp-microvolt = <0xe1d48 0xe1d48 0xf4240>;
        };

        opp-1000000000 {
            opp-hz = <0x0 0x3b9aca00>;
            opp-microvolt = <0xf4240 0xf4240 0xf4240>;
            status = "disabled";
        };
    };

    bus-npu {
        compatible = "rockchip,rk3568-bus";
        rockchip,busfreq-policy = "clkfreq";
        clocks = <0x2 0x2>;
        clock-names = "bus";
        operating-points-v2 = <0x61>;
        status = "okay";
        bus-supply = <0x62>;
        pvtm-supply = <0x5>;
        phandle = <0x172>;
    };

    bus-npu-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        nvmem-cells = <0x7>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x0 0x14050 0x0 0x14051 0x16b48 0x1 0x16b49 0x186a0 0x2>;
        rockchip,pvtm-ch = <0x0 0x5>;
        phandle = <0x61>;

        opp-1000000000 {
            opp-hz = <0x0 0x3b9aca00>;
            opp-microvolt = <0xe7ef0>;
            opp-microvolt-L0 = <0xe7ef0>;
            opp-microvolt-L1 = <0xe1d48>;
            opp-microvolt-L2 = <0x0>;
        };

        opp-900000000 {
            opp-hz = <0x0 0x35a4e900>;
            opp-microvolt = <0x0>;
        };
    };

    iommu@fde4b000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfde4b000 0x0 0x40>;
        interrupts = <0x0 0x97 0x4>;
        interrupt-names = "rknpu_mmu";
        clocks = <0x1f 0x28 0x1f 0x29>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0x6>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x5e>;
    };

    gpu@fde60000 {
        compatible = "arm,mali-bifrost";
        reg = <0x0 0xfde60000 0x0 0x4000>;
        interrupts = <0x0 0x27 0x4 0x0 0x29 0x4 0x0 0x28 0x4>;
        interrupt-names = "GPU", "MMU", "JOB";
        upthreshold = <0x28>;
        downdifferential = <0xa>;
        clocks = <0x2 0x1 0x1f 0x1b>;
        clock-names = "clk_mali", "clk_gpu";
        power-domains = <0x21 0x7>;
        #cooling-cells = <0x2>;
        operating-points-v2 = <0x63>;
        status = "okay";
        mali-supply = <0x64>;
        phandle = <0x1d>;

        power-model {
            compatible = "simple-power-model";
            leakage-range = <0x5 0xf>;
            ls = <0xffffa23e 0x5927 0x0>;
            static-coefficient = <0x186a0>;
            dynamic-coefficient = <0x3b9>;
            ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>;
            thermal-zone = "gpu-thermal";
            phandle = <0x173>;
        };
    };

    opp-table2 {
        compatible = "operating-points-v2";
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0x65 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        phandle = <0x63>;

        opp-200000000 {
            opp-hz = <0x0 0xbebc200>;
            opp-microvolt = <0xc96a8>;
        };

        opp-300000000 {
            opp-hz = <0x0 0x11e1a300>;
            opp-microvolt = <0xc96a8>;
        };

        opp-400000000 {
            opp-hz = <0x0 0x17d78400>;
            opp-microvolt = <0xc96a8>;
        };

        opp-600000000 {
            opp-hz = <0x0 0x23c34600>;
            opp-microvolt = <0xc96a8>;
        };

        opp-700000000 {
            opp-hz = <0x0 0x29b92700>;
            opp-microvolt = <0xdbba0>;
        };

        opp-800000000 {
            opp-hz = <0x0 0x2faf0800>;
            opp-microvolt = <0xe7ef0>;
        };
    };

    pvtm@fde80000 {
        compatible = "rockchip,rk3568-gpu-pvtm";
        reg = <0x0 0xfde80000 0x0 0x100>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;

        pvtm@1 {
            reg = <0x1>;
            clocks = <0x1f 0x1e 0x1f 0x1d>;
            clock-names = "clk", "pclk";
            resets = <0x1f 0x24 0x1f 0x23>;
            reset-names = "rts", "rst-p";
            thermal-zone = "gpu-thermal";
        };
    };

    pvtm@fde90000 {
        compatible = "rockchip,rk3568-npu-pvtm";
        reg = <0x0 0xfde90000 0x0 0x100>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;

        pvtm@2 {
            reg = <0x2>;
            clocks = <0x1f 0x2b 0x1f 0x2a 0x1f 0x25>;
            clock-names = "clk", "pclk", "hclk";
            resets = <0x1f 0x2e 0x1f 0x2d>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };

    vdpu@fdea0400 {
        compatible = "rockchip,vpu-decoder-v2";
        reg = <0x0 0xfdea0400 0x0 0x400>;
        interrupts = <0x0 0x8b 0x4>;
        interrupt-names = "irq_dec";
        clocks = <0x1f 0xee 0x1f 0xef>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        resets = <0x1f 0x11a 0x1f 0x11b>;
        reset-names = "video_a", "video_h";
        iommus = <0x66>;
        power-domains = <0x21 0xb>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x0>;
        rockchip,resetgroup-node = <0x0>;
        status = "okay";
        phandle = <0x174>;
    };

    iommu@fdea0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdea0800 0x0 0x40>;
        interrupts = <0x0 0x8a 0x4>;
        interrupt-names = "vdpu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x1f 0xee 0x1f 0xef>;
        power-domains = <0x21 0xb>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x66>;
    };

    rk_rga@fdeb0000 {
        compatible = "rockchip,rga2";
        reg = <0x0 0xfdeb0000 0x0 0x1000>;
        interrupts = <0x0 0x5a 0x4>;
        clocks = <0x1f 0xf3 0x1f 0xf4 0x1f 0xf5>;
        clock-names = "aclk_rga", "hclk_rga", "clk_rga";
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x175>;
    };

    ebc@fdec0000 {
        compatible = "rockchip,rk3568-ebc-tcon";
        reg = <0x0 0xfdec0000 0x0 0x5000>;
        interrupts = <0x0 0x11 0x4>;
        clocks = <0x1f 0xf9 0x1f 0xfa>;
        clock-names = "hclk", "dclk";
        power-domains = <0x21 0xa>;
        rockchip,grf = <0x32>;
        pinctrl-names = "default";
        pinctrl-0 = <0x68>;
        status = "disabled";
        phandle = <0x176>;
    };

    jpegd@fded0000 {
        compatible = "rockchip,rkv-jpeg-decoder-v1";
        reg = <0x0 0xfded0000 0x0 0x400>;
        interrupts = <0x0 0x3e 0x4>;
        clocks = <0x1f 0xfb 0x1f 0xfc>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x1f 0x12c 0x1f 0x12d>;
        reset-names = "video_a", "video_h";
        iommus = <0x69>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x1>;
        rockchip,resetgroup-node = <0x1>;
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x177>;
    };

    iommu@fded0480 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfded0480 0x0 0x40>;
        interrupts = <0x0 0x3d 0x4>;
        interrupt-names = "jpegd_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x1f 0xfb 0x1f 0xfc>;
        power-domains = <0x21 0xa>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x69>;
    };

    vepu@fdee0000 {
        compatible = "rockchip,vpu-encoder-v2";
        reg = <0x0 0xfdee0000 0x0 0x400>;
        interrupts = <0x0 0x40 0x4>;
        clocks = <0x1f 0xfd 0x1f 0xfe>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x1f 0x12e 0x1f 0x12f>;
        reset-names = "video_a", "video_h";
        iommus = <0x6a>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x2>;
        rockchip,resetgroup-node = <0x2>;
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x178>;
    };

    iommu@fdee0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdee0800 0x0 0x40>;
        interrupts = <0x0 0x3f 0x4>;
        interrupt-names = "vepu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x1f 0xfd 0x1f 0xfe>;
        power-domains = <0x21 0xa>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x6a>;
    };

    iep@fdef0000 {
        compatible = "rockchip,iep-v2";
        reg = <0x0 0xfdef0000 0x0 0x500>;
        interrupts = <0x0 0x38 0x4>;
        clocks = <0x1f 0xf6 0x1f 0xf7 0x1f 0xf8>;
        clock-names = "aclk", "hclk", "sclk";
        resets = <0x1f 0x127 0x1f 0x128 0x1f 0x129>;
        reset-names = "rst_a", "rst_h", "rst_s";
        power-domains = <0x21 0xa>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x5>;
        rockchip,resetgroup-node = <0x5>;
        iommus = <0x6b>;
        status = "okay";
        phandle = <0x179>;
    };

    iommu@fdef0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdef0800 0x0 0x100>;
        interrupts = <0x0 0x38 0x4>;
        interrupt-names = "iep_mmu";
        clocks = <0x1f 0xf6 0x1f 0xf7>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x0>;
        power-domains = <0x21 0xa>;
        status = "okay";
        phandle = <0x6b>;
    };

    eink@fdf00000 {
        compatible = "rockchip,rk3568-eink-tcon";
        reg = <0x0 0xfdf00000 0x0 0x74>;
        interrupts = <0x0 0xb2 0x4>;
        clocks = <0x1f 0xff 0x1f 0x100>;
        clock-names = "pclk", "hclk";
        status = "disabled";
        phandle = <0x17a>;
    };

    rkvenc@fdf40000 {
        compatible = "rockchip,rkv-encoder-v1";
        reg = <0x0 0xfdf40000 0x0 0x400>;
        interrupts = <0x0 0x8c 0x4>;
        interrupt-names = "irq_enc";
        clocks = <0x1f 0x103 0x1f 0x104 0x1f 0x105>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x11b3dc40 0x0 0x11b3dc40>;
        resets = <0x1f 0x133 0x1f 0x134 0x1f 0x135>;
        reset-names = "video_a", "video_h", "video_core";
        assigned-clocks = <0x1f 0x103 0x1f 0x105>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40>;
        iommus = <0x6c>;
        node-name = "rkvenc";
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x3>;
        rockchip,resetgroup-node = <0x3>;
        power-domains = <0x21 0xe>;
        operating-points-v2 = <0x6d>;
        status = "okay";
        venc-supply = <0x62>;
        phandle = <0x17b>;
    };

    rkvenc-opp-table {
        compatible = "operating-points-v2";
        nvmem-cells = <0x7>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x0 0x14050 0x0 0x14051 0x16b48 0x1 0x16b49 0x186a0 0x2>;
        rockchip,pvtm-ch = <0x0 0x5>;
        phandle = <0x6d>;

        opp-297000000 {
            opp-hz = <0x0 0x11b3dc40>;
            opp-microvolt = <0x0>;
        };

        opp-400000000 {
            opp-hz = <0x0 0x17d78400>;
            opp-microvolt = <0xe7ef0>;
            opp-microvolt-L0 = <0xe7ef0>;
            opp-microvolt-L1 = <0xe1d48>;
            opp-microvolt-L2 = <0x0>;
        };
    };

    iommu@fdf40f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdf40f00 0x0 0x40 0x0 0xfdf40f40 0x0 0x40>;
        interrupts = <0x0 0x8d 0x4 0x0 0x8e 0x4>;
        interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
        clocks = <0x1f 0x103 0x1f 0x104>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        #iommu-cells = <0x0>;
        power-domains = <0x21 0xe>;
        status = "okay";
        phandle = <0x6c>;
    };

    rkvdec@fdf80200 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x0 0xfdf80200 0x0 0x400>;
        interrupts = <0x0 0x5b 0x4>;
        interrupt-names = "irq_dec";
        clocks = <0x1f 0x108 0x1f 0x109 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core", "clk_hevc_cabac";
        rockchip,normal-rates = <0x11b3dc40 0x0 0x11b3dc40 0x11b3dc40 0x23c34600>;
        rockchip,advanced-rates = <0x179a7b00 0x0 0x179a7b00 0x179a7b00 0x23c34600>;
        rockchip,default-max-load = <0x1fe000>;
        resets = <0x1f 0x142 0x1f 0x143 0x1f 0x144 0x1f 0x145 0x1f 0x146>;
        assigned-clocks = <0x1f 0x108 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>;
        reset-names = "video_a", "video_h", "video_cabac", "video_core", "video_hevc_cabac";
        power-domains = <0x21 0xd>;
        iommus = <0x6e>;
        rockchip,srv = <0x67>;
        rockchip,taskqueue-node = <0x4>;
        rockchip,resetgroup-node = <0x4>;
        rockchip,sram = <0x6f>;
        rockchip,rcb-iova = <0x10000000 0x10000>;
        rockchip,rcb-min-width = <0x200>;
        status = "okay";
        phandle = <0x17c>;
    };

    iommu@fdf80800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdf80800 0x0 0x40 0x0 0xfdf80840 0x0 0x40>;
        interrupts = <0x0 0x5c 0x4>;
        interrupt-names = "rkvdec_mmu";
        clocks = <0x1f 0x108 0x1f 0x109>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0xd>;
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x6e>;
    };

    mipi-csi2@fdfb0000 {
        compatible = "rockchip,rk3568-mipi-csi2";
        reg = <0x0 0xfdfb0000 0x0 0x10000>;
        reg-names = "csihost_regs";
        interrupts = <0x0 0x8 0x4 0x0 0x9 0x4>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x1f 0xd5>;
        clock-names = "pclk_csi2host";
        resets = <0x1f 0xff>;
        reset-names = "srst_csihost_p";
        status = "disabled";
        phandle = <0x17d>;
    };

    rkcif@fdfe0000 {
        compatible = "rockchip,rk3568-cif";
        reg = <0x0 0xfdfe0000 0x0 0x8000>;
        reg-names = "cif_regs";
        interrupts = <0x0 0x92 0x4>;
        interrupt-names = "cif-intr";
        clocks = <0x1f 0xce 0x1f 0xcf 0x1f 0xd0 0x1f 0xd1>;
        clock-names = "aclk_cif", "hclk_cif", "dclk_cif", "iclk_cif_g";
        resets = <0x1f 0xf7 0x1f 0xf8 0x1f 0xf9 0x1f 0xfb 0x1f 0xfa>;
        reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_p", "rst_cif_i";
        assigned-clocks = <0x1f 0xd0>;
        assigned-clock-rates = <0x11e1a300>;
        power-domains = <0x21 0x8>;
        rockchip,grf = <0x32>;
        iommus = <0x70>;
        status = "okay";
        phandle = <0x71>;
    };

    iommu@fdfe0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdfe0800 0x0 0x100>;
        interrupts = <0x0 0x92 0x4>;
        interrupt-names = "cif_mmu";
        clocks = <0x1f 0xce 0x1f 0xcf>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0x8>;
        rockchip,disable-mmu-reset;
        #iommu-cells = <0x0>;
        status = "disabled";
        phandle = <0x70>;
    };

    rkcif_dvp {
        compatible = "rockchip,rkcif-dvp";
        rockchip,hw = <0x71>;
        status = "okay";
        phandle = <0x73>;

        port {

            endpoint {
                remote-endpoint = <0x72>;
                bus-width = <0x8>;
                vsync-active = <0x0>;
                hsync-active = <0x1>;
                phandle = <0xd3>;
            };
        };
    };

    rkcif_dvp_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x73>;
        status = "disabled";
        phandle = <0x17e>;
    };

    rkcif_mipi_lvds {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x71>;
        status = "disabled";
        phandle = <0x74>;
    };

    rkcif_mipi_lvds_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x74>;
        status = "disabled";
        phandle = <0x17f>;
    };

    rkisp@fdff0000 {
        compatible = "rockchip,rk3568-rkisp";
        reg = <0x0 0xfdff0000 0x0 0x10000>;
        interrupts = <0x0 0x39 0x4 0x0 0x3a 0x4 0x0 0x3c 0x4>;
        interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
        clocks = <0x1f 0xd2 0x1f 0xd3 0x1f 0xd4>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp";
        resets = <0x1f 0xfd 0x1f 0xfc>;
        reset-names = "isp", "isp-h";
        rockchip,grf = <0x32>;
        power-domains = <0x21 0x8>;
        iommus = <0x75>;
        rockchip,iq-feature = <0x3fb 0xf7fe67ff>;
        status = "okay";
        phandle = <0x76>;
    };

    iommu@fdff1a00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfdff1a00 0x0 0x100>;
        interrupts = <0x0 0x3b 0x4>;
        interrupt-names = "isp_mmu";
        clocks = <0x1f 0xd2 0x1f 0xd3>;
        clock-names = "aclk", "iface";
        power-domains = <0x21 0x8>;
        #iommu-cells = <0x0>;
        rockchip,disable-mmu-reset;
        status = "okay";
        phandle = <0x75>;
    };

    rkisp-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x76>;
        status = "okay";
        phandle = <0x180>;

        port {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            endpoint@0 {
                reg = <0x0>;
                remote-endpoint = <0x77>;
                phandle = <0x10a>;
            };
        };
    };

    rkisp-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x76>;
        status = "disabled";
        phandle = <0x181>;
    };

    ethernet@fe010000 {
        compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
        reg = <0x0 0xfe010000 0x0 0x10000>;
        interrupts = <0x0 0x20 0x4 0x0 0x1d 0x4>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x32>;
        clocks = <0x1f 0x186 0x1f 0x189 0x1f 0x189 0x1f 0xc7 0x1f 0xc3 0x1f 0xc4 0x1f 0x189 0x1f 0xc8 0x1f 0xac>;
        clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref", "pclk_xpcs";
        resets = <0x1f 0xec>;
        reset-names = "stmmaceth";
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x78>;
        snps,mtl-rx-config = <0x79>;
        snps,mtl-tx-config = <0x7a>;
        status = "okay";
        phy-mode = "rgmii";
        clock_in_out = "output";
        snps,reset-gpio = <0x7b 0x1 0x1>;
        snps,reset-active-low;
        snps,reset-delays-us = <0x0 0x4e20 0x186a0>;
        assigned-clocks = <0x1f 0x189 0x1f 0x186>;
        assigned-clock-parents = <0x1f 0x187 0x1f 0xc5>;
        assigned-clock-rates = <0x0 0x7735940>;
        pinctrl-names = "default";
        pinctrl-0 = <0x7c 0x7d 0x7e 0x7f 0x80>;
        tx_delay = <0x41>;
        rx_delay = <0x2e>;
        phy-handle = <0x81>;
        phandle = <0x182>;

        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            phandle = <0x183>;

            phy@0 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <0x0>;
                phandle = <0x81>;
            };
        };

        stmmac-axi-config {
            snps,wr_osr_lmt = <0x4>;
            snps,rd_osr_lmt = <0x8>;
            snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>;
            phandle = <0x78>;
        };

        rx-queues-config {
            snps,rx-queues-to-use = <0x1>;
            phandle = <0x79>;

            queue0 {
            };
        };

        tx-queues-config {
            snps,tx-queues-to-use = <0x1>;
            phandle = <0x7a>;

            queue0 {
            };
        };
    };

    vop@fe040000 {
        compatible = "rockchip,rk3568-vop";
        reg = <0x0 0xfe040000 0x0 0x3000 0x0 0xfe044000 0x0 0x1000>;
        reg-names = "regs", "gamma_lut";
        rockchip,grf = <0x32>;
        interrupts = <0x0 0x94 0x4>;
        clocks = <0x1f 0xdd 0x1f 0xde 0x1f 0xdf 0x1f 0xe0 0x1f 0xe1>;
        clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
        iommus = <0x82>;
        power-domains = <0x21 0x9>;
        status = "okay";
        assigned-clocks = <0x1f 0xdf 0x1f 0xe0>;
        assigned-clock-parents = <0x31 0x2 0x1f 0x5>;
        support-multi-area;
        phandle = <0x184>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;
            phandle = <0x12>;

            port@0 {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                reg = <0x0>;
                phandle = <0x185>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x83>;
                    phandle = <0x8f>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x84>;
                    phandle = <0x15>;
                };

                endpoint@2 {
                    reg = <0x2>;
                    remote-endpoint = <0x85>;
                    phandle = <0x16>;
                };

                endpoint@3 {
                    reg = <0x3>;
                    remote-endpoint = <0x86>;
                    phandle = <0x17>;
                };
            };

            port@1 {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                reg = <0x1>;
                phandle = <0x186>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x87>;
                    phandle = <0x14>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x88>;
                    phandle = <0x98>;
                };

                endpoint@2 {
                    reg = <0x2>;
                    remote-endpoint = <0x89>;
                    phandle = <0xa5>;
                };

                endpoint@3 {
                    reg = <0x3>;
                    remote-endpoint = <0x8a>;
                    phandle = <0xa3>;
                };

                endpoint@4 {
                    reg = <0x4>;
                    remote-endpoint = <0x8b>;
                    phandle = <0x18>;
                };
            };

            port@2 {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                reg = <0x2>;
                phandle = <0x187>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x8c>;
                    phandle = <0x2f>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x8d>;
                    phandle = <0x19>;
                };
            };
        };
    };

    iommu@fe043e00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x0 0xfe043e00 0x0 0x100 0x0 0xfe043f00 0x0 0x100>;
        interrupts = <0x0 0x94 0x4>;
        interrupt-names = "vop_mmu";
        clocks = <0x1f 0xdd 0x1f 0xde>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x0>;
        status = "okay";
        phandle = <0x82>;
    };

    dsi@fe060000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x0 0xfe060000 0x0 0x10000>;
        interrupts = <0x0 0x44 0x4>;
        clocks = <0x1f 0xe8 0x1f 0xda 0x8e>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x1f 0x110>;
        reset-names = "apb";
        phys = <0x8e>;
        phy-names = "mipi_dphy";
        power-domains = <0x21 0x9>;
        rockchip,grf = <0x32>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x188>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x189>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x8f>;
                    status = "disabled";
                    phandle = <0x83>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x14>;
                    status = "okay";
                    phandle = <0x87>;
                };
            };

            port@1 {
                reg = <0x1>;

                endpoint {
                    remote-endpoint = <0x90>;
                    phandle = <0x96>;
                };
            };
        };

        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x0>;
            backlight = <0x91>;
            reset-delay-ms = <0x3c>;
            enable-delay-ms = <0x3c>;
            prepare-delay-ms = <0x3c>;
            unprepare-delay-ms = <0x3c>;
            disable-delay-ms = <0x3c>;
            dsi,flags = <0xa03>;
            dsi,format = <0x0>;
            dsi,lanes = <0x4>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x5000128 0x5000110>;
            power-supply = <0x92>;
            reset-gpios = <0x93 0x5 0x1>;
            pinctrl-names = "default";
            pinctrl-0 = <0x94>;
            phandle = <0x18a>;

            display-timings {
                native-mode = <0x95>;
                phandle = <0x18b>;

                timing0 {
                    clock-frequency = <0x7de2900>;
                    hactive = <0x438>;
                    vactive = <0x780>;
                    hfront-porch = <0xf>;
                    hsync-len = <0x2>;
                    hback-porch = <0x1e>;
                    vfront-porch = <0xf>;
                    vsync-len = <0x2>;
                    vback-porch = <0xf>;
                    hsync-active = <0x0>;
                    vsync-active = <0x0>;
                    de-active = <0x0>;
                    pixelclk-active = <0x1>;
                    phandle = <0x95>;
                };
            };

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;

                    endpoint {
                        remote-endpoint = <0x96>;
                        phandle = <0x90>;
                    };
                };
            };
        };
    };

    dsi@fe070000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x0 0xfe070000 0x0 0x10000>;
        interrupts = <0x0 0x45 0x4>;
        clocks = <0x1f 0xe9 0x1f 0xda 0x97>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x1f 0x111>;
        reset-names = "apb";
        phys = <0x97>;
        phy-names = "mipi_dphy";
        power-domains = <0x21 0x9>;
        rockchip,grf = <0x32>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x18c>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x18d>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x15>;
                    status = "disabled";
                    phandle = <0x84>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x98>;
                    status = "disabled";
                    phandle = <0x88>;
                };
            };

            port@1 {
                reg = <0x1>;

                endpoint {
                    remote-endpoint = <0x99>;
                    phandle = <0x9f>;
                };
            };
        };

        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x0>;
            backlight = <0x9a>;
            reset-delay-ms = <0x3c>;
            enable-delay-ms = <0x3c>;
            prepare-delay-ms = <0x3c>;
            unprepare-delay-ms = <0x3c>;
            disable-delay-ms = <0x3c>;
            dsi,flags = <0xa03>;
            dsi,format = <0x0>;
            dsi,lanes = <0x4>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x5000128 0x5000110>;
            power-supply = <0x9b>;
            reset-gpios = <0x9c 0x16 0x1>;
            pinctrl-names = "default";
            pinctrl-0 = <0x9d>;
            phandle = <0x18e>;

            display-timings {
                native-mode = <0x9e>;
                phandle = <0x18f>;

                timing0 {
                    clock-frequency = <0x7de2900>;
                    hactive = <0x438>;
                    vactive = <0x780>;
                    hfront-porch = <0xf>;
                    hsync-len = <0x2>;
                    hback-porch = <0x1e>;
                    vfront-porch = <0xf>;
                    vsync-len = <0x2>;
                    vback-porch = <0xf>;
                    hsync-active = <0x0>;
                    vsync-active = <0x0>;
                    de-active = <0x0>;
                    pixelclk-active = <0x1>;
                    phandle = <0x9e>;
                };
            };

            ports {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                port@0 {
                    reg = <0x0>;

                    endpoint {
                        remote-endpoint = <0x9f>;
                        phandle = <0x99>;
                    };
                };
            };
        };
    };

    hdmi@fe0a0000 {
        compatible = "rockchip,rk3568-dw-hdmi";
        reg = <0x0 0xfe0a0000 0x0 0x20000>;
        interrupts = <0x0 0x2d 0x4>;
        clocks = <0x1f 0xe6 0x1f 0xe7 0x1f 0x193 0x31 0x2 0x1f 0xde>;
        clock-names = "iahb", "isfr", "cec", "ref", "hclk";
        power-domains = <0x21 0x9>;
        reg-io-width = <0x4>;
        rockchip,grf = <0x32>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xa0 0xa1 0xa2>;
        status = "okay";
        rockchip,phy-table = <0x58834d4 0x8009 0x0 0x270 0x9d5b340 0x800b 0x0 0x26d 0xb1069a8 0x800b 0x0 0x1ed 0x11b3dc40 0x800b 0x0 0x1ad 0x2367b880 0x8029 0x0 0x88 0x0 0x0 0x0 0x0>;
        phandle = <0x122>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x190>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x17>;
                    status = "okay";
                    phandle = <0x86>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0xa3>;
                    status = "disabled";
                    phandle = <0x8a>;
                };
            };
        };
    };

    edp@fe0c0000 {
        compatible = "rockchip,rk3568-edp";
        reg = <0x0 0xfe0c0000 0x0 0x10000>;
        interrupts = <0x0 0x12 0x4>;
        clocks = <0x31 0x29 0x1f 0xea 0x1f 0xeb 0x1f 0xda>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x1f 0x113 0x1f 0x112>;
        reset-names = "dp", "apb";
        phys = <0xa4>;
        phy-names = "dp";
        power-domains = <0x21 0x9>;
        status = "okay";
        hpd-gpios = <0x93 0x7 0x0>;
        phandle = <0x191>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                phandle = <0x192>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x16>;
                    status = "okay";
                    phandle = <0x85>;
                };

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0xa5>;
                    status = "disabled";
                    phandle = <0x89>;
                };
            };
        };
    };

    qos@fe128000 {
        compatible = "syscon";
        reg = <0x0 0xfe128000 0x0 0x20>;
        phandle = <0x46>;
    };

    qos@fe138080 {
        compatible = "syscon";
        reg = <0x0 0xfe138080 0x0 0x20>;
        phandle = <0x55>;
    };

    qos@fe138100 {
        compatible = "syscon";
        reg = <0x0 0xfe138100 0x0 0x20>;
        phandle = <0x56>;
    };

    qos@fe138180 {
        compatible = "syscon";
        reg = <0x0 0xfe138180 0x0 0x20>;
        phandle = <0x57>;
    };

    qos@fe148000 {
        compatible = "syscon";
        reg = <0x0 0xfe148000 0x0 0x20>;
        phandle = <0x47>;
    };

    qos@fe148080 {
        compatible = "syscon";
        reg = <0x0 0xfe148080 0x0 0x20>;
        phandle = <0x48>;
    };

    qos@fe148100 {
        compatible = "syscon";
        reg = <0x0 0xfe148100 0x0 0x20>;
        phandle = <0x49>;
    };

    qos@fe150000 {
        compatible = "syscon";
        reg = <0x0 0xfe150000 0x0 0x20>;
        phandle = <0x53>;
    };

    qos@fe158000 {
        compatible = "syscon";
        reg = <0x0 0xfe158000 0x0 0x20>;
        phandle = <0x4d>;
    };

    qos@fe158100 {
        compatible = "syscon";
        reg = <0x0 0xfe158100 0x0 0x20>;
        phandle = <0x4e>;
    };

    qos@fe158180 {
        compatible = "syscon";
        reg = <0x0 0xfe158180 0x0 0x20>;
        phandle = <0x4f>;
    };

    qos@fe158200 {
        compatible = "syscon";
        reg = <0x0 0xfe158200 0x0 0x20>;
        phandle = <0x50>;
    };

    qos@fe158280 {
        compatible = "syscon";
        reg = <0x0 0xfe158280 0x0 0x20>;
        phandle = <0x51>;
    };

    qos@fe158300 {
        compatible = "syscon";
        reg = <0x0 0xfe158300 0x0 0x20>;
        phandle = <0x52>;
    };

    qos@fe180000 {
        compatible = "syscon";
        reg = <0x0 0xfe180000 0x0 0x20>;
        phandle = <0x45>;
    };

    qos@fe190000 {
        compatible = "syscon";
        reg = <0x0 0xfe190000 0x0 0x20>;
        phandle = <0x58>;
    };

    qos@fe190280 {
        compatible = "syscon";
        reg = <0x0 0xfe190280 0x0 0x20>;
        phandle = <0x59>;
    };

    qos@fe190300 {
        compatible = "syscon";
        reg = <0x0 0xfe190300 0x0 0x20>;
        phandle = <0x5a>;
    };

    qos@fe190380 {
        compatible = "syscon";
        reg = <0x0 0xfe190380 0x0 0x20>;
        phandle = <0x5b>;
    };

    qos@fe190400 {
        compatible = "syscon";
        reg = <0x0 0xfe190400 0x0 0x20>;
        phandle = <0x5c>;
    };

    qos@fe198000 {
        compatible = "syscon";
        reg = <0x0 0xfe198000 0x0 0x20>;
        phandle = <0x54>;
    };

    qos@fe1a8000 {
        compatible = "syscon";
        reg = <0x0 0xfe1a8000 0x0 0x20>;
        phandle = <0x4a>;
    };

    qos@fe1a8080 {
        compatible = "syscon";
        reg = <0x0 0xfe1a8080 0x0 0x20>;
        phandle = <0x4b>;
    };

    qos@fe1a8100 {
        compatible = "syscon";
        reg = <0x0 0xfe1a8100 0x0 0x20>;
        phandle = <0x4c>;
    };

    dwmmc@fe000000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x0 0xfe000000 0x0 0x4000>;
        interrupts = <0x0 0x64 0x4>;
        max-frequency = <0x8f0d180>;
        clocks = <0x1f 0xc1 0x1f 0xc2 0x1f 0x18e 0x1f 0x18f>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x100>;
        resets = <0x1f 0xeb>;
        reset-names = "reset";
        status = "disabled";
        phandle = <0x193>;
    };

    dfi@fe230000 {
        reg = <0x0 0xfe230000 0x0 0x400>;
        compatible = "rockchip,rk3568-dfi";
        rockchip,pmugrf = <0x33>;
        status = "disabled";
        phandle = <0xa6>;
    };

    dmc {
        compatible = "rockchip,rk3568-dmc";
        interrupts = <0x0 0xa 0x4>;
        interrupt-names = "complete";
        devfreq-events = <0xa6>;
        clocks = <0x1f 0x1a2>;
        clock-names = "dmc_clk";
        operating-points-v2 = <0xa7>;
        ddr_timing = <0xa8>;
        vop-bw-dmc-freq = <0x0 0x1f9 0x4f1a0 0x1fa 0x1869f 0x80e80>;
        upthreshold = <0x28>;
        downdifferential = <0x14>;
        system-status-freq = <0x1 0xbe6e0 0x8 0xbe6e0 0x2 0xbe6e0 0x10 0xbe6e0 0x10000 0xbe6e0 0x1000 0xbe6e0 0x4000 0xbe6e0 0x2000 0xbe6e0 0xc00 0xbe6e0>;
        auto-min-freq = <0x4f1a0>;
        auto-freq-en = <0x1>;
        #cooling-cells = <0x2>;
        status = "disabled";
        center-supply = <0x62>;
        phandle = <0x13>;
    };

    dmc-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>;
        nvmem-cells = <0xa9 0x7 0x8>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x1388>;
        rockchip,low-temp = <0x0>;
        rockchip,low-temp-adjust-volt = <0x0 0x618 0x61a8>;
        rockchip,leakage-voltage-sel = <0x1 0x50 0x0 0x51 0xfe 0x1>;
        phandle = <0xa7>;

        opp-324000000 {
            opp-hz = <0x0 0x134fd900>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };

        opp-528000000 {
            opp-hz = <0x0 0x1f78a400>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };

        opp-780000000 {
            opp-hz = <0x0 0x2e7ddb00>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };

        opp-920000000 {
            opp-hz = <0x0 0x36d61600>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
            status = "disabled";
        };

        opp-1056000000 {
            opp-hz = <0x0 0x3ef14800>;
            opp-microvolt = <0xdbba0>;
            opp-microvolt-L0 = <0xdbba0>;
            opp-microvolt-L1 = <0xcf850>;
        };
    };

    pcie@fe260000 {
        compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
        #address-cells = <0x3>;
        #size-cells = <0x2>;
        bus-range = <0x0 0xf>;
        clocks = <0x1f 0x81 0x1f 0x82 0x1f 0x83 0x1f 0x84 0x1f 0x85>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
        device_type = "pci";
        interrupts = <0x0 0x4b 0x4 0x0 0x4a 0x4 0x0 0x49 0x4 0x0 0x48 0x4 0x0 0x47 0x4>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x1>;
        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
        interrupt-map = <0x0 0x0 0x0 0x1 0xaa 0x0 0x0 0x0 0x0 0x2 0xaa 0x1 0x0 0x0 0x0 0x3 0xaa 0x2 0x0 0x0 0x0 0x4 0xaa 0x3>;
        linux,pci-domain = <0x0>;
        num-ib-windows = <0x6>;
        num-ob-windows = <0x2>;
        max-link-speed = <0x2>;
        msi-map = <0x0 0xab 0x0 0x1000>;
        num-lanes = <0x1>;
        phys = <0x22 0x2>;
        phy-names = "pcie-phy";
        power-domains = <0x21 0xf>;
        ranges = <0x800 0x0 0x0 0x3 0x0 0x0 0x800000 0x81000000 0x0 0x800000 0x3 0x800000 0x0 0x100000 0x83000000 0x0 0x900000 0x3 0x900000 0x0 0x3f700000>;
        reg = <0x3 0xc0000000 0x0 0x400000 0x0 0xfe260000 0x0 0x10000>;
        reg-names = "pcie-dbi", "pcie-apb";
        resets = <0x1f 0xa1>;
        reset-names = "pipe";
        status = "disabled";
        phandle = <0x194>;

        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x0>;
            #interrupt-cells = <0x1>;
            interrupt-parent = <0x1>;
            interrupts = <0x0 0x48 0x1>;
            phandle = <0xaa>;
        };
    };

    dwmmc@fe2b0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x0 0xfe2b0000 0x0 0x4000>;
        interrupts = <0x0 0x62 0x4>;
        max-frequency = <0x8f0d180>;
        clocks = <0x1f 0xb0 0x1f 0xb1 0x1f 0x18a 0x1f 0x18b>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x100>;
        resets = <0x1f 0xd4>;
        reset-names = "reset";
        status = "okay";
        supports-sd;
        bus-width = <0x4>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        disable-wp;
        sd-uhs-sdr104;
        vmmc-supply = <0xac>;
        vqmmc-supply = <0x2b>;
        pinctrl-names = "default";
        pinctrl-0 = <0xad 0xae 0xaf 0xb0>;
        phandle = <0x195>;
    };

    dwmmc@fe2c0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x0 0xfe2c0000 0x0 0x4000>;
        interrupts = <0x0 0x63 0x4>;
        max-frequency = <0x8f0d180>;
        clocks = <0x1f 0xb2 0x1f 0xb3 0x1f 0x18c 0x1f 0x18d>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x100>;
        resets = <0x1f 0xd6>;
        reset-names = "reset";
        status = "okay";
        supports-sdio;
        bus-width = <0x4>;
        disable-wp;
        cap-sd-highspeed;
        cap-sdio-irq;
        keep-power-in-suspend;
        mmc-pwrseq = <0xb1>;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <0xb2 0xb3 0xb4>;
        sd-uhs-sdr104;
        phandle = <0x196>;
    };

    sfc@fe300000 {
        compatible = "rockchip,sfc";
        reg = <0x0 0xfe300000 0x0 0x4000>;
        interrupts = <0x0 0x65 0x4>;
        clocks = <0x1f 0x78 0x1f 0x76>;
        clock-names = "clk_sfc", "hclk_sfc";
        assigned-clocks = <0x1f 0x78>;
        assigned-clock-rates = <0x5f5e100>;
        status = "okay";
        phandle = <0x197>;
    };

    sdhci@fe310000 {
        compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
        reg = <0x0 0xfe310000 0x0 0x10000>;
        interrupts = <0x0 0x13 0x4>;
        assigned-clocks = <0x1f 0x7b 0x1f 0x7d>;
        assigned-clock-rates = <0xbebc200 0x16e3600>;
        clocks = <0x1f 0x7c 0x1f 0x7a 0x1f 0x79 0x1f 0x7b 0x1f 0x7d>;
        clock-names = "core", "bus", "axi", "block", "timer";
        status = "okay";
        bus-width = <0x8>;
        supports-emmc;
        non-removable;
        max-frequency = <0xbebc200>;
        phandle = <0x198>;
    };

    nandc@fe330000 {
        compatible = "rockchip,rk-nandc-v9";
        reg = <0x0 0xfe330000 0x0 0x4000>;
        interrupts = <0x0 0x46 0x4>;
        nandc_id = <0x0>;
        clocks = <0x1f 0x75 0x1f 0x74>;
        clock-names = "clk_nandc", "hclk_nandc";
        status = "okay";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        phandle = <0x199>;

        nand@0 {
            reg = <0x0>;
            nand-bus-width = <0x8>;
            nand-ecc-mode = "hw";
            nand-ecc-strength = <0x10>;
            nand-ecc-step-size = <0x400>;
        };
    };

    crypto@fe380000 {
        compatible = "rockchip,rk3568-crypto";
        reg = <0x0 0xfe380000 0x0 0x4000>;
        interrupts = <0x0 0x4 0x4>;
        clocks = <0x1f 0x6a 0x1f 0x6b 0x1f 0x6c 0x1f 0x6d>;
        clock-names = "aclk", "hclk", "sclk", "apb_pclk";
        assigned-clocks = <0x1f 0x6c>;
        assigned-clock-rates = <0xbebc200>;
        resets = <0x1f 0x69>;
        reset-names = "crypto-rst";
        status = "disabled";
        phandle = <0x19a>;
    };

    rng@fe388000 {
        compatible = "rockchip,cryptov2-rng";
        reg = <0x0 0xfe388000 0x0 0x2000>;
        clocks = <0x1f 0x70 0x1f 0x6f>;
        clock-names = "clk_trng", "hclk_trng";
        resets = <0x1f 0x6d>;
        reset-names = "reset";
        status = "okay";
        phandle = <0x19b>;
    };

    otp@fe38c000 {
        compatible = "rockchip,rk3568-otp";
        reg = <0x0 0xfe38c000 0x0 0x4000>;
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        clocks = <0x1f 0x73 0x1f 0x72 0x1f 0x71 0x1f 0x181>;
        clock-names = "usr", "sbpi", "apb", "phy";
        resets = <0x1f 0x1cf>;
        reset-names = "otp_phy";
        phandle = <0x19c>;

        cpu-code@2 {
            reg = <0x2 0x2>;
            phandle = <0xf>;
        };

        cpu-version@8 {
            reg = <0x8 0x1>;
            bits = <0x3 0x3>;
            phandle = <0xe>;
        };

        mbist-vmin@9 {
            reg = <0x9 0x1>;
            bits = <0x0 0x4>;
            phandle = <0x8>;
        };

        id@a {
            reg = <0xa 0x10>;
            phandle = <0xd>;
        };

        cpu-leakage@1a {
            reg = <0x1a 0x1>;
            phandle = <0x6>;
        };

        log-leakage@1b {
            reg = <0x1b 0x1>;
            phandle = <0xa9>;
        };

        npu-leakage@1c {
            reg = <0x1c 0x1>;
            phandle = <0x60>;
        };

        gpu-leakage@1d {
            reg = <0x1d 0x1>;
            phandle = <0x65>;
        };

        core-pvtm@2a {
            reg = <0x2a 0x2>;
            phandle = <0x7>;
        };
    };

    i2s@fe400000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe400000 0x0 0x1000>;
        interrupts = <0x0 0x34 0x4>;
        clocks = <0x1f 0x3f 0x1f 0x43 0x1f 0x39>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x0>;
        dma-names = "tx";
        resets = <0x1f 0x50 0x1f 0x51>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        rockchip,playback-only;
        #sound-dai-cells = <0x0>;
        status = "okay";
        phandle = <0x121>;
    };

    i2s@fe410000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe410000 0x0 0x1000>;
        interrupts = <0x0 0x35 0x4>;
        clocks = <0x1f 0x47 0x1f 0x4b 0x1f 0x3a>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x2 0xb5 0x3>;
        dma-names = "tx", "rx";
        resets = <0x1f 0x52 0x1f 0x53>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xb6 0xb7 0xb8 0xb9>;
        status = "disabled";
        rockchip,clk-trcm = <0x1>;
        phandle = <0xc6>;
    };

    i2s@fe420000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe420000 0x0 0x1000>;
        interrupts = <0x0 0x36 0x4>;
        clocks = <0x1f 0x4f 0x1f 0x4f 0x1f 0x3b>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x4 0xb5 0x5>;
        dma-names = "tx", "rx";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        rockchip,clk-trcm = <0x1>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xba 0xbb 0xbc 0xbd>;
        status = "disabled";
        phandle = <0x19d>;
    };

    i2s@fe430000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x0 0xfe430000 0x0 0x1000>;
        interrupts = <0x0 0x37 0x4>;
        clocks = <0x1f 0x53 0x1f 0x57 0x1f 0x3c>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0xb5 0x6 0xb5 0x7>;
        dma-names = "tx", "rx";
        resets = <0x1f 0x55 0x1f 0x56>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x1f>;
        rockchip,grf = <0x32>;
        rockchip,clk-trcm = <0x1>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xbe 0xbf 0xc0 0xc1>;
        status = "okay";
        phandle = <0x11d>;
    };

    pdm@fe440000 {
        compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
        reg = <0x0 0xfe440000 0x0 0x1000>;
        clocks = <0x1f 0x5a 0x1f 0x59>;
        clock-names = "pdm_clk", "pdm_hclk";
        dmas = <0xb5 0x9>;
        dma-names = "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0xc2 0xc3 0xc4 0xc5>;
        #sound-dai-cells = <0x0>;
        status = "disabled";
        phandle = <0x123>;
    };

    vad@fe450000 {
        compatible = "rockchip,rk3568-vad";
        reg = <0x0 0xfe450000 0x0 0x10000>;
        reg-names = "vad";
        clocks = <0x1f 0x5b>;
        clock-names = "hclk";
        interrupts = <0x0 0x89 0x4>;
        rockchip,audio-src = <0xc6>;
        rockchip,det-channel = <0x0>;
        rockchip,mode = <0x0>;
        #sound-dai-cells = <0x0>;
        status = "disabled";
        rockchip,buffer-time-ms = <0x80>;
        phandle = <0x128>;
    };

    spdif@fe460000 {
        compatible = "rockchip,rk3568-spdif";
        reg = <0x0 0xfe460000 0x0 0x1000>;
        interrupts = <0x0 0x66 0x4>;
        dmas = <0xb5 0x1>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x1f 0x5f 0x1f 0x5c>;
        #sound-dai-cells = <0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0xc7>;
        status = "okay";
        phandle = <0x126>;
    };

    audpwm@fe470000 {
        compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
        reg = <0x0 0xfe470000 0x0 0x1000>;
        clocks = <0x1f 0x63 0x1f 0x60>;
        clock-names = "clk", "hclk";
        dmas = <0xb5 0x8>;
        dma-names = "tx";
        #sound-dai-cells = <0x0>;
        rockchip,sample-width-bits = <0xb>;
        rockchip,interpolat-points = <0x1>;
        status = "disabled";
        phandle = <0x19e>;
    };

    codec-digital@fe478000 {
        compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
        reg = <0x0 0xfe478000 0x0 0x1000>;
        clocks = <0x1f 0x67 0x1f 0x66 0x1f 0x65 0x1f 0x64>;
        clock-names = "adc", "dac", "i2c", "pclk";
        pinctrl-names = "default";
        pinctrl-0 = <0xc8>;
        resets = <0x1f 0x5f>;
        reset-names = "reset";
        rockchip,grf = <0x32>;
        #sound-dai-cells = <0x0>;
        status = "disabled";
        phandle = <0x11e>;
    };

    dmac@fe530000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x0 0xfe530000 0x0 0x4000>;
        interrupts = <0x0 0xe 0x4 0x0 0xd 0x4>;
        clocks = <0x1f 0x10d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x1>;
        arm,pl330-periph-burst;
        phandle = <0x3f>;
    };

    dmac@fe550000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x0 0xfe550000 0x0 0x4000>;
        interrupts = <0x0 0x10 0x4 0x0 0xf 0x4>;
        clocks = <0x1f 0x10d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x1>;
        arm,pl330-periph-burst;
        phandle = <0xb5>;
    };

    rkscr@fe560000 {
        compatible = "rockchip-scr";
        reg = <0x0 0xfe560000 0x0 0x10000>;
        interrupts = <0x0 0x61 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xc9>;
        clocks = <0x1f 0x114>;
        clock-names = "g_pclk_sim_card";
        status = "disabled";
        phandle = <0x19f>;
    };

    can@fe570000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x0 0xfe570000 0x0 0x1000>;
        interrupts = <0x0 0x1 0x4>;
        clocks = <0x1f 0x141 0x1f 0x140>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x1f 0x155 0x1f 0x154>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x1>;
        rx-fifo-depth = <0x6>;
        status = "disabled";
        assigned-clocks = <0x1f 0x141>;
        assigned-clock-rates = <0x8f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0xca>;
        phandle = <0x1a0>;
    };

    can@fe580000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x0 0xfe580000 0x0 0x1000>;
        interrupts = <0x0 0x2 0x4>;
        clocks = <0x1f 0x143 0x1f 0x142>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x1f 0x157 0x1f 0x156>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x1>;
        rx-fifo-depth = <0x6>;
        status = "disabled";
        assigned-clocks = <0x1f 0x143>;
        assigned-clock-rates = <0x8f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcb>;
        phandle = <0x1a1>;
    };

    can@fe590000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x0 0xfe590000 0x0 0x1000>;
        interrupts = <0x0 0x3 0x4>;
        clocks = <0x1f 0x145 0x1f 0x144>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x1f 0x159 0x1f 0x158>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x1>;
        rx-fifo-depth = <0x6>;
        status = "disabled";
        assigned-clocks = <0x1f 0x145>;
        assigned-clock-rates = <0x8f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcc>;
        phandle = <0x1a2>;
    };

    i2c@fe5a0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5a0000 0x0 0x1000>;
        clocks = <0x1f 0x148 0x1f 0x147>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x2f 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcd>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x1a3>;

        gt1x@14 {
            compatible = "goodix,gt1x";
            reg = <0x14>;
            pinctrl-names = "default";
            pinctrl-0 = <0xce>;
            goodix,rst-gpio = <0x35 0xe 0x0>;
            goodix,irq-gpio = <0x35 0xd 0x8>;
            power-supply = <0x92>;
            status = "disabled";
            phandle = <0x1a4>;
        };
    };

    i2c@fe5b0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5b0000 0x0 0x1000>;
        clocks = <0x1f 0x14a 0x1f 0x149>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x30 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xcf>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x1a5>;

        gc2145@3c {
            status = "okay";
            compatible = "galaxycore,gc2145";
            reg = <0x3c>;
            clocks = <0x1f 0xd6>;
            clock-names = "xvclk";
            power-domains = <0x21 0x8>;
            pinctrl-names = "default";
            pinctrl-0 = <0xd0 0xd1 0xd2>;
            power-gpios = <0x7b 0x1c 0x0>;
            pwdn-gpios = <0x7b 0x1a 0x0>;
            rockchip,camera-module-index = <0x1>;
            rockchip,camera-module-facing = "front";
            rockchip,camera-module-name = "CameraKing";
            rockchip,camera-module-lens-name = "Largan";
            phandle = <0x1a6>;

            port {

                endpoint {
                    remote-endpoint = <0xd3>;
                    phandle = <0x72>;
                };
            };
        };

        ov5695@36 {
            status = "okay";
            compatible = "ovti,ov5695";
            reg = <0x36>;
            clocks = <0x1f 0xd7>;
            clock-names = "xvclk";
            power-domains = <0x21 0x8>;
            pinctrl-names = "default";
            pinctrl-0 = <0xd4>;
            reset-gpios = <0x7b 0x18 0x0>;
            pwdn-gpios = <0x7b 0x16 0x0>;
            rockchip,camera-module-index = <0x0>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "TongJu";
            rockchip,camera-module-lens-name = "CHT842-MD";
            phandle = <0x1a7>;

            port {

                endpoint {
                    remote-endpoint = <0xd5>;
                    data-lanes = <0x1 0x2>;
                    phandle = <0x108>;
                };
            };
        };

        gc8034@37 {
            compatible = "galaxycore,gc8034";
            status = "okay";
            reg = <0x37>;
            clocks = <0x1f 0xd7>;
            clock-names = "xvclk";
            power-domains = <0x21 0x8>;
            pinctrl-names = "default";
            pinctrl-0 = <0xd4>;
            reset-gpios = <0x7b 0x18 0x1>;
            pwdn-gpios = <0x7b 0x16 0x1>;
            rockchip,camera-module-index = <0x0>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "RK-CMK-8M-2-v1";
            rockchip,camera-module-lens-name = "CK8401";
            phandle = <0x1a8>;

            port {

                endpoint {
                    remote-endpoint = <0xd6>;
                    data-lanes = <0x1 0x2 0x3 0x4>;
                    phandle = <0x109>;
                };
            };
        };
    };

    i2c@fe5c0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5c0000 0x0 0x1000>;
        clocks = <0x1f 0x14c 0x1f 0x14b>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x31 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xd7>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x1a9>;
    };

    i2c@fe5d0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5d0000 0x0 0x1000>;
        clocks = <0x1f 0x14e 0x1f 0x14d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x32 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xd8>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "disabled";
        phandle = <0x1aa>;
    };

    i2c@fe5e0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x0 0xfe5e0000 0x0 0x1000>;
        clocks = <0x1f 0x150 0x1f 0x14f>;
        clock-names = "i2c", "pclk";
        interrupts = <0x0 0x33 0x4>;
        pinctrl-names = "default";
        pinctrl-0 = <0xd9>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        status = "okay";
        phandle = <0x1ab>;

        mxc6655xa@15 {
            status = "okay";
            compatible = "gs_mxc6655xa";
            pinctrl-names = "default";
            pinctrl-0 = <0xda>;
            reg = <0x15>;
            irq-gpio = <0x7b 0x11 0x8>;
            irq_enable = <0x0>;
            poll_delay_ms = <0x1e>;
            type = <0x2>;
            power-off-in-suspend = <0x1>;
            layout = <0x1>;
            phandle = <0x1ac>;
        };
    };

    timer@fe5f0000 {
        compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
        reg = <0x0 0xfe5f0000 0x0 0x1000>;
        interrupts = <0x0 0x6d 0x4>;
        clocks = <0x1f 0x16c 0x1f 0x16d>;
        clock-names = "pclk", "timer";
        phandle = <0x1ad>;
    };

    watchdog@fe600000 {
        compatible = "snps,dw-wdt";
        reg = <0x0 0xfe600000 0x0 0x100>;
        clocks = <0x1f 0x116 0x1f 0x115>;
        clock-names = "tclk", "pclk";
        interrupts = <0x0 0x95 0x4>;
        status = "okay";
        phandle = <0x1ae>;
    };

    spi@fe610000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe610000 0x0 0x1000>;
        interrupts = <0x0 0x67 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x152 0x1f 0x151>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x14 0x3f 0x15>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xdb 0xdc 0xdd>;
        pinctrl-1 = <0xdb 0xdc 0xde>;
        status = "disabled";
        phandle = <0x1af>;
    };

    spi@fe620000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe620000 0x0 0x1000>;
        interrupts = <0x0 0x68 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x154 0x1f 0x153>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x16 0x3f 0x17>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xdf 0xe0 0xe1>;
        pinctrl-1 = <0xdf 0xe0 0xe2>;
        status = "disabled";
        phandle = <0x1b0>;
    };

    spi@fe630000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe630000 0x0 0x1000>;
        interrupts = <0x0 0x69 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x156 0x1f 0x155>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x18 0x3f 0x19>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xe3 0xe4 0xe5>;
        pinctrl-1 = <0xe3 0xe4 0xe6>;
        status = "disabled";
        phandle = <0x1b1>;
    };

    spi@fe640000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x0 0xfe640000 0x0 0x1000>;
        interrupts = <0x0 0x6a 0x4>;
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        clocks = <0x1f 0x158 0x1f 0x157>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x3f 0x1a 0x3f 0x1b>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0xe7 0xe8 0xe9>;
        pinctrl-1 = <0xe7 0xe8 0xea>;
        status = "disabled";
        phandle = <0x1b2>;
    };

    serial@fe650000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe650000 0x0 0x100>;
        interrupts = <0x0 0x75 0x4>;
        clocks = <0x1f 0x11f 0x1f 0x11c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x2 0x3f 0x3>;
        pinctrl-names = "default";
        pinctrl-0 = <0xeb 0xec>;
        status = "okay";
        phandle = <0x1b3>;
    };

    serial@fe660000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe660000 0x0 0x100>;
        interrupts = <0x0 0x76 0x4>;
        clocks = <0x1f 0x123 0x1f 0x120>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x4 0x3f 0x5>;
        pinctrl-names = "default";
        pinctrl-0 = <0xed>;
        status = "disabled";
        phandle = <0x1b4>;
    };

    serial@fe670000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe670000 0x0 0x100>;
        interrupts = <0x0 0x77 0x4>;
        clocks = <0x1f 0x127 0x1f 0x124>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x6 0x3f 0x7>;
        pinctrl-names = "default";
        pinctrl-0 = <0xee>;
        status = "disabled";
        phandle = <0x1b5>;
    };

    serial@fe680000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe680000 0x0 0x100>;
        interrupts = <0x0 0x78 0x4>;
        clocks = <0x1f 0x12b 0x1f 0x128>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x8 0x3f 0x9>;
        pinctrl-names = "default";
        pinctrl-0 = <0xef>;
        status = "disabled";
        phandle = <0x1b6>;
    };

    serial@fe690000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe690000 0x0 0x100>;
        interrupts = <0x0 0x79 0x4>;
        clocks = <0x1f 0x12f 0x1f 0x12c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0xa 0x3f 0xb>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf0>;
        status = "disabled";
        phandle = <0x1b7>;
    };

    serial@fe6a0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6a0000 0x0 0x100>;
        interrupts = <0x0 0x7a 0x4>;
        clocks = <0x1f 0x133 0x1f 0x130>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0xc 0x3f 0xd>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf1>;
        status = "disabled";
        phandle = <0x1b8>;
    };

    serial@fe6b0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6b0000 0x0 0x100>;
        interrupts = <0x0 0x7b 0x4>;
        clocks = <0x1f 0x137 0x1f 0x134>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0xe 0x3f 0xf>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf2>;
        status = "disabled";
        phandle = <0x1b9>;
    };

    serial@fe6c0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6c0000 0x0 0x100>;
        interrupts = <0x0 0x7c 0x4>;
        clocks = <0x1f 0x13b 0x1f 0x138>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x10 0x3f 0x11>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf3>;
        status = "disabled";
        phandle = <0x1ba>;
    };

    serial@fe6d0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x0 0xfe6d0000 0x0 0x100>;
        interrupts = <0x0 0x7d 0x4>;
        clocks = <0x1f 0x13f 0x1f 0x13c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x2>;
        reg-io-width = <0x4>;
        dmas = <0x3f 0x12 0x3f 0x13>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf4>;
        status = "disabled";
        phandle = <0x1bb>;
    };

    pwm@fe6e0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6e0000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf5>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x11f>;
    };

    pwm@fe6e0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6e0010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf6>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x120>;
    };

    pwm@fe6e0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6e0020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf7>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1bc>;
    };

    pwm@fe6e0030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x0 0xfe6e0030 0x0 0x10>;
        interrupts = <0x0 0x53 0x4 0x0 0x57 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "default";
        pinctrl-0 = <0xf8>;
        clocks = <0x1f 0x15a 0x1f 0x159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        remote_pwm_id = <0x3>;
        handle_cpu_id = <0x1>;
        remote_support_psci = <0x0>;
        phandle = <0x1bd>;

        ir_key1 {
            rockchip,usercode = <0x4040>;
            rockchip,key_table = <0xf2 0xe8 0xba 0x9e 0xf4 0x67 0xf1 0x6c 0xef 0x69 0xee 0x6a 0xbd 0x66 0xea 0x73 0xe3 0x72 0xe2 0xd9 0xb2 0x74 0xbc 0x71 0xec 0x8b 0xbf 0x190 0xe0 0x191 0xe1 0x192 0xe9 0xb7 0xe6 0xf8 0xe8 0xb9 0xe7 0xba 0xf0 0x184 0xbe 0x175>;
        };

        ir_key2 {
            rockchip,usercode = <0xff00>;
            rockchip,key_table = <0xf9 0x66 0xbf 0x9e 0xfb 0x8b 0xaa 0xe8 0xb9 0x67 0xe9 0x6c 0xb8 0x69 0xea 0x6a 0xeb 0x72 0xef 0x73 0xf7 0x71 0xe7 0x74 0xfc 0x74 0xa9 0x72 0xa8 0x72 0xe0 0x72 0xa5 0x72 0xab 0xb7 0xb7 0x184 0xe8 0x184 0xf8 0xb8 0xaf 0xb9 0xed 0x72 0xee 0xba 0xb3 0x72 0xf1 0x72 0xf2 0x72 0xf3 0xd9 0xb4 0x72 0xbe 0xd9>;
        };

        ir_key3 {
            rockchip,usercode = <0x1dcc>;
            rockchip,key_table = <0xee 0xe8 0xf0 0x9e 0xf8 0x67 0xbb 0x6c 0xef 0x69 0xed 0x6a 0xfc 0x66 0xf1 0x73 0xfd 0x72 0xb7 0xd9 0xff 0x74 0xf3 0x71 0xbf 0x8b 0xf9 0x191 0xf5 0x192 0xb3 0x184 0xbe 0x2 0xba 0x3 0xb2 0x4 0xbd 0x5 0xf9 0x6 0xb1 0x7 0xfc 0x8 0xf8 0x9 0xb0 0xa 0xb6 0xb 0xb5 0xe>;
        };
    };

    pwm@fe6f0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xf9>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1be>;
    };

    pwm@fe6f0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfa>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1bf>;
    };

    pwm@fe6f0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfb>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c0>;
    };

    pwm@fe6f0030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe6f0030 0x0 0x10>;
        interrupts = <0x0 0x54 0x4 0x0 0x58 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfc>;
        clocks = <0x1f 0x15d 0x1f 0x15c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c1>;
    };

    pwm@fe700000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700000 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfd>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c2>;
    };

    pwm@fe700010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700010 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xfe>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c3>;
    };

    pwm@fe700020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700020 0x0 0x10>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0xff>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c4>;
    };

    pwm@fe700030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x0 0xfe700030 0x0 0x10>;
        interrupts = <0x0 0x55 0x4 0x0 0x59 0x4>;
        #pwm-cells = <0x3>;
        pinctrl-names = "active";
        pinctrl-0 = <0x100>;
        clocks = <0x1f 0x160 0x1f 0x15f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x1c5>;
    };

    tsadc@fe710000 {
        compatible = "rockchip,rk3568-tsadc";
        reg = <0x0 0xfe710000 0x0 0x100>;
        interrupts = <0x0 0x73 0x4>;
        rockchip,grf = <0x32>;
        clocks = <0x1f 0x111 0x1f 0x10f>;
        clock-names = "tsadc", "apb_pclk";
        assigned-clocks = <0x1f 0x110 0x1f 0x111>;
        assigned-clock-rates = <0x1036640 0xaae60>;
        resets = <0x1f 0x182 0x1f 0x181 0x1f 0x1d7>;
        reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
        #thermal-sensor-cells = <0x1>;
        rockchip,hw-tshut-temp = <0x1d4c0>;
        rockchip,hw-tshut-mode = <0x0>;
        rockchip,hw-tshut-polarity = <0x0>;
        pinctrl-names = "gpio", "otpout";
        pinctrl-0 = <0x101>;
        pinctrl-1 = <0x102>;
        status = "okay";
        phandle = <0x1b>;
    };

    saradc@fe720000 {
        compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
        reg = <0x0 0xfe720000 0x0 0x100>;
        interrupts = <0x0 0x5d 0x4>;
        #io-channel-cells = <0x1>;
        clocks = <0x1f 0x113 0x1f 0x112>;
        clock-names = "saradc", "apb_pclk";
        resets = <0x1f 0x180>;
        reset-names = "saradc-apb";
        status = "okay";
        vref-supply = <0x103>;
        phandle = <0x11b>;
    };

    mailbox@fe780000 {
        compatible = "rockchip,rk3568-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x0 0xfe780000 0x0 0x1000>;
        interrupts = <0x0 0xb7 0x4 0x0 0xb8 0x4 0x0 0xb9 0x4 0x0 0xba 0x4>;
        clocks = <0x1f 0x11b>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x1>;
        status = "disabled";
        phandle = <0x1c6>;
    };

    phy@fe830000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x0 0xfe830000 0x0 0x100>;
        #phy-cells = <0x1>;
        clocks = <0x31 0x22 0x1f 0x17d 0x1f 0x7f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x31 0x22>;
        assigned-clock-rates = <0x5f5e100>;
        resets = <0x1f 0x1c6 0x1f 0x1c7>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x104>;
        rockchip,pipe-phy-grf = <0x105>;
        status = "okay";
        phandle = <0x20>;
    };

    phy@fe840000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x0 0xfe840000 0x0 0x100>;
        #phy-cells = <0x1>;
        clocks = <0x31 0x25 0x1f 0x17e 0x1f 0x7f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x31 0x25>;
        assigned-clock-rates = <0x5f5e100>;
        resets = <0x1f 0x1c8 0x1f 0x1c9>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x104>;
        rockchip,pipe-phy-grf = <0x106>;
        status = "disabled";
        phandle = <0x22>;
    };

    mipi-dphy@fe850000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x0 0xfe850000 0x0 0x10000>;
        clocks = <0x31 0x17 0x1f 0x17a>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy_pll";
        #clock-cells = <0x0>;
        resets = <0x1f 0x1bb>;
        reset-names = "apb";
        power-domains = <0x21 0x9>;
        #phy-cells = <0x0>;
        rockchip,grf = <0x32>;
        status = "okay";
        phandle = <0x8e>;
    };

    video-phy@fe850000 {
        compatible = "rockchip,rk3568-video-phy";
        reg = <0x0 0xfe850000 0x0 0x10000 0x0 0xfe060000 0x0 0x10000>;
        clocks = <0x31 0x17 0x1f 0x17a 0x1f 0xe8>;
        clock-names = "ref", "pclk_phy", "pclk_host";
        #clock-cells = <0x0>;
        resets = <0x1f 0x1bb>;
        reset-names = "rst";
        power-domains = <0x21 0x9>;
        #phy-cells = <0x0>;
        status = "disabled";
        phandle = <0x2e>;
    };

    mipi-dphy@fe860000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x0 0xfe860000 0x0 0x10000>;
        clocks = <0x31 0x19 0x1f 0x17b>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy1_pll";
        #clock-cells = <0x0>;
        resets = <0x1f 0x1bc>;
        reset-names = "apb";
        power-domains = <0x21 0x9>;
        #phy-cells = <0x0>;
        rockchip,grf = <0x32>;
        status = "disabled";
        phandle = <0x97>;
    };

    csi2-dphy-hw@fe870000 {
        compatible = "rockchip,rk3568-csi2-dphy-hw";
        reg = <0x0 0xfe870000 0x0 0x1000>;
        clocks = <0x1f 0x179>;
        clock-names = "pclk";
        rockchip,grf = <0x32>;
        status = "okay";
        phandle = <0x107>;
    };

    csi2-dphy0 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x107>;
        status = "okay";
        phandle = <0x1c7>;

        ports {
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            port@0 {
                reg = <0x0>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                endpoint@1 {
                    reg = <0x1>;
                    remote-endpoint = <0x108>;
                    data-lanes = <0x1 0x2>;
                    phandle = <0xd5>;
                };

                endpoint@2 {
                    reg = <0x2>;
                    remote-endpoint = <0x109>;
                    data-lanes = <0x1 0x2 0x3 0x4>;
                    phandle = <0xd6>;
                };
            };

            port@1 {
                reg = <0x1>;
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                endpoint@0 {
                    reg = <0x0>;
                    remote-endpoint = <0x10a>;
                    phandle = <0x77>;
                };
            };
        };
    };

    csi2-dphy1 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x107>;
        status = "disabled";
        phandle = <0x1c8>;
    };

    csi2-dphy2 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x107>;
        status = "disabled";
        phandle = <0x1c9>;
    };

    usb2-phy@fe8a0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x0 0xfe8a0000 0x0 0x10000>;
        interrupts = <0x0 0x87 0x4>;
        clocks = <0x31 0x13>;
        clock-names = "phyclk";
        #clock-cells = <0x0>;
        assigned-clocks = <0x1f 0xb>;
        assigned-clock-parents = <0x24>;
        clock-output-names = "usb480m_phy";
        rockchip,usbgrf = <0x10b>;
        status = "okay";
        phandle = <0x24>;

        host-port {
            #phy-cells = <0x0>;
            status = "okay";
            phy-supply = <0x10c>;
            phandle = <0x25>;
        };

        otg-port {
            #phy-cells = <0x0>;
            status = "okay";
            vbus-supply = <0x10d>;
            phandle = <0x23>;
        };
    };

    usb2-phy@fe8b0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x0 0xfe8b0000 0x0 0x10000>;
        interrupts = <0x0 0x88 0x4>;
        clocks = <0x31 0x15>;
        clock-names = "phyclk";
        #clock-cells = <0x0>;
        rockchip,usbgrf = <0x10e>;
        status = "okay";
        phandle = <0x26>;

        host-port {
            #phy-cells = <0x0>;
            status = "okay";
            phy-supply = <0x10c>;
            phandle = <0x28>;
        };

        otg-port {
            #phy-cells = <0x0>;
            status = "okay";
            phy-supply = <0x10c>;
            phandle = <0x27>;
        };
    };

    pinctrl {
        compatible = "rockchip,rk3568-pinctrl";
        rockchip,grf = <0x32>;
        rockchip,pmu = <0x33>;
        #address-cells = <0x2>;
        #size-cells = <0x2>;
        ranges;
        pinctrl-names = "default";
        pinctrl-0 = <0x10f>;
        phandle = <0x110>;

        gpio@fdd60000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfdd60000 0x0 0x100>;
            interrupts = <0x0 0x21 0x4>;
            clocks = <0x31 0x2e 0x31 0xc>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x0 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x35>;
        };

        gpio@fe740000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe740000 0x0 0x100>;
            interrupts = <0x0 0x22 0x4>;
            clocks = <0x1f 0x163 0x1f 0x164>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x20 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x93>;
        };

        gpio@fe750000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe750000 0x0 0x100>;
            interrupts = <0x0 0x23 0x4>;
            clocks = <0x1f 0x165 0x1f 0x166>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x40 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x12e>;
        };

        gpio@fe760000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe760000 0x0 0x100>;
            interrupts = <0x0 0x24 0x4>;
            clocks = <0x1f 0x167 0x1f 0x168>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x60 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x7b>;
        };

        gpio@fe770000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x0 0xfe770000 0x0 0x100>;
            interrupts = <0x0 0x25 0x4>;
            clocks = <0x1f 0x169 0x1f 0x16a>;
            gpio-controller;
            #gpio-cells = <0x2>;
            gpio-ranges = <0x110 0x0 0x80 0x20>;
            interrupt-controller;
            #interrupt-cells = <0x2>;
            phandle = <0x9c>;
        };

        pcfg-pull-up {
            bias-pull-up;
            phandle = <0x113>;
        };

        pcfg-pull-down {
            bias-pull-down;
            phandle = <0x11a>;
        };

        pcfg-pull-none {
            bias-disable;
            phandle = <0x111>;
        };

        pcfg-pull-none-drv-level-1 {
            bias-disable;
            drive-strength = <0x1>;
            phandle = <0x115>;
        };

        pcfg-pull-none-drv-level-2 {
            bias-disable;
            drive-strength = <0x2>;
            phandle = <0x114>;
        };

        pcfg-pull-none-drv-level-3 {
            bias-disable;
            drive-strength = <0x3>;
            phandle = <0x119>;
        };

        pcfg-pull-up-drv-level-1 {
            bias-pull-up;
            drive-strength = <0x1>;
            phandle = <0x118>;
        };

        pcfg-pull-up-drv-level-2 {
            bias-pull-up;
            drive-strength = <0x2>;
            phandle = <0x112>;
        };

        pcfg-pull-none-smt {
            bias-disable;
            input-schmitt-enable;
            phandle = <0x116>;
        };

        pcfg-output-low {
            output-low;
            phandle = <0x117>;
        };

        acodec {

            acodec-pins {
                rockchip,pins = <0x1 0x9 0x5 0x111 0x1 0x1 0x5 0x111 0x1 0x0 0x5 0x111 0x1 0x7 0x5 0x111 0x1 0x8 0x5 0x111 0x1 0x3 0x5 0x111 0x1 0x5 0x5 0x111>;
                phandle = <0xc8>;
            };
        };

        cam {

            cam-clkout0 {
                rockchip,pins = <0x4 0x7 0x1 0x111>;
                phandle = <0xd4>;
            };

            camera-pwr {
                rockchip,pins = <0x0 0x11 0x0 0x111>;
                phandle = <0x133>;
            };
        };

        can0 {

            can0m1-pins {
                rockchip,pins = <0x2 0x2 0x4 0x111 0x2 0x1 0x4 0x111>;
                phandle = <0xca>;
            };
        };

        can1 {

            can1m1-pins {
                rockchip,pins = <0x4 0x12 0x3 0x111 0x4 0x13 0x3 0x111>;
                phandle = <0xcb>;
            };
        };

        can2 {

            can2m1-pins {
                rockchip,pins = <0x2 0x9 0x4 0x111 0x2 0xa 0x4 0x111>;
                phandle = <0xcc>;
            };
        };

        cif {

            cif-clk {
                rockchip,pins = <0x4 0x10 0x1 0x111>;
                phandle = <0xd0>;
            };

            cif-dvp-clk {
                rockchip,pins = <0x4 0x11 0x1 0x111 0x4 0xe 0x1 0x111 0x4 0xf 0x1 0x111>;
                phandle = <0xd1>;
            };

            cif-dvp-bus16 {
                rockchip,pins = <0x3 0x1e 0x1 0x111 0x3 0x1f 0x1 0x111 0x4 0x0 0x1 0x111 0x4 0x1 0x1 0x111 0x4 0x2 0x1 0x111 0x4 0x3 0x1 0x111 0x4 0x4 0x1 0x111 0x4 0x5 0x1 0x111>;
                phandle = <0xd2>;
            };
        };

        clk32k {

            clk32k-out0 {
                rockchip,pins = <0x0 0x8 0x2 0x111>;
                phandle = <0x1e>;
            };
        };

        ebc {

            ebc-pins {
                rockchip,pins = <0x4 0x10 0x2 0x111 0x4 0xb 0x2 0x111 0x4 0xc 0x2 0x111 0x4 0x6 0x2 0x111 0x4 0x11 0x2 0x111 0x3 0x16 0x2 0x111 0x3 0x17 0x2 0x111 0x3 0x18 0x2 0x111 0x3 0x19 0x2 0x111 0x3 0x1a 0x2 0x111 0x3 0x1b 0x2 0x111 0x3 0x1c 0x2 0x111 0x3 0x1d 0x2 0x111 0x3 0x1e 0x2 0x111 0x3 0x1f 0x2 0x111 0x4 0x0 0x2 0x111 0x4 0x1 0x2 0x111 0x4 0x2 0x2 0x111 0x4 0x3 0x2 0x111 0x4 0x4 0x2 0x111 0x4 0x5 0x2 0x111 0x4 0xe 0x2 0x111 0x4 0xf 0x2 0x111>;
                phandle = <0x68>;
            };
        };

        gmac1 {

            gmac1m0-miim {
                rockchip,pins = <0x3 0x14 0x3 0x111 0x3 0x15 0x3 0x111>;
                phandle = <0x7c>;
            };

            gmac1m0-rx-bus2 {
                rockchip,pins = <0x3 0x9 0x3 0x111 0x3 0xa 0x3 0x111 0x3 0xb 0x3 0x111>;
                phandle = <0x7e>;
            };
        };

        hdmitx {

            hdmitxm0-cec {
                rockchip,pins = <0x4 0x19 0x1 0x111>;
                phandle = <0xa2>;
            };

            hdmitx-scl {
                rockchip,pins = <0x4 0x17 0x1 0x111>;
                phandle = <0xa0>;
            };

            hdmitx-sda {
                rockchip,pins = <0x4 0x18 0x1 0x111>;
                phandle = <0xa1>;
            };
        };

        i2c0 {

            i2c0-xfer {
                rockchip,pins = <0x0 0x9 0x1 0x116 0x0 0xa 0x1 0x116>;
                phandle = <0x34>;
            };
        };

        i2c1 {

            i2c1-xfer {
                rockchip,pins = <0x0 0xb 0x1 0x116 0x0 0xc 0x1 0x116>;
                phandle = <0xcd>;
            };
        };

        i2c2 {

            i2c2m1-xfer {
                rockchip,pins = <0x4 0xd 0x1 0x116 0x4 0xc 0x1 0x116>;
                phandle = <0xcf>;
            };
        };

        i2c3 {

            i2c3m0-xfer {
                rockchip,pins = <0x1 0x1 0x1 0x116 0x1 0x0 0x1 0x116>;
                phandle = <0xd7>;
            };
        };

        i2c4 {

            i2c4m0-xfer {
                rockchip,pins = <0x4 0xb 0x1 0x116 0x4 0xa 0x1 0x116>;
                phandle = <0xd8>;
            };
        };

        i2c5 {

            i2c5m0-xfer {
                rockchip,pins = <0x3 0xb 0x4 0x116 0x3 0xc 0x4 0x116>;
                phandle = <0xd9>;
            };
        };

        i2s1 {

            i2s1m0-lrcktx {
                rockchip,pins = <0x1 0x5 0x1 0x111>;
                phandle = <0xb7>;
            };

            i2s1m0-sclktx {
                rockchip,pins = <0x1 0x3 0x1 0x111>;
                phandle = <0xb6>;
            };

            i2s1m0-sdi0 {
                rockchip,pins = <0x1 0xb 0x1 0x111>;
                phandle = <0xb8>;
            };

            i2s1m0-sdo0 {
                rockchip,pins = <0x1 0x7 0x1 0x111>;
                phandle = <0xb9>;
            };
        };

        i2s2 {

            i2s2m0-lrcktx {
                rockchip,pins = <0x2 0x13 0x1 0x111>;
                phandle = <0xbb>;
            };

            i2s2m0-sclktx {
                rockchip,pins = <0x2 0x12 0x1 0x111>;
                phandle = <0xba>;
            };

            i2s2m0-sdi {
                rockchip,pins = <0x2 0x15 0x1 0x111>;
                phandle = <0xbc>;
            };

            i2s2m0-sdo {
                rockchip,pins = <0x2 0x14 0x1 0x111>;
                phandle = <0xbd>;
            };
        };

        i2s3 {

            i2s3m1-lrck {
                rockchip,pins = <0x4 0x14 0x5 0x111>;
                phandle = <0xbf>;
            };

            i2s3m1-mclk {
                rockchip,pins = <0x4 0x12 0x5 0x111>;
                phandle = <0x3d>;
            };

            i2s3m1-sclk {
                rockchip,pins = <0x4 0x13 0x5 0x111>;
                phandle = <0xbe>;
            };

            i2s3m1-sdi {
                rockchip,pins = <0x4 0x16 0x5 0x111>;
                phandle = <0xc0>;
            };

            i2s3m1-sdo {
                rockchip,pins = <0x4 0x15 0x5 0x111>;
                phandle = <0xc1>;
            };
        };

        lcdc {

            lcdc-ctl {
                rockchip,pins = <0x3 0x0 0x1 0x111 0x2 0x18 0x1 0x111 0x2 0x19 0x1 0x111 0x2 0x1a 0x1 0x111 0x2 0x1b 0x1 0x111 0x2 0x1c 0x1 0x111 0x2 0x1d 0x1 0x111 0x2 0x1e 0x1 0x111 0x2 0x1f 0x1 0x111 0x3 0x1 0x1 0x111 0x3 0x2 0x1 0x111 0x3 0x3 0x1 0x111 0x3 0x4 0x1 0x111 0x3 0x5 0x1 0x111 0x3 0x6 0x1 0x111 0x3 0x7 0x1 0x111 0x3 0x8 0x1 0x111 0x3 0x9 0x1 0x111 0x3 0xa 0x1 0x111 0x3 0xb 0x1 0x111 0x3 0xc 0x1 0x111 0x3 0xd 0x1 0x111 0x3 0xe 0x1 0x111 0x3 0xf 0x1 0x111 0x3 0x10 0x1 0x111 0x3 0x13 0x1 0x111 0x3 0x11 0x1 0x111 0x3 0x12 0x1 0x111>;
                phandle = <0x30>;
            };
        };

        pdm {

            pdmm1-clk1 {
                rockchip,pins = <0x4 0x0 0x4 0x111>;
                phandle = <0xc2>;
            };

            pdmm1-sdi1 {
                rockchip,pins = <0x4 0x1 0x4 0x111>;
                phandle = <0xc3>;
            };

            pdmm1-sdi2 {
                rockchip,pins = <0x4 0x2 0x5 0x111>;
                phandle = <0xc4>;
            };

            pdmm1-sdi3 {
                rockchip,pins = <0x4 0x3 0x5 0x111>;
                phandle = <0xc5>;
            };
        };

        pmic {

            pmic_int {
                rockchip,pins = <0x0 0x3 0x0 0x113>;
                phandle = <0x36>;
            };

            soc_slppin_gpio {
                rockchip,pins = <0x0 0x2 0x0 0x117>;
                phandle = <0x39>;
            };

            soc_slppin_slp {
                rockchip,pins = <0x0 0x2 0x1 0x111>;
                phandle = <0x37>;
            };

            soc_slppin_rst {
                rockchip,pins = <0x0 0x2 0x2 0x111>;
                phandle = <0x1ca>;
            };
        };

        pwm0 {

            pwm0m0-pins {
                rockchip,pins = <0x0 0xf 0x1 0x111>;
                phandle = <0x41>;
            };
        };

        pwm1 {

            pwm1m0-pins {
                rockchip,pins = <0x0 0x10 0x1 0x111>;
                phandle = <0x42>;
            };
        };

        pwm2 {

            pwm2m0-pins {
                rockchip,pins = <0x0 0x11 0x1 0x111>;
                phandle = <0x43>;
            };
        };

        pwm3 {

            pwm3-pins {
                rockchip,pins = <0x0 0x12 0x1 0x111>;
                phandle = <0x44>;
            };
        };

        pwm4 {

            pwm4-pins {
                rockchip,pins = <0x0 0x13 0x1 0x111>;
                phandle = <0xf5>;
            };
        };

        pwm5 {

            pwm5-pins {
                rockchip,pins = <0x0 0x14 0x1 0x111>;
                phandle = <0xf6>;
            };
        };

        pwm6 {

            pwm6-pins {
                rockchip,pins = <0x0 0x15 0x1 0x111>;
                phandle = <0xf7>;
            };
        };

        pwm7 {

            pwm7-pins {
                rockchip,pins = <0x0 0x16 0x1 0x111>;
                phandle = <0xf8>;
            };
        };

        pwm8 {

            pwm8m0-pins {
                rockchip,pins = <0x3 0x9 0x5 0x111>;
                phandle = <0xf9>;
            };
        };

        pwm9 {

            pwm9m0-pins {
                rockchip,pins = <0x3 0xa 0x5 0x111>;
                phandle = <0xfa>;
            };
        };

        pwm10 {

            pwm10m0-pins {
                rockchip,pins = <0x3 0xd 0x5 0x111>;
                phandle = <0xfb>;
            };
        };

        pwm11 {

            pwm11m0-pins {
                rockchip,pins = <0x3 0xe 0x5 0x111>;
                phandle = <0xfc>;
            };
        };

        pwm12 {

            pwm12m0-pins {
                rockchip,pins = <0x3 0xf 0x2 0x111>;
                phandle = <0xfd>;
            };
        };

        pwm13 {

            pwm13m0-pins {
                rockchip,pins = <0x3 0x10 0x2 0x111>;
                phandle = <0xfe>;
            };
        };

        pwm14 {

            pwm14m0-pins {
                rockchip,pins = <0x3 0x14 0x1 0x111>;
                phandle = <0xff>;
            };
        };

        pwm15 {

            pwm15m0-pins {
                rockchip,pins = <0x3 0x15 0x1 0x111>;
                phandle = <0x100>;
            };
        };

        scr {

            scr-pins {
                rockchip,pins = <0x1 0x2 0x3 0x111 0x1 0x7 0x3 0x113 0x1 0x3 0x3 0x113 0x1 0x5 0x3 0x111>;
                phandle = <0xc9>;
            };
        };

        sdmmc0 {

            sdmmc0-bus4 {
                rockchip,pins = <0x1 0x1d 0x1 0x112 0x1 0x1e 0x1 0x112 0x1 0x1f 0x1 0x112 0x2 0x0 0x1 0x112>;
                phandle = <0xad>;
            };

            sdmmc0-clk {
                rockchip,pins = <0x2 0x2 0x1 0x112>;
                phandle = <0xae>;
            };

            sdmmc0-cmd {
                rockchip,pins = <0x2 0x1 0x1 0x112>;
                phandle = <0xaf>;
            };

            sdmmc0-det {
                rockchip,pins = <0x0 0x4 0x1 0x113>;
                phandle = <0xb0>;
            };
        };

        sdmmc1 {

            sdmmc1-bus4 {
                rockchip,pins = <0x2 0x3 0x1 0x112 0x2 0x4 0x1 0x112 0x2 0x5 0x1 0x112 0x2 0x6 0x1 0x112>;
                phandle = <0xb2>;
            };

            sdmmc1-clk {
                rockchip,pins = <0x2 0x8 0x1 0x112>;
                phandle = <0xb4>;
            };

            sdmmc1-cmd {
                rockchip,pins = <0x2 0x7 0x1 0x112>;
                phandle = <0xb3>;
            };
        };

        spdif {

            spdifm0-tx {
                rockchip,pins = <0x1 0x4 0x4 0x111>;
                phandle = <0xc7>;
            };
        };

        spi0 {

            spi0m0-pins {
                rockchip,pins = <0x0 0xd 0x2 0x111 0x0 0x15 0x2 0x111 0x0 0xe 0x2 0x111>;
                phandle = <0xdd>;
            };

            spi0m0-cs0 {
                rockchip,pins = <0x0 0x16 0x2 0x111>;
                phandle = <0xdb>;
            };

            spi0m0-cs1 {
                rockchip,pins = <0x0 0x14 0x2 0x111>;
                phandle = <0xdc>;
            };
        };

        spi1 {

            spi1m0-pins {
                rockchip,pins = <0x2 0xd 0x3 0x111 0x2 0xe 0x3 0x111 0x2 0xf 0x4 0x111>;
                phandle = <0xe1>;
            };

            spi1m0-cs0 {
                rockchip,pins = <0x2 0x10 0x4 0x111>;
                phandle = <0xdf>;
            };

            spi1m0-cs1 {
                rockchip,pins = <0x2 0x16 0x3 0x111>;
                phandle = <0xe0>;
            };
        };

        spi2 {

            spi2m0-pins {
                rockchip,pins = <0x2 0x11 0x4 0x111 0x2 0x12 0x4 0x111 0x2 0x13 0x4 0x111>;
                phandle = <0xe5>;
            };

            spi2m0-cs0 {
                rockchip,pins = <0x2 0x14 0x4 0x111>;
                phandle = <0xe3>;
            };

            spi2m0-cs1 {
                rockchip,pins = <0x2 0x15 0x4 0x111>;
                phandle = <0xe4>;
            };
        };

        spi3 {

            spi3m0-pins {
                rockchip,pins = <0x4 0xb 0x4 0x111 0x4 0x8 0x4 0x111 0x4 0xa 0x4 0x111>;
                phandle = <0xe9>;
            };

            spi3m0-cs0 {
                rockchip,pins = <0x4 0x6 0x4 0x111>;
                phandle = <0xe7>;
            };

            spi3m0-cs1 {
                rockchip,pins = <0x4 0x7 0x4 0x111>;
                phandle = <0xe8>;
            };
        };

        tsadc {

            tsadc-shutorg {
                rockchip,pins = <0x0 0x1 0x2 0x111>;
                phandle = <0x102>;
            };
        };

        uart0 {

            uart0-xfer {
                rockchip,pins = <0x0 0x10 0x3 0x113 0x0 0x11 0x3 0x113>;
                phandle = <0x40>;
            };
        };

        uart1 {

            uart1m0-xfer {
                rockchip,pins = <0x2 0xb 0x2 0x113 0x2 0xc 0x2 0x113>;
                phandle = <0xeb>;
            };

            uart1m0-ctsn {
                rockchip,pins = <0x2 0xe 0x2 0x111>;
                phandle = <0xec>;
            };

            uart1m0-rtsn {
                rockchip,pins = <0x2 0xd 0x2 0x111>;
                phandle = <0x130>;
            };
        };

        uart2 {

            uart2m0-xfer {
                rockchip,pins = <0x0 0x18 0x1 0x113 0x0 0x19 0x1 0x113>;
                phandle = <0xed>;
            };
        };

        uart3 {

            uart3m0-xfer {
                rockchip,pins = <0x1 0x0 0x2 0x113 0x1 0x1 0x2 0x113>;
                phandle = <0xee>;
            };
        };

        uart4 {

            uart4m0-xfer {
                rockchip,pins = <0x1 0x4 0x2 0x113 0x1 0x6 0x2 0x113>;
                phandle = <0xef>;
            };
        };

        uart5 {

            uart5m0-xfer {
                rockchip,pins = <0x2 0x1 0x3 0x113 0x2 0x2 0x3 0x113>;
                phandle = <0xf0>;
            };
        };

        uart6 {

            uart6m0-xfer {
                rockchip,pins = <0x2 0x3 0x3 0x113 0x2 0x4 0x3 0x113>;
                phandle = <0xf1>;
            };
        };

        uart7 {

            uart7m0-xfer {
                rockchip,pins = <0x2 0x5 0x3 0x113 0x2 0x6 0x3 0x113>;
                phandle = <0xf2>;
            };
        };

        uart8 {

            uart8m0-xfer {
                rockchip,pins = <0x2 0x16 0x2 0x113 0x2 0x15 0x3 0x113>;
                phandle = <0xf3>;
            };
        };

        uart9 {

            uart9m0-xfer {
                rockchip,pins = <0x2 0x7 0x3 0x113 0x2 0x8 0x3 0x113>;
                phandle = <0xf4>;
            };
        };

        spi0-hs {

            spi0m0-pins {
                rockchip,pins = <0x0 0xd 0x2 0x118 0x0 0x15 0x2 0x118 0x0 0xe 0x2 0x118>;
                phandle = <0xde>;
            };
        };

        spi1-hs {

            spi1m0-pins {
                rockchip,pins = <0x2 0xd 0x3 0x118 0x2 0xe 0x3 0x118 0x2 0xf 0x4 0x118>;
                phandle = <0xe2>;
            };
        };

        spi2-hs {

            spi2m0-pins {
                rockchip,pins = <0x2 0x11 0x4 0x118 0x2 0x12 0x4 0x118 0x2 0x13 0x4 0x118>;
                phandle = <0xe6>;
            };
        };

        spi3-hs {

            spi3m0-pins {
                rockchip,pins = <0x4 0xb 0x4 0x118 0x4 0x8 0x4 0x118 0x4 0xa 0x4 0x118>;
                phandle = <0xea>;
            };
        };

        gmac-txd-level3 {

            gmac1m0-tx-bus2-level3 {
                rockchip,pins = <0x3 0xd 0x3 0x119 0x3 0xe 0x3 0x119 0x3 0xf 0x3 0x111>;
                phandle = <0x7d>;
            };

            gmac1m0-rgmii-bus-level3 {
                rockchip,pins = <0x3 0x4 0x3 0x111 0x3 0x5 0x3 0x111 0x3 0x2 0x3 0x119 0x3 0x3 0x3 0x119>;
                phandle = <0x80>;
            };
        };

        gmac-txc-level2 {

            gmac1m0-rgmii-clk-level2 {
                rockchip,pins = <0x3 0x7 0x3 0x111 0x3 0x6 0x3 0x114>;
                phandle = <0x7f>;
            };
        };

        gpio-func {

            tsadc-gpio-func {
                rockchip,pins = <0x0 0x1 0x0 0x111>;
                phandle = <0x101>;
            };
        };

        mxc6655xa {

            mxc6655xa_irq_gpio {
                rockchip,pins = <0x3 0x11 0x0 0x111>;
                phandle = <0xda>;
            };
        };

        touch {

            touch-gpio {
                rockchip,pins = <0x0 0xd 0x0 0x113 0x0 0xe 0x0 0x111>;
                phandle = <0xce>;
            };
        };

        sdio-pwrseq {

            wifi-enable-h {
                rockchip,pins = <0x2 0x9 0x0 0x111>;
                phandle = <0x12d>;
            };
        };

        usb {

            vcc5v0-host-en {
                rockchip,pins = <0x0 0x6 0x0 0x111>;
                phandle = <0x12a>;
            };

            vcc5v0-otg-en {
                rockchip,pins = <0x0 0x5 0x0 0x111>;
                phandle = <0x12b>;
            };
        };

        wireless-bluetooth {

            uart8-gpios {
                rockchip,pins = <0x2 0x9 0x0 0x111>;
                phandle = <0x1cb>;
            };

            uart1-gpios {
                rockchip,pins = <0x2 0xd 0x0 0x111>;
                phandle = <0x131>;
            };
        };

        headphone {

            hp-det {
                rockchip,pins = <0x4 0xb 0x0 0x11a>;
                phandle = <0x132>;
            };
        };

        lcd0 {

            lcd-rst-gpio {
                rockchip,pins = <0x1 0x5 0x0 0x111>;
                phandle = <0x94>;
            };
        };

        lcd1 {

            lcd1-rst-gpio {
                rockchip,pins = <0x4 0x16 0x0 0x111>;
                phandle = <0x9d>;
            };
        };

        wireless-wlan {

            wifi-host-wake-irq {
                rockchip,pins = <0x2 0xa 0x0 0x11a>;
                phandle = <0x12f>;
            };
        };

        fddis_ctr {

            dis-ctl {
                rockchip,pins = <0x0 0xb 0x0 0x113 0x0 0xc 0x0 0x113>;
                phandle = <0x10f>;
            };
        };
    };

    adc-keys {
        compatible = "adc-keys";
        io-channels = <0x11b 0x0>;
        io-channel-names = "buttons";
        keyup-threshold-microvolt = <0x1b7740>;
        poll-interval = <0x64>;
        phandle = <0x1cc>;

        vol-up-key {
            label = "volume up";
            linux,code = <0x73>;
            press-threshold-microvolt = <0x6d6>;
        };

        vol-down-key {
            label = "volume down";
            linux,code = <0x72>;
            press-threshold-microvolt = <0x48a1c>;
        };

        menu-key {
            label = "menu";
            linux,code = <0x8b>;
            press-threshold-microvolt = <0xef420>;
        };

        back-key {
            label = "back";
            linux,code = <0x9e>;
            press-threshold-microvolt = <0x13eb9c>;
        };
    };

    audiopwmout-diff {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,audiopwmout-diff";
        simple-audio-card,mclk-fs = <0x100>;
        simple-audio-card,bitclock-master = <0x11c>;
        simple-audio-card,frame-master = <0x11c>;
        phandle = <0x1cd>;

        simple-audio-card,cpu {
            sound-dai = <0x11d>;
        };

        simple-audio-card,codec {
            sound-dai = <0x11e>;
            phandle = <0x11c>;
        };
    };

    backlight {
        compatible = "pwm-backlight";
        pwms = <0x11f 0x0 0x61a8 0x0>;
        brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
        default-brightness-level = <0xc8>;
        phandle = <0x91>;
    };

    backlight1 {
        compatible = "pwm-backlight";
        pwms = <0x120 0x0 0x61a8 0x0>;
        brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
        default-brightness-level = <0xc8>;
        phandle = <0x9a>;
    };

    dc-12v {
        compatible = "regulator-fixed";
        regulator-name = "dc_12v";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0xb71b00>;
        regulator-max-microvolt = <0xb71b00>;
        phandle = <0x129>;
    };

    hdmi-sound {
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <0x80>;
        simple-audio-card,name = "rockchip,hdmi";
        status = "okay";
        phandle = <0x1ce>;

        simple-audio-card,cpu {
            sound-dai = <0x121>;
        };

        simple-audio-card,codec {
            sound-dai = <0x122>;
        };
    };

    dummy-codec {
        status = "disabled";
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0x0>;
        phandle = <0x124>;
    };

    pdm-mic-array {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,name = "rockchip,pdm-mic-array";
        phandle = <0x1cf>;

        simple-audio-card,cpu {
            sound-dai = <0x123>;
        };

        simple-audio-card,codec {
            sound-dai = <0x124>;
        };
    };

    rk809-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,rk809-codec";
        simple-audio-card,mclk-fs = <0x100>;
        phandle = <0x1d0>;

        simple-audio-card,cpu {
            sound-dai = <0x11d>;
        };

        simple-audio-card,codec {
            sound-dai = <0x125>;
        };
    };

    spdif-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,name = "ROCKCHIP,SPDIF";

        simple-audio-card,cpu {
            sound-dai = <0x126>;
        };

        simple-audio-card,codec {
            sound-dai = <0x127>;
        };
    };

    spdif-out {
        status = "okay";
        compatible = "linux,spdif-dit";
        #sound-dai-cells = <0x0>;
        phandle = <0x127>;
    };

    vad-sound {
        status = "disabled";
        compatible = "rockchip,multicodecs-card";
        rockchip,card-name = "rockchip,rk3568-vad";
        rockchip,cpu = <0xc6>;
        rockchip,codec = <0x125 0x128>;
        phandle = <0x1d1>;
    };

    vcc3v3-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x325aa0>;
        regulator-max-microvolt = <0x325aa0>;
        vin-supply = <0x129>;
        phandle = <0x3c>;
    };

    vcc5v0-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x4c4b40>;
        regulator-max-microvolt = <0x4c4b40>;
        vin-supply = <0x129>;
        phandle = <0x3e>;
    };

    vcc5v0-host-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x35 0x6 0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x12a>;
        regulator-name = "vcc5v0_host";
        regulator-always-on;
        phandle = <0x10c>;
    };

    vcc5v0-otg-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x35 0x5 0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x12b>;
        regulator-name = "vcc5v0_otg";
        phandle = <0x10d>;
    };

    vcc3v3-lcd0-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd0_n";
        regulator-boot-on;
        gpio = <0x35 0x10 0x0>;
        enable-active-high;
        phandle = <0x92>;

        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };

    vcc3v3-lcd1-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd1_n";
        regulator-boot-on;
        phandle = <0x9b>;

        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };

    sdio-pwrseq {
        compatible = "mmc-pwrseq-simple";
        clocks = <0x12c 0x1>;
        clock-names = "ext_clock";
        pinctrl-names = "default";
        pinctrl-0 = <0x12d>;
        post-power-on-delay-ms = <0xc8>;
        reset-gpios = <0x12e 0x9 0x1>;
        phandle = <0xb1>;
    };

    wireless-wlan {
        compatible = "wlan-platdata";
        rockchip,grf = <0x32>;
        wifi_chip_type = "ap6398s";
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x12f>;
        WIFI,host_wake_irq = <0x12e 0xa 0x0>;
        phandle = <0x1d2>;
    };

    wireless-bluetooth {
        compatible = "bluetooth-platdata";
        clocks = <0x12c 0x1>;
        clock-names = "ext_clock";
        uart_rts_gpios = <0x12e 0xd 0x1>;
        pinctrl-names = "default", "rts_gpio";
        pinctrl-0 = <0x130>;
        pinctrl-1 = <0x131>;
        BT,reset_gpio = <0x12e 0xf 0x0>;
        BT,wake_gpio = <0x12e 0x11 0x0>;
        BT,wake_host_irq = <0x12e 0x10 0x0>;
        status = "okay";
        phandle = <0x1d3>;
    };

    test-power {
        status = "okay";
    };

    rk-headset {
        compatible = "rockchip_headset";
        headset_gpio = <0x9c 0xb 0x1>;
        pinctrl-names = "default";
        pinctrl-0 = <0x132>;
        phandle = <0x1d4>;
    };

    vcc3v3-vga {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_vga";
        regulator-always-on;
        regulator-boot-on;
        gpio = <0x9c 0xa 0x0>;
        enable-active-high;
        vin-supply = <0x3c>;
        phandle = <0x1d5>;
    };

    vcc-camera-regulator {
        compatible = "regulator-fixed";
        gpio = <0x35 0x11 0x0>;
        pinctrl-names = "default";
        pinctrl-0 = <0x133>;
        regulator-name = "vcc_camera";
        enable-active-high;
        regulator-always-on;
        regulator-boot-on;
        phandle = <0x1d6>;
    };

    chosen {
        bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0";
        phandle = <0x1d7>;
    };

    fiq-debugger {
        compatible = "rockchip,fiq-debugger";
        rockchip,serial-id = <0x2>;
        rockchip,wake-irq = <0x0>;
        rockchip,irq-mode-enable = <0x1>;
        rockchip,baudrate = <0x16e360>;
        interrupts = <0x0 0xfc 0x8>;
        pinctrl-names = "default";
        pinctrl-0 = <0xed>;
        status = "okay";
    };

    debug@fd904000 {
        compatible = "rockchip,debug";
        reg = <0x0 0xfd904000 0x0 0x1000 0x0 0xfd905000 0x0 0x1000 0x0 0xfd906000 0x0 0x1000 0x0 0xfd907000 0x0 0x1000>;
        phandle = <0x1d8>;
    };

    cspmu@fd90c000 {
        compatible = "rockchip,cspmu";
        reg = <0x0 0xfd90c000 0x0 0x1000 0x0 0xfd90d000 0x0 0x1000 0x0 0xfd90e000 0x0 0x1000 0x0 0xfd90f000 0x0 0x1000>;
        phandle = <0x1d9>;
    };

    leds {
        compatible = "gpio-leds";

        power-green {
            gpios = <0x35 0x1b 0x1>;
            linux,default-trigger = "none";
            default-state = "off";
        };

        power-red {
            gpios = <0x35 0x1c 0x0>;
            linux,default-trigger = "none";
            default-state = "off";
        };
    };

    fddis_dev {
        compatible = "fddis_dev";
        fddis_gpio_clk = <0x35 0xb 0x0>;
        fddis_gpio_dat = <0x35 0xc 0x0>;
        status = "okay";
    };

    resume_reboot {
        compatible = "resume_reboot";
        status = "okay";
    };

    __symbols__ {
        ddr_timing = "/ddr_timing";
        cpu0 = "/cpus/cpu@0";
        cpu1 = "/cpus/cpu@100";
        cpu2 = "/cpus/cpu@200";
        cpu3 = "/cpus/cpu@300";
        CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
        cpu0_opp_table = "/cpu0-opp-table";
        display_subsystem = "/display-subsystem";
        route_dsi0 = "/display-subsystem/route/route-dsi0";
        route_dsi1 = "/display-subsystem/route/route-dsi1";
        route_edp = "/display-subsystem/route/route-edp";
        route_hdmi = "/display-subsystem/route/route-hdmi";
        route_lvds = "/display-subsystem/route/route-lvds";
        route_rgb = "/display-subsystem/route/route-rgb";
        optee = "/firmware/optee";
        scmi = "/firmware/scmi";
        scmi_clk = "/firmware/scmi/protocol@14";
        sdei = "/firmware/sdei";
        mpp_srv = "/mpp-srv";
        reserved_memory = "/reserved-memory";
        drm_logo = "/reserved-memory/drm-logo@00000000";
        drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000";
        ramoops = "/reserved-memory/ramoops@110000";
        rockchip_suspend = "/rockchip-suspend";
        rockchip_system_monitor = "/rockchip-system-monitor";
        thermal_zones = "/thermal-zones";
        soc_thermal = "/thermal-zones/soc-thermal";
        threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
        target = "/thermal-zones/soc-thermal/trips/trip-point-1";
        soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
        gpu_thermal = "/thermal-zones/gpu-thermal";
        gmac1_clkin = "/external-gmac1-clock";
        gmac1_xpcsclk = "/xpcs-gmac1-clock";
        i2s1_mclkin_rx = "/i2s1-mclkin-rx";
        i2s1_mclkin_tx = "/i2s1-mclkin-tx";
        i2s2_mclkin = "/i2s2-mclkin";
        i2s3_mclkin = "/i2s3-mclkin";
        mpll = "/mpll";
        xin24m = "/xin24m";
        xin32k = "/xin32k";
        scmi_shmem = "/scmi-shmem@10f000";
        sata1 = "/sata@fc400000";
        sata2 = "/sata@fc800000";
        usbdrd30 = "/usbdrd";
        usbdrd_dwc3 = "/usbdrd/dwc3@fcc00000";
        usbhost30 = "/usbhost";
        usbhost_dwc3 = "/usbhost/dwc3@fd000000";
        gic = "/interrupt-controller@fd400000";
        its = "/interrupt-controller@fd400000/interrupt-controller@fd440000";
        usb_host0_ehci = "/usb@fd800000";
        usb_host0_ohci = "/usb@fd840000";
        usb_host1_ehci = "/usb@fd880000";
        usb_host1_ohci = "/usb@fd8c0000";
        xpcs = "/syscon@fda00000";
        pmugrf = "/syscon@fdc20000";
        pmu_io_domains = "/syscon@fdc20000/io-domains";
        reboot_mode = "/syscon@fdc20000/reboot-mode";
        pipegrf = "/syscon@fdc50000";
        grf = "/syscon@fdc60000";
        io_domains = "/syscon@fdc60000/io-domains";
        lvds = "/syscon@fdc60000/lvds";
        lvds_in_vp1 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@1";
        lvds_in_vp2 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@2";
        rgb = "/syscon@fdc60000/rgb";
        rgb_in_vp2 = "/syscon@fdc60000/rgb/ports/port@0/endpoint@2";
        pipe_phy_grf0 = "/syscon@fdc70000";
        pipe_phy_grf1 = "/syscon@fdc80000";
        pipe_phy_grf2 = "/syscon@fdc90000";
        usb2phy0_grf = "/syscon@fdca0000";
        usb2phy1_grf = "/syscon@fdca8000";
        edp_phy = "/edp-phy@fdcb0000";
        sram = "/sram@fdcc0000";
        rkvdec_sram = "/sram@fdcc0000/rkvdec-sram@0";
        pmucru = "/clock-controller@fdd00000";
        cru = "/clock-controller@fdd20000";
        i2c0 = "/i2c@fdd40000";
        rk809 = "/i2c@fdd40000/pmic@20";
        pinctrl_rk8xx = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx";
        rk817_slppin_null = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_null";
        rk817_slppin_slp = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_slp";
        rk817_slppin_pwrdn = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_pwrdn";
        rk817_slppin_rst = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_rst";
        vdd_logic = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG1";
        vdd_gpu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG2";
        vcc_ddr = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG3";
        vdd_npu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG4";
        vdda0v9_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG1";
        vdda_0v9 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG2";
        vdda0v9_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG3";
        vccio_acodec = "/i2c@fdd40000/pmic@20/regulators/LDO_REG4";
        vccio_sd = "/i2c@fdd40000/pmic@20/regulators/LDO_REG5";
        vcc3v3_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG6";
        vcca_1v8 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG7";
        vcca1v8_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG8";
        vcca1v8_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG9";
        vcc_1v8 = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG5";
        vcc_3v3 = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG1";
        vcc3v3_sd = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG2";
        rk809_codec = "/i2c@fdd40000/pmic@20/codec";
        vdd_cpu = "/i2c@fdd40000/tcs4526@10";
        uart0 = "/serial@fdd50000";
        pwm0 = "/pwm@fdd70000";
        pwm1 = "/pwm@fdd70010";
        pwm2 = "/pwm@fdd70020";
        pwm3 = "/pwm@fdd70030";
        pmu = "/power-management@fdd90000";
        power = "/power-management@fdd90000/power-controller";
        rknpu = "/npu@fde40000";
        npu_opp_table = "/npu-opp-table";
        bus_npu = "/bus-npu";
        bus_npu_opp_table = "/bus-npu-opp-table";
        rknpu_mmu = "/iommu@fde4b000";
        gpu = "/gpu@fde60000";
        gpu_power_model = "/gpu@fde60000/power-model";
        gpu_opp_table = "/opp-table2";
        vdpu = "/vdpu@fdea0400";
        vdpu_mmu = "/iommu@fdea0800";
        rk_rga = "/rk_rga@fdeb0000";
        ebc = "/ebc@fdec0000";
        jpegd = "/jpegd@fded0000";
        jpegd_mmu = "/iommu@fded0480";
        vepu = "/vepu@fdee0000";
        vepu_mmu = "/iommu@fdee0800";
        iep = "/iep@fdef0000";
        iep_mmu = "/iommu@fdef0800";
        eink = "/eink@fdf00000";
        rkvenc = "/rkvenc@fdf40000";
        rkvenc_opp_table = "/rkvenc-opp-table";
        rkvenc_mmu = "/iommu@fdf40f00";
        rkvdec = "/rkvdec@fdf80200";
        rkvdec_mmu = "/iommu@fdf80800";
        mipi_csi2 = "/mipi-csi2@fdfb0000";
        rkcif = "/rkcif@fdfe0000";
        rkcif_mmu = "/iommu@fdfe0800";
        rkcif_dvp = "/rkcif_dvp";
        dvp_in_bcam = "/rkcif_dvp/port/endpoint";
        rkcif_dvp_sditf = "/rkcif_dvp_sditf";
        rkcif_mipi_lvds = "/rkcif_mipi_lvds";
        rkcif_mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf";
        rkisp = "/rkisp@fdff0000";
        rkisp_mmu = "/iommu@fdff1a00";
        rkisp_vir0 = "/rkisp-vir0";
        isp0_in = "/rkisp-vir0/port/endpoint@0";
        rkisp_vir1 = "/rkisp-vir1";
        gmac1 = "/ethernet@fe010000";
        mdio1 = "/ethernet@fe010000/mdio";
        rgmii_phy1 = "/ethernet@fe010000/mdio/phy@0";
        gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config";
        gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config";
        gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config";
        vop = "/vop@fe040000";
        vop_out = "/vop@fe040000/ports";
        vp0 = "/vop@fe040000/ports/port@0";
        vp0_out_dsi0 = "/vop@fe040000/ports/port@0/endpoint@0";
        vp0_out_dsi1 = "/vop@fe040000/ports/port@0/endpoint@1";
        vp0_out_edp = "/vop@fe040000/ports/port@0/endpoint@2";
        vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@3";
        vp1 = "/vop@fe040000/ports/port@1";
        vp1_out_dsi0 = "/vop@fe040000/ports/port@1/endpoint@0";
        vp1_out_dsi1 = "/vop@fe040000/ports/port@1/endpoint@1";
        vp1_out_edp = "/vop@fe040000/ports/port@1/endpoint@2";
        vp1_out_hdmi = "/vop@fe040000/ports/port@1/endpoint@3";
        vp1_out_lvds = "/vop@fe040000/ports/port@1/endpoint@4";
        vp2 = "/vop@fe040000/ports/port@2";
        vp2_out_lvds = "/vop@fe040000/ports/port@2/endpoint@0";
        vp2_out_rgb = "/vop@fe040000/ports/port@2/endpoint@1";
        vop_mmu = "/iommu@fe043e00";
        dsi0 = "/dsi@fe060000";
        dsi0_in = "/dsi@fe060000/ports/port@0";
        dsi0_in_vp0 = "/dsi@fe060000/ports/port@0/endpoint@0";
        dsi0_in_vp1 = "/dsi@fe060000/ports/port@0/endpoint@1";
        dsi_out_panel = "/dsi@fe060000/ports/port@1/endpoint";
        dsi0_panel = "/dsi@fe060000/panel@0";
        disp_timings0 = "/dsi@fe060000/panel@0/display-timings";
        dsi0_timing0 = "/dsi@fe060000/panel@0/display-timings/timing0";
        panel_in_dsi = "/dsi@fe060000/panel@0/ports/port@0/endpoint";
        dsi1 = "/dsi@fe070000";
        dsi1_in = "/dsi@fe070000/ports/port@0";
        dsi1_in_vp0 = "/dsi@fe070000/ports/port@0/endpoint@0";
        dsi1_in_vp1 = "/dsi@fe070000/ports/port@0/endpoint@1";
        dsi1_out_panel = "/dsi@fe070000/ports/port@1/endpoint";
        dsi1_panel = "/dsi@fe070000/panel@0";
        disp_timings1 = "/dsi@fe070000/panel@0/display-timings";
        dsi1_timing0 = "/dsi@fe070000/panel@0/display-timings/timing0";
        panel_in_dsi1 = "/dsi@fe070000/panel@0/ports/port@0/endpoint";
        hdmi = "/hdmi@fe0a0000";
        hdmi_in = "/hdmi@fe0a0000/ports/port";
        hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port/endpoint@0";
        hdmi_in_vp1 = "/hdmi@fe0a0000/ports/port/endpoint@1";
        edp = "/edp@fe0c0000";
        edp_in = "/edp@fe0c0000/ports/port@0";
        edp_in_vp0 = "/edp@fe0c0000/ports/port@0/endpoint@0";
        edp_in_vp1 = "/edp@fe0c0000/ports/port@0/endpoint@1";
        qos_gpu = "/qos@fe128000";
        qos_rkvenc_rd_m0 = "/qos@fe138080";
        qos_rkvenc_rd_m1 = "/qos@fe138100";
        qos_rkvenc_wr_m0 = "/qos@fe138180";
        qos_isp = "/qos@fe148000";
        qos_vicap0 = "/qos@fe148080";
        qos_vicap1 = "/qos@fe148100";
        qos_vpu = "/qos@fe150000";
        qos_ebc = "/qos@fe158000";
        qos_iep = "/qos@fe158100";
        qos_jpeg_dec = "/qos@fe158180";
        qos_jpeg_enc = "/qos@fe158200";
        qos_rga_rd = "/qos@fe158280";
        qos_rga_wr = "/qos@fe158300";
        qos_npu = "/qos@fe180000";
        qos_pcie2x1 = "/qos@fe190000";
        qos_sata1 = "/qos@fe190280";
        qos_sata2 = "/qos@fe190300";
        qos_usb3_0 = "/qos@fe190380";
        qos_usb3_1 = "/qos@fe190400";
        qos_rkvdec = "/qos@fe198000";
        qos_hdcp = "/qos@fe1a8000";
        qos_vop_m0 = "/qos@fe1a8080";
        qos_vop_m1 = "/qos@fe1a8100";
        sdmmc2 = "/dwmmc@fe000000";
        dfi = "/dfi@fe230000";
        dmc = "/dmc";
        dmc_opp_table = "/dmc-opp-table";
        pcie2x1 = "/pcie@fe260000";
        pcie2x1_intc = "/pcie@fe260000/legacy-interrupt-controller";
        sdmmc0 = "/dwmmc@fe2b0000";
        sdmmc1 = "/dwmmc@fe2c0000";
        sfc = "/sfc@fe300000";
        sdhci = "/sdhci@fe310000";
        nandc0 = "/nandc@fe330000";
        crypto = "/crypto@fe380000";
        rng = "/rng@fe388000";
        otp = "/otp@fe38c000";
        cpu_code = "/otp@fe38c000/cpu-code@2";
        otp_cpu_version = "/otp@fe38c000/cpu-version@8";
        mbist_vmin = "/otp@fe38c000/mbist-vmin@9";
        otp_id = "/otp@fe38c000/id@a";
        cpu_leakage = "/otp@fe38c000/cpu-leakage@1a";
        log_leakage = "/otp@fe38c000/log-leakage@1b";
        npu_leakage = "/otp@fe38c000/npu-leakage@1c";
        gpu_leakage = "/otp@fe38c000/gpu-leakage@1d";
        core_pvtm = "/otp@fe38c000/core-pvtm@2a";
        i2s0_8ch = "/i2s@fe400000";
        i2s1_8ch = "/i2s@fe410000";
        i2s2_2ch = "/i2s@fe420000";
        i2s3_2ch = "/i2s@fe430000";
        pdm = "/pdm@fe440000";
        vad = "/vad@fe450000";
        spdif_8ch = "/spdif@fe460000";
        audpwm = "/audpwm@fe470000";
        dig_acodec = "/codec-digital@fe478000";
        dmac0 = "/dmac@fe530000";
        dmac1 = "/dmac@fe550000";
        scr = "/rkscr@fe560000";
        can0 = "/can@fe570000";
        can1 = "/can@fe580000";
        can2 = "/can@fe590000";
        i2c1 = "/i2c@fe5a0000";
        gt1x = "/i2c@fe5a0000/gt1x@14";
        i2c2 = "/i2c@fe5b0000";
        gc2145 = "/i2c@fe5b0000/gc2145@3c";
        gc2145_out = "/i2c@fe5b0000/gc2145@3c/port/endpoint";
        ov5695 = "/i2c@fe5b0000/ov5695@36";
        ov5695_out = "/i2c@fe5b0000/ov5695@36/port/endpoint";
        gc8034 = "/i2c@fe5b0000/gc8034@37";
        gc8034_out = "/i2c@fe5b0000/gc8034@37/port/endpoint";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mxc6655xa = "/i2c@fe5e0000/mxc6655xa@15";
        rktimer = "/timer@fe5f0000";
        wdt = "/watchdog@fe600000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
        uart1 = "/serial@fe650000";
        uart2 = "/serial@fe660000";
        uart3 = "/serial@fe670000";
        uart4 = "/serial@fe680000";
        uart5 = "/serial@fe690000";
        uart6 = "/serial@fe6a0000";
        uart7 = "/serial@fe6b0000";
        uart8 = "/serial@fe6c0000";
        uart9 = "/serial@fe6d0000";
        pwm4 = "/pwm@fe6e0000";
        pwm5 = "/pwm@fe6e0010";
        pwm6 = "/pwm@fe6e0020";
        pwm7 = "/pwm@fe6e0030";
        pwm8 = "/pwm@fe6f0000";
        pwm9 = "/pwm@fe6f0010";
        pwm10 = "/pwm@fe6f0020";
        pwm11 = "/pwm@fe6f0030";
        pwm12 = "/pwm@fe700000";
        pwm13 = "/pwm@fe700010";
        pwm14 = "/pwm@fe700020";
        pwm15 = "/pwm@fe700030";
        tsadc = "/tsadc@fe710000";
        saradc = "/saradc@fe720000";
        mailbox = "/mailbox@fe780000";
        combphy1_usq = "/phy@fe830000";
        combphy2_psq = "/phy@fe840000";
        mipi_dphy0 = "/mipi-dphy@fe850000";
        video_phy0 = "/video-phy@fe850000";
        mipi_dphy1 = "/mipi-dphy@fe860000";
        csi2_dphy_hw = "/csi2-dphy-hw@fe870000";
        csi2_dphy0 = "/csi2-dphy0";
        mipi_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1";
        mipi_in_ucam1 = "/csi2-dphy0/ports/port@0/endpoint@2";
        csidphy_out = "/csi2-dphy0/ports/port@1/endpoint@0";
        csi2_dphy1 = "/csi2-dphy1";
        csi2_dphy2 = "/csi2-dphy2";
        usb2phy0 = "/usb2-phy@fe8a0000";
        u2phy0_host = "/usb2-phy@fe8a0000/host-port";
        u2phy0_otg = "/usb2-phy@fe8a0000/otg-port";
        usb2phy1 = "/usb2-phy@fe8b0000";
        u2phy1_host = "/usb2-phy@fe8b0000/host-port";
        u2phy1_otg = "/usb2-phy@fe8b0000/otg-port";
        pinctrl = "/pinctrl";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        pcfg_pull_up = "/pinctrl/pcfg-pull-up";
        pcfg_pull_down = "/pinctrl/pcfg-pull-down";
        pcfg_pull_none = "/pinctrl/pcfg-pull-none";
        pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
        pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
        pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
        pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
        pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
        pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
        pcfg_output_low = "/pinctrl/pcfg-output-low";
        acodec_pins = "/pinctrl/acodec/acodec-pins";
        cam_clkout0 = "/pinctrl/cam/cam-clkout0";
        camera_pwr = "/pinctrl/cam/camera-pwr";
        can0m1_pins = "/pinctrl/can0/can0m1-pins";
        can1m1_pins = "/pinctrl/can1/can1m1-pins";
        can2m1_pins = "/pinctrl/can2/can2m1-pins";
        cif_clk = "/pinctrl/cif/cif-clk";
        cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
        cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
        clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
        ebc_pins = "/pinctrl/ebc/ebc-pins";
        gmac1m0_miim = "/pinctrl/gmac1/gmac1m0-miim";
        gmac1m0_rx_bus2 = "/pinctrl/gmac1/gmac1m0-rx-bus2";
        hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec";
        hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl";
        hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda";
        i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
        i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
        i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer";
        i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
        i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
        i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
        i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx";
        i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx";
        i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
        i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
        i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx";
        i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx";
        i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi";
        i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo";
        i2s3m1_lrck = "/pinctrl/i2s3/i2s3m1-lrck";
        i2s3m1_mclk = "/pinctrl/i2s3/i2s3m1-mclk";
        i2s3m1_sclk = "/pinctrl/i2s3/i2s3m1-sclk";
        i2s3m1_sdi = "/pinctrl/i2s3/i2s3m1-sdi";
        i2s3m1_sdo = "/pinctrl/i2s3/i2s3m1-sdo";
        lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl";
        pdmm1_clk1 = "/pinctrl/pdm/pdmm1-clk1";
        pdmm1_sdi1 = "/pinctrl/pdm/pdmm1-sdi1";
        pdmm1_sdi2 = "/pinctrl/pdm/pdmm1-sdi2";
        pdmm1_sdi3 = "/pinctrl/pdm/pdmm1-sdi3";
        pmic_int = "/pinctrl/pmic/pmic_int";
        soc_slppin_gpio = "/pinctrl/pmic/soc_slppin_gpio";
        soc_slppin_slp = "/pinctrl/pmic/soc_slppin_slp";
        soc_slppin_rst = "/pinctrl/pmic/soc_slppin_rst";
        pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
        pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
        pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
        pwm3_pins = "/pinctrl/pwm3/pwm3-pins";
        pwm4_pins = "/pinctrl/pwm4/pwm4-pins";
        pwm5_pins = "/pinctrl/pwm5/pwm5-pins";
        pwm6_pins = "/pinctrl/pwm6/pwm6-pins";
        pwm7_pins = "/pinctrl/pwm7/pwm7-pins";
        pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
        pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
        pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
        pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
        pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
        pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
        pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
        pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
        scr_pins = "/pinctrl/scr/scr-pins";
        sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4";
        sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk";
        sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd";
        sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det";
        sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4";
        sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk";
        sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd";
        spdifm0_tx = "/pinctrl/spdif/spdifm0-tx";
        spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
        spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
        spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
        spi1m0_pins = "/pinctrl/spi1/spi1m0-pins";
        spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0";
        spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1";
        spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
        spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
        spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
        spi3m0_pins = "/pinctrl/spi3/spi3m0-pins";
        spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0";
        spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1";
        tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg";
        uart0_xfer = "/pinctrl/uart0/uart0-xfer";
        uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer";
        uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn";
        uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn";
        uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
        uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
        uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
        uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
        uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer";
        uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer";
        uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
        uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer";
        spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins";
        spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins";
        spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins";
        spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins";
        gmac1m0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-tx-bus2-level3";
        gmac1m0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-rgmii-bus-level3";
        gmac1m0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m0-rgmii-clk-level2";
        tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func";
        mxc6655xa_irq_gpio = "/pinctrl/mxc6655xa/mxc6655xa_irq_gpio";
        touch_gpio = "/pinctrl/touch/touch-gpio";
        wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h";
        vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en";
        vcc5v0_otg_en = "/pinctrl/usb/vcc5v0-otg-en";
        uart8_gpios = "/pinctrl/wireless-bluetooth/uart8-gpios";
        uart1_gpios = "/pinctrl/wireless-bluetooth/uart1-gpios";
        hp_det = "/pinctrl/headphone/hp-det";
        lcd0_rst_gpio = "/pinctrl/lcd0/lcd-rst-gpio";
        lcd1_rst_gpio = "/pinctrl/lcd1/lcd1-rst-gpio";
        wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq";
        dis_ctl = "/pinctrl/fddis_ctr/dis-ctl";
        adc_keys = "/adc-keys";
        audiopwmout_diff = "/audiopwmout-diff";
        master = "/audiopwmout-diff/simple-audio-card,codec";
        backlight = "/backlight";
        backlight1 = "/backlight1";
        dc_12v = "/dc-12v";
        hdmi_sound = "/hdmi-sound";
        pdmics = "/dummy-codec";
        pdm_mic_array = "/pdm-mic-array";
        rk809_sound = "/rk809-sound";
        spdif_out = "/spdif-out";
        vad_sound = "/vad-sound";
        vcc3v3_sys = "/vcc3v3-sys";
        vcc5v0_sys = "/vcc5v0-sys";
        vcc5v0_host = "/vcc5v0-host-regulator";
        vcc5v0_otg = "/vcc5v0-otg-regulator";
        vcc3v3_lcd0_n = "/vcc3v3-lcd0-n";
        vcc3v3_lcd1_n = "/vcc3v3-lcd1-n";
        sdio_pwrseq = "/sdio-pwrseq";
        wireless_wlan = "/wireless-wlan";
        wireless_bluetooth = "/wireless-bluetooth";
        rk_headset = "/rk-headset";
        vcc3v3_vga = "/vcc3v3-vga";
        vcc_camera = "/vcc-camera-regulator";
        chosen = "/chosen";
        debug = "/debug@fd904000";
        cspmu = "/cspmu@fd90c000";
    };
};

 

Edited by hotnikq
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Hqnicolas

Hqnicolas

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Posted
Quote

pmuio1-supply = <&vcc3v3_pmu>; not asked
pmuio2-supply = <&vcc_3v3>;
vccio1-supply = <&vccio_acodec>; 3,3
vccio2-supply = <&vcc_1v8>; not asked
vccio3-supply = <&vccio_sd>; 3,3
vccio4-supply = <&vcca1v8_pmu>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc1v8_dvp>;
vccio7-supply = <&vcc_3v3>;

 
When Compile VCCio

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Hqnicolas

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to compile Armbian build 4,19 M2 Station image.
change files to corresponding DTS file 


BOARD_TYPE_1.dts

Quote

/dts-v1/;
// magic:        0xd00dfeed
// totalsize:        0x1eb87 (125831)
// off_dt_struct:    0x38
// off_dt_strings:    0x1bc6c
// off_mem_rsvmap:    0x28
// version:        17
// last_comp_version:    16
// boot_cpuid_phys:    0x0
// size_dt_strings:    0x2f1b
// size_dt_struct:    0x1bc34

/ {
    compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566";
    interrupt-parent = <0x00000001>;
    #address-cells = <0x00000002>;
    #size-cells = <0x00000002>;
    model = "Rockchip RK3566 EVB3 DDR3 V10 Board";
    ddr_timing {
        compatible = "rockchip,ddr-timing";
        ddr2_speed_bin = <0x00000000>;
        ddr3_speed_bin = <0x00000015>;
        ddr4_speed_bin = <0x0000000c>;
        pd_idle = <0x0000000d>;
        sr_idle = <0x0000005d>;
        sr_mc_gate_idle = <0x00000000>;
        srpd_lite_idle = <0x00000000>;
        standby_idle = <0x00000000>;
        auto_pd_dis_freq = <0x0000042a>;
        auto_sr_dis_freq = <0x00000320>;
        ddr2_dll_dis_freq = <0x0000012c>;
        ddr3_dll_dis_freq = <0x0000012c>;
        ddr4_dll_dis_freq = <0x00000271>;
        phy_dll_dis_freq = <0x00000190>;
        ddr2_odt_dis_freq = <0x00000064>;
        phy_ddr2_odt_dis_freq = <0x00000064>;
        ddr2_drv = <0x00000002>;
        ddr2_odt = <0x00000040>;
        phy_ddr2_ca_drv = <0x00000000>;
        phy_ddr2_ck_drv = <0x00000000>;
        phy_ddr2_dq_drv = <0x00000000>;
        phy_ddr2_odt = <0x00000000>;
        ddr3_odt_dis_freq = <0x0000014d>;
        phy_ddr3_odt_dis_freq = <0x0000014d>;
        ddr3_drv = <0x00000002>;
        ddr3_odt = <0x00000040>;
        phy_ddr3_ca_drv = <0x00000000>;
        phy_ddr3_ck_drv = <0x00000000>;
        phy_ddr3_dq_drv = <0x00000000>;
        phy_ddr3_odt = <0x00000000>;
        phy_lpddr2_odt_dis_freq = <0x0000014d>;
        lpddr2_drv = <0x00000002>;
        phy_lpddr2_ca_drv = <0x00000000>;
        phy_lpddr2_ck_drv = <0x00000000>;
        phy_lpddr2_dq_drv = <0x00000000>;
        phy_lpddr2_odt = <0x00000000>;
        lpddr3_odt_dis_freq = <0x0000014d>;
        phy_lpddr3_odt_dis_freq = <0x0000014d>;
        lpddr3_drv = <0x00000001>;
        lpddr3_odt = <0x00000002>;
        phy_lpddr3_ca_drv = <0x00000000>;
        phy_lpddr3_ck_drv = <0x00000000>;
        phy_lpddr3_dq_drv = <0x00000000>;
        phy_lpddr3_odt = <0x00000000>;
        lpddr4_odt_dis_freq = <0x0000014d>;
        phy_lpddr4_odt_dis_freq = <0x0000014d>;
        lpddr4_drv = <0x00000030>;
        lpddr4_dq_odt = <0x00000001>;
        lpddr4_ca_odt = <0x00000000>;
        phy_lpddr4_ca_drv = <0x00000000>;
        phy_lpddr4_ck_cs_drv = <0x00000000>;
        phy_lpddr4_dq_drv = <0x00000000>;
        phy_lpddr4_odt = <0x00000000>;
        ddr4_odt_dis_freq = <0x00000271>;
        phy_ddr4_odt_dis_freq = <0x00000271>;
        ddr4_drv = <0x00000000>;
        ddr4_odt = <0x00000200>;
        phy_ddr4_ca_drv = <0x00000000>;
        phy_ddr4_ck_drv = <0x00000000>;
        phy_ddr4_dq_drv = <0x00000000>;
        phy_ddr4_odt = <0x00000000>;
        phandle = <0x000000a8>;
    };
    aliases {
        csi2dphy0 = "/csi2-dphy0";
        csi2dphy1 = "/csi2-dphy1";
        csi2dphy2 = "/csi2-dphy2";
        dsi0 = "/dsi@fe060000";
        dsi1 = "/dsi@fe070000";
        ethernet1 = "/ethernet@fe010000";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        i2c0 = "/i2c@fdd40000";
        i2c1 = "/i2c@fe5a0000";
        i2c2 = "/i2c@fe5b0000";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mmc0 = "/dwmmc@fe2b0000";
        mmc1 = "/dwmmc@fe2c0000";
        mmc2 = "/sdhci@fe310000";
        mmc3 = "/dwmmc@fe000000";
        serial0 = "/serial@fdd50000";
        serial1 = "/serial@fe650000";
        serial2 = "/serial@fe660000";
        serial3 = "/serial@fe670000";
        serial4 = "/serial@fe680000";
        serial5 = "/serial@fe690000";
        serial6 = "/serial@fe6a0000";
        serial7 = "/serial@fe6b0000";
        serial8 = "/serial@fe6c0000";
        serial9 = "/serial@fe6d0000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
    };
    cpus {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000000>;
        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000000>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            #cooling-cells = <0x00000002>;
            dynamic-power-coefficient = <0x000000bb>;
            cpu-supply = <0x00000005>;
            phandle = <0x00000009>;
            power-model {
                compatible = "simple-power-model";
                leakage-range = <0x0000000a 0x00000028>;
                ls = <0xffffdc14 0x000018d8 0x00000000>;
                static-coefficient = <0x000186a0>;
                ts = <0x0001476e 0x0003263d 0xffffef34 0x00000047>;
                thermal-zone = "soc-thermal";
            };
        };
        cpu@100 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000100>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000a>;
        };
        cpu@200 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000200>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000b>;
        };
        cpu@300 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000300>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000c>;
        };
        idle-states {
            entry-method = "psci";
            cpu-sleep {
                compatible = "arm,idle-state";
                local-timer-stop;
                arm,psci-suspend-param = <0x00010000>;
                entry-latency-us = <0x00000064>;
                exit-latency-us = <0x00000078>;
                min-residency-us = <0x000003e8>;
                phandle = <0x00000004>;
            };
        };
    };
    cpu0-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000006 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-freq = <0x000639c0>;
        rockchip,pvtm-volt = <0x000dbba0>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        rockchip,pvtm-sample-time = <0x000003e8>;
        rockchip,pvtm-number = <0x0000000a>;
        rockchip,pvtm-error = <0x000003e8>;
        rockchip,pvtm-ref-temp = <0x00000028>;
        rockchip,pvtm-temp-prop = <0x0000001a 0x0000001a>;
        rockchip,thermal-zone = "soc-thermal";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000648 0x000124f8>;
        phandle = <0x00000003>;
        opp-408000000 {
            opp-hz = <0x00000000 0x18519600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-816000000 {
            opp-hz = <0x00000000 0x30a32c00>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            opp-suspend;
            status = "disabled";
        };
        opp-1104000000 {
            opp-hz = <0x00000000 0x41cdb400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-1416000000 {
            opp-hz = <0x00000000 0x54667200>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1608000000 {
            opp-hz = <0x00000000 0x5fd82200>;
            opp-microvolt = <0x000f4240 0x000f4240 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1800000000 {
            opp-hz = <0x00000000 0x6b49d200>;
            opp-microvolt = <0x00100590 0x00100590 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
    };
    arm-pmu {
        compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
        interrupts = <0x00000000 0x000000e4 0x00000004 0x00000000 0x000000e5 0x00000004 0x00000000 0x000000e6 0x00000004 0x00000000 0x000000e7 0x00000004>;
        interrupt-affinity = <0x00000009 0x0000000a 0x0000000b 0x0000000c>;
    };
    cpuinfo {
        compatible = "rockchip,cpuinfo";
        nvmem-cells = <0x0000000d 0x0000000e 0x0000000f>;
        nvmem-cell-names = "id", "cpu-version", "cpu-code";
    };
    display-subsystem {
        compatible = "rockchip,display-subsystem";
        memory-region = <0x00000010 0x00000011>;
        memory-region-names = "drm-logo", "drm-cubic-lut";
        ports = <0x00000012>;
        devfreq = <0x00000013>;
        phandle = <0x00000134>;
        route {
            route-dsi0 {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000014>;
                phandle = <0x00000135>;
            };
            route-dsi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000015>;
                phandle = <0x00000136>;
            };
            route-edp {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000016>;
                phandle = <0x00000137>;
            };
            route-hdmi {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000017>;
                phandle = <0x00000138>;
            };
            route-lvds {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000018>;
                phandle = <0x00000139>;
            };
            route-rgb {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000019>;
                phandle = <0x0000013a>;
            };
        };
    };
    firmware {
        optee {
            compatible = "linaro,optee-tz";
            method = "smc";
            phandle = <0x0000013b>;
        };
        scmi {
            compatible = "arm,scmi-smc";
            shmem = <0x0000001a>;
            arm,smc-id = <0x82000010>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x0000013c>;
            protocol@14 {
                reg = <0x00000014>;
                #clock-cells = <0x00000001>;
                rockchip,clk-init = "Tfr";
                phandle = <0x00000002>;
            };
        };
        sdei {
            compatible = "arm,sdei-1.0";
            method = "smc";
            phandle = <0x0000013d>;
        };
    };
    mpp-srv {
        compatible = "rockchip,mpp-service";
        rockchip,taskqueue-count = <0x00000006>;
        rockchip,resetgroup-count = <0x00000006>;
        status = "okay";
        phandle = <0x00000067>;
    };
    psci {
        compatible = "arm,psci-1.0";
        method = "smc";
    };
    reserved-memory {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        phandle = <0x0000013e>;
        drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000010>;
        };
        drm-cubic-lut@00000000 {
            compatible = "rockchip,drm-cubic-lut";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000011>;
        };
        linux,cma {
            compatible = "shared-dma-pool";
            inactive;
            reusable;
            reg = <0x00000000 0x10000000 0x00000000 0x00800000>;
            linux,cma-default;
        };
        ramoops@110000 {
            compatible = "ramoops";
            reg = <0x00000000 0x00110000 0x00000000 0x000f0000>;
            record-size = <0x00020000>;
            console-size = <0x00080000>;
            ftrace-size = <0x00000000>;
            pmsg-size = <0x00050000>;
            phandle = <0x0000013f>;
        };
    };
    rockchip-suspend {
        compatible = "rockchip,pm-rk3568";
        status = "okay";
        rockchip,sleep-debug-en = <0x00000001>;
        rockchip,sleep-mode-config = <0x000004e4>;
        rockchip,wakeup-config = <0x00002001>;
        rockchip,virtual-poweroff = <0x00000001>;
        phandle = <0x00000140>;
    };
    rockchip-system-monitor {
        compatible = "rockchip,system-monitor";
        rockchip,thermal-zone = "soc-thermal";
        phandle = <0x00000141>;
    };
    thermal-zones {
        phandle = <0x00000142>;
        soc-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            sustainable-power = <0x000005c3>;
            thermal-sensors = <0x0000001b 0x00000000>;
            phandle = <0x00000143>;
            trips {
                trip-point-0 {
                    temperature = <0x00011170>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x00000144>;
                };
                trip-point-1 {
                    temperature = <0x00014c08>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x0000001c>;
                };
                soc-crit {
                    temperature = <0x0001c138>;
                    hysteresis = <0x000007d0>;
                    type = "critical";
                    phandle = <0x00000145>;
                };
            };
            cooling-maps {
                map0 {
                    trip = <0x0000001c>;
                    cooling-device = <0x00000009 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
                map1 {
                    trip = <0x0000001c>;
                    cooling-device = <0x0000001d 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
            };
        };
        gpu-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x0000001b 0x00000001>;
            phandle = <0x00000146>;
        };
    };
    timer {
        compatible = "arm,armv8-timer";
        interrupts = <0x00000001 0x0000000d 0x00000f04 0x00000001 0x0000000e 0x00000f04 0x00000001 0x0000000b 0x00000f04 0x00000001 0x0000000a 0x00000f04>;
        arm,no-tick-in-suspend;
    };
    external-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "gmac1_clkin";
        #clock-cells = <0x00000000>;
        phandle = <0x00000147>;
    };
    xpcs-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "clk_gmac1_xpcs_mii";
        #clock-cells = <0x00000000>;
        phandle = <0x00000148>;
    };
    i2s1-mclkin-rx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_rx";
        phandle = <0x00000149>;
    };
    i2s1-mclkin-tx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_tx";
        phandle = <0x0000014a>;
    };
    i2s2-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s2_mclkin";
        phandle = <0x0000014b>;
    };
    i2s3-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s3_mclkin";
        phandle = <0x0000014c>;
    };
    mpll {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x2faf0800>;
        clock-output-names = "mpll";
        phandle = <0x0000014d>;
    };
    xin24m {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x016e3600>;
        clock-output-names = "xin24m";
        phandle = <0x0000014e>;
    };
    xin32k {
        compatible = "fixed-clock";
        clock-frequency = <0x00008000>;
        clock-output-names = "xin32k";
        #clock-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000001e>;
        phandle = <0x0000014f>;
    };
    scmi-shmem@10f000 {
        compatible = "arm,scmi-shmem";
        reg = <0x00000000 0x0010f000 0x00000000 0x00000100>;
        phandle = <0x0000001a>;
    };
    sata@fc400000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc400000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000009b 0x0000001f 0x0000009c 0x0000001f 0x0000009d>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x0000005f 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000020 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000150>;
    };
    sata@fc800000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc800000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x000000a0 0x0000001f 0x000000a1 0x0000001f 0x000000a2>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x00000060 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000022 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000151>;
    };
    usbdrd {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a6 0x0000001f 0x000000a7 0x0000001f 0x000000a5 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000152>;
        dwc3@fcc00000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfcc00000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000a9 0x00000004>;
            dr_mode = "host";
            phys = <0x00000023>;
            phy-names = "usb2-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000094>;
            reset-names = "usb3-otg";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            extcon = <0x00000024>;
            maximum-speed = "high-speed";
            snps,dis_u2_susphy_quirk;
            phandle = <0x00000153>;
        };
    };
    usbhost {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a9 0x0000001f 0x000000aa 0x0000001f 0x000000a8 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000154>;
        dwc3@fd000000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfd000000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000aa 0x00000004>;
            dr_mode = "host";
            phys = <0x00000025 0x00000020 0x00000004>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000095>;
            reset-names = "usb3-host";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            phandle = <0x00000155>;
        };
    };
    interrupt-controller@fd400000 {
        compatible = "arm,gic-v3";
        #interrupt-cells = <0x00000003>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        interrupt-controller;
        reg = <0x00000000 0xfd400000 0x00000000 0x00010000 0x00000000 0xfd460000 0x00000000 0x000c0000>;
        interrupts = <0x00000001 0x00000009 0x00000004>;
        phandle = <0x00000001>;
        interrupt-controller@fd440000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x00000001>;
            reg = <0x00000000 0xfd440000 0x00000000 0x00020000>;
            phandle = <0x000000ab>;
        };
    };
    usb@fd800000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd800000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000082 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000156>;
    };
    usb@fd840000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd840000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000083 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000157>;
    };
    usb@fd880000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd880000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000085 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000158>;
    };
    usb@fd8c0000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd8c0000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000086 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000159>;
    };
    syscon@fda00000 {
        compatible = "rockchip,rk3568-xpcs", "syscon";
        reg = <0x00000000 0xfda00000 0x00000000 0x00200000>;
        status = "disabled";
        phandle = <0x0000015a>;
    };
    syscon@fdc20000 {
        compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc20000 0x00000000 0x00010000>;
        phandle = <0x00000033>;
        io-domains {
            compatible = "rockchip,rk3568-pmu-io-voltage-domain";
            status = "okay";
            pmuio1-supply = <0x00000029>;
            pmuio2-supply = <0x00000029>;
            vccio1-supply = <0x0000002a>;
            vccio3-supply = <0x0000002b>;
            vccio4-supply = <0x0000002c>;
            vccio5-supply = <0x0000002d>;
            vccio6-supply = <0x0000002c>;
            vccio7-supply = <0x0000002d>;
            phandle = <0x0000015b>;
        };
        reboot-mode {
            compatible = "syscon-reboot-mode";
            offset = <0x00000200>;
            mode-bootloader = <0x5242c301>;
            mode-charge = <0x5242c30b>;
            mode-fastboot = <0x5242c309>;
            mode-loader = <0x5242c301>;
            mode-normal = <0x5242c300>;
            mode-recovery = <0x5242c303>;
            mode-ums = <0x5242c30c>;
            mode-panic = <0x5242c307>;
            mode-watchdog = <0x5242c308>;
            phandle = <0x0000015c>;
        };
    };
    syscon@fdc50000 {
        compatible = "rockchip,rk3568-pipegrf", "syscon";
        reg = <0x00000000 0xfdc50000 0x00000000 0x00001000>;
        phandle = <0x00000104>;
    };
    syscon@fdc60000 {
        compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc60000 0x00000000 0x00010000>;
        phandle = <0x00000032>;
        io-domains {
            compatible = "rockchip,rk3568-io-voltage-domain";
            status = "disabled";
            phandle = <0x0000015d>;
        };
        lvds {
            compatible = "rockchip,rk3568-lvds";
            phys = <0x0000002e>;
            phy-names = "phy";
            status = "disabled";
            phandle = <0x0000015e>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@1 {
                        reg = <0x00000001>;
                        remote-endpoint = <0x00000018>;
                        status = "disabled";
                        phandle = <0x0000008b>;
                    };
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x0000002f>;
                        status = "disabled";
                        phandle = <0x0000008c>;
                    };
                };
            };
        };
        rgb {
            compatible = "rockchip,rk3568-rgb";
            pinctrl-names = "default";
            pinctrl-0 = <0x00000030>;
            status = "disabled";
            phandle = <0x0000015f>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x00000019>;
                        status = "disabled";
                        phandle = <0x0000008d>;
                    };
                };
            };
        };
    };
    syscon@fdc70000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc70000 0x00000000 0x00001000>;
        phandle = <0x00000160>;
    };
    syscon@fdc80000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc80000 0x00000000 0x00001000>;
        phandle = <0x00000105>;
    };
    syscon@fdc90000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc90000 0x00000000 0x00001000>;
        phandle = <0x00000106>;
    };
    syscon@fdca0000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca0000 0x00000000 0x00008000>;
        phandle = <0x0000010b>;
    };
    syscon@fdca8000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca8000 0x00000000 0x00008000>;
        phandle = <0x0000010e>;
    };
    edp-phy@fdcb0000 {
        compatible = "rockchip,rk3568-edp-phy";
        reg = <0x00000000 0xfdcb0000 0x00000000 0x00008000>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x00000192>;
        clock-names = "refclk", "pclk";
        resets = <0x0000001f 0x000001d6>;
        reset-names = "apb";
        #phy-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000000a4>;
    };
    sram@fdcc0000 {
        compatible = "mmio-sram";
        reg = <0x00000000 0xfdcc0000 0x00000000 0x0000b000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges = <0x00000000 0x00000000 0xfdcc0000 0x0000b000>;
        phandle = <0x00000161>;
        rkvdec-sram@0 {
            reg = <0x00000000 0x0000b000>;
            phandle = <0x0000006f>;
        };
    };
    clock-controller@fdd00000 {
        compatible = "rockchip,rk3568-pmucru";
        reg = <0x00000000 0xfdd00000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        rockchip,pmugrf = <0x00000033>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000032>;
        assigned-clock-parents = <0x00000031 0x00000005>;
        phandle = <0x00000031>;
    };
    clock-controller@fdd20000 {
        compatible = "rockchip,rk3568-cru";
        reg = <0x00000000 0xfdd20000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000005 0x0000001f 0x00000106 0x0000001f 0x0000010b 0x00000031 0x00000001 0x00000031 0x0000002b 0x0000001f 0x00000003 0x0000001f 0x0000019b 0x0000001f 0x00000009 0x0000001f 0x0000019c 0x0000001f 0x0000019d 0x0000001f 0x000001a1 0x0000001f 0x0000019e 0x0000001f 0x0000019f 0x0000001f 0x000001a0 0x0000001f 0x00000004 0x0000001f 0x0000010d 0x0000001f 0x0000010e 0x0000001f 0x00000173 0x0000001f 0x00000174 0x0000001f 0x00000175 0x0000001f 0x00000176 0x0000001f 0x000000c9 0x0000001f 0x000000ca 0x0000001f 0x00000006 0x0000001f 0x0000007e 0x0000001f 0x0000007f 0x0000001f 0x0000003d 0x0000001f 0x00000041 0x0000001f 0x00000045 0x0000001f 0x00000049 0x0000001f 0x0000004d 0x0000001f 0x0000004d 0x0000001f 0x00000055 0x0000001f 0x00000051 0x0000001f 0x0000005d 0x0000001f 0x000000dd>;
        assigned-clock-rates = <0x00008000 0x11e1a300 0x11e1a300 0x0bebc200 0x05f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0x0ee6b280 0x07735940 0x05f5e100 0x03b9aca0 0x02faf080 0x017d7840 0x46cf7100 0x08f0d180 0x05f5e100 0x1dcd6500 0x17d78400 0x08f0d180 0x05f5e100 0x11e1a300 0x08f0d180 0x47868c00 0x17d78400 0x05f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
        assigned-clock-parents = <0x00000031 0x00000008 0x0000001f 0x00000004 0x0000001f 0x00000004>;
        phandle = <0x0000001f>;
    };
    i2c@fdd40000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfdd40000 0x00000000 0x00001000>;
        clocks = <0x00000031 0x00000007 0x00000031 0x0000002d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002e 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000034>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000162>;
        pmic@20 {
            compatible = "rockchip,rk809";
            reg = <0x00000020>;
            interrupt-parent = <0x00000035>;
            interrupts = <0x00000003 0x00000008>;
            pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
            pinctrl-0 = <0x00000036>;
            pinctrl-1 = <0x00000037 0x00000038>;
            pinctrl-2 = <0x00000039 0x0000003a>;
            pinctrl-3 = <0x00000039 0x0000003b>;
            rockchip,system-power-controller;
            wakeup-source;
            #clock-cells = <0x00000001>;
            clock-output-names = "rk808-clkout1", "rk808-clkout2";
            pmic-reset-func = <0x00000000>;
            not-save-power-en = <0x00000001>;
            vcc1-supply = <0x0000003c>;
            vcc2-supply = <0x0000003c>;
            vcc3-supply = <0x0000003c>;
            vcc4-supply = <0x0000003c>;
            vcc5-supply = <0x0000003c>;
            vcc6-supply = <0x0000003c>;
            vcc7-supply = <0x0000003c>;
            vcc8-supply = <0x0000003c>;
            vcc9-supply = <0x0000003c>;
            phandle = <0x0000012c>;
            pwrkey {
                status = "okay";
            };
            pinctrl_rk8xx {
                gpio-controller;
                #gpio-cells = <0x00000002>;
                phandle = <0x00000163>;
                rk817_slppin_null {
                    pins = "gpio_slp";
                    function = "pin_fun0";
                    phandle = <0x00000164>;
                };
                rk817_slppin_slp {
                    pins = "gpio_slp";
                    function = "pin_fun1";
                    phandle = <0x00000038>;
                };
                rk817_slppin_pwrdn {
                    pins = "gpio_slp";
                    function = "pin_fun2";
                    phandle = <0x0000003a>;
                };
                rk817_slppin_rst {
                    pins = "gpio_slp";
                    function = "pin_fun3";
                    phandle = <0x0000003b>;
                };
            };
            regulators {
                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_logic";
                    phandle = <0x00000062>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_gpu";
                    phandle = <0x00000064>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vcc_ddr";
                    phandle = <0x00000165>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                    };
                };
                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_npu";
                    phandle = <0x0000005f>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG1 {
                    regulator-boot-on;
                    regulator-always-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_image";
                    phandle = <0x00000166>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda_0v9";
                    phandle = <0x00000167>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_pmu";
                    phandle = <0x00000168>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x000dbba0>;
                    };
                };
                LDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_acodec";
                    phandle = <0x0000002a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_sd";
                    phandle = <0x0000002b>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vcc3v3_pmu";
                    phandle = <0x00000029>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x00325aa0>;
                    };
                };
                LDO_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca_1v8";
                    phandle = <0x00000103>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_pmu";
                    phandle = <0x00000169>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001b7740>;
                    };
                };
                LDO_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_image";
                    phandle = <0x0000016a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcc_1v8";
                    phandle = <0x0000002c>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc_3v3";
                    phandle = <0x0000002d>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc3v3_sd";
                    phandle = <0x000000ac>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };
            codec {
                #sound-dai-cells = <0x00000000>;
                compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
                clocks = <0x0000001f 0x000001a4>;
                clock-names = "mclk";
                assigned-clocks = <0x0000001f 0x000001a4 0x0000001f 0x000001a8>;
                assigned-clock-rates = <0x00bb8000>;
                assigned-clock-parents = <0x0000001f 0x00000054 0x0000001f 0x000001a4>;
                pinctrl-names = "default";
                pinctrl-0 = <0x0000003d>;
                hp-volume = <0x00000014>;
                spk-volume = <0x00000003>;
                mic-in-differential;
                status = "okay";
                phandle = <0x00000125>;
            };
        };
        sti8070@40 {
            compatible = "silergy,syr827";
            reg = <0x00000040>;
            vin-supply = <0x0000003e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x00100590>;
            regulator-max-microvolt = <0x001535b0>;
            regulator-ramp-delay = <0x000008fc>;
            fcs,suspend-voltage-selector = <0x00000001>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x00000005>;
            regulator-state-mem {
                regulator-off-in-suspend;
            };
        };
    };
    serial@fdd50000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfdd50000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000074 0x00000004>;
        clocks = <0x00000031 0x0000000b 0x00000031 0x0000002c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000000 0x0000003f 0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000040>;
        status = "disabled";
        phandle = <0x0000016b>;
    };
    pwm@fdd70000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000041>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016c>;
    };
    pwm@fdd70010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000042>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016d>;
    };
    pwm@fdd70020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000043>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016e>;
    };
    pwm@fdd70030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfdd70030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000052 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000044>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "okay";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x0000016f>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000bd 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000e5 0x00000066 0x000000e7 0x00000073 0x000000e8 0x00000072 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x000000a4 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000a4 0x0000008d 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
        ir_key4 {
            rockchip,usercode = <0x0000fe01>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000e6 0x0000009e 0x000000e9 0x00000067 0x000000e5 0x0000006c 0x000000ae 0x00000069 0x000000af 0x0000006a 0x000000ee 0x00000066 0x000000e7 0x00000073 0x000000ef 0x00000072 0x000000bf 0x00000074 0x000000be 0x00000071 0x000000b3 0x0000008b 0x000000ff 0x00000184 0x000000b1 0x00000002 0x000000f2 0x00000003 0x000000f3 0x00000004 0x000000b5 0x00000005 0x000000f6 0x00000006 0x000000f7 0x00000007 0x000000b9 0x00000008 0x000000fa 0x00000009 0x000000fb 0x0000000a 0x000000fe 0x0000000b 0x000000bd 0x0000000e 0x000000bc 0x000000b7 0x000000f0 0x000000ba 0x000000b4 0x0000019c 0x000000b8 0x0000001e 0x000000b0 0x00000197>;
        };
        ir_key5 {
            rockchip,usercode = <0x00007f80>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000d8 0x0000009e 0x000000c7 0x00000067 0x000000bf 0x0000006c 0x000000c8 0x00000069 0x000000c6 0x0000006a 0x0000008c 0x00000066 0x00000078 0x00000073 0x00000076 0x00000072 0x0000007e 0x00000074 0x0000007c 0x0000008b 0x000000b7 0x00000184>;
        };
        ir_key6 {
            rockchip,usercode = <0x0000fd01>;
            rockchip,key_table = <0x00000031 0x000000e8 0x0000002f 0x0000009e 0x00000035 0x00000067 0x0000002d 0x0000006c 0x00000066 0x00000069 0x0000003e 0x0000006a 0x0000006a 0x00000066 0x0000005e 0x00000073 0x00000047 0x00000072 0x00000023 0x00000074 0x0000003a 0x00000184 0x0000000d 0x00000040>;
        };
    };
    power-management@fdd90000 {
        compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdd90000 0x00000000 0x00001000>;
        phandle = <0x00000170>;
        power-controller {
            compatible = "rockchip,rk3568-power-controller";
            #power-domain-cells = <0x00000001>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000021>;
            pd_npu@6 {
                reg = <0x00000006>;
                clocks = <0x0000001f 0x00000027 0x0000001f 0x00000025 0x0000001f 0x00000026>;
                pm_qos = <0x00000045>;
            };
            pd_gpu@7 {
                reg = <0x00000007>;
                clocks = <0x0000001f 0x00000019 0x0000001f 0x0000001a>;
                pm_qos = <0x00000046>;
            };
            pd_vi@8 {
                reg = <0x00000008>;
                clocks = <0x0000001f 0x000000cc 0x0000001f 0x000000cd>;
                pm_qos = <0x00000047 0x00000048 0x00000049>;
            };
            pd_vo@9 {
                reg = <0x00000009>;
                clocks = <0x0000001f 0x000000da 0x0000001f 0x000000db 0x0000001f 0x000000dc>;
                pm_qos = <0x0000004a 0x0000004b 0x0000004c>;
            };
            pd_rga@10 {
                reg = <0x0000000a>;
                clocks = <0x0000001f 0x000000f1 0x0000001f 0x000000f2>;
                pm_qos = <0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052>;
            };
            pd_vpu@11 {
                reg = <0x0000000b>;
                clocks = <0x0000001f 0x000000ed>;
                pm_qos = <0x00000053>;
            };
            pd_rkvdec@13 {
                clocks = <0x0000001f 0x00000107>;
                reg = <0x0000000d>;
                pm_qos = <0x00000054>;
            };
            pd_rkvenc@14 {
                reg = <0x0000000e>;
                clocks = <0x0000001f 0x00000102>;
                pm_qos = <0x00000055 0x00000056 0x00000057>;
            };
            pd_pipe@15 {
                reg = <0x0000000f>;
                clocks = <0x0000001f 0x0000007f>;
                pm_qos = <0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c>;
            };
        };
    };
    pvtm@fde00000 {
        compatible = "rockchip,rk3568-core-pvtm";
        reg = <0x00000000 0xfde00000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@0 {
            reg = <0x00000000>;
            clocks = <0x0000001f 0x00000013 0x0000001f 0x000001c2>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x0000001a 0x0000001f 0x00000019>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    npu@fde40000 {
        compatible = "rockchip,rknpu";
        reg = <0x00000000 0xfde40000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        clocks = <0x00000002 0x00000002 0x0000001f 0x00000023 0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "scmi_clk", "clk", "aclk", "hclk";
        assigned-clocks = <0x0000001f 0x00000023>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x0000001f 0x0000002b 0x0000001f 0x0000002c>;
        reset-names = "srst_a", "srst_h";
        power-domains = <0x00000021 0x00000006>;
        operating-points-v2 = <0x0000005d>;
        iommus = <0x0000005e>;
        status = "okay";
        rknpu-supply = <0x0000005f>;
        phandle = <0x00000171>;
    };
    npu-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000060 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x000002bc 0x0000c350>;
        phandle = <0x0000005d>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000cf850 0x000cf850 0x000f4240>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000d59f8 0x000d59f8 0x000f4240>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x000f4240>;
        };
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000f4240 0x000f4240 0x000f4240>;
            status = "disabled";
        };
    };
    bus-npu {
        compatible = "rockchip,rk3568-bus";
        rockchip,busfreq-policy = "clkfreq";
        clocks = <0x00000002 0x00000002>;
        clock-names = "bus";
        operating-points-v2 = <0x00000061>;
        status = "okay";
        bus-supply = <0x00000062>;
        pvtm-supply = <0x00000005>;
        phandle = <0x00000172>;
    };
    bus-npu-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x00000061>;
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x00000000>;
        };
    };
    iommu@fde4b000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfde4b000 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        interrupt-names = "rknpu_mmu";
        clocks = <0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000006>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000005e>;
    };
    gpu@fde60000 {
        compatible = "arm,mali-bifrost";
        reg = <0x00000000 0xfde60000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000027 0x00000004 0x00000000 0x00000029 0x00000004 0x00000000 0x00000028 0x00000004>;
        interrupt-names = "GPU", "MMU", "JOB";
        upthreshold = <0x00000028>;
        downdifferential = <0x0000000a>;
        clocks = <0x00000002 0x00000001 0x0000001f 0x0000001b>;
        clock-names = "clk_mali", "clk_gpu";
        power-domains = <0x00000021 0x00000007>;
        #cooling-cells = <0x00000002>;
        operating-points-v2 = <0x00000063>;
        status = "okay";
        mali-supply = <0x00000064>;
        phandle = <0x0000001d>;
        power-model {
            compatible = "simple-power-model";
            leakage-range = <0x00000005 0x0000000f>;
            ls = <0xffffa23e 0x00005927 0x00000000>;
            static-coefficient = <0x000186a0>;
            dynamic-coefficient = <0x000003b9>;
            ts = <0xfffe56a6 0x0000f87a 0xfffffab5 0x00000014>;
            thermal-zone = "gpu-thermal";
            phandle = <0x00000173>;
        };
    };
    opp-table2 {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000065 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        phandle = <0x00000063>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11e1a300>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000dbba0>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000e7ef0>;
        };
    };
    pvtm@fde80000 {
        compatible = "rockchip,rk3568-gpu-pvtm";
        reg = <0x00000000 0xfde80000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@1 {
            reg = <0x00000001>;
            clocks = <0x0000001f 0x0000001e 0x0000001f 0x0000001d>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x00000024 0x0000001f 0x00000023>;
            reset-names = "rts", "rst-p";
            thermal-zone = "gpu-thermal";
        };
    };
    pvtm@fde90000 {
        compatible = "rockchip,rk3568-npu-pvtm";
        reg = <0x00000000 0xfde90000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@2 {
            reg = <0x00000002>;
            clocks = <0x0000001f 0x0000002b 0x0000001f 0x0000002a 0x0000001f 0x00000025>;
            clock-names = "clk", "pclk", "hclk";
            resets = <0x0000001f 0x0000002e 0x0000001f 0x0000002d>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    vdpu@fdea0400 {
        compatible = "rockchip,vpu-decoder-v2";
        reg = <0x00000000 0xfdea0400 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        resets = <0x0000001f 0x0000011a 0x0000001f 0x0000011b>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000066>;
        power-domains = <0x00000021 0x0000000b>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000000>;
        rockchip,resetgroup-node = <0x00000000>;
        status = "okay";
        phandle = <0x00000174>;
    };
    iommu@fdea0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdea0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008a 0x00000004>;
        interrupt-names = "vdpu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        power-domains = <0x00000021 0x0000000b>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000066>;
    };
    rk_rga@fdeb0000 {
        compatible = "rockchip,rga2";
        reg = <0x00000000 0xfdeb0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000005a 0x00000004>;
        clocks = <0x0000001f 0x000000f3 0x0000001f 0x000000f4 0x0000001f 0x000000f5>;
        clock-names = "aclk_rga", "hclk_rga", "clk_rga";
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000175>;
    };
    ebc@fdec0000 {
        compatible = "rockchip,rk3568-ebc-tcon";
        reg = <0x00000000 0xfdec0000 0x00000000 0x00005000>;
        interrupts = <0x00000000 0x00000011 0x00000004>;
        clocks = <0x0000001f 0x000000f9 0x0000001f 0x000000fa>;
        clock-names = "hclk", "dclk";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,grf = <0x00000032>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000068>;
        status = "disabled";
        phandle = <0x00000176>;
    };
    jpegd@fded0000 {
        compatible = "rockchip,rkv-jpeg-decoder-v1";
        reg = <0x00000000 0xfded0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000003e 0x00000004>;
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012c 0x0000001f 0x0000012d>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000069>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000001>;
        rockchip,resetgroup-node = <0x00000001>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000177>;
    };
    iommu@fded0480 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfded0480 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003d 0x00000004>;
        interrupt-names = "jpegd_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000069>;
    };
    vepu@fdee0000 {
        compatible = "rockchip,vpu-encoder-v2";
        reg = <0x00000000 0xfdee0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x00000040 0x00000004>;
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012e 0x0000001f 0x0000012f>;
        reset-names = "video_a", "video_h";
        iommus = <0x0000006a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000002>;
        rockchip,resetgroup-node = <0x00000002>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000178>;
    };
    iommu@fdee0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdee0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003f 0x00000004>;
        interrupt-names = "vepu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006a>;
    };
    iep@fdef0000 {
        compatible = "rockchip,iep-v2";
        reg = <0x00000000 0xfdef0000 0x00000000 0x00000500>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7 0x0000001f 0x000000f8>;
        clock-names = "aclk", "hclk", "sclk";
        resets = <0x0000001f 0x00000127 0x0000001f 0x00000128 0x0000001f 0x00000129>;
        reset-names = "rst_a", "rst_h", "rst_s";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000005>;
        rockchip,resetgroup-node = <0x00000005>;
        iommus = <0x0000006b>;
        status = "okay";
        phandle = <0x00000179>;
    };
    iommu@fdef0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdef0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        interrupt-names = "iep_mmu";
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x0000006b>;
    };
    eink@fdf00000 {
        compatible = "rockchip,rk3568-eink-tcon";
        reg = <0x00000000 0xfdf00000 0x00000000 0x00000074>;
        interrupts = <0x00000000 0x000000b2 0x00000004>;
        clocks = <0x0000001f 0x000000ff 0x0000001f 0x00000100>;
        clock-names = "pclk", "hclk";
        status = "disabled";
        phandle = <0x0000017a>;
    };
    rkvenc@fdf40000 {
        compatible = "rockchip,rkv-encoder-v1";
        reg = <0x00000000 0xfdf40000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008c 0x00000004>;
        interrupt-names = "irq_enc";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104 0x0000001f 0x00000105>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40>;
        resets = <0x0000001f 0x00000133 0x0000001f 0x00000134 0x0000001f 0x00000135>;
        reset-names = "video_a", "video_h", "video_core";
        assigned-clocks = <0x0000001f 0x00000103 0x0000001f 0x00000105>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40>;
        iommus = <0x0000006c>;
        node-name = "rkvenc";
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000003>;
        rockchip,resetgroup-node = <0x00000003>;
        power-domains = <0x00000021 0x0000000e>;
        operating-points-v2 = <0x0000006d>;
        status = "okay";
        venc-supply = <0x00000062>;
        phandle = <0x0000017b>;
    };
    rkvenc-opp-table {
        compatible = "operating-points-v2";
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x0000006d>;
        opp-297000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x00000000>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
    };
    iommu@fdf40f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf40f00 0x00000000 0x00000040 0x00000000 0xfdf40f40 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008d 0x00000004 0x00000000 0x0000008e 0x00000004>;
        interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000e>;
        status = "okay";
        phandle = <0x0000006c>;
    };
    rkvdec@fdf80200 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x00000000 0xfdf80200 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000005b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core", "clk_hevc_cabac";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40 0x11b3dc40 0x23c34600>;
        rockchip,advanced-rates = <0x179a7b00 0x00000000 0x179a7b00 0x179a7b00 0x23c34600>;
        rockchip,default-max-load = <0x001fe000>;
        resets = <0x0000001f 0x00000142 0x0000001f 0x00000143 0x0000001f 0x00000144 0x0000001f 0x00000145 0x0000001f 0x00000146>;
        assigned-clocks = <0x0000001f 0x00000108 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>;
        reset-names = "video_a", "video_h", "video_cabac", "video_core", "video_hevc_cabac";
        power-domains = <0x00000021 0x0000000d>;
        iommus = <0x0000006e>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000004>;
        rockchip,resetgroup-node = <0x00000004>;
        rockchip,sram = <0x0000006f>;
        rockchip,rcb-iova = <0x10000000 0x00010000>;
        rockchip,rcb-min-width = <0x00000200>;
        status = "okay";
        phandle = <0x0000017c>;
    };
    iommu@fdf80800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf80800 0x00000000 0x00000040 0x00000000 0xfdf80840 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000005c 0x00000004>;
        interrupt-names = "rkvdec_mmu";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x0000000d>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006e>;
    };
    mipi-csi2@fdfb0000 {
        compatible = "rockchip,rk3568-mipi-csi2";
        reg = <0x00000000 0xfdfb0000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000008 0x00000004 0x00000000 0x00000009 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x0000001f 0x000000d5>;
        clock-names = "pclk_csi2host";
        resets = <0x0000001f 0x000000ff>;
        reset-names = "srst_csihost_p";
        status = "disabled";
        phandle = <0x0000017d>;
    };
    rkcif@fdfe0000 {
        compatible = "rockchip,rk3568-cif";
        reg = <0x00000000 0xfdfe0000 0x00000000 0x00008000>;
        reg-names = "cif_regs";
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif-intr";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf 0x0000001f 0x000000d0 0x0000001f 0x000000d1>;
        clock-names = "aclk_cif", "hclk_cif", "dclk_cif", "iclk_cif_g";
        resets = <0x0000001f 0x000000f7 0x0000001f 0x000000f8 0x0000001f 0x000000f9 0x0000001f 0x000000fb 0x0000001f 0x000000fa>;
        reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_p", "rst_cif_i";
        assigned-clocks = <0x0000001f 0x000000d0>;
        assigned-clock-rates = <0x11e1a300>;
        power-domains = <0x00000021 0x00000008>;
        rockchip,grf = <0x00000032>;
        iommus = <0x00000070>;
        status = "okay";
        phandle = <0x00000071>;
    };
    iommu@fdfe0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdfe0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif_mmu";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        rockchip,disable-mmu-reset;
        #iommu-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000070>;
    };
    rkcif_dvp {
        compatible = "rockchip,rkcif-dvp";
        rockchip,hw = <0x00000071>;
        status = "okay";
        phandle = <0x00000073>;
        port {
            endpoint {
                remote-endpoint = <0x00000072>;
                bus-width = <0x00000008>;
                vsync-active = <0x00000000>;
                hsync-active = <0x00000001>;
                phandle = <0x000000d3>;
            };
        };
    };
    rkcif_dvp_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000073>;
        status = "disabled";
        phandle = <0x0000017e>;
    };
    rkcif_mipi_lvds {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000071>;
        status = "disabled";
        phandle = <0x00000074>;
    };
    rkcif_mipi_lvds_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000074>;
        status = "disabled";
        phandle = <0x0000017f>;
    };
    rkisp@fdff0000 {
        compatible = "rockchip,rk3568-rkisp";
        reg = <0x00000000 0xfdff0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000039 0x00000004 0x00000000 0x0000003a 0x00000004 0x00000000 0x0000003c 0x00000004>;
        interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3 0x0000001f 0x000000d4>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp";
        resets = <0x0000001f 0x000000fd 0x0000001f 0x000000fc>;
        reset-names = "isp", "isp-h";
        rockchip,grf = <0x00000032>;
        power-domains = <0x00000021 0x00000008>;
        iommus = <0x00000075>;
        rockchip,iq-feature = <0x000003fb 0xf7fe67ff>;
        status = "okay";
        phandle = <0x00000076>;
    };
    iommu@fdff1a00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdff1a00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000003b 0x00000004>;
        interrupt-names = "isp_mmu";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "okay";
        phandle = <0x00000075>;
    };
    rkisp-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "okay";
        phandle = <0x00000180>;
        port {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            endpoint@0 {
                reg = <0x00000000>;
                remote-endpoint = <0x00000077>;
                phandle = <0x0000010a>;
            };
        };
    };
    rkisp-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "disabled";
        phandle = <0x00000181>;
    };
    ethernet@fe010000 {
        compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
        reg = <0x00000000 0xfe010000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000020 0x00000004 0x00000000 0x0000001d 0x00000004>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000186 0x0000001f 0x00000189 0x0000001f 0x00000189 0x0000001f 0x000000c7 0x0000001f 0x000000c3 0x0000001f 0x000000c4 0x0000001f 0x00000189 0x0000001f 0x000000c8 0x0000001f 0x000000ac>;
        clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref", "pclk_xpcs";
        resets = <0x0000001f 0x000000ec>;
        reset-names = "stmmaceth";
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x00000078>;
        snps,mtl-rx-config = <0x00000079>;
        snps,mtl-tx-config = <0x0000007a>;
        status = "okay";
        phy-mode = "rgmii";
        clock_in_out = "output";
        snps,reset-gpio = <0x0000007b 0x00000001 0x00000001>;
        snps,reset-active-low;
        snps,reset-delays-us = <0x00000000 0x00004e20 0x000186a0>;
        assigned-clocks = <0x0000001f 0x00000189 0x0000001f 0x00000186>;
        assigned-clock-parents = <0x0000001f 0x00000187 0x0000001f 0x000000c5>;
        assigned-clock-rates = <0x00000000 0x07735940>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080>;
        tx_delay = <0x00000041>;
        rx_delay = <0x0000002e>;
        phy-handle = <0x00000081>;
        phandle = <0x00000182>;
        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000183>;
            phy@0 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <0x00000000>;
                phandle = <0x00000081>;
            };
        };
        stmmac-axi-config {
            snps,wr_osr_lmt = <0x00000004>;
            snps,rd_osr_lmt = <0x00000008>;
            snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>;
            phandle = <0x00000078>;
        };
        rx-queues-config {
            snps,rx-queues-to-use = <0x00000001>;
            phandle = <0x00000079>;
            queue0 {
            };
        };
        tx-queues-config {
            snps,tx-queues-to-use = <0x00000001>;
            phandle = <0x0000007a>;
            queue0 {
            };
        };
    };
    vop@fe040000 {
        compatible = "rockchip,rk3568-vop";
        reg = <0x00000000 0xfe040000 0x00000000 0x00003000 0x00000000 0xfe044000 0x00000000 0x00001000>;
        reg-names = "regs", "gamma_lut";
        rockchip,grf = <0x00000032>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de 0x0000001f 0x000000df 0x0000001f 0x000000e0 0x0000001f 0x000000e1>;
        clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
        iommus = <0x00000082>;
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        assigned-clocks = <0x0000001f 0x000000df 0x0000001f 0x000000e0>;
        assigned-clock-parents = <0x00000031 0x00000002 0x0000001f 0x00000005>;
        support-multi-area;
        phandle = <0x00000184>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000012>;
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                phandle = <0x00000185>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000083>;
                    phandle = <0x0000008f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000084>;
                    phandle = <0x00000015>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000085>;
                    phandle = <0x00000016>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x00000086>;
                    phandle = <0x00000017>;
                };
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                phandle = <0x00000186>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000087>;
                    phandle = <0x00000014>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000088>;
                    phandle = <0x00000098>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000089>;
                    phandle = <0x000000a5>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x0000008a>;
                    phandle = <0x000000a3>;
                };
                endpoint@4 {
                    reg = <0x00000004>;
                    remote-endpoint = <0x0000008b>;
                    phandle = <0x00000018>;
                };
            };
            port@2 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000002>;
                phandle = <0x00000187>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008c>;
                    phandle = <0x0000002f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000008d>;
                    phandle = <0x00000019>;
                };
            };
        };
    };
    iommu@fe043e00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfe043e00 0x00000000 0x00000100 0x00000000 0xfe043f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        interrupt-names = "vop_mmu";
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000082>;
    };
    dsi@fe060000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe060000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000044 0x00000004>;
        clocks = <0x0000001f 0x000000e8 0x0000001f 0x000000da 0x0000008e>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000110>;
        reset-names = "apb";
        phys = <0x0000008e>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000188>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000189>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008f>;
                    status = "disabled";
                    phandle = <0x00000083>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000014>;
                    status = "okay";
                    phandle = <0x00000087>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000090>;
                    phandle = <0x00000096>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x00000091>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x00000092>;
            reset-gpios = <0x00000093 0x00000005 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x00000094>;
            phandle = <0x0000018a>;
            display-timings {
                native-mode = <0x00000095>;
                phandle = <0x0000018b>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x00000095>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x00000096>;
                        phandle = <0x00000090>;
                    };
                };
            };
        };
    };
    dsi@fe070000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe070000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000045 0x00000004>;
        clocks = <0x0000001f 0x000000e9 0x0000001f 0x000000da 0x00000097>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000111>;
        reset-names = "apb";
        phys = <0x00000097>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000018c>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x0000018d>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000015>;
                    status = "disabled";
                    phandle = <0x00000084>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000098>;
                    status = "disabled";
                    phandle = <0x00000088>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000099>;
                    phandle = <0x0000009f>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x0000009a>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x0000009b>;
            reset-gpios = <0x0000009c 0x00000016 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000009d>;
            phandle = <0x0000018e>;
            display-timings {
                native-mode = <0x0000009e>;
                phandle = <0x0000018f>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x0000009e>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x0000009f>;
                        phandle = <0x00000099>;
                    };
                };
            };
        };
    };
    hdmi@fe0a0000 {
        compatible = "rockchip,rk3568-dw-hdmi";
        reg = <0x00000000 0xfe0a0000 0x00000000 0x00020000>;
        interrupts = <0x00000000 0x0000002d 0x00000004>;
        clocks = <0x0000001f 0x000000e6 0x0000001f 0x000000e7 0x0000001f 0x00000193 0x00000031 0x00000002 0x0000001f 0x000000de>;
        clock-names = "iahb", "isfr", "cec", "ref", "hclk";
        power-domains = <0x00000021 0x00000009>;
        reg-io-width = <0x00000004>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000a0 0x000000a1 0x000000a2>;
        status = "okay";
        rockchip,phy-table = <0x058834d4 0x00008009 0x00000000 0x00000270 0x09d5b340 0x0000800b 0x00000000 0x0000026d 0x0b1069a8 0x0000800b 0x00000000 0x000001ed 0x11b3dc40 0x0000800b 0x00000000 0x000001ad 0x2367b880 0x00008029 0x00000000 0x00000088 0x00000000 0x00000000 0x00000000 0x00000000>;
        phandle = <0x00000122>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000190>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000017>;
                    status = "okay";
                    phandle = <0x00000086>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a3>;
                    status = "disabled";
                    phandle = <0x0000008a>;
                };
            };
        };
    };
    edp@fe0c0000 {
        compatible = "rockchip,rk3568-edp";
        reg = <0x00000000 0xfe0c0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000012 0x00000004>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x000000ea 0x0000001f 0x000000eb 0x0000001f 0x000000da>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        reset-names = "dp", "apb";
        phys = <0x000000a4>;
        phy-names = "dp";
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        hpd-gpios = <0x00000093 0x00000007 0x00000000>;
        phandle = <0x00000191>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000192>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000016>;
                    status = "okay";
                    phandle = <0x00000085>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a5>;
                    status = "disabled";
                    phandle = <0x00000089>;
                };
            };
        };
    };
    qos@fe128000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe128000 0x00000000 0x00000020>;
        phandle = <0x00000046>;
    };
    qos@fe138080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138080 0x00000000 0x00000020>;
        phandle = <0x00000055>;
    };
    qos@fe138100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138100 0x00000000 0x00000020>;
        phandle = <0x00000056>;
    };
    qos@fe138180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138180 0x00000000 0x00000020>;
        phandle = <0x00000057>;
    };
    qos@fe148000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148000 0x00000000 0x00000020>;
        phandle = <0x00000047>;
    };
    qos@fe148080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148080 0x00000000 0x00000020>;
        phandle = <0x00000048>;
    };
    qos@fe148100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148100 0x00000000 0x00000020>;
        phandle = <0x00000049>;
    };
    qos@fe150000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe150000 0x00000000 0x00000020>;
        phandle = <0x00000053>;
    };
    qos@fe158000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158000 0x00000000 0x00000020>;
        phandle = <0x0000004d>;
    };
    qos@fe158100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158100 0x00000000 0x00000020>;
        phandle = <0x0000004e>;
    };
    qos@fe158180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158180 0x00000000 0x00000020>;
        phandle = <0x0000004f>;
    };
    qos@fe158200 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158200 0x00000000 0x00000020>;
        phandle = <0x00000050>;
    };
    qos@fe158280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158280 0x00000000 0x00000020>;
        phandle = <0x00000051>;
    };
    qos@fe158300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158300 0x00000000 0x00000020>;
        phandle = <0x00000052>;
    };
    qos@fe180000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe180000 0x00000000 0x00000020>;
        phandle = <0x00000045>;
    };
    qos@fe190000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190000 0x00000000 0x00000020>;
        phandle = <0x00000058>;
    };
    qos@fe190280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190280 0x00000000 0x00000020>;
        phandle = <0x00000059>;
    };
    qos@fe190300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190300 0x00000000 0x00000020>;
        phandle = <0x0000005a>;
    };
    qos@fe190380 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190380 0x00000000 0x00000020>;
        phandle = <0x0000005b>;
    };
    qos@fe190400 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190400 0x00000000 0x00000020>;
        phandle = <0x0000005c>;
    };
    qos@fe198000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe198000 0x00000000 0x00000020>;
        phandle = <0x00000054>;
    };
    qos@fe1a8000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8000 0x00000000 0x00000020>;
        phandle = <0x0000004a>;
    };
    qos@fe1a8080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8080 0x00000000 0x00000020>;
        phandle = <0x0000004b>;
    };
    qos@fe1a8100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8100 0x00000000 0x00000020>;
        phandle = <0x0000004c>;
    };
    dwmmc@fe000000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe000000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000064 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000c1 0x0000001f 0x000000c2 0x0000001f 0x0000018e 0x0000001f 0x0000018f>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000eb>;
        reset-names = "reset";
        status = "disabled";
        phandle = <0x00000193>;
    };
    dfi@fe230000 {
        reg = <0x00000000 0xfe230000 0x00000000 0x00000400>;
        compatible = "rockchip,rk3568-dfi";
        rockchip,pmugrf = <0x00000033>;
        status = "disabled";
        phandle = <0x000000a6>;
    };
    dmc {
        compatible = "rockchip,rk3568-dmc";
        interrupts = <0x00000000 0x0000000a 0x00000004>;
        interrupt-names = "complete";
        devfreq-events = <0x000000a6>;
        clocks = <0x0000001f 0x000001a2>;
        clock-names = "dmc_clk";
        operating-points-v2 = <0x000000a7>;
        ddr_timing = <0x000000a8>;
        vop-bw-dmc-freq = <0x00000000 0x000001f9 0x0004f1a0 0x000001fa 0x0001869f 0x00080e80>;
        upthreshold = <0x00000028>;
        downdifferential = <0x00000014>;
        system-status-freq = <0x00000001 0x000be6e0 0x00000008 0x000be6e0 0x00000002 0x000be6e0 0x00000010 0x000be6e0 0x00010000 0x000be6e0 0x00001000 0x000be6e0 0x00004000 0x000be6e0 0x00002000 0x000be6e0 0x00000c00 0x000be6e0>;
        auto-min-freq = <0x0004f1a0>;
        auto-freq-en = <0x00000001>;
        #cooling-cells = <0x00000002>;
        status = "disabled";
        center-supply = <0x00000062>;
        phandle = <0x00000013>;
    };
    dmc-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x000000a9 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000618 0x000061a8>;
        rockchip,leakage-voltage-sel = <0x00000001 0x00000050 0x00000000 0x00000051 0x000000fe 0x00000001>;
        phandle = <0x000000a7>;
        opp-324000000 {
            opp-hz = <0x00000000 0x134fd900>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-528000000 {
            opp-hz = <0x00000000 0x1f78a400>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-780000000 {
            opp-hz = <0x00000000 0x2e7ddb00>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-920000000 {
            opp-hz = <0x00000000 0x36d61600>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
            status = "disabled";
        };
        opp-1056000000 {
            opp-hz = <0x00000000 0x3ef14800>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
    };
    pcie@fe260000 {
        compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000000 0x0000000f>;
        clocks = <0x0000001f 0x00000081 0x0000001f 0x00000082 0x0000001f 0x00000083 0x0000001f 0x00000084 0x0000001f 0x00000085>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
        device_type = "pci";
        interrupts = <0x00000000 0x0000004b 0x00000004 0x00000000 0x0000004a 0x00000004 0x00000000 0x00000049 0x00000004 0x00000000 0x00000048 0x00000004 0x00000000 0x00000047 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x000000aa 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x000000aa 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x000000aa 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x000000aa 0x00000003>;
        linux,pci-domain = <0x00000000>;
        num-ib-windows = <0x00000006>;
        num-ob-windows = <0x00000002>;
        max-link-speed = <0x00000002>;
        msi-map = <0x00000000 0x000000ab 0x00000000 0x00001000>;
        num-lanes = <0x00000001>;
        phys = <0x00000022 0x00000002>;
        phy-names = "pcie-phy";
        power-domains = <0x00000021 0x0000000f>;
        ranges = <0x00000800 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00800000 0x81000000 0x00000000 0x00800000 0x00000003 0x00800000 0x00000000 0x00100000 0x83000000 0x00000000 0x00900000 0x00000003 0x00900000 0x00000000 0x3f700000>;
        reg = <0x00000003 0xc0000000 0x00000000 0x00400000 0x00000000 0xfe260000 0x00000000 0x00010000>;
        reg-names = "pcie-dbi", "pcie-apb";
        resets = <0x0000001f 0x000000a1>;
        reset-names = "pipe";
        status = "disabled";
        phandle = <0x00000194>;
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x00000048 0x00000001>;
            phandle = <0x000000aa>;
        };
    };
    dwmmc@fe2b0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2b0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000062 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b0 0x0000001f 0x000000b1 0x0000001f 0x0000018a 0x0000001f 0x0000018b>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d4>;
        reset-names = "reset";
        status = "okay";
        supports-sd;
        bus-width = <0x00000004>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        disable-wp;
        sd-uhs-sdr104;
        vmmc-supply = <0x000000ac>;
        vqmmc-supply = <0x0000002b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ad 0x000000ae 0x000000af 0x000000b0>;
        phandle = <0x00000195>;
    };
    dwmmc@fe2c0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2c0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000063 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b2 0x0000001f 0x000000b3 0x0000001f 0x0000018c 0x0000001f 0x0000018d>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d6>;
        reset-names = "reset";
        status = "okay";
        supports-sdio;
        bus-width = <0x00000004>;
        disable-wp;
        cap-sd-highspeed;
        cap-sdio-irq;
        keep-power-in-suspend;
        mmc-pwrseq = <0x000000b1>;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b2 0x000000b3 0x000000b4>;
        sd-uhs-sdr104;
        phandle = <0x00000196>;
    };
    sfc@fe300000 {
        compatible = "rockchip,sfc";
        reg = <0x00000000 0xfe300000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000065 0x00000004>;
        clocks = <0x0000001f 0x00000078 0x0000001f 0x00000076>;
        clock-names = "clk_sfc", "hclk_sfc";
        assigned-clocks = <0x0000001f 0x00000078>;
        assigned-clock-rates = <0x05f5e100>;
        status = "okay";
        phandle = <0x00000197>;
    };
    sdhci@fe310000 {
        compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
        reg = <0x00000000 0xfe310000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000013 0x00000004>;
        assigned-clocks = <0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        assigned-clock-rates = <0x0bebc200 0x016e3600>;
        clocks = <0x0000001f 0x0000007c 0x0000001f 0x0000007a 0x0000001f 0x00000079 0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        clock-names = "core", "bus", "axi", "block", "timer";
        status = "okay";
        bus-width = <0x00000008>;
        supports-emmc;
        non-removable;
        max-frequency = <0x0bebc200>;
        phandle = <0x00000198>;
    };
    nandc@fe330000 {
        compatible = "rockchip,rk-nandc-v9";
        reg = <0x00000000 0xfe330000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000046 0x00000004>;
        nandc_id = <0x00000000>;
        clocks = <0x0000001f 0x00000075 0x0000001f 0x00000074>;
        clock-names = "clk_nandc", "hclk_nandc";
        status = "okay";
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        phandle = <0x00000199>;
        nand@0 {
            reg = <0x00000000>;
            nand-bus-width = <0x00000008>;
            nand-ecc-mode = "hw";
            nand-ecc-strength = <0x00000010>;
            nand-ecc-step-size = <0x00000400>;
        };
    };
    crypto@fe380000 {
        compatible = "rockchip,rk3568-crypto";
        reg = <0x00000000 0xfe380000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000004 0x00000004>;
        clocks = <0x0000001f 0x0000006a 0x0000001f 0x0000006b 0x0000001f 0x0000006c 0x0000001f 0x0000006d>;
        clock-names = "aclk", "hclk", "sclk", "apb_pclk";
        assigned-clocks = <0x0000001f 0x0000006c>;
        assigned-clock-rates = <0x0bebc200>;
        resets = <0x0000001f 0x00000069>;
        reset-names = "crypto-rst";
        status = "disabled";
        phandle = <0x0000019a>;
    };
    rng@fe388000 {
        compatible = "rockchip,cryptov2-rng";
        reg = <0x00000000 0xfe388000 0x00000000 0x00002000>;
        clocks = <0x0000001f 0x00000070 0x0000001f 0x0000006f>;
        clock-names = "clk_trng", "hclk_trng";
        resets = <0x0000001f 0x0000006d>;
        reset-names = "reset";
        status = "okay";
        phandle = <0x0000019b>;
    };
    otp@fe38c000 {
        compatible = "rockchip,rk3568-otp";
        reg = <0x00000000 0xfe38c000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000073 0x0000001f 0x00000072 0x0000001f 0x00000071 0x0000001f 0x00000181>;
        clock-names = "usr", "sbpi", "apb", "phy";
        resets = <0x0000001f 0x000001cf>;
        reset-names = "otp_phy";
        phandle = <0x0000019c>;
        cpu-code@2 {
            reg = <0x00000002 0x00000002>;
            phandle = <0x0000000f>;
        };
        cpu-version@8 {
            reg = <0x00000008 0x00000001>;
            bits = <0x00000003 0x00000003>;
            phandle = <0x0000000e>;
        };
        mbist-vmin@9 {
            reg = <0x00000009 0x00000001>;
            bits = <0x00000000 0x00000004>;
            phandle = <0x00000008>;
        };
        id@a {
            reg = <0x0000000a 0x00000010>;
            phandle = <0x0000000d>;
        };
        cpu-leakage@1a {
            reg = <0x0000001a 0x00000001>;
            phandle = <0x00000006>;
        };
        log-leakage@1b {
            reg = <0x0000001b 0x00000001>;
            phandle = <0x000000a9>;
        };
        npu-leakage@1c {
            reg = <0x0000001c 0x00000001>;
            phandle = <0x00000060>;
        };
        gpu-leakage@1d {
            reg = <0x0000001d 0x00000001>;
            phandle = <0x00000065>;
        };
        core-pvtm@2a {
            reg = <0x0000002a 0x00000002>;
            phandle = <0x00000007>;
        };
    };
    i2s@fe400000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe400000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000034 0x00000004>;
        clocks = <0x0000001f 0x0000003f 0x0000001f 0x00000043 0x0000001f 0x00000039>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000000>;
        dma-names = "tx";
        resets = <0x0000001f 0x00000050 0x0000001f 0x00000051>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000121>;
    };
    i2s@fe410000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe410000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000035 0x00000004>;
        clocks = <0x0000001f 0x00000047 0x0000001f 0x0000004b 0x0000001f 0x0000003a>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000002 0x000000b5 0x00000003>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000052 0x0000001f 0x00000053>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b6 0x000000b7 0x000000b8 0x000000b9>;
        status = "disabled";
        rockchip,clk-trcm = <0x00000001>;
        phandle = <0x000000c6>;
    };
    i2s@fe420000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe420000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000036 0x00000004>;
        clocks = <0x0000001f 0x0000004f 0x0000001f 0x0000004f 0x0000001f 0x0000003b>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000004 0x000000b5 0x00000005>;
        dma-names = "tx", "rx";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ba 0x000000bb 0x000000bc 0x000000bd>;
        status = "disabled";
        phandle = <0x0000019d>;
    };
    i2s@fe430000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe430000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000037 0x00000004>;
        clocks = <0x0000001f 0x00000053 0x0000001f 0x00000057 0x0000001f 0x0000003c>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000006 0x000000b5 0x00000007>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000055 0x0000001f 0x00000056>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000be 0x000000bf 0x000000c0 0x000000c1>;
        status = "okay";
        phandle = <0x0000011d>;
    };
    pdm@fe440000 {
        compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
        reg = <0x00000000 0xfe440000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000005a 0x0000001f 0x00000059>;
        clock-names = "pdm_clk", "pdm_hclk";
        dmas = <0x000000b5 0x00000009>;
        dma-names = "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c2 0x000000c3 0x000000c4 0x000000c5>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000123>;
    };
    vad@fe450000 {
        compatible = "rockchip,rk3568-vad";
        reg = <0x00000000 0xfe450000 0x00000000 0x00010000>;
        reg-names = "vad";
        clocks = <0x0000001f 0x0000005b>;
        clock-names = "hclk";
        interrupts = <0x00000000 0x00000089 0x00000004>;
        rockchip,audio-src = <0x000000c6>;
        rockchip,det-channel = <0x00000000>;
        rockchip,mode = <0x00000000>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        rockchip,buffer-time-ms = <0x00000080>;
        phandle = <0x00000128>;
    };
    spdif@fe460000 {
        compatible = "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfe460000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000066 0x00000004>;
        dmas = <0x000000b5 0x00000001>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x0000001f 0x0000005f 0x0000001f 0x0000005c>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c7>;
        status = "okay";
        phandle = <0x00000126>;
    };
    audpwm@fe470000 {
        compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
        reg = <0x00000000 0xfe470000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000063 0x0000001f 0x00000060>;
        clock-names = "clk", "hclk";
        dmas = <0x000000b5 0x00000008>;
        dma-names = "tx";
        #sound-dai-cells = <0x00000000>;
        rockchip,sample-width-bits = <0x0000000b>;
        rockchip,interpolat-points = <0x00000001>;
        status = "disabled";
        phandle = <0x0000019e>;
    };
    codec-digital@fe478000 {
        compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
        reg = <0x00000000 0xfe478000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000067 0x0000001f 0x00000066 0x0000001f 0x00000065 0x0000001f 0x00000064>;
        clock-names = "adc", "dac", "i2c", "pclk";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c8>;
        resets = <0x0000001f 0x0000005f>;
        reset-names = "reset";
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000011e>;
    };
    dmac@fe530000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe530000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x0000000e 0x00000004 0x00000000 0x0000000d 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x0000003f>;
    };
    dmac@fe550000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe550000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000010 0x00000004 0x00000000 0x0000000f 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x000000b5>;
    };
    rkscr@fe560000 {
        compatible = "rockchip-scr";
        reg = <0x00000000 0xfe560000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000061 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c9>;
        clocks = <0x0000001f 0x00000114>;
        clock-names = "g_pclk_sim_card";
        status = "disabled";
        phandle = <0x0000019f>;
    };
    can@fe570000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe570000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000001 0x00000004>;
        clocks = <0x0000001f 0x00000141 0x0000001f 0x00000140>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000155 0x0000001f 0x00000154>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000141>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ca>;
        phandle = <0x000001a0>;
    };
    can@fe580000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe580000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000002 0x00000004>;
        clocks = <0x0000001f 0x00000143 0x0000001f 0x00000142>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000157 0x0000001f 0x00000156>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000143>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cb>;
        phandle = <0x000001a1>;
    };
    can@fe590000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe590000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000003 0x00000004>;
        clocks = <0x0000001f 0x00000145 0x0000001f 0x00000144>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000159 0x0000001f 0x00000158>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000145>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cc>;
        phandle = <0x000001a2>;
    };
    i2c@fe5a0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5a0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000148 0x0000001f 0x00000147>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002f 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cd>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a3>;
        gt1x@14 {
            compatible = "goodix,gt1x";
            reg = <0x00000014>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000ce>;
            goodix,rst-gpio = <0x00000035 0x0000000e 0x00000000>;
            goodix,irq-gpio = <0x00000035 0x0000000d 0x00000008>;
            power-supply = <0x00000092>;
            status = "disabled";
            phandle = <0x000001a4>;
        };
    };
    i2c@fe5b0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5b0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014a 0x0000001f 0x00000149>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000030 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cf>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001a5>;
        gc2145@3c {
            status = "okay";
            compatible = "galaxycore,gc2145";
            reg = <0x0000003c>;
            clocks = <0x0000001f 0x000000d6>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d0 0x000000d1 0x000000d2>;
            power-gpios = <0x0000007b 0x0000001c 0x00000000>;
            pwdn-gpios = <0x0000007b 0x0000001a 0x00000000>;
            rockchip,camera-module-index = <0x00000001>;
            rockchip,camera-module-facing = "front";
            rockchip,camera-module-name = "CameraKing";
            rockchip,camera-module-lens-name = "Largan";
            phandle = <0x000001a6>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d3>;
                    phandle = <0x00000072>;
                };
            };
        };
        ov5695@36 {
            status = "okay";
            compatible = "ovti,ov5695";
            reg = <0x00000036>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000000>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000000>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "TongJu";
            rockchip,camera-module-lens-name = "CHT842-MD";
            phandle = <0x000001a7>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d5>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x00000108>;
                };
            };
        };
        gc8034@37 {
            compatible = "galaxycore,gc8034";
            status = "okay";
            reg = <0x00000037>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000001>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000001>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "RK-CMK-8M-2-v1";
            rockchip,camera-module-lens-name = "CK8401";
            phandle = <0x000001a8>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d6>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x00000109>;
                };
            };
        };
    };
    i2c@fe5c0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5c0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014c 0x0000001f 0x0000014b>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000031 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d7>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a9>;
    };
    i2c@fe5d0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5d0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014e 0x0000001f 0x0000014d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000032 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d8>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001aa>;
    };
    i2c@fe5e0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5e0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000150 0x0000001f 0x0000014f>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000033 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d9>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001ab>;
        mxc6655xa@15 {
            status = "okay";
            compatible = "gs_mxc6655xa";
            pinctrl-names = "default";
            pinctrl-0 = <0x000000da>;
            reg = <0x00000015>;
            irq-gpio = <0x0000007b 0x00000011 0x00000008>;
            irq_enable = <0x00000000>;
            poll_delay_ms = <0x0000001e>;
            type = <0x00000002>;
            power-off-in-suspend = <0x00000001>;
            layout = <0x00000001>;
            phandle = <0x000001ac>;
        };
    };
    timer@fe5f0000 {
        compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
        reg = <0x00000000 0xfe5f0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006d 0x00000004>;
        clocks = <0x0000001f 0x0000016c 0x0000001f 0x0000016d>;
        clock-names = "pclk", "timer";
        phandle = <0x000001ad>;
    };
    watchdog@fe600000 {
        compatible = "snps,dw-wdt";
        reg = <0x00000000 0xfe600000 0x00000000 0x00000100>;
        clocks = <0x0000001f 0x00000116 0x0000001f 0x00000115>;
        clock-names = "tclk", "pclk";
        interrupts = <0x00000000 0x00000095 0x00000004>;
        status = "okay";
        phandle = <0x000001ae>;
    };
    spi@fe610000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe610000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000067 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000152 0x0000001f 0x00000151>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000014 0x0000003f 0x00000015>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000db 0x000000dc 0x000000dd>;
        pinctrl-1 = <0x000000db 0x000000dc 0x000000de>;
        status = "disabled";
        phandle = <0x000001af>;
    };
    spi@fe620000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe620000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000068 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000154 0x0000001f 0x00000153>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000016 0x0000003f 0x00000017>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000df 0x000000e0 0x000000e1>;
        pinctrl-1 = <0x000000df 0x000000e0 0x000000e2>;
        status = "disabled";
        phandle = <0x000001b0>;
    };
    spi@fe630000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe630000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000069 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000156 0x0000001f 0x00000155>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000018 0x0000003f 0x00000019>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e3 0x000000e4 0x000000e5>;
        pinctrl-1 = <0x000000e3 0x000000e4 0x000000e6>;
        status = "disabled";
        phandle = <0x000001b1>;
    };
    spi@fe640000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe640000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006a 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000158 0x0000001f 0x00000157>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x0000001a 0x0000003f 0x0000001b>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e7 0x000000e8 0x000000e9>;
        pinctrl-1 = <0x000000e7 0x000000e8 0x000000ea>;
        status = "disabled";
        phandle = <0x000001b2>;
    };
    serial@fe650000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe650000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000075 0x00000004>;
        clocks = <0x0000001f 0x0000011f 0x0000001f 0x0000011c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000002 0x0000003f 0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000eb 0x000000ec>;
        status = "okay";
        phandle = <0x000001b3>;
    };
    serial@fe660000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe660000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000076 0x00000004>;
        clocks = <0x0000001f 0x00000123 0x0000001f 0x00000120>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000004 0x0000003f 0x00000005>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ed>;
        status = "disabled";
        phandle = <0x000001b4>;
    };
    serial@fe670000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe670000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000077 0x00000004>;
        clocks = <0x0000001f 0x00000127 0x0000001f 0x00000124>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000006 0x0000003f 0x00000007>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ee>;
        status = "disabled";
        phandle = <0x000001b5>;
    };
    serial@fe680000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe680000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000078 0x00000004>;
        clocks = <0x0000001f 0x0000012b 0x0000001f 0x00000128>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000008 0x0000003f 0x00000009>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ef>;
        status = "disabled";
        phandle = <0x000001b6>;
    };
    serial@fe690000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe690000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000079 0x00000004>;
        clocks = <0x0000001f 0x0000012f 0x0000001f 0x0000012c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000a 0x0000003f 0x0000000b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f0>;
        status = "disabled";
        phandle = <0x000001b7>;
    };
    serial@fe6a0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6a0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007a 0x00000004>;
        clocks = <0x0000001f 0x00000133 0x0000001f 0x00000130>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000c 0x0000003f 0x0000000d>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f1>;
        status = "disabled";
        phandle = <0x000001b8>;
    };
    serial@fe6b0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6b0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007b 0x00000004>;
        clocks = <0x0000001f 0x00000137 0x0000001f 0x00000134>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000e 0x0000003f 0x0000000f>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f2>;
        status = "disabled";
        phandle = <0x000001b9>;
    };
    serial@fe6c0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6c0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007c 0x00000004>;
        clocks = <0x0000001f 0x0000013b 0x0000001f 0x00000138>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000010 0x0000003f 0x00000011>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f3>;
        status = "disabled";
        phandle = <0x000001ba>;
    };
    serial@fe6d0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6d0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007d 0x00000004>;
        clocks = <0x0000001f 0x0000013f 0x0000001f 0x0000013c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000012 0x0000003f 0x00000013>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f4>;
        status = "disabled";
        phandle = <0x000001bb>;
    };
    pwm@fe6e0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f5>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x0000011f>;
    };
    pwm@fe6e0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f6>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x00000120>;
    };
    pwm@fe6e0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f7>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bc>;
    };
    pwm@fe6e0030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfe6e0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000053 0x00000004 0x00000000 0x00000057 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f8>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x000001bd>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000ba 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000bd 0x00000066 0x000000ea 0x00000073 0x000000e3 0x00000072 0x000000e2 0x000000d9 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x00000072 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
    };
    pwm@fe6f0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f9>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001be>;
    };
    pwm@fe6f0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fa>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bf>;
    };
    pwm@fe6f0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fb>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c0>;
    };
    pwm@fe6f0030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000054 0x00000004 0x00000000 0x00000058 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fc>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c1>;
    };
    pwm@fe700000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fd>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c2>;
    };
    pwm@fe700010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fe>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c3>;
    };
    pwm@fe700020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000ff>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c4>;
    };
    pwm@fe700030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000055 0x00000004 0x00000000 0x00000059 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000100>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c5>;
    };
    tsadc@fe710000 {
        compatible = "rockchip,rk3568-tsadc";
        reg = <0x00000000 0xfe710000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000073 0x00000004>;
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000111 0x0000001f 0x0000010f>;
        clock-names = "tsadc", "apb_pclk";
        assigned-clocks = <0x0000001f 0x00000110 0x0000001f 0x00000111>;
        assigned-clock-rates = <0x01036640 0x000aae60>;
        resets = <0x0000001f 0x00000182 0x0000001f 0x00000181 0x0000001f 0x000001d7>;
        reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
        #thermal-sensor-cells = <0x00000001>;
        rockchip,hw-tshut-temp = <0x0001d4c0>;
        rockchip,hw-tshut-mode = <0x00000000>;
        rockchip,hw-tshut-polarity = <0x00000000>;
        pinctrl-names = "gpio", "otpout";
        pinctrl-0 = <0x00000101>;
        pinctrl-1 = <0x00000102>;
        status = "okay";
        phandle = <0x0000001b>;
    };
    saradc@fe720000 {
        compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
        reg = <0x00000000 0xfe720000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000005d 0x00000004>;
        #io-channel-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        clock-names = "saradc", "apb_pclk";
        resets = <0x0000001f 0x00000180>;
        reset-names = "saradc-apb";
        status = "okay";
        vref-supply = <0x00000103>;
        phandle = <0x0000011b>;
    };
    mailbox@fe780000 {
        compatible = "rockchip,rk3568-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x00000000 0xfe780000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b7 0x00000004 0x00000000 0x000000b8 0x00000004 0x00000000 0x000000b9 0x00000004 0x00000000 0x000000ba 0x00000004>;
        clocks = <0x0000001f 0x0000011b>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x00000001>;
        status = "disabled";
        phandle = <0x000001c6>;
    };
    phy@fe830000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe830000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000022 0x0000001f 0x0000017d 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000022>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c6 0x0000001f 0x000001c7>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000105>;
        status = "okay";
        phandle = <0x00000020>;
    };
    phy@fe840000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe840000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000025 0x0000001f 0x0000017e 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000025>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c8 0x0000001f 0x000001c9>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000106>;
        status = "disabled";
        phandle = <0x00000022>;
    };
    mipi-dphy@fe850000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x0000008e>;
    };
    video-phy@fe850000 {
        compatible = "rockchip,rk3568-video-phy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000 0x00000000 0xfe060000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a 0x0000001f 0x000000e8>;
        clock-names = "ref", "pclk_phy", "pclk_host";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "rst";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000002e>;
    };
    mipi-dphy@fe860000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe860000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000019 0x0000001f 0x0000017b>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy1_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bc>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "disabled";
        phandle = <0x00000097>;
    };
    csi2-dphy-hw@fe870000 {
        compatible = "rockchip,rk3568-csi2-dphy-hw";
        reg = <0x00000000 0xfe870000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000179>;
        clock-names = "pclk";
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x00000107>;
    };
    csi2-dphy0 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "okay";
        phandle = <0x000001c7>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000108>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x000000d5>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000109>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x000000d6>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000010a>;
                    phandle = <0x00000077>;
                };
            };
        };
    };
    csi2-dphy1 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c8>;
    };
    csi2-dphy2 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c9>;
    };
    usb2-phy@fe8a0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8a0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000087 0x00000004>;
        clocks = <0x00000031 0x00000013>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        assigned-clocks = <0x0000001f 0x0000000b>;
        assigned-clock-parents = <0x00000024>;
        clock-output-names = "usb480m_phy";
        rockchip,usbgrf = <0x0000010b>;
        status = "okay";
        phandle = <0x00000024>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000025>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            vbus-supply = <0x0000010d>;
            phandle = <0x00000023>;
        };
    };
    usb2-phy@fe8b0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8b0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000088 0x00000004>;
        clocks = <0x00000031 0x00000015>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        rockchip,usbgrf = <0x0000010e>;
        status = "okay";
        phandle = <0x00000026>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000028>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000027>;
        };
    };
    pinctrl {
        compatible = "rockchip,rk3568-pinctrl";
        rockchip,grf = <0x00000032>;
        rockchip,pmu = <0x00000033>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000010f>;
        phandle = <0x00000110>;
        gpio@fdd60000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfdd60000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000021 0x00000004>;
            clocks = <0x00000031 0x0000002e 0x00000031 0x0000000c>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000000 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000035>;
        };
        gpio@fe740000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe740000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000022 0x00000004>;
            clocks = <0x0000001f 0x00000163 0x0000001f 0x00000164>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000020 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000093>;
        };
        gpio@fe750000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe750000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000023 0x00000004>;
            clocks = <0x0000001f 0x00000165 0x0000001f 0x00000166>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000040 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000012e>;
        };
        gpio@fe760000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe760000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000024 0x00000004>;
            clocks = <0x0000001f 0x00000167 0x0000001f 0x00000168>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000060 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000007b>;
        };
        gpio@fe770000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe770000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000025 0x00000004>;
            clocks = <0x0000001f 0x00000169 0x0000001f 0x0000016a>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000080 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000009c>;
        };
        pcfg-pull-up {
            bias-pull-up;
            phandle = <0x00000113>;
        };
        pcfg-pull-down {
            bias-pull-down;
            phandle = <0x0000011a>;
        };
        pcfg-pull-none {
            bias-disable;
            phandle = <0x00000111>;
        };
        pcfg-pull-none-drv-level-1 {
            bias-disable;
            drive-strength = <0x00000001>;
            phandle = <0x00000115>;
        };
        pcfg-pull-none-drv-level-2 {
            bias-disable;
            drive-strength = <0x00000002>;
            phandle = <0x00000114>;
        };
        pcfg-pull-none-drv-level-3 {
            bias-disable;
            drive-strength = <0x00000003>;
            phandle = <0x00000119>;
        };
        pcfg-pull-up-drv-level-1 {
            bias-pull-up;
            drive-strength = <0x00000001>;
            phandle = <0x00000118>;
        };
        pcfg-pull-up-drv-level-2 {
            bias-pull-up;
            drive-strength = <0x00000002>;
            phandle = <0x00000112>;
        };
        pcfg-pull-none-smt {
            bias-disable;
            input-schmitt-enable;
            phandle = <0x00000116>;
        };
        pcfg-output-low {
            output-low;
            phandle = <0x00000117>;
        };
        acodec {
            acodec-pins {
                rockchip,pins = <0x00000001 0x00000009 0x00000005 0x00000111 0x00000001 0x00000001 0x00000005 0x00000111 0x00000001 0x00000000 0x00000005 0x00000111 0x00000001 0x00000007 0x00000005 0x00000111 0x00000001 0x00000008 0x00000005 0x00000111 0x00000001 0x00000003 0x00000005 0x00000111 0x00000001 0x00000005 0x00000005 0x00000111>;
                phandle = <0x000000c8>;
            };
        };
        cam {
            cam-clkout0 {
                rockchip,pins = <0x00000004 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000d4>;
            };
            camera-pwr {
                rockchip,pins = <0x00000000 0x00000011 0x00000000 0x00000111>;
                phandle = <0x00000133>;
            };
        };
        can0 {
            can0m1-pins {
                rockchip,pins = <0x00000002 0x00000002 0x00000004 0x00000111 0x00000002 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000ca>;
            };
        };
        can1 {
            can1m1-pins {
                rockchip,pins = <0x00000004 0x00000012 0x00000003 0x00000111 0x00000004 0x00000013 0x00000003 0x00000111>;
                phandle = <0x000000cb>;
            };
        };
        can2 {
            can2m1-pins {
                rockchip,pins = <0x00000002 0x00000009 0x00000004 0x00000111 0x00000002 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000cc>;
            };
        };
        cif {
            cif-clk {
                rockchip,pins = <0x00000004 0x00000010 0x00000001 0x00000111>;
                phandle = <0x000000d0>;
            };
            cif-dvp-clk {
                rockchip,pins = <0x00000004 0x00000011 0x00000001 0x00000111 0x00000004 0x0000000e 0x00000001 0x00000111 0x00000004 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x000000d1>;
            };
            cif-dvp-bus16 {
                rockchip,pins = <0x00000003 0x0000001e 0x00000001 0x00000111 0x00000003 0x0000001f 0x00000001 0x00000111 0x00000004 0x00000000 0x00000001 0x00000111 0x00000004 0x00000001 0x00000001 0x00000111 0x00000004 0x00000002 0x00000001 0x00000111 0x00000004 0x00000003 0x00000001 0x00000111 0x00000004 0x00000004 0x00000001 0x00000111 0x00000004 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000d2>;
            };
        };
        clk32k {
            clk32k-out0 {
                rockchip,pins = <0x00000000 0x00000008 0x00000002 0x00000111>;
                phandle = <0x0000001e>;
            };
        };
        ebc {
            ebc-pins {
                rockchip,pins = <0x00000004 0x00000010 0x00000002 0x00000111 0x00000004 0x0000000b 0x00000002 0x00000111 0x00000004 0x0000000c 0x00000002 0x00000111 0x00000004 0x00000006 0x00000002 0x00000111 0x00000004 0x00000011 0x00000002 0x00000111 0x00000003 0x00000016 0x00000002 0x00000111 0x00000003 0x00000017 0x00000002 0x00000111 0x00000003 0x00000018 0x00000002 0x00000111 0x00000003 0x00000019 0x00000002 0x00000111 0x00000003 0x0000001a 0x00000002 0x00000111 0x00000003 0x0000001b 0x00000002 0x00000111 0x00000003 0x0000001c 0x00000002 0x00000111 0x00000003 0x0000001d 0x00000002 0x00000111 0x00000003 0x0000001e 0x00000002 0x00000111 0x00000003 0x0000001f 0x00000002 0x00000111 0x00000004 0x00000000 0x00000002 0x00000111 0x00000004 0x00000001 0x00000002 0x00000111 0x00000004 0x00000002 0x00000002 0x00000111 0x00000004 0x00000003 0x00000002 0x00000111 0x00000004 0x00000004 0x00000002 0x00000111 0x00000004 0x00000005 0x00000002 0x00000111 0x00000004 0x0000000e 0x00000002 0x00000111 0x00000004 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x00000068>;
            };
        };
        gmac1 {
            gmac1m0-miim {
                rockchip,pins = <0x00000003 0x00000014 0x00000003 0x00000111 0x00000003 0x00000015 0x00000003 0x00000111>;
                phandle = <0x0000007c>;
            };
            gmac1m0-rx-bus2 {
                rockchip,pins = <0x00000003 0x00000009 0x00000003 0x00000111 0x00000003 0x0000000a 0x00000003 0x00000111 0x00000003 0x0000000b 0x00000003 0x00000111>;
                phandle = <0x0000007e>;
            };
        };
        hdmitx {
            hdmitxm0-cec {
                rockchip,pins = <0x00000004 0x00000019 0x00000001 0x00000111>;
                phandle = <0x000000a2>;
            };
            hdmitx-scl {
                rockchip,pins = <0x00000004 0x00000017 0x00000001 0x00000111>;
                phandle = <0x000000a0>;
            };
            hdmitx-sda {
                rockchip,pins = <0x00000004 0x00000018 0x00000001 0x00000111>;
                phandle = <0x000000a1>;
            };
        };
        i2c0 {
            i2c0-xfer {
                rockchip,pins = <0x00000000 0x00000009 0x00000001 0x00000116 0x00000000 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x00000034>;
            };
        };
        i2c1 {
            i2c1-xfer {
                rockchip,pins = <0x00000000 0x0000000b 0x00000001 0x00000116 0x00000000 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cd>;
            };
        };
        i2c2 {
            i2c2m1-xfer {
                rockchip,pins = <0x00000004 0x0000000d 0x00000001 0x00000116 0x00000004 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cf>;
            };
        };
        i2c3 {
            i2c3m0-xfer {
                rockchip,pins = <0x00000001 0x00000001 0x00000001 0x00000116 0x00000001 0x00000000 0x00000001 0x00000116>;
                phandle = <0x000000d7>;
            };
        };
        i2c4 {
            i2c4m0-xfer {
                rockchip,pins = <0x00000004 0x0000000b 0x00000001 0x00000116 0x00000004 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x000000d8>;
            };
        };
        i2c5 {
            i2c5m0-xfer {
                rockchip,pins = <0x00000003 0x0000000b 0x00000004 0x00000116 0x00000003 0x0000000c 0x00000004 0x00000116>;
                phandle = <0x000000d9>;
            };
        };
        i2s1 {
            i2s1m0-lrcktx {
                rockchip,pins = <0x00000001 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000b7>;
            };
            i2s1m0-sclktx {
                rockchip,pins = <0x00000001 0x00000003 0x00000001 0x00000111>;
                phandle = <0x000000b6>;
            };
            i2s1m0-sdi0 {
                rockchip,pins = <0x00000001 0x0000000b 0x00000001 0x00000111>;
                phandle = <0x000000b8>;
            };
            i2s1m0-sdo0 {
                rockchip,pins = <0x00000001 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000b9>;
            };
        };
        i2s2 {
            i2s2m0-lrcktx {
                rockchip,pins = <0x00000002 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000bb>;
            };
            i2s2m0-sclktx {
                rockchip,pins = <0x00000002 0x00000012 0x00000001 0x00000111>;
                phandle = <0x000000ba>;
            };
            i2s2m0-sdi {
                rockchip,pins = <0x00000002 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000bc>;
            };
            i2s2m0-sdo {
                rockchip,pins = <0x00000002 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000bd>;
            };
        };
        i2s3 {
            i2s3m1-lrck {
                rockchip,pins = <0x00000004 0x00000014 0x00000005 0x00000111>;
                phandle = <0x000000bf>;
            };
            i2s3m1-mclk {
                rockchip,pins = <0x00000004 0x00000012 0x00000005 0x00000111>;
                phandle = <0x0000003d>;
            };
            i2s3m1-sclk {
                rockchip,pins = <0x00000004 0x00000013 0x00000005 0x00000111>;
                phandle = <0x000000be>;
            };
            i2s3m1-sdi {
                rockchip,pins = <0x00000004 0x00000016 0x00000005 0x00000111>;
                phandle = <0x000000c0>;
            };
            i2s3m1-sdo {
                rockchip,pins = <0x00000004 0x00000015 0x00000005 0x00000111>;
                phandle = <0x000000c1>;
            };
        };
        lcdc {
            lcdc-ctl {
                rockchip,pins = <0x00000003 0x00000000 0x00000001 0x00000111 0x00000002 0x00000018 0x00000001 0x00000111 0x00000002 0x00000019 0x00000001 0x00000111 0x00000002 0x0000001a 0x00000001 0x00000111 0x00000002 0x0000001b 0x00000001 0x00000111 0x00000002 0x0000001c 0x00000001 0x00000111 0x00000002 0x0000001d 0x00000001 0x00000111 0x00000002 0x0000001e 0x00000001 0x00000111 0x00000002 0x0000001f 0x00000001 0x00000111 0x00000003 0x00000001 0x00000001 0x00000111 0x00000003 0x00000002 0x00000001 0x00000111 0x00000003 0x00000003 0x00000001 0x00000111 0x00000003 0x00000004 0x00000001 0x00000111 0x00000003 0x00000005 0x00000001 0x00000111 0x00000003 0x00000006 0x00000001 0x00000111 0x00000003 0x00000007 0x00000001 0x00000111 0x00000003 0x00000008 0x00000001 0x00000111 0x00000003 0x00000009 0x00000001 0x00000111 0x00000003 0x0000000a 0x00000001 0x00000111 0x00000003 0x0000000b 0x00000001 0x00000111 0x00000003 0x0000000c 0x00000001 0x00000111 0x00000003 0x0000000d 0x00000001 0x00000111 0x00000003 0x0000000e 0x00000001 0x00000111 0x00000003 0x0000000f 0x00000001 0x00000111 0x00000003 0x00000010 0x00000001 0x00000111 0x00000003 0x00000013 0x00000001 0x00000111 0x00000003 0x00000011 0x00000001 0x00000111 0x00000003 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000030>;
            };
        };
        pdm {
            pdmm1-clk1 {
                rockchip,pins = <0x00000004 0x00000000 0x00000004 0x00000111>;
                phandle = <0x000000c2>;
            };
            pdmm1-sdi1 {
                rockchip,pins = <0x00000004 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000c3>;
            };
            pdmm1-sdi2 {
                rockchip,pins = <0x00000004 0x00000002 0x00000005 0x00000111>;
                phandle = <0x000000c4>;
            };
            pdmm1-sdi3 {
                rockchip,pins = <0x00000004 0x00000003 0x00000005 0x00000111>;
                phandle = <0x000000c5>;
            };
        };
        pmic {
            pmic_int {
                rockchip,pins = <0x00000000 0x00000003 0x00000000 0x00000113>;
                phandle = <0x00000036>;
            };
            soc_slppin_gpio {
                rockchip,pins = <0x00000000 0x00000002 0x00000000 0x00000117>;
                phandle = <0x00000039>;
            };
            soc_slppin_slp {
                rockchip,pins = <0x00000000 0x00000002 0x00000001 0x00000111>;
                phandle = <0x00000037>;
            };
            soc_slppin_rst {
                rockchip,pins = <0x00000000 0x00000002 0x00000002 0x00000111>;
                phandle = <0x000001ca>;
            };
        };
        pwm0 {
            pwm0m0-pins {
                rockchip,pins = <0x00000000 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x00000041>;
            };
        };
        pwm1 {
            pwm1m0-pins {
                rockchip,pins = <0x00000000 0x00000010 0x00000001 0x00000111>;
                phandle = <0x00000042>;
            };
        };
        pwm2 {
            pwm2m0-pins {
                rockchip,pins = <0x00000000 0x00000011 0x00000001 0x00000111>;
                phandle = <0x00000043>;
            };
        };
        pwm3 {
            pwm3-pins {
                rockchip,pins = <0x00000000 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000044>;
            };
        };
        pwm4 {
            pwm4-pins {
                rockchip,pins = <0x00000000 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000f5>;
            };
        };
        pwm5 {
            pwm5-pins {
                rockchip,pins = <0x00000000 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000f6>;
            };
        };
        pwm6 {
            pwm6-pins {
                rockchip,pins = <0x00000000 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000f7>;
            };
        };
        pwm7 {
            pwm7-pins {
                rockchip,pins = <0x00000000 0x00000016 0x00000001 0x00000111>;
                phandle = <0x000000f8>;
            };
        };
        pwm8 {
            pwm8m0-pins {
                rockchip,pins = <0x00000003 0x00000009 0x00000005 0x00000111>;
                phandle = <0x000000f9>;
            };
        };
        pwm9 {
            pwm9m0-pins {
                rockchip,pins = <0x00000003 0x0000000a 0x00000005 0x00000111>;
                phandle = <0x000000fa>;
            };
        };
        pwm10 {
            pwm10m0-pins {
                rockchip,pins = <0x00000003 0x0000000d 0x00000005 0x00000111>;
                phandle = <0x000000fb>;
            };
        };
        pwm11 {
            pwm11m0-pins {
                rockchip,pins = <0x00000003 0x0000000e 0x00000005 0x00000111>;
                phandle = <0x000000fc>;
            };
        };
        pwm12 {
            pwm12m0-pins {
                rockchip,pins = <0x00000003 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x000000fd>;
            };
        };
        pwm13 {
            pwm13m0-pins {
                rockchip,pins = <0x00000003 0x00000010 0x00000002 0x00000111>;
                phandle = <0x000000fe>;
            };
        };
        pwm14 {
            pwm14m0-pins {
                rockchip,pins = <0x00000003 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000ff>;
            };
        };
        pwm15 {
            pwm15m0-pins {
                rockchip,pins = <0x00000003 0x00000015 0x00000001 0x00000111>;
                phandle = <0x00000100>;
            };
        };
        scr {
            scr-pins {
                rockchip,pins = <0x00000001 0x00000002 0x00000003 0x00000111 0x00000001 0x00000007 0x00000003 0x00000113 0x00000001 0x00000003 0x00000003 0x00000113 0x00000001 0x00000005 0x00000003 0x00000111>;
                phandle = <0x000000c9>;
            };
        };
        sdmmc0 {
            sdmmc0-bus4 {
                rockchip,pins = <0x00000001 0x0000001d 0x00000001 0x00000112 0x00000001 0x0000001e 0x00000001 0x00000112 0x00000001 0x0000001f 0x00000001 0x00000112 0x00000002 0x00000000 0x00000001 0x00000112>;
                phandle = <0x000000ad>;
            };
            sdmmc0-clk {
                rockchip,pins = <0x00000002 0x00000002 0x00000001 0x00000112>;
                phandle = <0x000000ae>;
            };
            sdmmc0-cmd {
                rockchip,pins = <0x00000002 0x00000001 0x00000001 0x00000112>;
                phandle = <0x000000af>;
            };
            sdmmc0-det {
                rockchip,pins = <0x00000000 0x00000004 0x00000001 0x00000113>;
                phandle = <0x000000b0>;
            };
        };
        sdmmc1 {
            sdmmc1-bus4 {
                rockchip,pins = <0x00000002 0x00000003 0x00000001 0x00000112 0x00000002 0x00000004 0x00000001 0x00000112 0x00000002 0x00000005 0x00000001 0x00000112 0x00000002 0x00000006 0x00000001 0x00000112>;
                phandle = <0x000000b2>;
            };
            sdmmc1-clk {
                rockchip,pins = <0x00000002 0x00000008 0x00000001 0x00000112>;
                phandle = <0x000000b4>;
            };
            sdmmc1-cmd {
                rockchip,pins = <0x00000002 0x00000007 0x00000001 0x00000112>;
                phandle = <0x000000b3>;
            };
        };
        spdif {
            spdifm0-tx {
                rockchip,pins = <0x00000001 0x00000004 0x00000004 0x00000111>;
                phandle = <0x000000c7>;
            };
        };
        spi0 {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000111 0x00000000 0x00000015 0x00000002 0x00000111 0x00000000 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000dd>;
            };
            spi0m0-cs0 {
                rockchip,pins = <0x00000000 0x00000016 0x00000002 0x00000111>;
                phandle = <0x000000db>;
            };
            spi0m0-cs1 {
                rockchip,pins = <0x00000000 0x00000014 0x00000002 0x00000111>;
                phandle = <0x000000dc>;
            };
        };
        spi1 {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000111 0x00000002 0x0000000e 0x00000003 0x00000111 0x00000002 0x0000000f 0x00000004 0x00000111>;
                phandle = <0x000000e1>;
            };
            spi1m0-cs0 {
                rockchip,pins = <0x00000002 0x00000010 0x00000004 0x00000111>;
                phandle = <0x000000df>;
            };
            spi1m0-cs1 {
                rockchip,pins = <0x00000002 0x00000016 0x00000003 0x00000111>;
                phandle = <0x000000e0>;
            };
        };
        spi2 {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000111 0x00000002 0x00000012 0x00000004 0x00000111 0x00000002 0x00000013 0x00000004 0x00000111>;
                phandle = <0x000000e5>;
            };
            spi2m0-cs0 {
                rockchip,pins = <0x00000002 0x00000014 0x00000004 0x00000111>;
                phandle = <0x000000e3>;
            };
            spi2m0-cs1 {
                rockchip,pins = <0x00000002 0x00000015 0x00000004 0x00000111>;
                phandle = <0x000000e4>;
            };
        };
        spi3 {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000111 0x00000004 0x00000008 0x00000004 0x00000111 0x00000004 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000e9>;
            };
            spi3m0-cs0 {
                rockchip,pins = <0x00000004 0x00000006 0x00000004 0x00000111>;
                phandle = <0x000000e7>;
            };
            spi3m0-cs1 {
                rockchip,pins = <0x00000004 0x00000007 0x00000004 0x00000111>;
                phandle = <0x000000e8>;
            };
        };
        tsadc {
            tsadc-shutorg {
                rockchip,pins = <0x00000000 0x00000001 0x00000002 0x00000111>;
                phandle = <0x00000102>;
            };
        };
        uart0 {
            uart0-xfer {
                rockchip,pins = <0x00000000 0x00000010 0x00000003 0x00000113 0x00000000 0x00000011 0x00000003 0x00000113>;
                phandle = <0x00000040>;
            };
        };
        uart1 {
            uart1m0-xfer {
                rockchip,pins = <0x00000002 0x0000000b 0x00000002 0x00000113 0x00000002 0x0000000c 0x00000002 0x00000113>;
                phandle = <0x000000eb>;
            };
            uart1m0-ctsn {
                rockchip,pins = <0x00000002 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000ec>;
            };
            uart1m0-rtsn {
                rockchip,pins = <0x00000002 0x0000000d 0x00000002 0x00000111>;
                phandle = <0x00000130>;
            };
        };
        uart2 {
            uart2m0-xfer {
                rockchip,pins = <0x00000000 0x00000018 0x00000001 0x00000113 0x00000000 0x00000019 0x00000001 0x00000113>;
                phandle = <0x000000ed>;
            };
        };
        uart3 {
            uart3m0-xfer {
                rockchip,pins = <0x00000001 0x00000000 0x00000002 0x00000113 0x00000001 0x00000001 0x00000002 0x00000113>;
                phandle = <0x000000ee>;
            };
        };
        uart4 {
            uart4m0-xfer {
                rockchip,pins = <0x00000001 0x00000004 0x00000002 0x00000113 0x00000001 0x00000006 0x00000002 0x00000113>;
                phandle = <0x000000ef>;
            };
        };
        uart5 {
            uart5m0-xfer {
                rockchip,pins = <0x00000002 0x00000001 0x00000003 0x00000113 0x00000002 0x00000002 0x00000003 0x00000113>;
                phandle = <0x000000f0>;
            };
        };
        uart6 {
            uart6m0-xfer {
                rockchip,pins = <0x00000002 0x00000003 0x00000003 0x00000113 0x00000002 0x00000004 0x00000003 0x00000113>;
                phandle = <0x000000f1>;
            };
        };
        uart7 {
            uart7m0-xfer {
                rockchip,pins = <0x00000002 0x00000005 0x00000003 0x00000113 0x00000002 0x00000006 0x00000003 0x00000113>;
                phandle = <0x000000f2>;
            };
        };
        uart8 {
            uart8m0-xfer {
                rockchip,pins = <0x00000002 0x00000016 0x00000002 0x00000113 0x00000002 0x00000015 0x00000003 0x00000113>;
                phandle = <0x000000f3>;
            };
        };
        uart9 {
            uart9m0-xfer {
                rockchip,pins = <0x00000002 0x00000007 0x00000003 0x00000113 0x00000002 0x00000008 0x00000003 0x00000113>;
                phandle = <0x000000f4>;
            };
        };
        spi0-hs {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000118 0x00000000 0x00000015 0x00000002 0x00000118 0x00000000 0x0000000e 0x00000002 0x00000118>;
                phandle = <0x000000de>;
            };
        };
        spi1-hs {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000118 0x00000002 0x0000000e 0x00000003 0x00000118 0x00000002 0x0000000f 0x00000004 0x00000118>;
                phandle = <0x000000e2>;
            };
        };
        spi2-hs {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000118 0x00000002 0x00000012 0x00000004 0x00000118 0x00000002 0x00000013 0x00000004 0x00000118>;
                phandle = <0x000000e6>;
            };
        };
        spi3-hs {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000118 0x00000004 0x00000008 0x00000004 0x00000118 0x00000004 0x0000000a 0x00000004 0x00000118>;
                phandle = <0x000000ea>;
            };
        };
        gmac-txd-level3 {
            gmac1m0-tx-bus2-level3 {
                rockchip,pins = <0x00000003 0x0000000d 0x00000003 0x00000119 0x00000003 0x0000000e 0x00000003 0x00000119 0x00000003 0x0000000f 0x00000003 0x00000111>;
                phandle = <0x0000007d>;
            };
            gmac1m0-rgmii-bus-level3 {
                rockchip,pins = <0x00000003 0x00000004 0x00000003 0x00000111 0x00000003 0x00000005 0x00000003 0x00000111 0x00000003 0x00000002 0x00000003 0x00000119 0x00000003 0x00000003 0x00000003 0x00000119>;
                phandle = <0x00000080>;
            };
        };
        gmac-txc-level2 {
            gmac1m0-rgmii-clk-level2 {
                rockchip,pins = <0x00000003 0x00000007 0x00000003 0x00000111 0x00000003 0x00000006 0x00000003 0x00000114>;
                phandle = <0x0000007f>;
            };
        };
        gpio-func {
            tsadc-gpio-func {
                rockchip,pins = <0x00000000 0x00000001 0x00000000 0x00000111>;
                phandle = <0x00000101>;
            };
        };
        mxc6655xa {
            mxc6655xa_irq_gpio {
                rockchip,pins = <0x00000003 0x00000011 0x00000000 0x00000111>;
                phandle = <0x000000da>;
            };
        };
        touch {
            touch-gpio {
                rockchip,pins = <0x00000000 0x0000000d 0x00000000 0x00000113 0x00000000 0x0000000e 0x00000000 0x00000111>;
                phandle = <0x000000ce>;
            };
        };
        sdio-pwrseq {
            wifi-enable-h {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x0000012d>;
            };
        };
        usb {
            vcc5v0-host-en {
                rockchip,pins = <0x00000000 0x00000006 0x00000000 0x00000111>;
                phandle = <0x0000012a>;
            };
            vcc5v0-otg-en {
                rockchip,pins = <0x00000000 0x00000005 0x00000000 0x00000111>;
                phandle = <0x0000012b>;
            };
        };
        wireless-bluetooth {
            uart8-gpios {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x000001cb>;
            };
            uart1-gpios {
                rockchip,pins = <0x00000002 0x0000000d 0x00000000 0x00000111>;
                phandle = <0x00000131>;
            };
        };
        headphone {
            hp-det {
                rockchip,pins = <0x00000004 0x0000000b 0x00000000 0x0000011a>;
                phandle = <0x00000132>;
            };
        };
        lcd0 {
            lcd-rst-gpio {
                rockchip,pins = <0x00000001 0x00000005 0x00000000 0x00000111>;
                phandle = <0x00000094>;
            };
        };
        lcd1 {
            lcd1-rst-gpio {
                rockchip,pins = <0x00000004 0x00000016 0x00000000 0x00000111>;
                phandle = <0x0000009d>;
            };
        };
        wireless-wlan {
            wifi-host-wake-irq {
                rockchip,pins = <0x00000002 0x0000000a 0x00000000 0x0000011a>;
                phandle = <0x0000012f>;
            };
        };
        fddis_ctr {
            dis-ctl {
                rockchip,pins = <0x00000000 0x0000000b 0x00000000 0x00000113 0x00000000 0x0000000c 0x00000000 0x00000113>;
                phandle = <0x0000010f>;
            };
        };
    };
    adc-keys {
        compatible = "adc-keys";
        io-channels = <0x0000011b 0x00000000>;
        io-channel-names = "buttons";
        keyup-threshold-microvolt = <0x001b7740>;
        poll-interval = <0x00000064>;
        phandle = <0x000001cc>;
        vol-up-key {
            label = "volume up";
            linux,code = <0x00000073>;
            press-threshold-microvolt = <0x000006d6>;
        };
        vol-down-key {
            label = "volume down";
            linux,code = <0x00000072>;
            press-threshold-microvolt = <0x00048a1c>;
        };
        menu-key {
            label = "menu";
            linux,code = <0x0000008b>;
            press-threshold-microvolt = <0x000ef420>;
        };
        back-key {
            label = "back";
            linux,code = <0x0000009e>;
            press-threshold-microvolt = <0x0013eb9c>;
        };
    };
    audiopwmout-diff {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,audiopwmout-diff";
        simple-audio-card,mclk-fs = <0x00000100>;
        simple-audio-card,bitclock-master = <0x0000011c>;
        simple-audio-card,frame-master = <0x0000011c>;
        phandle = <0x000001cd>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x0000011e>;
            phandle = <0x0000011c>;
        };
    };
    backlight {
        compatible = "pwm-backlight";
        pwms = <0x0000011f 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x00000091>;
    };
    backlight1 {
        compatible = "pwm-backlight";
        pwms = <0x00000120 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x0000009a>;
    };
    dc-12v {
        compatible = "regulator-fixed";
        regulator-name = "dc_12v";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00b71b00>;
        regulator-max-microvolt = <0x00b71b00>;
        phandle = <0x00000129>;
    };
    hdmi-sound {
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <0x00000080>;
        simple-audio-card,name = "rockchip,hdmi";
        status = "okay";
        phandle = <0x000001ce>;
        simple-audio-card,cpu {
            sound-dai = <0x00000121>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000122>;
        };
    };
    dummy-codec {
        status = "disabled";
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000124>;
    };
    pdm-mic-array {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,name = "rockchip,pdm-mic-array";
        phandle = <0x000001cf>;
        simple-audio-card,cpu {
            sound-dai = <0x00000123>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000124>;
        };
    };
    rk809-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,rk809-codec";
        simple-audio-card,mclk-fs = <0x00000100>;
        phandle = <0x000001d0>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000125>;
        };
    };
    spdif-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,name = "ROCKCHIP,SPDIF";
        simple-audio-card,cpu {
            sound-dai = <0x00000126>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000127>;
        };
    };
    spdif-out {
        status = "okay";
        compatible = "linux,spdif-dit";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000127>;
    };
    vad-sound {
        status = "disabled";
        compatible = "rockchip,multicodecs-card";
        rockchip,card-name = "rockchip,rk3568-vad";
        rockchip,cpu = <0x000000c6>;
        rockchip,codec = <0x00000125 0x00000128>;
        phandle = <0x000001d1>;
    };
    vcc3v3-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00325aa0>;
        regulator-max-microvolt = <0x00325aa0>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003c>;
    };
    vcc5v0-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003e>;
    };
    vcc5v0-host-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000006 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012a>;
        regulator-name = "vcc5v0_host";
        regulator-always-on;
        phandle = <0x0000010c>;
    };
    vcc5v0-otg-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000005 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012b>;
        regulator-name = "vcc5v0_otg";
        phandle = <0x0000010d>;
    };
    vcc3v3-lcd0-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd0_n";
        regulator-boot-on;
        gpio = <0x00000035 0x00000010 0x00000000>;
        enable-active-high;
        phandle = <0x00000092>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    vcc3v3-lcd1-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd1_n";
        regulator-boot-on;
        phandle = <0x0000009b>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    sdio-pwrseq {
        compatible = "mmc-pwrseq-simple";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012d>;
        post-power-on-delay-ms = <0x000000c8>;
        reset-gpios = <0x0000012e 0x00000009 0x00000001>;
        phandle = <0x000000b1>;
    };
    wireless-wlan {
        compatible = "wlan-platdata";
        rockchip,grf = <0x00000032>;
        wifi_chip_type = "ap6398s";
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012f>;
        WIFI,host_wake_irq = <0x0000012e 0x0000000a 0x00000000>;
        phandle = <0x000001d2>;
    };
    wireless-bluetooth {
        compatible = "bluetooth-platdata";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        uart_rts_gpios = <0x0000012e 0x0000000d 0x00000001>;
        pinctrl-names = "default", "rts_gpio";
        pinctrl-0 = <0x00000130>;
        pinctrl-1 = <0x00000131>;
        BT,reset_gpio = <0x0000012e 0x0000000f 0x00000000>;
        BT,wake_gpio = <0x0000012e 0x00000011 0x00000000>;
        BT,wake_host_irq = <0x0000012e 0x00000010 0x00000000>;
        status = "okay";
        phandle = <0x000001d3>;
    };
    test-power {
        status = "okay";
    };
    rk-headset {
        compatible = "rockchip_headset";
        headset_gpio = <0x0000009c 0x0000000b 0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000132>;
        phandle = <0x000001d4>;
    };
    vcc3v3-vga {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_vga";
        regulator-always-on;
        regulator-boot-on;
        gpio = <0x0000009c 0x0000000a 0x00000000>;
        enable-active-high;
        vin-supply = <0x0000003c>;
        phandle = <0x000001d5>;
    };
    vcc-camera-regulator {
        compatible = "regulator-fixed";
        gpio = <0x00000035 0x00000011 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000133>;
        regulator-name = "vcc_camera";
        enable-active-high;
        regulator-always-on;
        regulator-boot-on;
        phandle = <0x000001d6>;
    };
    chosen {
        bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0";
        phandle = <0x000001d7>;
    };
    fiq-debugger {
        compatible = "rockchip,fiq-debugger";
        rockchip,serial-id = <0x00000002>;
        rockchip,wake-irq = <0x00000000>;
        rockchip,irq-mode-enable = <0x00000001>;
        rockchip,baudrate = <0x0016e360>;
        interrupts = <0x00000000 0x000000fc 0x00000008>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ed>;
        status = "okay";
    };
    debug@fd904000 {
        compatible = "rockchip,debug";
        reg = <0x00000000 0xfd904000 0x00000000 0x00001000 0x00000000 0xfd905000 0x00000000 0x00001000 0x00000000 0xfd906000 0x00000000 0x00001000 0x00000000 0xfd907000 0x00000000 0x00001000>;
        phandle = <0x000001d8>;
    };
    cspmu@fd90c000 {
        compatible = "rockchip,cspmu";
        reg = <0x00000000 0xfd90c000 0x00000000 0x00001000 0x00000000 0xfd90d000 0x00000000 0x00001000 0x00000000 0xfd90e000 0x00000000 0x00001000 0x00000000 0xfd90f000 0x00000000 0x00001000>;
        phandle = <0x000001d9>;
    };
    leds {
        compatible = "gpio-leds";
        power-green {
            gpios = <0x00000035 0x0000001b 0x00000001>;
            linux,default-trigger = "none";
            default-state = "off";
        };
        power-red {
            gpios = <0x00000035 0x0000001c 0x00000000>;
            linux,default-trigger = "none";
            default-state = "off";
        };
    };
    fddis_dev {
        compatible = "fddis_dev";
        fddis_gpio_clk = <0x00000035 0x0000000b 0x00000000>;
        fddis_gpio_dat = <0x00000035 0x0000000c 0x00000000>;
        status = "okay";
    };
    resume_reboot {
        compatible = "resume_reboot";
        status = "okay";
    };
    __symbols__ {
        ddr_timing = "/ddr_timing";
        cpu0 = "/cpus/cpu@0";
        cpu1 = "/cpus/cpu@100";
        cpu2 = "/cpus/cpu@200";
        cpu3 = "/cpus/cpu@300";
        CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
        cpu0_opp_table = "/cpu0-opp-table";
        display_subsystem = "/display-subsystem";
        route_dsi0 = "/display-subsystem/route/route-dsi0";
        route_dsi1 = "/display-subsystem/route/route-dsi1";
        route_edp = "/display-subsystem/route/route-edp";
        route_hdmi = "/display-subsystem/route/route-hdmi";
        route_lvds = "/display-subsystem/route/route-lvds";
        route_rgb = "/display-subsystem/route/route-rgb";
        optee = "/firmware/optee";
        scmi = "/firmware/scmi";
        scmi_clk = "/firmware/scmi/protocol@14";
        sdei = "/firmware/sdei";
        mpp_srv = "/mpp-srv";
        reserved_memory = "/reserved-memory";
        drm_logo = "/reserved-memory/drm-logo@00000000";
        drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000";
        ramoops = "/reserved-memory/ramoops@110000";
        rockchip_suspend = "/rockchip-suspend";
        rockchip_system_monitor = "/rockchip-system-monitor";
        thermal_zones = "/thermal-zones";
        soc_thermal = "/thermal-zones/soc-thermal";
        threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
        target = "/thermal-zones/soc-thermal/trips/trip-point-1";
        soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
        gpu_thermal = "/thermal-zones/gpu-thermal";
        gmac1_clkin = "/external-gmac1-clock";
        gmac1_xpcsclk = "/xpcs-gmac1-clock";
        i2s1_mclkin_rx = "/i2s1-mclkin-rx";
        i2s1_mclkin_tx = "/i2s1-mclkin-tx";
        i2s2_mclkin = "/i2s2-mclkin";
        i2s3_mclkin = "/i2s3-mclkin";
        mpll = "/mpll";
        xin24m = "/xin24m";
        xin32k = "/xin32k";
        scmi_shmem = "/scmi-shmem@10f000";
        sata1 = "/sata@fc400000";
        sata2 = "/sata@fc800000";
        usbdrd30 = "/usbdrd";
        usbdrd_dwc3 = "/usbdrd/dwc3@fcc00000";
        usbhost30 = "/usbhost";
        usbhost_dwc3 = "/usbhost/dwc3@fd000000";
        gic = "/interrupt-controller@fd400000";
        its = "/interrupt-controller@fd400000/interrupt-controller@fd440000";
        usb_host0_ehci = "/usb@fd800000";
        usb_host0_ohci = "/usb@fd840000";
        usb_host1_ehci = "/usb@fd880000";
        usb_host1_ohci = "/usb@fd8c0000";
        xpcs = "/syscon@fda00000";
        pmugrf = "/syscon@fdc20000";
        pmu_io_domains = "/syscon@fdc20000/io-domains";
        reboot_mode = "/syscon@fdc20000/reboot-mode";
        pipegrf = "/syscon@fdc50000";
        grf = "/syscon@fdc60000";
        io_domains = "/syscon@fdc60000/io-domains";
        lvds = "/syscon@fdc60000/lvds";
        lvds_in_vp1 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@1";
        lvds_in_vp2 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@2";
        rgb = "/syscon@fdc60000/rgb";
        rgb_in_vp2 = "/syscon@fdc60000/rgb/ports/port@0/endpoint@2";
        pipe_phy_grf0 = "/syscon@fdc70000";
        pipe_phy_grf1 = "/syscon@fdc80000";
        pipe_phy_grf2 = "/syscon@fdc90000";
        usb2phy0_grf = "/syscon@fdca0000";
        usb2phy1_grf = "/syscon@fdca8000";
        edp_phy = "/edp-phy@fdcb0000";
        sram = "/sram@fdcc0000";
        rkvdec_sram = "/sram@fdcc0000/rkvdec-sram@0";
        pmucru = "/clock-controller@fdd00000";
        cru = "/clock-controller@fdd20000";
        i2c0 = "/i2c@fdd40000";
        rk809 = "/i2c@fdd40000/pmic@20";
        pinctrl_rk8xx = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx";
        rk817_slppin_null = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_null";
        rk817_slppin_slp = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_slp";
        rk817_slppin_pwrdn = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_pwrdn";
        rk817_slppin_rst = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_rst";
        vdd_logic = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG1";
        vdd_gpu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG2";
        vcc_ddr = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG3";
        vdd_npu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG4";
        vdda0v9_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG1";
        vdda_0v9 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG2";
        vdda0v9_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG3";
        vccio_acodec = "/i2c@fdd40000/pmic@20/regulators/LDO_REG4";
        vccio_sd = "/i2c@fdd40000/pmic@20/regulators/LDO_REG5";
        vcc3v3_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG6";
        vcca_1v8 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG7";
        vcca1v8_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG8";
        vcca1v8_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG9";
        vcc_1v8 = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG5";
        vcc_3v3 = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG1";
        vcc3v3_sd = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG2";
        rk809_codec = "/i2c@fdd40000/pmic@20/codec";
        vdd_cpu = "/i2c@fdd40000/sti8070@40";
        uart0 = "/serial@fdd50000";
        pwm0 = "/pwm@fdd70000";
        pwm1 = "/pwm@fdd70010";
        pwm2 = "/pwm@fdd70020";
        pwm3 = "/pwm@fdd70030";
        pmu = "/power-management@fdd90000";
        power = "/power-management@fdd90000/power-controller";
        rknpu = "/npu@fde40000";
        npu_opp_table = "/npu-opp-table";
        bus_npu = "/bus-npu";
        bus_npu_opp_table = "/bus-npu-opp-table";
        rknpu_mmu = "/iommu@fde4b000";
        gpu = "/gpu@fde60000";
        gpu_power_model = "/gpu@fde60000/power-model";
        gpu_opp_table = "/opp-table2";
        vdpu = "/vdpu@fdea0400";
        vdpu_mmu = "/iommu@fdea0800";
        rk_rga = "/rk_rga@fdeb0000";
        ebc = "/ebc@fdec0000";
        jpegd = "/jpegd@fded0000";
        jpegd_mmu = "/iommu@fded0480";
        vepu = "/vepu@fdee0000";
        vepu_mmu = "/iommu@fdee0800";
        iep = "/iep@fdef0000";
        iep_mmu = "/iommu@fdef0800";
        eink = "/eink@fdf00000";
        rkvenc = "/rkvenc@fdf40000";
        rkvenc_opp_table = "/rkvenc-opp-table";
        rkvenc_mmu = "/iommu@fdf40f00";
        rkvdec = "/rkvdec@fdf80200";
        rkvdec_mmu = "/iommu@fdf80800";
        mipi_csi2 = "/mipi-csi2@fdfb0000";
        rkcif = "/rkcif@fdfe0000";
        rkcif_mmu = "/iommu@fdfe0800";
        rkcif_dvp = "/rkcif_dvp";
        dvp_in_bcam = "/rkcif_dvp/port/endpoint";
        rkcif_dvp_sditf = "/rkcif_dvp_sditf";
        rkcif_mipi_lvds = "/rkcif_mipi_lvds";
        rkcif_mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf";
        rkisp = "/rkisp@fdff0000";
        rkisp_mmu = "/iommu@fdff1a00";
        rkisp_vir0 = "/rkisp-vir0";
        isp0_in = "/rkisp-vir0/port/endpoint@0";
        rkisp_vir1 = "/rkisp-vir1";
        gmac1 = "/ethernet@fe010000";
        mdio1 = "/ethernet@fe010000/mdio";
        rgmii_phy1 = "/ethernet@fe010000/mdio/phy@0";
        gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config";
        gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config";
        gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config";
        vop = "/vop@fe040000";
        vop_out = "/vop@fe040000/ports";
        vp0 = "/vop@fe040000/ports/port@0";
        vp0_out_dsi0 = "/vop@fe040000/ports/port@0/endpoint@0";
        vp0_out_dsi1 = "/vop@fe040000/ports/port@0/endpoint@1";
        vp0_out_edp = "/vop@fe040000/ports/port@0/endpoint@2";
        vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@3";
        vp1 = "/vop@fe040000/ports/port@1";
        vp1_out_dsi0 = "/vop@fe040000/ports/port@1/endpoint@0";
        vp1_out_dsi1 = "/vop@fe040000/ports/port@1/endpoint@1";
        vp1_out_edp = "/vop@fe040000/ports/port@1/endpoint@2";
        vp1_out_hdmi = "/vop@fe040000/ports/port@1/endpoint@3";
        vp1_out_lvds = "/vop@fe040000/ports/port@1/endpoint@4";
        vp2 = "/vop@fe040000/ports/port@2";
        vp2_out_lvds = "/vop@fe040000/ports/port@2/endpoint@0";
        vp2_out_rgb = "/vop@fe040000/ports/port@2/endpoint@1";
        vop_mmu = "/iommu@fe043e00";
        dsi0 = "/dsi@fe060000";
        dsi0_in = "/dsi@fe060000/ports/port@0";
        dsi0_in_vp0 = "/dsi@fe060000/ports/port@0/endpoint@0";
        dsi0_in_vp1 = "/dsi@fe060000/ports/port@0/endpoint@1";
        dsi_out_panel = "/dsi@fe060000/ports/port@1/endpoint";
        dsi0_panel = "/dsi@fe060000/panel@0";
        disp_timings0 = "/dsi@fe060000/panel@0/display-timings";
        dsi0_timing0 = "/dsi@fe060000/panel@0/display-timings/timing0";
        panel_in_dsi = "/dsi@fe060000/panel@0/ports/port@0/endpoint";
        dsi1 = "/dsi@fe070000";
        dsi1_in = "/dsi@fe070000/ports/port@0";
        dsi1_in_vp0 = "/dsi@fe070000/ports/port@0/endpoint@0";
        dsi1_in_vp1 = "/dsi@fe070000/ports/port@0/endpoint@1";
        dsi1_out_panel = "/dsi@fe070000/ports/port@1/endpoint";
        dsi1_panel = "/dsi@fe070000/panel@0";
        disp_timings1 = "/dsi@fe070000/panel@0/display-timings";
        dsi1_timing0 = "/dsi@fe070000/panel@0/display-timings/timing0";
        panel_in_dsi1 = "/dsi@fe070000/panel@0/ports/port@0/endpoint";
        hdmi = "/hdmi@fe0a0000";
        hdmi_in = "/hdmi@fe0a0000/ports/port";
        hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port/endpoint@0";
        hdmi_in_vp1 = "/hdmi@fe0a0000/ports/port/endpoint@1";
        edp = "/edp@fe0c0000";
        edp_in = "/edp@fe0c0000/ports/port@0";
        edp_in_vp0 = "/edp@fe0c0000/ports/port@0/endpoint@0";
        edp_in_vp1 = "/edp@fe0c0000/ports/port@0/endpoint@1";
        qos_gpu = "/qos@fe128000";
        qos_rkvenc_rd_m0 = "/qos@fe138080";
        qos_rkvenc_rd_m1 = "/qos@fe138100";
        qos_rkvenc_wr_m0 = "/qos@fe138180";
        qos_isp = "/qos@fe148000";
        qos_vicap0 = "/qos@fe148080";
        qos_vicap1 = "/qos@fe148100";
        qos_vpu = "/qos@fe150000";
        qos_ebc = "/qos@fe158000";
        qos_iep = "/qos@fe158100";
        qos_jpeg_dec = "/qos@fe158180";
        qos_jpeg_enc = "/qos@fe158200";
        qos_rga_rd = "/qos@fe158280";
        qos_rga_wr = "/qos@fe158300";
        qos_npu = "/qos@fe180000";
        qos_pcie2x1 = "/qos@fe190000";
        qos_sata1 = "/qos@fe190280";
        qos_sata2 = "/qos@fe190300";
        qos_usb3_0 = "/qos@fe190380";
        qos_usb3_1 = "/qos@fe190400";
        qos_rkvdec = "/qos@fe198000";
        qos_hdcp = "/qos@fe1a8000";
        qos_vop_m0 = "/qos@fe1a8080";
        qos_vop_m1 = "/qos@fe1a8100";
        sdmmc2 = "/dwmmc@fe000000";
        dfi = "/dfi@fe230000";
        dmc = "/dmc";
        dmc_opp_table = "/dmc-opp-table";
        pcie2x1 = "/pcie@fe260000";
        pcie2x1_intc = "/pcie@fe260000/legacy-interrupt-controller";
        sdmmc0 = "/dwmmc@fe2b0000";
        sdmmc1 = "/dwmmc@fe2c0000";
        sfc = "/sfc@fe300000";
        sdhci = "/sdhci@fe310000";
        nandc0 = "/nandc@fe330000";
        crypto = "/crypto@fe380000";
        rng = "/rng@fe388000";
        otp = "/otp@fe38c000";
        cpu_code = "/otp@fe38c000/cpu-code@2";
        otp_cpu_version = "/otp@fe38c000/cpu-version@8";
        mbist_vmin = "/otp@fe38c000/mbist-vmin@9";
        otp_id = "/otp@fe38c000/id@a";
        cpu_leakage = "/otp@fe38c000/cpu-leakage@1a";
        log_leakage = "/otp@fe38c000/log-leakage@1b";
        npu_leakage = "/otp@fe38c000/npu-leakage@1c";
        gpu_leakage = "/otp@fe38c000/gpu-leakage@1d";
        core_pvtm = "/otp@fe38c000/core-pvtm@2a";
        i2s0_8ch = "/i2s@fe400000";
        i2s1_8ch = "/i2s@fe410000";
        i2s2_2ch = "/i2s@fe420000";
        i2s3_2ch = "/i2s@fe430000";
        pdm = "/pdm@fe440000";
        vad = "/vad@fe450000";
        spdif_8ch = "/spdif@fe460000";
        audpwm = "/audpwm@fe470000";
        dig_acodec = "/codec-digital@fe478000";
        dmac0 = "/dmac@fe530000";
        dmac1 = "/dmac@fe550000";
        scr = "/rkscr@fe560000";
        can0 = "/can@fe570000";
        can1 = "/can@fe580000";
        can2 = "/can@fe590000";
        i2c1 = "/i2c@fe5a0000";
        gt1x = "/i2c@fe5a0000/gt1x@14";
        i2c2 = "/i2c@fe5b0000";
        gc2145 = "/i2c@fe5b0000/gc2145@3c";
        gc2145_out = "/i2c@fe5b0000/gc2145@3c/port/endpoint";
        ov5695 = "/i2c@fe5b0000/ov5695@36";
        ov5695_out = "/i2c@fe5b0000/ov5695@36/port/endpoint";
        gc8034 = "/i2c@fe5b0000/gc8034@37";
        gc8034_out = "/i2c@fe5b0000/gc8034@37/port/endpoint";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mxc6655xa = "/i2c@fe5e0000/mxc6655xa@15";
        rktimer = "/timer@fe5f0000";
        wdt = "/watchdog@fe600000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
        uart1 = "/serial@fe650000";
        uart2 = "/serial@fe660000";
        uart3 = "/serial@fe670000";
        uart4 = "/serial@fe680000";
        uart5 = "/serial@fe690000";
        uart6 = "/serial@fe6a0000";
        uart7 = "/serial@fe6b0000";
        uart8 = "/serial@fe6c0000";
        uart9 = "/serial@fe6d0000";
        pwm4 = "/pwm@fe6e0000";
        pwm5 = "/pwm@fe6e0010";
        pwm6 = "/pwm@fe6e0020";
        pwm7 = "/pwm@fe6e0030";
        pwm8 = "/pwm@fe6f0000";
        pwm9 = "/pwm@fe6f0010";
        pwm10 = "/pwm@fe6f0020";
        pwm11 = "/pwm@fe6f0030";
        pwm12 = "/pwm@fe700000";
        pwm13 = "/pwm@fe700010";
        pwm14 = "/pwm@fe700020";
        pwm15 = "/pwm@fe700030";
        tsadc = "/tsadc@fe710000";
        saradc = "/saradc@fe720000";
        mailbox = "/mailbox@fe780000";
        combphy1_usq = "/phy@fe830000";
        combphy2_psq = "/phy@fe840000";
        mipi_dphy0 = "/mipi-dphy@fe850000";
        video_phy0 = "/video-phy@fe850000";
        mipi_dphy1 = "/mipi-dphy@fe860000";
        csi2_dphy_hw = "/csi2-dphy-hw@fe870000";
        csi2_dphy0 = "/csi2-dphy0";
        mipi_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1";
        mipi_in_ucam1 = "/csi2-dphy0/ports/port@0/endpoint@2";
        csidphy_out = "/csi2-dphy0/ports/port@1/endpoint@0";
        csi2_dphy1 = "/csi2-dphy1";
        csi2_dphy2 = "/csi2-dphy2";
        usb2phy0 = "/usb2-phy@fe8a0000";
        u2phy0_host = "/usb2-phy@fe8a0000/host-port";
        u2phy0_otg = "/usb2-phy@fe8a0000/otg-port";
        usb2phy1 = "/usb2-phy@fe8b0000";
        u2phy1_host = "/usb2-phy@fe8b0000/host-port";
        u2phy1_otg = "/usb2-phy@fe8b0000/otg-port";
        pinctrl = "/pinctrl";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        pcfg_pull_up = "/pinctrl/pcfg-pull-up";
        pcfg_pull_down = "/pinctrl/pcfg-pull-down";
        pcfg_pull_none = "/pinctrl/pcfg-pull-none";
        pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
        pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
        pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
        pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
        pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
        pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
        pcfg_output_low = "/pinctrl/pcfg-output-low";
        acodec_pins = "/pinctrl/acodec/acodec-pins";
        cam_clkout0 = "/pinctrl/cam/cam-clkout0";
        camera_pwr = "/pinctrl/cam/camera-pwr";
        can0m1_pins = "/pinctrl/can0/can0m1-pins";
        can1m1_pins = "/pinctrl/can1/can1m1-pins";
        can2m1_pins = "/pinctrl/can2/can2m1-pins";
        cif_clk = "/pinctrl/cif/cif-clk";
        cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
        cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
        clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
        ebc_pins = "/pinctrl/ebc/ebc-pins";
        gmac1m0_miim = "/pinctrl/gmac1/gmac1m0-miim";
        gmac1m0_rx_bus2 = "/pinctrl/gmac1/gmac1m0-rx-bus2";
        hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec";
        hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl";
        hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda";
        i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
        i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
        i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer";
        i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
        i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
        i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
        i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx";
        i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx";
        i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
        i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
        i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx";
        i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx";
        i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi";
        i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo";
        i2s3m1_lrck = "/pinctrl/i2s3/i2s3m1-lrck";
        i2s3m1_mclk = "/pinctrl/i2s3/i2s3m1-mclk";
        i2s3m1_sclk = "/pinctrl/i2s3/i2s3m1-sclk";
        i2s3m1_sdi = "/pinctrl/i2s3/i2s3m1-sdi";
        i2s3m1_sdo = "/pinctrl/i2s3/i2s3m1-sdo";
        lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl";
        pdmm1_clk1 = "/pinctrl/pdm/pdmm1-clk1";
        pdmm1_sdi1 = "/pinctrl/pdm/pdmm1-sdi1";
        pdmm1_sdi2 = "/pinctrl/pdm/pdmm1-sdi2";
        pdmm1_sdi3 = "/pinctrl/pdm/pdmm1-sdi3";
        pmic_int = "/pinctrl/pmic/pmic_int";
        soc_slppin_gpio = "/pinctrl/pmic/soc_slppin_gpio";
        soc_slppin_slp = "/pinctrl/pmic/soc_slppin_slp";
        soc_slppin_rst = "/pinctrl/pmic/soc_slppin_rst";
        pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
        pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
        pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
        pwm3_pins = "/pinctrl/pwm3/pwm3-pins";
        pwm4_pins = "/pinctrl/pwm4/pwm4-pins";
        pwm5_pins = "/pinctrl/pwm5/pwm5-pins";
        pwm6_pins = "/pinctrl/pwm6/pwm6-pins";
        pwm7_pins = "/pinctrl/pwm7/pwm7-pins";
        pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
        pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
        pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
        pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
        pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
        pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
        pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
        pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
        scr_pins = "/pinctrl/scr/scr-pins";
        sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4";
        sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk";
        sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd";
        sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det";
        sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4";
        sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk";
        sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd";
        spdifm0_tx = "/pinctrl/spdif/spdifm0-tx";
        spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
        spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
        spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
        spi1m0_pins = "/pinctrl/spi1/spi1m0-pins";
        spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0";
        spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1";
        spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
        spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
        spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
        spi3m0_pins = "/pinctrl/spi3/spi3m0-pins";
        spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0";
        spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1";
        tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg";
        uart0_xfer = "/pinctrl/uart0/uart0-xfer";
        uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer";
        uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn";
        uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn";
        uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
        uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
        uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
        uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
        uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer";
        uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer";
        uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
        uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer";
        spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins";
        spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins";
        spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins";
        spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins";
        gmac1m0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-tx-bus2-level3";
        gmac1m0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-rgmii-bus-level3";
        gmac1m0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m0-rgmii-clk-level2";
        tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func";
        mxc6655xa_irq_gpio = "/pinctrl/mxc6655xa/mxc6655xa_irq_gpio";
        touch_gpio = "/pinctrl/touch/touch-gpio";
        wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h";
        vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en";
        vcc5v0_otg_en = "/pinctrl/usb/vcc5v0-otg-en";
        uart8_gpios = "/pinctrl/wireless-bluetooth/uart8-gpios";
        uart1_gpios = "/pinctrl/wireless-bluetooth/uart1-gpios";
        hp_det = "/pinctrl/headphone/hp-det";
        lcd0_rst_gpio = "/pinctrl/lcd0/lcd-rst-gpio";
        lcd1_rst_gpio = "/pinctrl/lcd1/lcd1-rst-gpio";
        wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq";
        dis_ctl = "/pinctrl/fddis_ctr/dis-ctl";
        adc_keys = "/adc-keys";
        audiopwmout_diff = "/audiopwmout-diff";
        master = "/audiopwmout-diff/simple-audio-card,codec";
        backlight = "/backlight";
        backlight1 = "/backlight1";
        dc_12v = "/dc-12v";
        hdmi_sound = "/hdmi-sound";
        pdmics = "/dummy-codec";
        pdm_mic_array = "/pdm-mic-array";
        rk809_sound = "/rk809-sound";
        spdif_out = "/spdif-out";
        vad_sound = "/vad-sound";
        vcc3v3_sys = "/vcc3v3-sys";
        vcc5v0_sys = "/vcc5v0-sys";
        vcc5v0_host = "/vcc5v0-host-regulator";
        vcc5v0_otg = "/vcc5v0-otg-regulator";
        vcc3v3_lcd0_n = "/vcc3v3-lcd0-n";
        vcc3v3_lcd1_n = "/vcc3v3-lcd1-n";
        sdio_pwrseq = "/sdio-pwrseq";
        wireless_wlan = "/wireless-wlan";
        wireless_bluetooth = "/wireless-bluetooth";
        rk_headset = "/rk-headset";
        vcc3v3_vga = "/vcc3v3-vga";
        vcc_camera = "/vcc-camera-regulator";
        chosen = "/chosen";
        debug = "/debug@fd904000";
        cspmu = "/cspmu@fd90c000";
    };
};
 



BOARD_TYPE_2.dts

Quote

/dts-v1/;
// magic:        0xd00dfeed
// totalsize:        0x1eb83 (125827)
// off_dt_struct:    0x38
// off_dt_strings:    0x1bc68
// off_mem_rsvmap:    0x28
// version:        17
// last_comp_version:    16
// boot_cpuid_phys:    0x0
// size_dt_strings:    0x2f1b
// size_dt_struct:    0x1bc30

/ {
    compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566";
    interrupt-parent = <0x00000001>;
    #address-cells = <0x00000002>;
    #size-cells = <0x00000002>;
    model = "Rockchip RK3566 EVB3 DDR3 V10 Board";
    ddr_timing {
        compatible = "rockchip,ddr-timing";
        ddr2_speed_bin = <0x00000000>;
        ddr3_speed_bin = <0x00000015>;
        ddr4_speed_bin = <0x0000000c>;
        pd_idle = <0x0000000d>;
        sr_idle = <0x0000005d>;
        sr_mc_gate_idle = <0x00000000>;
        srpd_lite_idle = <0x00000000>;
        standby_idle = <0x00000000>;
        auto_pd_dis_freq = <0x0000042a>;
        auto_sr_dis_freq = <0x00000320>;
        ddr2_dll_dis_freq = <0x0000012c>;
        ddr3_dll_dis_freq = <0x0000012c>;
        ddr4_dll_dis_freq = <0x00000271>;
        phy_dll_dis_freq = <0x00000190>;
        ddr2_odt_dis_freq = <0x00000064>;
        phy_ddr2_odt_dis_freq = <0x00000064>;
        ddr2_drv = <0x00000002>;
        ddr2_odt = <0x00000040>;
        phy_ddr2_ca_drv = <0x00000000>;
        phy_ddr2_ck_drv = <0x00000000>;
        phy_ddr2_dq_drv = <0x00000000>;
        phy_ddr2_odt = <0x00000000>;
        ddr3_odt_dis_freq = <0x0000014d>;
        phy_ddr3_odt_dis_freq = <0x0000014d>;
        ddr3_drv = <0x00000002>;
        ddr3_odt = <0x00000040>;
        phy_ddr3_ca_drv = <0x00000000>;
        phy_ddr3_ck_drv = <0x00000000>;
        phy_ddr3_dq_drv = <0x00000000>;
        phy_ddr3_odt = <0x00000000>;
        phy_lpddr2_odt_dis_freq = <0x0000014d>;
        lpddr2_drv = <0x00000002>;
        phy_lpddr2_ca_drv = <0x00000000>;
        phy_lpddr2_ck_drv = <0x00000000>;
        phy_lpddr2_dq_drv = <0x00000000>;
        phy_lpddr2_odt = <0x00000000>;
        lpddr3_odt_dis_freq = <0x0000014d>;
        phy_lpddr3_odt_dis_freq = <0x0000014d>;
        lpddr3_drv = <0x00000001>;
        lpddr3_odt = <0x00000002>;
        phy_lpddr3_ca_drv = <0x00000000>;
        phy_lpddr3_ck_drv = <0x00000000>;
        phy_lpddr3_dq_drv = <0x00000000>;
        phy_lpddr3_odt = <0x00000000>;
        lpddr4_odt_dis_freq = <0x0000014d>;
        phy_lpddr4_odt_dis_freq = <0x0000014d>;
        lpddr4_drv = <0x00000030>;
        lpddr4_dq_odt = <0x00000001>;
        lpddr4_ca_odt = <0x00000000>;
        phy_lpddr4_ca_drv = <0x00000000>;
        phy_lpddr4_ck_cs_drv = <0x00000000>;
        phy_lpddr4_dq_drv = <0x00000000>;
        phy_lpddr4_odt = <0x00000000>;
        ddr4_odt_dis_freq = <0x00000271>;
        phy_ddr4_odt_dis_freq = <0x00000271>;
        ddr4_drv = <0x00000000>;
        ddr4_odt = <0x00000200>;
        phy_ddr4_ca_drv = <0x00000000>;
        phy_ddr4_ck_drv = <0x00000000>;
        phy_ddr4_dq_drv = <0x00000000>;
        phy_ddr4_odt = <0x00000000>;
        phandle = <0x000000a8>;
    };
    aliases {
        csi2dphy0 = "/csi2-dphy0";
        csi2dphy1 = "/csi2-dphy1";
        csi2dphy2 = "/csi2-dphy2";
        dsi0 = "/dsi@fe060000";
        dsi1 = "/dsi@fe070000";
        ethernet1 = "/ethernet@fe010000";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        i2c0 = "/i2c@fdd40000";
        i2c1 = "/i2c@fe5a0000";
        i2c2 = "/i2c@fe5b0000";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mmc0 = "/dwmmc@fe2b0000";
        mmc1 = "/dwmmc@fe2c0000";
        mmc2 = "/sdhci@fe310000";
        mmc3 = "/dwmmc@fe000000";
        serial0 = "/serial@fdd50000";
        serial1 = "/serial@fe650000";
        serial2 = "/serial@fe660000";
        serial3 = "/serial@fe670000";
        serial4 = "/serial@fe680000";
        serial5 = "/serial@fe690000";
        serial6 = "/serial@fe6a0000";
        serial7 = "/serial@fe6b0000";
        serial8 = "/serial@fe6c0000";
        serial9 = "/serial@fe6d0000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
    };
    cpus {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000000>;
        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000000>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            #cooling-cells = <0x00000002>;
            dynamic-power-coefficient = <0x000000bb>;
            cpu-supply = <0x00000005>;
            phandle = <0x00000009>;
            power-model {
                compatible = "simple-power-model";
                leakage-range = <0x0000000a 0x00000028>;
                ls = <0xffffdc14 0x000018d8 0x00000000>;
                static-coefficient = <0x000186a0>;
                ts = <0x0001476e 0x0003263d 0xffffef34 0x00000047>;
                thermal-zone = "soc-thermal";
            };
        };
        cpu@100 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000100>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000a>;
        };
        cpu@200 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000200>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000b>;
        };
        cpu@300 {
            device_type = "cpu";
            compatible = "arm,cortex-a55";
            reg = <0x00000000 0x00000300>;
            enable-method = "psci";
            clocks = <0x00000002 0x00000000>;
            operating-points-v2 = <0x00000003>;
            cpu-idle-states = <0x00000004>;
            phandle = <0x0000000c>;
        };
        idle-states {
            entry-method = "psci";
            cpu-sleep {
                compatible = "arm,idle-state";
                local-timer-stop;
                arm,psci-suspend-param = <0x00010000>;
                entry-latency-us = <0x00000064>;
                exit-latency-us = <0x00000078>;
                min-residency-us = <0x000003e8>;
                phandle = <0x00000004>;
            };
        };
    };
    cpu0-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000006 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-freq = <0x000639c0>;
        rockchip,pvtm-volt = <0x000dbba0>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        rockchip,pvtm-sample-time = <0x000003e8>;
        rockchip,pvtm-number = <0x0000000a>;
        rockchip,pvtm-error = <0x000003e8>;
        rockchip,pvtm-ref-temp = <0x00000028>;
        rockchip,pvtm-temp-prop = <0x0000001a 0x0000001a>;
        rockchip,thermal-zone = "soc-thermal";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000648 0x000124f8>;
        phandle = <0x00000003>;
        opp-408000000 {
            opp-hz = <0x00000000 0x18519600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-816000000 {
            opp-hz = <0x00000000 0x30a32c00>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            opp-suspend;
            status = "disabled";
        };
        opp-1104000000 {
            opp-hz = <0x00000000 0x41cdb400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
            status = "disabled";
        };
        opp-1416000000 {
            opp-hz = <0x00000000 0x54667200>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1608000000 {
            opp-hz = <0x00000000 0x5fd82200>;
            opp-microvolt = <0x000f4240 0x000f4240 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
        opp-1800000000 {
            opp-hz = <0x00000000 0x6b49d200>;
            opp-microvolt = <0x00100590 0x00100590 0x00118c30>;
            clock-latency-ns = <0x00009c40>;
        };
    };
    arm-pmu {
        compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
        interrupts = <0x00000000 0x000000e4 0x00000004 0x00000000 0x000000e5 0x00000004 0x00000000 0x000000e6 0x00000004 0x00000000 0x000000e7 0x00000004>;
        interrupt-affinity = <0x00000009 0x0000000a 0x0000000b 0x0000000c>;
    };
    cpuinfo {
        compatible = "rockchip,cpuinfo";
        nvmem-cells = <0x0000000d 0x0000000e 0x0000000f>;
        nvmem-cell-names = "id", "cpu-version", "cpu-code";
    };
    display-subsystem {
        compatible = "rockchip,display-subsystem";
        memory-region = <0x00000010 0x00000011>;
        memory-region-names = "drm-logo", "drm-cubic-lut";
        ports = <0x00000012>;
        devfreq = <0x00000013>;
        phandle = <0x00000134>;
        route {
            route-dsi0 {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000014>;
                phandle = <0x00000135>;
            };
            route-dsi1 {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000015>;
                phandle = <0x00000136>;
            };
            route-edp {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000016>;
                phandle = <0x00000137>;
            };
            route-hdmi {
                status = "okay";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000017>;
                phandle = <0x00000138>;
            };
            route-lvds {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000018>;
                phandle = <0x00000139>;
            };
            route-rgb {
                status = "disabled";
                logo,uboot = "logo.bmp";
                logo,kernel = "logo_kernel.bmp";
                logo,mode = "center";
                charge_logo,mode = "center";
                connect = <0x00000019>;
                phandle = <0x0000013a>;
            };
        };
    };
    firmware {
        optee {
            compatible = "linaro,optee-tz";
            method = "smc";
            phandle = <0x0000013b>;
        };
        scmi {
            compatible = "arm,scmi-smc";
            shmem = <0x0000001a>;
            arm,smc-id = <0x82000010>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x0000013c>;
            protocol@14 {
                reg = <0x00000014>;
                #clock-cells = <0x00000001>;
                rockchip,clk-init = "Tfr";
                phandle = <0x00000002>;
            };
        };
        sdei {
            compatible = "arm,sdei-1.0";
            method = "smc";
            phandle = <0x0000013d>;
        };
    };
    mpp-srv {
        compatible = "rockchip,mpp-service";
        rockchip,taskqueue-count = <0x00000006>;
        rockchip,resetgroup-count = <0x00000006>;
        status = "okay";
        phandle = <0x00000067>;
    };
    psci {
        compatible = "arm,psci-1.0";
        method = "smc";
    };
    reserved-memory {
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        phandle = <0x0000013e>;
        drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000010>;
        };
        drm-cubic-lut@00000000 {
            compatible = "rockchip,drm-cubic-lut";
            reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
            phandle = <0x00000011>;
        };
        linux,cma {
            compatible = "shared-dma-pool";
            inactive;
            reusable;
            reg = <0x00000000 0x10000000 0x00000000 0x00800000>;
            linux,cma-default;
        };
        ramoops@110000 {
            compatible = "ramoops";
            reg = <0x00000000 0x00110000 0x00000000 0x000f0000>;
            record-size = <0x00020000>;
            console-size = <0x00080000>;
            ftrace-size = <0x00000000>;
            pmsg-size = <0x00050000>;
            phandle = <0x0000013f>;
        };
    };
    rockchip-suspend {
        compatible = "rockchip,pm-rk3568";
        status = "okay";
        rockchip,sleep-debug-en = <0x00000001>;
        rockchip,sleep-mode-config = <0x000004e4>;
        rockchip,wakeup-config = <0x00002001>;
        rockchip,virtual-poweroff = <0x00000001>;
        phandle = <0x00000140>;
    };
    rockchip-system-monitor {
        compatible = "rockchip,system-monitor";
        rockchip,thermal-zone = "soc-thermal";
        phandle = <0x00000141>;
    };
    thermal-zones {
        phandle = <0x00000142>;
        soc-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            sustainable-power = <0x000005c3>;
            thermal-sensors = <0x0000001b 0x00000000>;
            phandle = <0x00000143>;
            trips {
                trip-point-0 {
                    temperature = <0x00011170>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x00000144>;
                };
                trip-point-1 {
                    temperature = <0x00014c08>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    phandle = <0x0000001c>;
                };
                soc-crit {
                    temperature = <0x0001c138>;
                    hysteresis = <0x000007d0>;
                    type = "critical";
                    phandle = <0x00000145>;
                };
            };
            cooling-maps {
                map0 {
                    trip = <0x0000001c>;
                    cooling-device = <0x00000009 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
                map1 {
                    trip = <0x0000001c>;
                    cooling-device = <0x0000001d 0xffffffff 0xffffffff>;
                    contribution = <0x00000400>;
                };
            };
        };
        gpu-thermal {
            polling-delay-passive = <0x00000014>;
            polling-delay = <0x000003e8>;
            thermal-sensors = <0x0000001b 0x00000001>;
            phandle = <0x00000146>;
        };
    };
    timer {
        compatible = "arm,armv8-timer";
        interrupts = <0x00000001 0x0000000d 0x00000f04 0x00000001 0x0000000e 0x00000f04 0x00000001 0x0000000b 0x00000f04 0x00000001 0x0000000a 0x00000f04>;
        arm,no-tick-in-suspend;
    };
    external-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "gmac1_clkin";
        #clock-cells = <0x00000000>;
        phandle = <0x00000147>;
    };
    xpcs-gmac1-clock {
        compatible = "fixed-clock";
        clock-frequency = <0x07735940>;
        clock-output-names = "clk_gmac1_xpcs_mii";
        #clock-cells = <0x00000000>;
        phandle = <0x00000148>;
    };
    i2s1-mclkin-rx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_rx";
        phandle = <0x00000149>;
    };
    i2s1-mclkin-tx {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s1_mclkin_tx";
        phandle = <0x0000014a>;
    };
    i2s2-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s2_mclkin";
        phandle = <0x0000014b>;
    };
    i2s3-mclkin {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x00bb8000>;
        clock-output-names = "i2s3_mclkin";
        phandle = <0x0000014c>;
    };
    mpll {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x2faf0800>;
        clock-output-names = "mpll";
        phandle = <0x0000014d>;
    };
    xin24m {
        compatible = "fixed-clock";
        #clock-cells = <0x00000000>;
        clock-frequency = <0x016e3600>;
        clock-output-names = "xin24m";
        phandle = <0x0000014e>;
    };
    xin32k {
        compatible = "fixed-clock";
        clock-frequency = <0x00008000>;
        clock-output-names = "xin32k";
        #clock-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000001e>;
        phandle = <0x0000014f>;
    };
    scmi-shmem@10f000 {
        compatible = "arm,scmi-shmem";
        reg = <0x00000000 0x0010f000 0x00000000 0x00000100>;
        phandle = <0x0000001a>;
    };
    sata@fc400000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc400000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000009b 0x0000001f 0x0000009c 0x0000001f 0x0000009d>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x0000005f 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000020 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000150>;
    };
    sata@fc800000 {
        compatible = "snps,dwc-ahci";
        reg = <0x00000000 0xfc800000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x000000a0 0x0000001f 0x000000a1 0x0000001f 0x000000a2>;
        clock-names = "sata", "pmalive", "rxoob";
        interrupts = <0x00000000 0x00000060 0x00000004>;
        interrupt-names = "hostc";
        phys = <0x00000022 0x00000001>;
        phy-names = "sata-phy";
        ports-implemented = <0x00000001>;
        power-domains = <0x00000021 0x0000000f>;
        status = "disabled";
        phandle = <0x00000151>;
    };
    usbdrd {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a6 0x0000001f 0x000000a7 0x0000001f 0x000000a5 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000152>;
        dwc3@fcc00000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfcc00000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000a9 0x00000004>;
            dr_mode = "host";
            phys = <0x00000023>;
            phy-names = "usb2-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000094>;
            reset-names = "usb3-otg";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            extcon = <0x00000024>;
            maximum-speed = "high-speed";
            snps,dis_u2_susphy_quirk;
            phandle = <0x00000153>;
        };
    };
    usbhost {
        compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
        clocks = <0x0000001f 0x000000a9 0x0000001f 0x000000aa 0x0000001f 0x000000a8 0x0000001f 0x0000007f>;
        clock-names = "ref_clk", "suspend_clk", "bus_clk", "pipe_clk";
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        status = "okay";
        phandle = <0x00000154>;
        dwc3@fd000000 {
            compatible = "snps,dwc3";
            reg = <0x00000000 0xfd000000 0x00000000 0x00400000>;
            interrupts = <0x00000000 0x000000aa 0x00000004>;
            dr_mode = "host";
            phys = <0x00000025 0x00000020 0x00000004>;
            phy-names = "usb2-phy", "usb3-phy";
            phy_type = "utmi_wide";
            power-domains = <0x00000021 0x0000000f>;
            resets = <0x0000001f 0x00000095>;
            reset-names = "usb3-host";
            snps,dis_enblslpm_quirk;
            snps,dis-u2-freeclk-exists-quirk;
            snps,dis-del-phy-power-chg-quirk;
            snps,dis-tx-ipgap-linecheck-quirk;
            snps,xhci-trb-ent-quirk;
            status = "okay";
            phandle = <0x00000155>;
        };
    };
    interrupt-controller@fd400000 {
        compatible = "arm,gic-v3";
        #interrupt-cells = <0x00000003>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        interrupt-controller;
        reg = <0x00000000 0xfd400000 0x00000000 0x00010000 0x00000000 0xfd460000 0x00000000 0x000c0000>;
        interrupts = <0x00000001 0x00000009 0x00000004>;
        phandle = <0x00000001>;
        interrupt-controller@fd440000 {
            compatible = "arm,gic-v3-its";
            msi-controller;
            #msi-cells = <0x00000001>;
            reg = <0x00000000 0xfd440000 0x00000000 0x00020000>;
            phandle = <0x000000ab>;
        };
    };
    usb@fd800000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd800000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000082 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000156>;
    };
    usb@fd840000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd840000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000083 0x00000004>;
        clocks = <0x0000001f 0x000000bd 0x0000001f 0x000000be 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000027>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000157>;
    };
    usb@fd880000 {
        compatible = "generic-ehci";
        reg = <0x00000000 0xfd880000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000085 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000158>;
    };
    usb@fd8c0000 {
        compatible = "generic-ohci";
        reg = <0x00000000 0xfd8c0000 0x00000000 0x00040000>;
        interrupts = <0x00000000 0x00000086 0x00000004>;
        clocks = <0x0000001f 0x000000bf 0x0000001f 0x000000c0 0x0000001f 0x000000bc 0x00000026>;
        clock-names = "usbhost", "arbiter", "pclk", "utmi";
        phys = <0x00000028>;
        phy-names = "usb2-phy";
        status = "disabled";
        phandle = <0x00000159>;
    };
    syscon@fda00000 {
        compatible = "rockchip,rk3568-xpcs", "syscon";
        reg = <0x00000000 0xfda00000 0x00000000 0x00200000>;
        status = "disabled";
        phandle = <0x0000015a>;
    };
    syscon@fdc20000 {
        compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc20000 0x00000000 0x00010000>;
        phandle = <0x00000033>;
        io-domains {
            compatible = "rockchip,rk3568-pmu-io-voltage-domain";
            status = "okay";
            pmuio1-supply = <0x00000029>;
            pmuio2-supply = <0x00000029>;
            vccio1-supply = <0x0000002a>;
            vccio3-supply = <0x0000002b>;
            vccio4-supply = <0x0000002c>;
            vccio5-supply = <0x0000002d>;
            vccio6-supply = <0x0000002c>;
            vccio7-supply = <0x0000002d>;
            phandle = <0x0000015b>;
        };
        reboot-mode {
            compatible = "syscon-reboot-mode";
            offset = <0x00000200>;
            mode-bootloader = <0x5242c301>;
            mode-charge = <0x5242c30b>;
            mode-fastboot = <0x5242c309>;
            mode-loader = <0x5242c301>;
            mode-normal = <0x5242c300>;
            mode-recovery = <0x5242c303>;
            mode-ums = <0x5242c30c>;
            mode-panic = <0x5242c307>;
            mode-watchdog = <0x5242c308>;
            phandle = <0x0000015c>;
        };
    };
    syscon@fdc50000 {
        compatible = "rockchip,rk3568-pipegrf", "syscon";
        reg = <0x00000000 0xfdc50000 0x00000000 0x00001000>;
        phandle = <0x00000104>;
    };
    syscon@fdc60000 {
        compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdc60000 0x00000000 0x00010000>;
        phandle = <0x00000032>;
        io-domains {
            compatible = "rockchip,rk3568-io-voltage-domain";
            status = "disabled";
            phandle = <0x0000015d>;
        };
        lvds {
            compatible = "rockchip,rk3568-lvds";
            phys = <0x0000002e>;
            phy-names = "phy";
            status = "disabled";
            phandle = <0x0000015e>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@1 {
                        reg = <0x00000001>;
                        remote-endpoint = <0x00000018>;
                        status = "disabled";
                        phandle = <0x0000008b>;
                    };
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x0000002f>;
                        status = "disabled";
                        phandle = <0x0000008c>;
                    };
                };
            };
        };
        rgb {
            compatible = "rockchip,rk3568-rgb";
            pinctrl-names = "default";
            pinctrl-0 = <0x00000030>;
            status = "disabled";
            phandle = <0x0000015f>;
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    endpoint@2 {
                        reg = <0x00000002>;
                        remote-endpoint = <0x00000019>;
                        status = "disabled";
                        phandle = <0x0000008d>;
                    };
                };
            };
        };
    };
    syscon@fdc70000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc70000 0x00000000 0x00001000>;
        phandle = <0x00000160>;
    };
    syscon@fdc80000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc80000 0x00000000 0x00001000>;
        phandle = <0x00000105>;
    };
    syscon@fdc90000 {
        compatible = "rockchip,pipe-phy-grf", "syscon";
        reg = <0x00000000 0xfdc90000 0x00000000 0x00001000>;
        phandle = <0x00000106>;
    };
    syscon@fdca0000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca0000 0x00000000 0x00008000>;
        phandle = <0x0000010b>;
    };
    syscon@fdca8000 {
        compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
        reg = <0x00000000 0xfdca8000 0x00000000 0x00008000>;
        phandle = <0x0000010e>;
    };
    edp-phy@fdcb0000 {
        compatible = "rockchip,rk3568-edp-phy";
        reg = <0x00000000 0xfdcb0000 0x00000000 0x00008000>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x00000192>;
        clock-names = "refclk", "pclk";
        resets = <0x0000001f 0x000001d6>;
        reset-names = "apb";
        #phy-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000000a4>;
    };
    sram@fdcc0000 {
        compatible = "mmio-sram";
        reg = <0x00000000 0xfdcc0000 0x00000000 0x0000b000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges = <0x00000000 0x00000000 0xfdcc0000 0x0000b000>;
        phandle = <0x00000161>;
        rkvdec-sram@0 {
            reg = <0x00000000 0x0000b000>;
            phandle = <0x0000006f>;
        };
    };
    clock-controller@fdd00000 {
        compatible = "rockchip,rk3568-pmucru";
        reg = <0x00000000 0xfdd00000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        rockchip,pmugrf = <0x00000033>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000032>;
        assigned-clock-parents = <0x00000031 0x00000005>;
        phandle = <0x00000031>;
    };
    clock-controller@fdd20000 {
        compatible = "rockchip,rk3568-cru";
        reg = <0x00000000 0xfdd20000 0x00000000 0x00001000>;
        rockchip,grf = <0x00000032>;
        #clock-cells = <0x00000001>;
        #reset-cells = <0x00000001>;
        assigned-clocks = <0x00000031 0x00000005 0x0000001f 0x00000106 0x0000001f 0x0000010b 0x00000031 0x00000001 0x00000031 0x0000002b 0x0000001f 0x00000003 0x0000001f 0x0000019b 0x0000001f 0x00000009 0x0000001f 0x0000019c 0x0000001f 0x0000019d 0x0000001f 0x000001a1 0x0000001f 0x0000019e 0x0000001f 0x0000019f 0x0000001f 0x000001a0 0x0000001f 0x00000004 0x0000001f 0x0000010d 0x0000001f 0x0000010e 0x0000001f 0x00000173 0x0000001f 0x00000174 0x0000001f 0x00000175 0x0000001f 0x00000176 0x0000001f 0x000000c9 0x0000001f 0x000000ca 0x0000001f 0x00000006 0x0000001f 0x0000007e 0x0000001f 0x0000007f 0x0000001f 0x0000003d 0x0000001f 0x00000041 0x0000001f 0x00000045 0x0000001f 0x00000049 0x0000001f 0x0000004d 0x0000001f 0x0000004d 0x0000001f 0x00000055 0x0000001f 0x00000051 0x0000001f 0x0000005d 0x0000001f 0x000000dd>;
        assigned-clock-rates = <0x00008000 0x11e1a300 0x11e1a300 0x0bebc200 0x05f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0x0ee6b280 0x07735940 0x05f5e100 0x03b9aca0 0x02faf080 0x017d7840 0x46cf7100 0x08f0d180 0x05f5e100 0x1dcd6500 0x17d78400 0x08f0d180 0x05f5e100 0x11e1a300 0x08f0d180 0x47868c00 0x17d78400 0x05f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>;
        assigned-clock-parents = <0x00000031 0x00000008 0x0000001f 0x00000004 0x0000001f 0x00000004>;
        phandle = <0x0000001f>;
    };
    i2c@fdd40000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfdd40000 0x00000000 0x00001000>;
        clocks = <0x00000031 0x00000007 0x00000031 0x0000002d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002e 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000034>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000162>;
        pmic@20 {
            compatible = "rockchip,rk809";
            reg = <0x00000020>;
            interrupt-parent = <0x00000035>;
            interrupts = <0x00000003 0x00000008>;
            pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
            pinctrl-0 = <0x00000036>;
            pinctrl-1 = <0x00000037 0x00000038>;
            pinctrl-2 = <0x00000039 0x0000003a>;
            pinctrl-3 = <0x00000039 0x0000003b>;
            rockchip,system-power-controller;
            wakeup-source;
            #clock-cells = <0x00000001>;
            clock-output-names = "rk808-clkout1", "rk808-clkout2";
            pmic-reset-func = <0x00000000>;
            not-save-power-en = <0x00000001>;
            vcc1-supply = <0x0000003c>;
            vcc2-supply = <0x0000003c>;
            vcc3-supply = <0x0000003c>;
            vcc4-supply = <0x0000003c>;
            vcc5-supply = <0x0000003c>;
            vcc6-supply = <0x0000003c>;
            vcc7-supply = <0x0000003c>;
            vcc8-supply = <0x0000003c>;
            vcc9-supply = <0x0000003c>;
            phandle = <0x0000012c>;
            pwrkey {
                status = "okay";
            };
            pinctrl_rk8xx {
                gpio-controller;
                #gpio-cells = <0x00000002>;
                phandle = <0x00000163>;
                rk817_slppin_null {
                    pins = "gpio_slp";
                    function = "pin_fun0";
                    phandle = <0x00000164>;
                };
                rk817_slppin_slp {
                    pins = "gpio_slp";
                    function = "pin_fun1";
                    phandle = <0x00000038>;
                };
                rk817_slppin_pwrdn {
                    pins = "gpio_slp";
                    function = "pin_fun2";
                    phandle = <0x0000003a>;
                };
                rk817_slppin_rst {
                    pins = "gpio_slp";
                    function = "pin_fun3";
                    phandle = <0x0000003b>;
                };
            };
            regulators {
                DCDC_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_logic";
                    phandle = <0x00000062>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_gpu";
                    phandle = <0x00000064>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vcc_ddr";
                    phandle = <0x00000165>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                    };
                };
                DCDC_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x0007a120>;
                    regulator-max-microvolt = <0x00149970>;
                    regulator-init-microvolt = <0x000dbba0>;
                    regulator-ramp-delay = <0x00001771>;
                    regulator-initial-mode = <0x00000002>;
                    regulator-name = "vdd_npu";
                    phandle = <0x0000005f>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG1 {
                    regulator-boot-on;
                    regulator-always-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_image";
                    phandle = <0x00000166>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda_0v9";
                    phandle = <0x00000167>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG3 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x000dbba0>;
                    regulator-max-microvolt = <0x000dbba0>;
                    regulator-name = "vdda0v9_pmu";
                    phandle = <0x00000168>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x000dbba0>;
                    };
                };
                LDO_REG4 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_acodec";
                    phandle = <0x0000002a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vccio_sd";
                    phandle = <0x0000002b>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG6 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x00325aa0>;
                    regulator-max-microvolt = <0x00325aa0>;
                    regulator-name = "vcc3v3_pmu";
                    phandle = <0x00000029>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x00325aa0>;
                    };
                };
                LDO_REG7 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca_1v8";
                    phandle = <0x00000103>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                LDO_REG8 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_pmu";
                    phandle = <0x00000169>;
                    regulator-state-mem {
                        regulator-on-in-suspend;
                        regulator-suspend-microvolt = <0x001b7740>;
                    };
                };
                LDO_REG9 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcca1v8_image";
                    phandle = <0x0000016a>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                DCDC_REG5 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-min-microvolt = <0x001b7740>;
                    regulator-max-microvolt = <0x001b7740>;
                    regulator-name = "vcc_1v8";
                    phandle = <0x0000002c>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG1 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc_3v3";
                    phandle = <0x0000002d>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
                SWITCH_REG2 {
                    regulator-always-on;
                    regulator-boot-on;
                    regulator-name = "vcc3v3_sd";
                    phandle = <0x000000ac>;
                    regulator-state-mem {
                        regulator-off-in-suspend;
                    };
                };
            };
            codec {
                #sound-dai-cells = <0x00000000>;
                compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
                clocks = <0x0000001f 0x000001a4>;
                clock-names = "mclk";
                assigned-clocks = <0x0000001f 0x000001a4 0x0000001f 0x000001a8>;
                assigned-clock-rates = <0x00bb8000>;
                assigned-clock-parents = <0x0000001f 0x00000054 0x0000001f 0x000001a4>;
                pinctrl-names = "default";
                pinctrl-0 = <0x0000003d>;
                hp-volume = <0x00000014>;
                spk-volume = <0x00000003>;
                mic-in-differential;
                status = "okay";
                phandle = <0x00000125>;
            };
        };
        tcs4526@10 {
            compatible = "tcs,tcs452x";
            reg = <0x00000010>;
            vin-supply = <0x0000003e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x00100590>;
            regulator-max-microvolt = <0x001535b0>;
            regulator-ramp-delay = <0x000008fc>;
            fcs,suspend-voltage-selector = <0x00000001>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x00000005>;
            regulator-state-mem {
                regulator-off-in-suspend;
            };
        };
    };
    serial@fdd50000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfdd50000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000074 0x00000004>;
        clocks = <0x00000031 0x0000000b 0x00000031 0x0000002c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000000 0x0000003f 0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000040>;
        status = "disabled";
        phandle = <0x0000016b>;
    };
    pwm@fdd70000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000041>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016c>;
    };
    pwm@fdd70010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000042>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016d>;
    };
    pwm@fdd70020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfdd70020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000043>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x0000016e>;
    };
    pwm@fdd70030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfdd70030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000052 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000044>;
        clocks = <0x00000031 0x0000000d 0x00000031 0x00000030>;
        clock-names = "pwm", "pclk";
        status = "okay";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x0000016f>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000bd 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000e5 0x00000066 0x000000e7 0x00000073 0x000000e8 0x00000072 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x000000a4 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000a4 0x0000008d 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
        ir_key4 {
            rockchip,usercode = <0x0000fe01>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000e6 0x0000009e 0x000000e9 0x00000067 0x000000e5 0x0000006c 0x000000ae 0x00000069 0x000000af 0x0000006a 0x000000ee 0x00000066 0x000000e7 0x00000073 0x000000ef 0x00000072 0x000000bf 0x00000074 0x000000be 0x00000071 0x000000b3 0x0000008b 0x000000ff 0x00000184 0x000000b1 0x00000002 0x000000f2 0x00000003 0x000000f3 0x00000004 0x000000b5 0x00000005 0x000000f6 0x00000006 0x000000f7 0x00000007 0x000000b9 0x00000008 0x000000fa 0x00000009 0x000000fb 0x0000000a 0x000000fe 0x0000000b 0x000000bd 0x0000000e 0x000000bc 0x000000b7 0x000000f0 0x000000ba 0x000000b4 0x0000019c 0x000000b8 0x0000001e 0x000000b0 0x00000197>;
        };
        ir_key5 {
            rockchip,usercode = <0x00007f80>;
            rockchip,key_table = <0x000000ec 0x000000e8 0x000000d8 0x0000009e 0x000000c7 0x00000067 0x000000bf 0x0000006c 0x000000c8 0x00000069 0x000000c6 0x0000006a 0x0000008c 0x00000066 0x00000078 0x00000073 0x00000076 0x00000072 0x0000007e 0x00000074 0x0000007c 0x0000008b 0x000000b7 0x00000184>;
        };
        ir_key6 {
            rockchip,usercode = <0x0000fd01>;
            rockchip,key_table = <0x00000031 0x000000e8 0x0000002f 0x0000009e 0x00000035 0x00000067 0x0000002d 0x0000006c 0x00000066 0x00000069 0x0000003e 0x0000006a 0x0000006a 0x00000066 0x0000005e 0x00000073 0x00000047 0x00000072 0x00000023 0x00000074 0x0000003a 0x00000184 0x0000000d 0x00000040>;
        };
    };
    power-management@fdd90000 {
        compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
        reg = <0x00000000 0xfdd90000 0x00000000 0x00001000>;
        phandle = <0x00000170>;
        power-controller {
            compatible = "rockchip,rk3568-power-controller";
            #power-domain-cells = <0x00000001>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "okay";
            phandle = <0x00000021>;
            pd_npu@6 {
                reg = <0x00000006>;
                clocks = <0x0000001f 0x00000027 0x0000001f 0x00000025 0x0000001f 0x00000026>;
                pm_qos = <0x00000045>;
            };
            pd_gpu@7 {
                reg = <0x00000007>;
                clocks = <0x0000001f 0x00000019 0x0000001f 0x0000001a>;
                pm_qos = <0x00000046>;
            };
            pd_vi@8 {
                reg = <0x00000008>;
                clocks = <0x0000001f 0x000000cc 0x0000001f 0x000000cd>;
                pm_qos = <0x00000047 0x00000048 0x00000049>;
            };
            pd_vo@9 {
                reg = <0x00000009>;
                clocks = <0x0000001f 0x000000da 0x0000001f 0x000000db 0x0000001f 0x000000dc>;
                pm_qos = <0x0000004a 0x0000004b 0x0000004c>;
            };
            pd_rga@10 {
                reg = <0x0000000a>;
                clocks = <0x0000001f 0x000000f1 0x0000001f 0x000000f2>;
                pm_qos = <0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052>;
            };
            pd_vpu@11 {
                reg = <0x0000000b>;
                clocks = <0x0000001f 0x000000ed>;
                pm_qos = <0x00000053>;
            };
            pd_rkvdec@13 {
                clocks = <0x0000001f 0x00000107>;
                reg = <0x0000000d>;
                pm_qos = <0x00000054>;
            };
            pd_rkvenc@14 {
                reg = <0x0000000e>;
                clocks = <0x0000001f 0x00000102>;
                pm_qos = <0x00000055 0x00000056 0x00000057>;
            };
            pd_pipe@15 {
                reg = <0x0000000f>;
                clocks = <0x0000001f 0x0000007f>;
                pm_qos = <0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c>;
            };
        };
    };
    pvtm@fde00000 {
        compatible = "rockchip,rk3568-core-pvtm";
        reg = <0x00000000 0xfde00000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@0 {
            reg = <0x00000000>;
            clocks = <0x0000001f 0x00000013 0x0000001f 0x000001c2>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x0000001a 0x0000001f 0x00000019>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    npu@fde40000 {
        compatible = "rockchip,rknpu";
        reg = <0x00000000 0xfde40000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        clocks = <0x00000002 0x00000002 0x0000001f 0x00000023 0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "scmi_clk", "clk", "aclk", "hclk";
        assigned-clocks = <0x0000001f 0x00000023>;
        assigned-clock-rates = <0x23c34600>;
        resets = <0x0000001f 0x0000002b 0x0000001f 0x0000002c>;
        reset-names = "srst_a", "srst_h";
        power-domains = <0x00000021 0x00000006>;
        operating-points-v2 = <0x0000005d>;
        iommus = <0x0000005e>;
        status = "okay";
        rknpu-supply = <0x0000005f>;
        phandle = <0x00000171>;
    };
    npu-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000060 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x000002bc 0x0000c350>;
        phandle = <0x0000005d>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000cf850 0x000cf850 0x000f4240>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000d59f8 0x000d59f8 0x000f4240>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x000e1d48 0x000e1d48 0x000f4240>;
        };
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000f4240 0x000f4240 0x000f4240>;
            status = "disabled";
        };
    };
    bus-npu {
        compatible = "rockchip,rk3568-bus";
        rockchip,busfreq-policy = "clkfreq";
        clocks = <0x00000002 0x00000002>;
        clock-names = "bus";
        operating-points-v2 = <0x00000061>;
        status = "okay";
        bus-supply = <0x00000062>;
        pvtm-supply = <0x00000005>;
        phandle = <0x00000172>;
    };
    bus-npu-opp-table {
        compatible = "operating-points-v2";
        opp-shared;
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x00000061>;
        opp-1000000000 {
            opp-hz = <0x00000000 0x3b9aca00>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
        opp-900000000 {
            opp-hz = <0x00000000 0x35a4e900>;
            opp-microvolt = <0x00000000>;
        };
    };
    iommu@fde4b000 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfde4b000 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x00000097 0x00000004>;
        interrupt-names = "rknpu_mmu";
        clocks = <0x0000001f 0x00000028 0x0000001f 0x00000029>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000006>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000005e>;
    };
    gpu@fde60000 {
        compatible = "arm,mali-bifrost";
        reg = <0x00000000 0xfde60000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000027 0x00000004 0x00000000 0x00000029 0x00000004 0x00000000 0x00000028 0x00000004>;
        interrupt-names = "GPU", "MMU", "JOB";
        upthreshold = <0x00000028>;
        downdifferential = <0x0000000a>;
        clocks = <0x00000002 0x00000001 0x0000001f 0x0000001b>;
        clock-names = "clk_mali", "clk_gpu";
        power-domains = <0x00000021 0x00000007>;
        #cooling-cells = <0x00000002>;
        operating-points-v2 = <0x00000063>;
        status = "okay";
        mali-supply = <0x00000064>;
        phandle = <0x0000001d>;
        power-model {
            compatible = "simple-power-model";
            leakage-range = <0x00000005 0x0000000f>;
            ls = <0xffffa23e 0x00005927 0x00000000>;
            static-coefficient = <0x000186a0>;
            dynamic-coefficient = <0x000003b9>;
            ts = <0xfffe56a6 0x0000f87a 0xfffffab5 0x00000014>;
            thermal-zone = "gpu-thermal";
            phandle = <0x00000173>;
        };
    };
    opp-table2 {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x00000065 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        phandle = <0x00000063>;
        opp-200000000 {
            opp-hz = <0x00000000 0x0bebc200>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-300000000 {
            opp-hz = <0x00000000 0x11e1a300>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-600000000 {
            opp-hz = <0x00000000 0x23c34600>;
            opp-microvolt = <0x000c96a8>;
        };
        opp-700000000 {
            opp-hz = <0x00000000 0x29b92700>;
            opp-microvolt = <0x000dbba0>;
        };
        opp-800000000 {
            opp-hz = <0x00000000 0x2faf0800>;
            opp-microvolt = <0x000e7ef0>;
        };
    };
    pvtm@fde80000 {
        compatible = "rockchip,rk3568-gpu-pvtm";
        reg = <0x00000000 0xfde80000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@1 {
            reg = <0x00000001>;
            clocks = <0x0000001f 0x0000001e 0x0000001f 0x0000001d>;
            clock-names = "clk", "pclk";
            resets = <0x0000001f 0x00000024 0x0000001f 0x00000023>;
            reset-names = "rts", "rst-p";
            thermal-zone = "gpu-thermal";
        };
    };
    pvtm@fde90000 {
        compatible = "rockchip,rk3568-npu-pvtm";
        reg = <0x00000000 0xfde90000 0x00000000 0x00000100>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pvtm@2 {
            reg = <0x00000002>;
            clocks = <0x0000001f 0x0000002b 0x0000001f 0x0000002a 0x0000001f 0x00000025>;
            clock-names = "clk", "pclk", "hclk";
            resets = <0x0000001f 0x0000002e 0x0000001f 0x0000002d>;
            reset-names = "rts", "rst-p";
            thermal-zone = "soc-thermal";
        };
    };
    vdpu@fdea0400 {
        compatible = "rockchip,vpu-decoder-v2";
        reg = <0x00000000 0xfdea0400 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        resets = <0x0000001f 0x0000011a 0x0000001f 0x0000011b>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000066>;
        power-domains = <0x00000021 0x0000000b>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000000>;
        rockchip,resetgroup-node = <0x00000000>;
        status = "okay";
        phandle = <0x00000174>;
    };
    iommu@fdea0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdea0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008a 0x00000004>;
        interrupt-names = "vdpu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000ee 0x0000001f 0x000000ef>;
        power-domains = <0x00000021 0x0000000b>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000066>;
    };
    rk_rga@fdeb0000 {
        compatible = "rockchip,rga2";
        reg = <0x00000000 0xfdeb0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000005a 0x00000004>;
        clocks = <0x0000001f 0x000000f3 0x0000001f 0x000000f4 0x0000001f 0x000000f5>;
        clock-names = "aclk_rga", "hclk_rga", "clk_rga";
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000175>;
    };
    ebc@fdec0000 {
        compatible = "rockchip,rk3568-ebc-tcon";
        reg = <0x00000000 0xfdec0000 0x00000000 0x00005000>;
        interrupts = <0x00000000 0x00000011 0x00000004>;
        clocks = <0x0000001f 0x000000f9 0x0000001f 0x000000fa>;
        clock-names = "hclk", "dclk";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,grf = <0x00000032>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000068>;
        status = "disabled";
        phandle = <0x00000176>;
    };
    jpegd@fded0000 {
        compatible = "rockchip,rkv-jpeg-decoder-v1";
        reg = <0x00000000 0xfded0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000003e 0x00000004>;
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012c 0x0000001f 0x0000012d>;
        reset-names = "video_a", "video_h";
        iommus = <0x00000069>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000001>;
        rockchip,resetgroup-node = <0x00000001>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000177>;
    };
    iommu@fded0480 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfded0480 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003d 0x00000004>;
        interrupt-names = "jpegd_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fb 0x0000001f 0x000000fc>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000069>;
    };
    vepu@fdee0000 {
        compatible = "rockchip,vpu-encoder-v2";
        reg = <0x00000000 0xfdee0000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x00000040 0x00000004>;
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        clock-names = "aclk_vcodec", "hclk_vcodec";
        rockchip,disable-auto-freq;
        resets = <0x0000001f 0x0000012e 0x0000001f 0x0000012f>;
        reset-names = "video_a", "video_h";
        iommus = <0x0000006a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000002>;
        rockchip,resetgroup-node = <0x00000002>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x00000178>;
    };
    iommu@fdee0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdee0800 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000003f 0x00000004>;
        interrupt-names = "vepu_mmu";
        clock-names = "aclk", "iface";
        clocks = <0x0000001f 0x000000fd 0x0000001f 0x000000fe>;
        power-domains = <0x00000021 0x0000000a>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006a>;
    };
    iep@fdef0000 {
        compatible = "rockchip,iep-v2";
        reg = <0x00000000 0xfdef0000 0x00000000 0x00000500>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7 0x0000001f 0x000000f8>;
        clock-names = "aclk", "hclk", "sclk";
        resets = <0x0000001f 0x00000127 0x0000001f 0x00000128 0x0000001f 0x00000129>;
        reset-names = "rst_a", "rst_h", "rst_s";
        power-domains = <0x00000021 0x0000000a>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000005>;
        rockchip,resetgroup-node = <0x00000005>;
        iommus = <0x0000006b>;
        status = "okay";
        phandle = <0x00000179>;
    };
    iommu@fdef0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdef0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000038 0x00000004>;
        interrupt-names = "iep_mmu";
        clocks = <0x0000001f 0x000000f6 0x0000001f 0x000000f7>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000a>;
        status = "okay";
        phandle = <0x0000006b>;
    };
    eink@fdf00000 {
        compatible = "rockchip,rk3568-eink-tcon";
        reg = <0x00000000 0xfdf00000 0x00000000 0x00000074>;
        interrupts = <0x00000000 0x000000b2 0x00000004>;
        clocks = <0x0000001f 0x000000ff 0x0000001f 0x00000100>;
        clock-names = "pclk", "hclk";
        status = "disabled";
        phandle = <0x0000017a>;
    };
    rkvenc@fdf40000 {
        compatible = "rockchip,rkv-encoder-v1";
        reg = <0x00000000 0xfdf40000 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000008c 0x00000004>;
        interrupt-names = "irq_enc";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104 0x0000001f 0x00000105>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40>;
        resets = <0x0000001f 0x00000133 0x0000001f 0x00000134 0x0000001f 0x00000135>;
        reset-names = "video_a", "video_h", "video_core";
        assigned-clocks = <0x0000001f 0x00000103 0x0000001f 0x00000105>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40>;
        iommus = <0x0000006c>;
        node-name = "rkvenc";
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000003>;
        rockchip,resetgroup-node = <0x00000003>;
        power-domains = <0x00000021 0x0000000e>;
        operating-points-v2 = <0x0000006d>;
        status = "okay";
        venc-supply = <0x00000062>;
        phandle = <0x0000017b>;
    };
    rkvenc-opp-table {
        compatible = "operating-points-v2";
        nvmem-cells = <0x00000007>;
        nvmem-cell-names = "pvtm";
        rockchip,pvtm-voltage-sel = <0x00000000 0x00014050 0x00000000 0x00014051 0x00016b48 0x00000001 0x00016b49 0x000186a0 0x00000002>;
        rockchip,pvtm-ch = <0x00000000 0x00000005>;
        phandle = <0x0000006d>;
        opp-297000000 {
            opp-hz = <0x00000000 0x11b3dc40>;
            opp-microvolt = <0x00000000>;
        };
        opp-400000000 {
            opp-hz = <0x00000000 0x17d78400>;
            opp-microvolt = <0x000e7ef0>;
            opp-microvolt-L0 = <0x000e7ef0>;
            opp-microvolt-L1 = <0x000e1d48>;
            opp-microvolt-L2 = <0x00000000>;
        };
    };
    iommu@fdf40f00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf40f00 0x00000000 0x00000040 0x00000000 0xfdf40f40 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000008d 0x00000004 0x00000000 0x0000008e 0x00000004>;
        interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
        clocks = <0x0000001f 0x00000103 0x0000001f 0x00000104>;
        clock-names = "aclk", "iface";
        rockchip,disable-mmu-reset;
        rockchip,enable-cmd-retry;
        #iommu-cells = <0x00000000>;
        power-domains = <0x00000021 0x0000000e>;
        status = "okay";
        phandle = <0x0000006c>;
    };
    rkvdec@fdf80200 {
        compatible = "rockchip,rkv-decoder-v2";
        reg = <0x00000000 0xfdf80200 0x00000000 0x00000400>;
        interrupts = <0x00000000 0x0000005b 0x00000004>;
        interrupt-names = "irq_dec";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core", "clk_hevc_cabac";
        rockchip,normal-rates = <0x11b3dc40 0x00000000 0x11b3dc40 0x11b3dc40 0x23c34600>;
        rockchip,advanced-rates = <0x179a7b00 0x00000000 0x179a7b00 0x179a7b00 0x23c34600>;
        rockchip,default-max-load = <0x001fe000>;
        resets = <0x0000001f 0x00000142 0x0000001f 0x00000143 0x0000001f 0x00000144 0x0000001f 0x00000145 0x0000001f 0x00000146>;
        assigned-clocks = <0x0000001f 0x00000108 0x0000001f 0x0000010a 0x0000001f 0x0000010b 0x0000001f 0x0000010c>;
        assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>;
        reset-names = "video_a", "video_h", "video_cabac", "video_core", "video_hevc_cabac";
        power-domains = <0x00000021 0x0000000d>;
        iommus = <0x0000006e>;
        rockchip,srv = <0x00000067>;
        rockchip,taskqueue-node = <0x00000004>;
        rockchip,resetgroup-node = <0x00000004>;
        rockchip,sram = <0x0000006f>;
        rockchip,rcb-iova = <0x10000000 0x00010000>;
        rockchip,rcb-min-width = <0x00000200>;
        status = "okay";
        phandle = <0x0000017c>;
    };
    iommu@fdf80800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdf80800 0x00000000 0x00000040 0x00000000 0xfdf80840 0x00000000 0x00000040>;
        interrupts = <0x00000000 0x0000005c 0x00000004>;
        interrupt-names = "rkvdec_mmu";
        clocks = <0x0000001f 0x00000108 0x0000001f 0x00000109>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x0000000d>;
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x0000006e>;
    };
    mipi-csi2@fdfb0000 {
        compatible = "rockchip,rk3568-mipi-csi2";
        reg = <0x00000000 0xfdfb0000 0x00000000 0x00010000>;
        reg-names = "csihost_regs";
        interrupts = <0x00000000 0x00000008 0x00000004 0x00000000 0x00000009 0x00000004>;
        interrupt-names = "csi-intr1", "csi-intr2";
        clocks = <0x0000001f 0x000000d5>;
        clock-names = "pclk_csi2host";
        resets = <0x0000001f 0x000000ff>;
        reset-names = "srst_csihost_p";
        status = "disabled";
        phandle = <0x0000017d>;
    };
    rkcif@fdfe0000 {
        compatible = "rockchip,rk3568-cif";
        reg = <0x00000000 0xfdfe0000 0x00000000 0x00008000>;
        reg-names = "cif_regs";
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif-intr";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf 0x0000001f 0x000000d0 0x0000001f 0x000000d1>;
        clock-names = "aclk_cif", "hclk_cif", "dclk_cif", "iclk_cif_g";
        resets = <0x0000001f 0x000000f7 0x0000001f 0x000000f8 0x0000001f 0x000000f9 0x0000001f 0x000000fb 0x0000001f 0x000000fa>;
        reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_p", "rst_cif_i";
        assigned-clocks = <0x0000001f 0x000000d0>;
        assigned-clock-rates = <0x11e1a300>;
        power-domains = <0x00000021 0x00000008>;
        rockchip,grf = <0x00000032>;
        iommus = <0x00000070>;
        status = "okay";
        phandle = <0x00000071>;
    };
    iommu@fdfe0800 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdfe0800 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000092 0x00000004>;
        interrupt-names = "cif_mmu";
        clocks = <0x0000001f 0x000000ce 0x0000001f 0x000000cf>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        rockchip,disable-mmu-reset;
        #iommu-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000070>;
    };
    rkcif_dvp {
        compatible = "rockchip,rkcif-dvp";
        rockchip,hw = <0x00000071>;
        status = "okay";
        phandle = <0x00000073>;
        port {
            endpoint {
                remote-endpoint = <0x00000072>;
                bus-width = <0x00000008>;
                vsync-active = <0x00000000>;
                hsync-active = <0x00000001>;
                phandle = <0x000000d3>;
            };
        };
    };
    rkcif_dvp_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000073>;
        status = "disabled";
        phandle = <0x0000017e>;
    };
    rkcif_mipi_lvds {
        compatible = "rockchip,rkcif-mipi-lvds";
        rockchip,hw = <0x00000071>;
        status = "disabled";
        phandle = <0x00000074>;
    };
    rkcif_mipi_lvds_sditf {
        compatible = "rockchip,rkcif-sditf";
        rockchip,cif = <0x00000074>;
        status = "disabled";
        phandle = <0x0000017f>;
    };
    rkisp@fdff0000 {
        compatible = "rockchip,rk3568-rkisp";
        reg = <0x00000000 0xfdff0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000039 0x00000004 0x00000000 0x0000003a 0x00000004 0x00000000 0x0000003c 0x00000004>;
        interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3 0x0000001f 0x000000d4>;
        clock-names = "aclk_isp", "hclk_isp", "clk_isp";
        resets = <0x0000001f 0x000000fd 0x0000001f 0x000000fc>;
        reset-names = "isp", "isp-h";
        rockchip,grf = <0x00000032>;
        power-domains = <0x00000021 0x00000008>;
        iommus = <0x00000075>;
        rockchip,iq-feature = <0x000003fb 0xf7fe67ff>;
        status = "okay";
        phandle = <0x00000076>;
    };
    iommu@fdff1a00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfdff1a00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000003b 0x00000004>;
        interrupt-names = "isp_mmu";
        clocks = <0x0000001f 0x000000d2 0x0000001f 0x000000d3>;
        clock-names = "aclk", "iface";
        power-domains = <0x00000021 0x00000008>;
        #iommu-cells = <0x00000000>;
        rockchip,disable-mmu-reset;
        status = "okay";
        phandle = <0x00000075>;
    };
    rkisp-vir0 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "okay";
        phandle = <0x00000180>;
        port {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            endpoint@0 {
                reg = <0x00000000>;
                remote-endpoint = <0x00000077>;
                phandle = <0x0000010a>;
            };
        };
    };
    rkisp-vir1 {
        compatible = "rockchip,rkisp-vir";
        rockchip,hw = <0x00000076>;
        status = "disabled";
        phandle = <0x00000181>;
    };
    ethernet@fe010000 {
        compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
        reg = <0x00000000 0xfe010000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000020 0x00000004 0x00000000 0x0000001d 0x00000004>;
        interrupt-names = "macirq", "eth_wake_irq";
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000186 0x0000001f 0x00000189 0x0000001f 0x00000189 0x0000001f 0x000000c7 0x0000001f 0x000000c3 0x0000001f 0x000000c4 0x0000001f 0x00000189 0x0000001f 0x000000c8 0x0000001f 0x000000ac>;
        clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref", "pclk_xpcs";
        resets = <0x0000001f 0x000000ec>;
        reset-names = "stmmaceth";
        snps,mixed-burst;
        snps,tso;
        snps,axi-config = <0x00000078>;
        snps,mtl-rx-config = <0x00000079>;
        snps,mtl-tx-config = <0x0000007a>;
        status = "okay";
        phy-mode = "rgmii";
        clock_in_out = "output";
        snps,reset-gpio = <0x0000007b 0x00000001 0x00000001>;
        snps,reset-active-low;
        snps,reset-delays-us = <0x00000000 0x00004e20 0x000186a0>;
        assigned-clocks = <0x0000001f 0x00000189 0x0000001f 0x00000186>;
        assigned-clock-parents = <0x0000001f 0x00000187 0x0000001f 0x000000c5>;
        assigned-clock-rates = <0x00000000 0x07735940>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080>;
        tx_delay = <0x00000041>;
        rx_delay = <0x0000002e>;
        phy-handle = <0x00000081>;
        phandle = <0x00000182>;
        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000183>;
            phy@0 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <0x00000000>;
                phandle = <0x00000081>;
            };
        };
        stmmac-axi-config {
            snps,wr_osr_lmt = <0x00000004>;
            snps,rd_osr_lmt = <0x00000008>;
            snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>;
            phandle = <0x00000078>;
        };
        rx-queues-config {
            snps,rx-queues-to-use = <0x00000001>;
            phandle = <0x00000079>;
            queue0 {
            };
        };
        tx-queues-config {
            snps,tx-queues-to-use = <0x00000001>;
            phandle = <0x0000007a>;
            queue0 {
            };
        };
    };
    vop@fe040000 {
        compatible = "rockchip,rk3568-vop";
        reg = <0x00000000 0xfe040000 0x00000000 0x00003000 0x00000000 0xfe044000 0x00000000 0x00001000>;
        reg-names = "regs", "gamma_lut";
        rockchip,grf = <0x00000032>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de 0x0000001f 0x000000df 0x0000001f 0x000000e0 0x0000001f 0x000000e1>;
        clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
        iommus = <0x00000082>;
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        assigned-clocks = <0x0000001f 0x000000df 0x0000001f 0x000000e0>;
        assigned-clock-parents = <0x00000031 0x00000002 0x0000001f 0x00000005>;
        support-multi-area;
        phandle = <0x00000184>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            phandle = <0x00000012>;
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                phandle = <0x00000185>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000083>;
                    phandle = <0x0000008f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000084>;
                    phandle = <0x00000015>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000085>;
                    phandle = <0x00000016>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x00000086>;
                    phandle = <0x00000017>;
                };
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                phandle = <0x00000186>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000087>;
                    phandle = <0x00000014>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000088>;
                    phandle = <0x00000098>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000089>;
                    phandle = <0x000000a5>;
                };
                endpoint@3 {
                    reg = <0x00000003>;
                    remote-endpoint = <0x0000008a>;
                    phandle = <0x000000a3>;
                };
                endpoint@4 {
                    reg = <0x00000004>;
                    remote-endpoint = <0x0000008b>;
                    phandle = <0x00000018>;
                };
            };
            port@2 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000002>;
                phandle = <0x00000187>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008c>;
                    phandle = <0x0000002f>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x0000008d>;
                    phandle = <0x00000019>;
                };
            };
        };
    };
    iommu@fe043e00 {
        compatible = "rockchip,iommu-v2";
        reg = <0x00000000 0xfe043e00 0x00000000 0x00000100 0x00000000 0xfe043f00 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000094 0x00000004>;
        interrupt-names = "vop_mmu";
        clocks = <0x0000001f 0x000000dd 0x0000001f 0x000000de>;
        clock-names = "aclk", "iface";
        #iommu-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000082>;
    };
    dsi@fe060000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe060000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000044 0x00000004>;
        clocks = <0x0000001f 0x000000e8 0x0000001f 0x000000da 0x0000008e>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000110>;
        reset-names = "apb";
        phys = <0x0000008e>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000188>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000189>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000008f>;
                    status = "disabled";
                    phandle = <0x00000083>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000014>;
                    status = "okay";
                    phandle = <0x00000087>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000090>;
                    phandle = <0x00000096>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x00000091>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x00000092>;
            reset-gpios = <0x00000093 0x00000005 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x00000094>;
            phandle = <0x0000018a>;
            display-timings {
                native-mode = <0x00000095>;
                phandle = <0x0000018b>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x00000095>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x00000096>;
                        phandle = <0x00000090>;
                    };
                };
            };
        };
    };
    dsi@fe070000 {
        compatible = "rockchip,rk3568-mipi-dsi";
        reg = <0x00000000 0xfe070000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000045 0x00000004>;
        clocks = <0x0000001f 0x000000e9 0x0000001f 0x000000da 0x00000097>;
        clock-names = "pclk", "hclk", "hs_clk";
        resets = <0x0000001f 0x00000111>;
        reset-names = "apb";
        phys = <0x00000097>;
        phy-names = "mipi_dphy";
        power-domains = <0x00000021 0x00000009>;
        rockchip,grf = <0x00000032>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000018c>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x0000018d>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000015>;
                    status = "disabled";
                    phandle = <0x00000084>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000098>;
                    status = "disabled";
                    phandle = <0x00000088>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint {
                    remote-endpoint = <0x00000099>;
                    phandle = <0x0000009f>;
                };
            };
        };
        panel@0 {
            status = "okay";
            compatible = "simple-panel-dsi";
            reg = <0x00000000>;
            backlight = <0x0000009a>;
            reset-delay-ms = <0x0000003c>;
            enable-delay-ms = <0x0000003c>;
            prepare-delay-ms = <0x0000003c>;
            unprepare-delay-ms = <0x0000003c>;
            disable-delay-ms = <0x0000003c>;
            dsi,flags = <0x00000a03>;
            dsi,format = <0x00000000>;
            dsi,lanes = <0x00000004>;
            panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29];
            panel-exit-sequence = <0x05000128 0x05000110>;
            power-supply = <0x0000009b>;
            reset-gpios = <0x0000009c 0x00000016 0x00000001>;
            pinctrl-names = "default";
            pinctrl-0 = <0x0000009d>;
            phandle = <0x0000018e>;
            display-timings {
                native-mode = <0x0000009e>;
                phandle = <0x0000018f>;
                timing0 {
                    clock-frequency = <0x07de2900>;
                    hactive = <0x00000438>;
                    vactive = <0x00000780>;
                    hfront-porch = <0x0000000f>;
                    hsync-len = <0x00000002>;
                    hback-porch = <0x0000001e>;
                    vfront-porch = <0x0000000f>;
                    vsync-len = <0x00000002>;
                    vback-porch = <0x0000000f>;
                    hsync-active = <0x00000000>;
                    vsync-active = <0x00000000>;
                    de-active = <0x00000000>;
                    pixelclk-active = <0x00000001>;
                    phandle = <0x0000009e>;
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@0 {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x0000009f>;
                        phandle = <0x00000099>;
                    };
                };
            };
        };
    };
    hdmi@fe0a0000 {
        compatible = "rockchip,rk3568-dw-hdmi";
        reg = <0x00000000 0xfe0a0000 0x00000000 0x00020000>;
        interrupts = <0x00000000 0x0000002d 0x00000004>;
        clocks = <0x0000001f 0x000000e6 0x0000001f 0x000000e7 0x0000001f 0x00000193 0x00000031 0x00000002 0x0000001f 0x000000de>;
        clock-names = "iahb", "isfr", "cec", "ref", "hclk";
        power-domains = <0x00000021 0x00000009>;
        reg-io-width = <0x00000004>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000a0 0x000000a1 0x000000a2>;
        status = "okay";
        rockchip,phy-table = <0x058834d4 0x00008009 0x00000000 0x00000270 0x09d5b340 0x0000800b 0x00000000 0x0000026d 0x0b1069a8 0x0000800b 0x00000000 0x000001ed 0x11b3dc40 0x0000800b 0x00000000 0x000001ad 0x2367b880 0x00008029 0x00000000 0x00000088 0x00000000 0x00000000 0x00000000 0x00000000>;
        phandle = <0x00000122>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000190>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000017>;
                    status = "okay";
                    phandle = <0x00000086>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a3>;
                    status = "disabled";
                    phandle = <0x0000008a>;
                };
            };
        };
    };
    edp@fe0c0000 {
        compatible = "rockchip,rk3568-edp";
        reg = <0x00000000 0xfe0c0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000012 0x00000004>;
        clocks = <0x00000031 0x00000029 0x0000001f 0x000000ea 0x0000001f 0x000000eb 0x0000001f 0x000000da>;
        clock-names = "dp", "pclk", "spdif", "hclk";
        resets = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        reset-names = "dp", "apb";
        phys = <0x000000a4>;
        phy-names = "dp";
        power-domains = <0x00000021 0x00000009>;
        status = "okay";
        hpd-gpios = <0x00000093 0x00000007 0x00000000>;
        phandle = <0x00000191>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                phandle = <0x00000192>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x00000016>;
                    status = "okay";
                    phandle = <0x00000085>;
                };
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x000000a5>;
                    status = "disabled";
                    phandle = <0x00000089>;
                };
            };
        };
    };
    qos@fe128000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe128000 0x00000000 0x00000020>;
        phandle = <0x00000046>;
    };
    qos@fe138080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138080 0x00000000 0x00000020>;
        phandle = <0x00000055>;
    };
    qos@fe138100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138100 0x00000000 0x00000020>;
        phandle = <0x00000056>;
    };
    qos@fe138180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe138180 0x00000000 0x00000020>;
        phandle = <0x00000057>;
    };
    qos@fe148000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148000 0x00000000 0x00000020>;
        phandle = <0x00000047>;
    };
    qos@fe148080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148080 0x00000000 0x00000020>;
        phandle = <0x00000048>;
    };
    qos@fe148100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe148100 0x00000000 0x00000020>;
        phandle = <0x00000049>;
    };
    qos@fe150000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe150000 0x00000000 0x00000020>;
        phandle = <0x00000053>;
    };
    qos@fe158000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158000 0x00000000 0x00000020>;
        phandle = <0x0000004d>;
    };
    qos@fe158100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158100 0x00000000 0x00000020>;
        phandle = <0x0000004e>;
    };
    qos@fe158180 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158180 0x00000000 0x00000020>;
        phandle = <0x0000004f>;
    };
    qos@fe158200 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158200 0x00000000 0x00000020>;
        phandle = <0x00000050>;
    };
    qos@fe158280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158280 0x00000000 0x00000020>;
        phandle = <0x00000051>;
    };
    qos@fe158300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe158300 0x00000000 0x00000020>;
        phandle = <0x00000052>;
    };
    qos@fe180000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe180000 0x00000000 0x00000020>;
        phandle = <0x00000045>;
    };
    qos@fe190000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190000 0x00000000 0x00000020>;
        phandle = <0x00000058>;
    };
    qos@fe190280 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190280 0x00000000 0x00000020>;
        phandle = <0x00000059>;
    };
    qos@fe190300 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190300 0x00000000 0x00000020>;
        phandle = <0x0000005a>;
    };
    qos@fe190380 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190380 0x00000000 0x00000020>;
        phandle = <0x0000005b>;
    };
    qos@fe190400 {
        compatible = "syscon";
        reg = <0x00000000 0xfe190400 0x00000000 0x00000020>;
        phandle = <0x0000005c>;
    };
    qos@fe198000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe198000 0x00000000 0x00000020>;
        phandle = <0x00000054>;
    };
    qos@fe1a8000 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8000 0x00000000 0x00000020>;
        phandle = <0x0000004a>;
    };
    qos@fe1a8080 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8080 0x00000000 0x00000020>;
        phandle = <0x0000004b>;
    };
    qos@fe1a8100 {
        compatible = "syscon";
        reg = <0x00000000 0xfe1a8100 0x00000000 0x00000020>;
        phandle = <0x0000004c>;
    };
    dwmmc@fe000000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe000000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000064 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000c1 0x0000001f 0x000000c2 0x0000001f 0x0000018e 0x0000001f 0x0000018f>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000eb>;
        reset-names = "reset";
        status = "disabled";
        phandle = <0x00000193>;
    };
    dfi@fe230000 {
        reg = <0x00000000 0xfe230000 0x00000000 0x00000400>;
        compatible = "rockchip,rk3568-dfi";
        rockchip,pmugrf = <0x00000033>;
        status = "disabled";
        phandle = <0x000000a6>;
    };
    dmc {
        compatible = "rockchip,rk3568-dmc";
        interrupts = <0x00000000 0x0000000a 0x00000004>;
        interrupt-names = "complete";
        devfreq-events = <0x000000a6>;
        clocks = <0x0000001f 0x000001a2>;
        clock-names = "dmc_clk";
        operating-points-v2 = <0x000000a7>;
        ddr_timing = <0x000000a8>;
        vop-bw-dmc-freq = <0x00000000 0x000001f9 0x0004f1a0 0x000001fa 0x0001869f 0x00080e80>;
        upthreshold = <0x00000028>;
        downdifferential = <0x00000014>;
        system-status-freq = <0x00000001 0x000be6e0 0x00000008 0x000be6e0 0x00000002 0x000be6e0 0x00000010 0x000be6e0 0x00010000 0x000be6e0 0x00001000 0x000be6e0 0x00004000 0x000be6e0 0x00002000 0x000be6e0 0x00000c00 0x000be6e0>;
        auto-min-freq = <0x0004f1a0>;
        auto-freq-en = <0x00000001>;
        #cooling-cells = <0x00000002>;
        status = "disabled";
        center-supply = <0x00000062>;
        phandle = <0x00000013>;
    };
    dmc-opp-table {
        compatible = "operating-points-v2";
        mbist-vmin = <0x000c96a8 0x000dbba0 0x000e7ef0>;
        nvmem-cells = <0x000000a9 0x00000007 0x00000008>;
        nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
        rockchip,temp-hysteresis = <0x00001388>;
        rockchip,low-temp = <0x00000000>;
        rockchip,low-temp-adjust-volt = <0x00000000 0x00000618 0x000061a8>;
        rockchip,leakage-voltage-sel = <0x00000001 0x00000050 0x00000000 0x00000051 0x000000fe 0x00000001>;
        phandle = <0x000000a7>;
        opp-324000000 {
            opp-hz = <0x00000000 0x134fd900>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-528000000 {
            opp-hz = <0x00000000 0x1f78a400>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-780000000 {
            opp-hz = <0x00000000 0x2e7ddb00>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
        opp-920000000 {
            opp-hz = <0x00000000 0x36d61600>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
            status = "disabled";
        };
        opp-1056000000 {
            opp-hz = <0x00000000 0x3ef14800>;
            opp-microvolt = <0x000dbba0>;
            opp-microvolt-L0 = <0x000dbba0>;
            opp-microvolt-L1 = <0x000cf850>;
        };
    };
    pcie@fe260000 {
        compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
        #address-cells = <0x00000003>;
        #size-cells = <0x00000002>;
        bus-range = <0x00000000 0x0000000f>;
        clocks = <0x0000001f 0x00000081 0x0000001f 0x00000082 0x0000001f 0x00000083 0x0000001f 0x00000084 0x0000001f 0x00000085>;
        clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
        device_type = "pci";
        interrupts = <0x00000000 0x0000004b 0x00000004 0x00000000 0x0000004a 0x00000004 0x00000000 0x00000049 0x00000004 0x00000000 0x00000048 0x00000004 0x00000000 0x00000047 0x00000004>;
        interrupt-names = "sys", "pmc", "msg", "legacy", "err";
        #interrupt-cells = <0x00000001>;
        interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
        interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x000000aa 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x000000aa 0x00000001 0x00000000 0x00000000 0x00000000 0x00000003 0x000000aa 0x00000002 0x00000000 0x00000000 0x00000000 0x00000004 0x000000aa 0x00000003>;
        linux,pci-domain = <0x00000000>;
        num-ib-windows = <0x00000006>;
        num-ob-windows = <0x00000002>;
        max-link-speed = <0x00000002>;
        msi-map = <0x00000000 0x000000ab 0x00000000 0x00001000>;
        num-lanes = <0x00000001>;
        phys = <0x00000022 0x00000002>;
        phy-names = "pcie-phy";
        power-domains = <0x00000021 0x0000000f>;
        ranges = <0x00000800 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00800000 0x81000000 0x00000000 0x00800000 0x00000003 0x00800000 0x00000000 0x00100000 0x83000000 0x00000000 0x00900000 0x00000003 0x00900000 0x00000000 0x3f700000>;
        reg = <0x00000003 0xc0000000 0x00000000 0x00400000 0x00000000 0xfe260000 0x00000000 0x00010000>;
        reg-names = "pcie-dbi", "pcie-apb";
        resets = <0x0000001f 0x000000a1>;
        reset-names = "pipe";
        status = "disabled";
        phandle = <0x00000194>;
        legacy-interrupt-controller {
            interrupt-controller;
            #address-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-parent = <0x00000001>;
            interrupts = <0x00000000 0x00000048 0x00000001>;
            phandle = <0x000000aa>;
        };
    };
    dwmmc@fe2b0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2b0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000062 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b0 0x0000001f 0x000000b1 0x0000001f 0x0000018a 0x0000001f 0x0000018b>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d4>;
        reset-names = "reset";
        status = "okay";
        supports-sd;
        bus-width = <0x00000004>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        disable-wp;
        sd-uhs-sdr104;
        vmmc-supply = <0x000000ac>;
        vqmmc-supply = <0x0000002b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ad 0x000000ae 0x000000af 0x000000b0>;
        phandle = <0x00000195>;
    };
    dwmmc@fe2c0000 {
        compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
        reg = <0x00000000 0xfe2c0000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000063 0x00000004>;
        max-frequency = <0x08f0d180>;
        clocks = <0x0000001f 0x000000b2 0x0000001f 0x000000b3 0x0000001f 0x0000018c 0x0000001f 0x0000018d>;
        clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
        fifo-depth = <0x00000100>;
        resets = <0x0000001f 0x000000d6>;
        reset-names = "reset";
        status = "okay";
        supports-sdio;
        bus-width = <0x00000004>;
        disable-wp;
        cap-sd-highspeed;
        cap-sdio-irq;
        keep-power-in-suspend;
        mmc-pwrseq = <0x000000b1>;
        non-removable;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b2 0x000000b3 0x000000b4>;
        sd-uhs-sdr104;
        phandle = <0x00000196>;
    };
    sfc@fe300000 {
        compatible = "rockchip,sfc";
        reg = <0x00000000 0xfe300000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000065 0x00000004>;
        clocks = <0x0000001f 0x00000078 0x0000001f 0x00000076>;
        clock-names = "clk_sfc", "hclk_sfc";
        assigned-clocks = <0x0000001f 0x00000078>;
        assigned-clock-rates = <0x05f5e100>;
        status = "okay";
        phandle = <0x00000197>;
    };
    sdhci@fe310000 {
        compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
        reg = <0x00000000 0xfe310000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000013 0x00000004>;
        assigned-clocks = <0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        assigned-clock-rates = <0x0bebc200 0x016e3600>;
        clocks = <0x0000001f 0x0000007c 0x0000001f 0x0000007a 0x0000001f 0x00000079 0x0000001f 0x0000007b 0x0000001f 0x0000007d>;
        clock-names = "core", "bus", "axi", "block", "timer";
        status = "okay";
        bus-width = <0x00000008>;
        supports-emmc;
        non-removable;
        max-frequency = <0x0bebc200>;
        phandle = <0x00000198>;
    };
    nandc@fe330000 {
        compatible = "rockchip,rk-nandc-v9";
        reg = <0x00000000 0xfe330000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000046 0x00000004>;
        nandc_id = <0x00000000>;
        clocks = <0x0000001f 0x00000075 0x0000001f 0x00000074>;
        clock-names = "clk_nandc", "hclk_nandc";
        status = "okay";
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        phandle = <0x00000199>;
        nand@0 {
            reg = <0x00000000>;
            nand-bus-width = <0x00000008>;
            nand-ecc-mode = "hw";
            nand-ecc-strength = <0x00000010>;
            nand-ecc-step-size = <0x00000400>;
        };
    };
    crypto@fe380000 {
        compatible = "rockchip,rk3568-crypto";
        reg = <0x00000000 0xfe380000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000004 0x00000004>;
        clocks = <0x0000001f 0x0000006a 0x0000001f 0x0000006b 0x0000001f 0x0000006c 0x0000001f 0x0000006d>;
        clock-names = "aclk", "hclk", "sclk", "apb_pclk";
        assigned-clocks = <0x0000001f 0x0000006c>;
        assigned-clock-rates = <0x0bebc200>;
        resets = <0x0000001f 0x00000069>;
        reset-names = "crypto-rst";
        status = "disabled";
        phandle = <0x0000019a>;
    };
    rng@fe388000 {
        compatible = "rockchip,cryptov2-rng";
        reg = <0x00000000 0xfe388000 0x00000000 0x00002000>;
        clocks = <0x0000001f 0x00000070 0x0000001f 0x0000006f>;
        clock-names = "clk_trng", "hclk_trng";
        resets = <0x0000001f 0x0000006d>;
        reset-names = "reset";
        status = "okay";
        phandle = <0x0000019b>;
    };
    otp@fe38c000 {
        compatible = "rockchip,rk3568-otp";
        reg = <0x00000000 0xfe38c000 0x00000000 0x00004000>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000073 0x0000001f 0x00000072 0x0000001f 0x00000071 0x0000001f 0x00000181>;
        clock-names = "usr", "sbpi", "apb", "phy";
        resets = <0x0000001f 0x000001cf>;
        reset-names = "otp_phy";
        phandle = <0x0000019c>;
        cpu-code@2 {
            reg = <0x00000002 0x00000002>;
            phandle = <0x0000000f>;
        };
        cpu-version@8 {
            reg = <0x00000008 0x00000001>;
            bits = <0x00000003 0x00000003>;
            phandle = <0x0000000e>;
        };
        mbist-vmin@9 {
            reg = <0x00000009 0x00000001>;
            bits = <0x00000000 0x00000004>;
            phandle = <0x00000008>;
        };
        id@a {
            reg = <0x0000000a 0x00000010>;
            phandle = <0x0000000d>;
        };
        cpu-leakage@1a {
            reg = <0x0000001a 0x00000001>;
            phandle = <0x00000006>;
        };
        log-leakage@1b {
            reg = <0x0000001b 0x00000001>;
            phandle = <0x000000a9>;
        };
        npu-leakage@1c {
            reg = <0x0000001c 0x00000001>;
            phandle = <0x00000060>;
        };
        gpu-leakage@1d {
            reg = <0x0000001d 0x00000001>;
            phandle = <0x00000065>;
        };
        core-pvtm@2a {
            reg = <0x0000002a 0x00000002>;
            phandle = <0x00000007>;
        };
    };
    i2s@fe400000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe400000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000034 0x00000004>;
        clocks = <0x0000001f 0x0000003f 0x0000001f 0x00000043 0x0000001f 0x00000039>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000000>;
        dma-names = "tx";
        resets = <0x0000001f 0x00000050 0x0000001f 0x00000051>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,playback-only;
        #sound-dai-cells = <0x00000000>;
        status = "okay";
        phandle = <0x00000121>;
    };
    i2s@fe410000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe410000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000035 0x00000004>;
        clocks = <0x0000001f 0x00000047 0x0000001f 0x0000004b 0x0000001f 0x0000003a>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000002 0x000000b5 0x00000003>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000052 0x0000001f 0x00000053>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000b6 0x000000b7 0x000000b8 0x000000b9>;
        status = "disabled";
        rockchip,clk-trcm = <0x00000001>;
        phandle = <0x000000c6>;
    };
    i2s@fe420000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe420000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000036 0x00000004>;
        clocks = <0x0000001f 0x0000004f 0x0000001f 0x0000004f 0x0000001f 0x0000003b>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000004 0x000000b5 0x00000005>;
        dma-names = "tx", "rx";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ba 0x000000bb 0x000000bc 0x000000bd>;
        status = "disabled";
        phandle = <0x0000019d>;
    };
    i2s@fe430000 {
        compatible = "rockchip,rk3568-i2s-tdm";
        reg = <0x00000000 0xfe430000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000037 0x00000004>;
        clocks = <0x0000001f 0x00000053 0x0000001f 0x00000057 0x0000001f 0x0000003c>;
        clock-names = "mclk_tx", "mclk_rx", "hclk";
        dmas = <0x000000b5 0x00000006 0x000000b5 0x00000007>;
        dma-names = "tx", "rx";
        resets = <0x0000001f 0x00000055 0x0000001f 0x00000056>;
        reset-names = "tx-m", "rx-m";
        rockchip,cru = <0x0000001f>;
        rockchip,grf = <0x00000032>;
        rockchip,clk-trcm = <0x00000001>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000be 0x000000bf 0x000000c0 0x000000c1>;
        status = "okay";
        phandle = <0x0000011d>;
    };
    pdm@fe440000 {
        compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
        reg = <0x00000000 0xfe440000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000005a 0x0000001f 0x00000059>;
        clock-names = "pdm_clk", "pdm_hclk";
        dmas = <0x000000b5 0x00000009>;
        dma-names = "rx";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c2 0x000000c3 0x000000c4 0x000000c5>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x00000123>;
    };
    vad@fe450000 {
        compatible = "rockchip,rk3568-vad";
        reg = <0x00000000 0xfe450000 0x00000000 0x00010000>;
        reg-names = "vad";
        clocks = <0x0000001f 0x0000005b>;
        clock-names = "hclk";
        interrupts = <0x00000000 0x00000089 0x00000004>;
        rockchip,audio-src = <0x000000c6>;
        rockchip,det-channel = <0x00000000>;
        rockchip,mode = <0x00000000>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        rockchip,buffer-time-ms = <0x00000080>;
        phandle = <0x00000128>;
    };
    spdif@fe460000 {
        compatible = "rockchip,rk3568-spdif";
        reg = <0x00000000 0xfe460000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000066 0x00000004>;
        dmas = <0x000000b5 0x00000001>;
        dma-names = "tx";
        clock-names = "mclk", "hclk";
        clocks = <0x0000001f 0x0000005f 0x0000001f 0x0000005c>;
        #sound-dai-cells = <0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c7>;
        status = "okay";
        phandle = <0x00000126>;
    };
    audpwm@fe470000 {
        compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
        reg = <0x00000000 0xfe470000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000063 0x0000001f 0x00000060>;
        clock-names = "clk", "hclk";
        dmas = <0x000000b5 0x00000008>;
        dma-names = "tx";
        #sound-dai-cells = <0x00000000>;
        rockchip,sample-width-bits = <0x0000000b>;
        rockchip,interpolat-points = <0x00000001>;
        status = "disabled";
        phandle = <0x0000019e>;
    };
    codec-digital@fe478000 {
        compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
        reg = <0x00000000 0xfe478000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000067 0x0000001f 0x00000066 0x0000001f 0x00000065 0x0000001f 0x00000064>;
        clock-names = "adc", "dac", "i2c", "pclk";
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c8>;
        resets = <0x0000001f 0x0000005f>;
        reset-names = "reset";
        rockchip,grf = <0x00000032>;
        #sound-dai-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000011e>;
    };
    dmac@fe530000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe530000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x0000000e 0x00000004 0x00000000 0x0000000d 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x0000003f>;
    };
    dmac@fe550000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x00000000 0xfe550000 0x00000000 0x00004000>;
        interrupts = <0x00000000 0x00000010 0x00000004 0x00000000 0x0000000f 0x00000004>;
        clocks = <0x0000001f 0x0000010d>;
        clock-names = "apb_pclk";
        #dma-cells = <0x00000001>;
        arm,pl330-periph-burst;
        phandle = <0x000000b5>;
    };
    rkscr@fe560000 {
        compatible = "rockchip-scr";
        reg = <0x00000000 0xfe560000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000061 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000c9>;
        clocks = <0x0000001f 0x00000114>;
        clock-names = "g_pclk_sim_card";
        status = "disabled";
        phandle = <0x0000019f>;
    };
    can@fe570000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe570000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000001 0x00000004>;
        clocks = <0x0000001f 0x00000141 0x0000001f 0x00000140>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000155 0x0000001f 0x00000154>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000141>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ca>;
        phandle = <0x000001a0>;
    };
    can@fe580000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe580000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000002 0x00000004>;
        clocks = <0x0000001f 0x00000143 0x0000001f 0x00000142>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000157 0x0000001f 0x00000156>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000143>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cb>;
        phandle = <0x000001a1>;
    };
    can@fe590000 {
        compatible = "rockchip,canfd-1.0";
        reg = <0x00000000 0xfe590000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000003 0x00000004>;
        clocks = <0x0000001f 0x00000145 0x0000001f 0x00000144>;
        clock-names = "baudclk", "apb_pclk";
        resets = <0x0000001f 0x00000159 0x0000001f 0x00000158>;
        reset-names = "can", "can-apb";
        tx-fifo-depth = <0x00000001>;
        rx-fifo-depth = <0x00000006>;
        status = "disabled";
        assigned-clocks = <0x0000001f 0x00000145>;
        assigned-clock-rates = <0x08f0d180>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cc>;
        phandle = <0x000001a2>;
    };
    i2c@fe5a0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5a0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000148 0x0000001f 0x00000147>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x0000002f 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cd>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a3>;
        gt1x@14 {
            compatible = "goodix,gt1x";
            reg = <0x00000014>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000ce>;
            goodix,rst-gpio = <0x00000035 0x0000000e 0x00000000>;
            goodix,irq-gpio = <0x00000035 0x0000000d 0x00000008>;
            power-supply = <0x00000092>;
            status = "disabled";
            phandle = <0x000001a4>;
        };
    };
    i2c@fe5b0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5b0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014a 0x0000001f 0x00000149>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000030 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000cf>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001a5>;
        gc2145@3c {
            status = "okay";
            compatible = "galaxycore,gc2145";
            reg = <0x0000003c>;
            clocks = <0x0000001f 0x000000d6>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d0 0x000000d1 0x000000d2>;
            power-gpios = <0x0000007b 0x0000001c 0x00000000>;
            pwdn-gpios = <0x0000007b 0x0000001a 0x00000000>;
            rockchip,camera-module-index = <0x00000001>;
            rockchip,camera-module-facing = "front";
            rockchip,camera-module-name = "CameraKing";
            rockchip,camera-module-lens-name = "Largan";
            phandle = <0x000001a6>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d3>;
                    phandle = <0x00000072>;
                };
            };
        };
        ov5695@36 {
            status = "okay";
            compatible = "ovti,ov5695";
            reg = <0x00000036>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000000>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000000>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "TongJu";
            rockchip,camera-module-lens-name = "CHT842-MD";
            phandle = <0x000001a7>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d5>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x00000108>;
                };
            };
        };
        gc8034@37 {
            compatible = "galaxycore,gc8034";
            status = "okay";
            reg = <0x00000037>;
            clocks = <0x0000001f 0x000000d7>;
            clock-names = "xvclk";
            power-domains = <0x00000021 0x00000008>;
            pinctrl-names = "default";
            pinctrl-0 = <0x000000d4>;
            reset-gpios = <0x0000007b 0x00000018 0x00000001>;
            pwdn-gpios = <0x0000007b 0x00000016 0x00000001>;
            rockchip,camera-module-index = <0x00000000>;
            rockchip,camera-module-facing = "back";
            rockchip,camera-module-name = "RK-CMK-8M-2-v1";
            rockchip,camera-module-lens-name = "CK8401";
            phandle = <0x000001a8>;
            port {
                endpoint {
                    remote-endpoint = <0x000000d6>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x00000109>;
                };
            };
        };
    };
    i2c@fe5c0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5c0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014c 0x0000001f 0x0000014b>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000031 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d7>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001a9>;
    };
    i2c@fe5d0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5d0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x0000014e 0x0000001f 0x0000014d>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000032 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d8>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x000001aa>;
    };
    i2c@fe5e0000 {
        compatible = "rockchip,rk3399-i2c";
        reg = <0x00000000 0xfe5e0000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000150 0x0000001f 0x0000014f>;
        clock-names = "i2c", "pclk";
        interrupts = <0x00000000 0x00000033 0x00000004>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000d9>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        status = "okay";
        phandle = <0x000001ab>;
        mxc6655xa@15 {
            status = "okay";
            compatible = "gs_mxc6655xa";
            pinctrl-names = "default";
            pinctrl-0 = <0x000000da>;
            reg = <0x00000015>;
            irq-gpio = <0x0000007b 0x00000011 0x00000008>;
            irq_enable = <0x00000000>;
            poll_delay_ms = <0x0000001e>;
            type = <0x00000002>;
            power-off-in-suspend = <0x00000001>;
            layout = <0x00000001>;
            phandle = <0x000001ac>;
        };
    };
    timer@fe5f0000 {
        compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer";
        reg = <0x00000000 0xfe5f0000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006d 0x00000004>;
        clocks = <0x0000001f 0x0000016c 0x0000001f 0x0000016d>;
        clock-names = "pclk", "timer";
        phandle = <0x000001ad>;
    };
    watchdog@fe600000 {
        compatible = "snps,dw-wdt";
        reg = <0x00000000 0xfe600000 0x00000000 0x00000100>;
        clocks = <0x0000001f 0x00000116 0x0000001f 0x00000115>;
        clock-names = "tclk", "pclk";
        interrupts = <0x00000000 0x00000095 0x00000004>;
        status = "okay";
        phandle = <0x000001ae>;
    };
    spi@fe610000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe610000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000067 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000152 0x0000001f 0x00000151>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000014 0x0000003f 0x00000015>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000db 0x000000dc 0x000000dd>;
        pinctrl-1 = <0x000000db 0x000000dc 0x000000de>;
        status = "disabled";
        phandle = <0x000001af>;
    };
    spi@fe620000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe620000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000068 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000154 0x0000001f 0x00000153>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000016 0x0000003f 0x00000017>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000df 0x000000e0 0x000000e1>;
        pinctrl-1 = <0x000000df 0x000000e0 0x000000e2>;
        status = "disabled";
        phandle = <0x000001b0>;
    };
    spi@fe630000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe630000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x00000069 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000156 0x0000001f 0x00000155>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x00000018 0x0000003f 0x00000019>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e3 0x000000e4 0x000000e5>;
        pinctrl-1 = <0x000000e3 0x000000e4 0x000000e6>;
        status = "disabled";
        phandle = <0x000001b1>;
    };
    spi@fe640000 {
        compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
        reg = <0x00000000 0xfe640000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x0000006a 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        clocks = <0x0000001f 0x00000158 0x0000001f 0x00000157>;
        clock-names = "spiclk", "apb_pclk";
        dmas = <0x0000003f 0x0000001a 0x0000003f 0x0000001b>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "high_speed";
        pinctrl-0 = <0x000000e7 0x000000e8 0x000000e9>;
        pinctrl-1 = <0x000000e7 0x000000e8 0x000000ea>;
        status = "disabled";
        phandle = <0x000001b2>;
    };
    serial@fe650000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe650000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000075 0x00000004>;
        clocks = <0x0000001f 0x0000011f 0x0000001f 0x0000011c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000002 0x0000003f 0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000eb 0x000000ec>;
        status = "okay";
        phandle = <0x000001b3>;
    };
    serial@fe660000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe660000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000076 0x00000004>;
        clocks = <0x0000001f 0x00000123 0x0000001f 0x00000120>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000004 0x0000003f 0x00000005>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ed>;
        status = "disabled";
        phandle = <0x000001b4>;
    };
    serial@fe670000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe670000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000077 0x00000004>;
        clocks = <0x0000001f 0x00000127 0x0000001f 0x00000124>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000006 0x0000003f 0x00000007>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ee>;
        status = "disabled";
        phandle = <0x000001b5>;
    };
    serial@fe680000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe680000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000078 0x00000004>;
        clocks = <0x0000001f 0x0000012b 0x0000001f 0x00000128>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000008 0x0000003f 0x00000009>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ef>;
        status = "disabled";
        phandle = <0x000001b6>;
    };
    serial@fe690000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe690000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000079 0x00000004>;
        clocks = <0x0000001f 0x0000012f 0x0000001f 0x0000012c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000a 0x0000003f 0x0000000b>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f0>;
        status = "disabled";
        phandle = <0x000001b7>;
    };
    serial@fe6a0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6a0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007a 0x00000004>;
        clocks = <0x0000001f 0x00000133 0x0000001f 0x00000130>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000c 0x0000003f 0x0000000d>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f1>;
        status = "disabled";
        phandle = <0x000001b8>;
    };
    serial@fe6b0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6b0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007b 0x00000004>;
        clocks = <0x0000001f 0x00000137 0x0000001f 0x00000134>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x0000000e 0x0000003f 0x0000000f>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f2>;
        status = "disabled";
        phandle = <0x000001b9>;
    };
    serial@fe6c0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6c0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007c 0x00000004>;
        clocks = <0x0000001f 0x0000013b 0x0000001f 0x00000138>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000010 0x0000003f 0x00000011>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f3>;
        status = "disabled";
        phandle = <0x000001ba>;
    };
    serial@fe6d0000 {
        compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
        reg = <0x00000000 0xfe6d0000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000007d 0x00000004>;
        clocks = <0x0000001f 0x0000013f 0x0000001f 0x0000013c>;
        clock-names = "baudclk", "apb_pclk";
        reg-shift = <0x00000002>;
        reg-io-width = <0x00000004>;
        dmas = <0x0000003f 0x00000012 0x0000003f 0x00000013>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f4>;
        status = "disabled";
        phandle = <0x000001bb>;
    };
    pwm@fe6e0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f5>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x0000011f>;
    };
    pwm@fe6e0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f6>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "okay";
        phandle = <0x00000120>;
    };
    pwm@fe6e0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6e0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f7>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bc>;
    };
    pwm@fe6e0030 {
        compatible = "rockchip,remotectl-pwm";
        reg = <0x00000000 0xfe6e0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000053 0x00000004 0x00000000 0x00000057 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000f8>;
        clocks = <0x0000001f 0x0000015a 0x0000001f 0x00000159>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        remote_pwm_id = <0x00000003>;
        handle_cpu_id = <0x00000001>;
        remote_support_psci = <0x00000000>;
        phandle = <0x000001bd>;
        ir_key1 {
            rockchip,usercode = <0x00004040>;
            rockchip,key_table = <0x000000f2 0x000000e8 0x000000ba 0x0000009e 0x000000f4 0x00000067 0x000000f1 0x0000006c 0x000000ef 0x00000069 0x000000ee 0x0000006a 0x000000bd 0x00000066 0x000000ea 0x00000073 0x000000e3 0x00000072 0x000000e2 0x000000d9 0x000000b2 0x00000074 0x000000bc 0x00000071 0x000000ec 0x0000008b 0x000000bf 0x00000190 0x000000e0 0x00000191 0x000000e1 0x00000192 0x000000e9 0x000000b7 0x000000e6 0x000000f8 0x000000e8 0x000000b9 0x000000e7 0x000000ba 0x000000f0 0x00000184 0x000000be 0x00000175>;
        };
        ir_key2 {
            rockchip,usercode = <0x0000ff00>;
            rockchip,key_table = <0x000000f9 0x00000066 0x000000bf 0x0000009e 0x000000fb 0x0000008b 0x000000aa 0x000000e8 0x000000b9 0x00000067 0x000000e9 0x0000006c 0x000000b8 0x00000069 0x000000ea 0x0000006a 0x000000eb 0x00000072 0x000000ef 0x00000073 0x000000f7 0x00000071 0x000000e7 0x00000074 0x000000fc 0x00000074 0x000000a9 0x00000072 0x000000a8 0x00000072 0x000000e0 0x00000072 0x000000a5 0x00000072 0x000000ab 0x000000b7 0x000000b7 0x00000184 0x000000e8 0x00000184 0x000000f8 0x000000b8 0x000000af 0x000000b9 0x000000ed 0x00000072 0x000000ee 0x000000ba 0x000000b3 0x00000072 0x000000f1 0x00000072 0x000000f2 0x00000072 0x000000f3 0x000000d9 0x000000b4 0x00000072 0x000000be 0x000000d9>;
        };
        ir_key3 {
            rockchip,usercode = <0x00001dcc>;
            rockchip,key_table = <0x000000ee 0x000000e8 0x000000f0 0x0000009e 0x000000f8 0x00000067 0x000000bb 0x0000006c 0x000000ef 0x00000069 0x000000ed 0x0000006a 0x000000fc 0x00000066 0x000000f1 0x00000073 0x000000fd 0x00000072 0x000000b7 0x000000d9 0x000000ff 0x00000074 0x000000f3 0x00000071 0x000000bf 0x0000008b 0x000000f9 0x00000191 0x000000f5 0x00000192 0x000000b3 0x00000184 0x000000be 0x00000002 0x000000ba 0x00000003 0x000000b2 0x00000004 0x000000bd 0x00000005 0x000000f9 0x00000006 0x000000b1 0x00000007 0x000000fc 0x00000008 0x000000f8 0x00000009 0x000000b0 0x0000000a 0x000000b6 0x0000000b 0x000000b5 0x0000000e>;
        };
    };
    pwm@fe6f0000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000f9>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001be>;
    };
    pwm@fe6f0010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fa>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001bf>;
    };
    pwm@fe6f0020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fb>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c0>;
    };
    pwm@fe6f0030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe6f0030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000054 0x00000004 0x00000000 0x00000058 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fc>;
        clocks = <0x0000001f 0x0000015d 0x0000001f 0x0000015c>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c1>;
    };
    pwm@fe700000 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700000 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fd>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c2>;
    };
    pwm@fe700010 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700010 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000fe>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c3>;
    };
    pwm@fe700020 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700020 0x00000000 0x00000010>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x000000ff>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c4>;
    };
    pwm@fe700030 {
        compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
        reg = <0x00000000 0xfe700030 0x00000000 0x00000010>;
        interrupts = <0x00000000 0x00000055 0x00000004 0x00000000 0x00000059 0x00000004>;
        #pwm-cells = <0x00000003>;
        pinctrl-names = "active";
        pinctrl-0 = <0x00000100>;
        clocks = <0x0000001f 0x00000160 0x0000001f 0x0000015f>;
        clock-names = "pwm", "pclk";
        status = "disabled";
        phandle = <0x000001c5>;
    };
    tsadc@fe710000 {
        compatible = "rockchip,rk3568-tsadc";
        reg = <0x00000000 0xfe710000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x00000073 0x00000004>;
        rockchip,grf = <0x00000032>;
        clocks = <0x0000001f 0x00000111 0x0000001f 0x0000010f>;
        clock-names = "tsadc", "apb_pclk";
        assigned-clocks = <0x0000001f 0x00000110 0x0000001f 0x00000111>;
        assigned-clock-rates = <0x01036640 0x000aae60>;
        resets = <0x0000001f 0x00000182 0x0000001f 0x00000181 0x0000001f 0x000001d7>;
        reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
        #thermal-sensor-cells = <0x00000001>;
        rockchip,hw-tshut-temp = <0x0001d4c0>;
        rockchip,hw-tshut-mode = <0x00000000>;
        rockchip,hw-tshut-polarity = <0x00000000>;
        pinctrl-names = "gpio", "otpout";
        pinctrl-0 = <0x00000101>;
        pinctrl-1 = <0x00000102>;
        status = "okay";
        phandle = <0x0000001b>;
    };
    saradc@fe720000 {
        compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
        reg = <0x00000000 0xfe720000 0x00000000 0x00000100>;
        interrupts = <0x00000000 0x0000005d 0x00000004>;
        #io-channel-cells = <0x00000001>;
        clocks = <0x0000001f 0x00000113 0x0000001f 0x00000112>;
        clock-names = "saradc", "apb_pclk";
        resets = <0x0000001f 0x00000180>;
        reset-names = "saradc-apb";
        status = "okay";
        vref-supply = <0x00000103>;
        phandle = <0x0000011b>;
    };
    mailbox@fe780000 {
        compatible = "rockchip,rk3568-mailbox", "rockchip,rk3368-mailbox";
        reg = <0x00000000 0xfe780000 0x00000000 0x00001000>;
        interrupts = <0x00000000 0x000000b7 0x00000004 0x00000000 0x000000b8 0x00000004 0x00000000 0x000000b9 0x00000004 0x00000000 0x000000ba 0x00000004>;
        clocks = <0x0000001f 0x0000011b>;
        clock-names = "pclk_mailbox";
        #mbox-cells = <0x00000001>;
        status = "disabled";
        phandle = <0x000001c6>;
    };
    phy@fe830000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe830000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000022 0x0000001f 0x0000017d 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000022>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c6 0x0000001f 0x000001c7>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000105>;
        status = "okay";
        phandle = <0x00000020>;
    };
    phy@fe840000 {
        compatible = "rockchip,rk3568-naneng-combphy";
        reg = <0x00000000 0xfe840000 0x00000000 0x00000100>;
        #phy-cells = <0x00000001>;
        clocks = <0x00000031 0x00000025 0x0000001f 0x0000017e 0x0000001f 0x0000007f>;
        clock-names = "refclk", "apbclk", "pipe_clk";
        assigned-clocks = <0x00000031 0x00000025>;
        assigned-clock-rates = <0x05f5e100>;
        resets = <0x0000001f 0x000001c8 0x0000001f 0x000001c9>;
        reset-names = "combphy-apb", "combphy";
        rockchip,pipe-grf = <0x00000104>;
        rockchip,pipe-phy-grf = <0x00000106>;
        status = "disabled";
        phandle = <0x00000022>;
    };
    mipi-dphy@fe850000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x0000008e>;
    };
    video-phy@fe850000 {
        compatible = "rockchip,rk3568-video-phy";
        reg = <0x00000000 0xfe850000 0x00000000 0x00010000 0x00000000 0xfe060000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000017 0x0000001f 0x0000017a 0x0000001f 0x000000e8>;
        clock-names = "ref", "pclk_phy", "pclk_host";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bb>;
        reset-names = "rst";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        status = "disabled";
        phandle = <0x0000002e>;
    };
    mipi-dphy@fe860000 {
        compatible = "rockchip,rk3568-mipi-dphy";
        reg = <0x00000000 0xfe860000 0x00000000 0x00010000>;
        clocks = <0x00000031 0x00000019 0x0000001f 0x0000017b>;
        clock-names = "ref", "pclk";
        clock-output-names = "mipi_dphy1_pll";
        #clock-cells = <0x00000000>;
        resets = <0x0000001f 0x000001bc>;
        reset-names = "apb";
        power-domains = <0x00000021 0x00000009>;
        #phy-cells = <0x00000000>;
        rockchip,grf = <0x00000032>;
        status = "disabled";
        phandle = <0x00000097>;
    };
    csi2-dphy-hw@fe870000 {
        compatible = "rockchip,rk3568-csi2-dphy-hw";
        reg = <0x00000000 0xfe870000 0x00000000 0x00001000>;
        clocks = <0x0000001f 0x00000179>;
        clock-names = "pclk";
        rockchip,grf = <0x00000032>;
        status = "okay";
        phandle = <0x00000107>;
    };
    csi2-dphy0 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "okay";
        phandle = <0x000001c7>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@1 {
                    reg = <0x00000001>;
                    remote-endpoint = <0x00000108>;
                    data-lanes = <0x00000001 0x00000002>;
                    phandle = <0x000000d5>;
                };
                endpoint@2 {
                    reg = <0x00000002>;
                    remote-endpoint = <0x00000109>;
                    data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>;
                    phandle = <0x000000d6>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                endpoint@0 {
                    reg = <0x00000000>;
                    remote-endpoint = <0x0000010a>;
                    phandle = <0x00000077>;
                };
            };
        };
    };
    csi2-dphy1 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c8>;
    };
    csi2-dphy2 {
        compatible = "rockchip,rk3568-csi2-dphy";
        rockchip,hw = <0x00000107>;
        status = "disabled";
        phandle = <0x000001c9>;
    };
    usb2-phy@fe8a0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8a0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000087 0x00000004>;
        clocks = <0x00000031 0x00000013>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        assigned-clocks = <0x0000001f 0x0000000b>;
        assigned-clock-parents = <0x00000024>;
        clock-output-names = "usb480m_phy";
        rockchip,usbgrf = <0x0000010b>;
        status = "okay";
        phandle = <0x00000024>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000025>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            vbus-supply = <0x0000010d>;
            phandle = <0x00000023>;
        };
    };
    usb2-phy@fe8b0000 {
        compatible = "rockchip,rk3568-usb2phy";
        reg = <0x00000000 0xfe8b0000 0x00000000 0x00010000>;
        interrupts = <0x00000000 0x00000088 0x00000004>;
        clocks = <0x00000031 0x00000015>;
        clock-names = "phyclk";
        #clock-cells = <0x00000000>;
        rockchip,usbgrf = <0x0000010e>;
        status = "okay";
        phandle = <0x00000026>;
        host-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000028>;
        };
        otg-port {
            #phy-cells = <0x00000000>;
            status = "okay";
            phy-supply = <0x0000010c>;
            phandle = <0x00000027>;
        };
    };
    pinctrl {
        compatible = "rockchip,rk3568-pinctrl";
        rockchip,grf = <0x00000032>;
        rockchip,pmu = <0x00000033>;
        #address-cells = <0x00000002>;
        #size-cells = <0x00000002>;
        ranges;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000010f>;
        phandle = <0x00000110>;
        gpio@fdd60000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfdd60000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000021 0x00000004>;
            clocks = <0x00000031 0x0000002e 0x00000031 0x0000000c>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000000 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000035>;
        };
        gpio@fe740000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe740000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000022 0x00000004>;
            clocks = <0x0000001f 0x00000163 0x0000001f 0x00000164>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000020 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x00000093>;
        };
        gpio@fe750000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe750000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000023 0x00000004>;
            clocks = <0x0000001f 0x00000165 0x0000001f 0x00000166>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000040 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000012e>;
        };
        gpio@fe760000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe760000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000024 0x00000004>;
            clocks = <0x0000001f 0x00000167 0x0000001f 0x00000168>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000060 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000007b>;
        };
        gpio@fe770000 {
            compatible = "rockchip,gpio-bank";
            reg = <0x00000000 0xfe770000 0x00000000 0x00000100>;
            interrupts = <0x00000000 0x00000025 0x00000004>;
            clocks = <0x0000001f 0x00000169 0x0000001f 0x0000016a>;
            gpio-controller;
            #gpio-cells = <0x00000002>;
            gpio-ranges = <0x00000110 0x00000000 0x00000080 0x00000020>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            phandle = <0x0000009c>;
        };
        pcfg-pull-up {
            bias-pull-up;
            phandle = <0x00000113>;
        };
        pcfg-pull-down {
            bias-pull-down;
            phandle = <0x0000011a>;
        };
        pcfg-pull-none {
            bias-disable;
            phandle = <0x00000111>;
        };
        pcfg-pull-none-drv-level-1 {
            bias-disable;
            drive-strength = <0x00000001>;
            phandle = <0x00000115>;
        };
        pcfg-pull-none-drv-level-2 {
            bias-disable;
            drive-strength = <0x00000002>;
            phandle = <0x00000114>;
        };
        pcfg-pull-none-drv-level-3 {
            bias-disable;
            drive-strength = <0x00000003>;
            phandle = <0x00000119>;
        };
        pcfg-pull-up-drv-level-1 {
            bias-pull-up;
            drive-strength = <0x00000001>;
            phandle = <0x00000118>;
        };
        pcfg-pull-up-drv-level-2 {
            bias-pull-up;
            drive-strength = <0x00000002>;
            phandle = <0x00000112>;
        };
        pcfg-pull-none-smt {
            bias-disable;
            input-schmitt-enable;
            phandle = <0x00000116>;
        };
        pcfg-output-low {
            output-low;
            phandle = <0x00000117>;
        };
        acodec {
            acodec-pins {
                rockchip,pins = <0x00000001 0x00000009 0x00000005 0x00000111 0x00000001 0x00000001 0x00000005 0x00000111 0x00000001 0x00000000 0x00000005 0x00000111 0x00000001 0x00000007 0x00000005 0x00000111 0x00000001 0x00000008 0x00000005 0x00000111 0x00000001 0x00000003 0x00000005 0x00000111 0x00000001 0x00000005 0x00000005 0x00000111>;
                phandle = <0x000000c8>;
            };
        };
        cam {
            cam-clkout0 {
                rockchip,pins = <0x00000004 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000d4>;
            };
            camera-pwr {
                rockchip,pins = <0x00000000 0x00000011 0x00000000 0x00000111>;
                phandle = <0x00000133>;
            };
        };
        can0 {
            can0m1-pins {
                rockchip,pins = <0x00000002 0x00000002 0x00000004 0x00000111 0x00000002 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000ca>;
            };
        };
        can1 {
            can1m1-pins {
                rockchip,pins = <0x00000004 0x00000012 0x00000003 0x00000111 0x00000004 0x00000013 0x00000003 0x00000111>;
                phandle = <0x000000cb>;
            };
        };
        can2 {
            can2m1-pins {
                rockchip,pins = <0x00000002 0x00000009 0x00000004 0x00000111 0x00000002 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000cc>;
            };
        };
        cif {
            cif-clk {
                rockchip,pins = <0x00000004 0x00000010 0x00000001 0x00000111>;
                phandle = <0x000000d0>;
            };
            cif-dvp-clk {
                rockchip,pins = <0x00000004 0x00000011 0x00000001 0x00000111 0x00000004 0x0000000e 0x00000001 0x00000111 0x00000004 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x000000d1>;
            };
            cif-dvp-bus16 {
                rockchip,pins = <0x00000003 0x0000001e 0x00000001 0x00000111 0x00000003 0x0000001f 0x00000001 0x00000111 0x00000004 0x00000000 0x00000001 0x00000111 0x00000004 0x00000001 0x00000001 0x00000111 0x00000004 0x00000002 0x00000001 0x00000111 0x00000004 0x00000003 0x00000001 0x00000111 0x00000004 0x00000004 0x00000001 0x00000111 0x00000004 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000d2>;
            };
        };
        clk32k {
            clk32k-out0 {
                rockchip,pins = <0x00000000 0x00000008 0x00000002 0x00000111>;
                phandle = <0x0000001e>;
            };
        };
        ebc {
            ebc-pins {
                rockchip,pins = <0x00000004 0x00000010 0x00000002 0x00000111 0x00000004 0x0000000b 0x00000002 0x00000111 0x00000004 0x0000000c 0x00000002 0x00000111 0x00000004 0x00000006 0x00000002 0x00000111 0x00000004 0x00000011 0x00000002 0x00000111 0x00000003 0x00000016 0x00000002 0x00000111 0x00000003 0x00000017 0x00000002 0x00000111 0x00000003 0x00000018 0x00000002 0x00000111 0x00000003 0x00000019 0x00000002 0x00000111 0x00000003 0x0000001a 0x00000002 0x00000111 0x00000003 0x0000001b 0x00000002 0x00000111 0x00000003 0x0000001c 0x00000002 0x00000111 0x00000003 0x0000001d 0x00000002 0x00000111 0x00000003 0x0000001e 0x00000002 0x00000111 0x00000003 0x0000001f 0x00000002 0x00000111 0x00000004 0x00000000 0x00000002 0x00000111 0x00000004 0x00000001 0x00000002 0x00000111 0x00000004 0x00000002 0x00000002 0x00000111 0x00000004 0x00000003 0x00000002 0x00000111 0x00000004 0x00000004 0x00000002 0x00000111 0x00000004 0x00000005 0x00000002 0x00000111 0x00000004 0x0000000e 0x00000002 0x00000111 0x00000004 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x00000068>;
            };
        };
        gmac1 {
            gmac1m0-miim {
                rockchip,pins = <0x00000003 0x00000014 0x00000003 0x00000111 0x00000003 0x00000015 0x00000003 0x00000111>;
                phandle = <0x0000007c>;
            };
            gmac1m0-rx-bus2 {
                rockchip,pins = <0x00000003 0x00000009 0x00000003 0x00000111 0x00000003 0x0000000a 0x00000003 0x00000111 0x00000003 0x0000000b 0x00000003 0x00000111>;
                phandle = <0x0000007e>;
            };
        };
        hdmitx {
            hdmitxm0-cec {
                rockchip,pins = <0x00000004 0x00000019 0x00000001 0x00000111>;
                phandle = <0x000000a2>;
            };
            hdmitx-scl {
                rockchip,pins = <0x00000004 0x00000017 0x00000001 0x00000111>;
                phandle = <0x000000a0>;
            };
            hdmitx-sda {
                rockchip,pins = <0x00000004 0x00000018 0x00000001 0x00000111>;
                phandle = <0x000000a1>;
            };
        };
        i2c0 {
            i2c0-xfer {
                rockchip,pins = <0x00000000 0x00000009 0x00000001 0x00000116 0x00000000 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x00000034>;
            };
        };
        i2c1 {
            i2c1-xfer {
                rockchip,pins = <0x00000000 0x0000000b 0x00000001 0x00000116 0x00000000 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cd>;
            };
        };
        i2c2 {
            i2c2m1-xfer {
                rockchip,pins = <0x00000004 0x0000000d 0x00000001 0x00000116 0x00000004 0x0000000c 0x00000001 0x00000116>;
                phandle = <0x000000cf>;
            };
        };
        i2c3 {
            i2c3m0-xfer {
                rockchip,pins = <0x00000001 0x00000001 0x00000001 0x00000116 0x00000001 0x00000000 0x00000001 0x00000116>;
                phandle = <0x000000d7>;
            };
        };
        i2c4 {
            i2c4m0-xfer {
                rockchip,pins = <0x00000004 0x0000000b 0x00000001 0x00000116 0x00000004 0x0000000a 0x00000001 0x00000116>;
                phandle = <0x000000d8>;
            };
        };
        i2c5 {
            i2c5m0-xfer {
                rockchip,pins = <0x00000003 0x0000000b 0x00000004 0x00000116 0x00000003 0x0000000c 0x00000004 0x00000116>;
                phandle = <0x000000d9>;
            };
        };
        i2s1 {
            i2s1m0-lrcktx {
                rockchip,pins = <0x00000001 0x00000005 0x00000001 0x00000111>;
                phandle = <0x000000b7>;
            };
            i2s1m0-sclktx {
                rockchip,pins = <0x00000001 0x00000003 0x00000001 0x00000111>;
                phandle = <0x000000b6>;
            };
            i2s1m0-sdi0 {
                rockchip,pins = <0x00000001 0x0000000b 0x00000001 0x00000111>;
                phandle = <0x000000b8>;
            };
            i2s1m0-sdo0 {
                rockchip,pins = <0x00000001 0x00000007 0x00000001 0x00000111>;
                phandle = <0x000000b9>;
            };
        };
        i2s2 {
            i2s2m0-lrcktx {
                rockchip,pins = <0x00000002 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000bb>;
            };
            i2s2m0-sclktx {
                rockchip,pins = <0x00000002 0x00000012 0x00000001 0x00000111>;
                phandle = <0x000000ba>;
            };
            i2s2m0-sdi {
                rockchip,pins = <0x00000002 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000bc>;
            };
            i2s2m0-sdo {
                rockchip,pins = <0x00000002 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000bd>;
            };
        };
        i2s3 {
            i2s3m1-lrck {
                rockchip,pins = <0x00000004 0x00000014 0x00000005 0x00000111>;
                phandle = <0x000000bf>;
            };
            i2s3m1-mclk {
                rockchip,pins = <0x00000004 0x00000012 0x00000005 0x00000111>;
                phandle = <0x0000003d>;
            };
            i2s3m1-sclk {
                rockchip,pins = <0x00000004 0x00000013 0x00000005 0x00000111>;
                phandle = <0x000000be>;
            };
            i2s3m1-sdi {
                rockchip,pins = <0x00000004 0x00000016 0x00000005 0x00000111>;
                phandle = <0x000000c0>;
            };
            i2s3m1-sdo {
                rockchip,pins = <0x00000004 0x00000015 0x00000005 0x00000111>;
                phandle = <0x000000c1>;
            };
        };
        lcdc {
            lcdc-ctl {
                rockchip,pins = <0x00000003 0x00000000 0x00000001 0x00000111 0x00000002 0x00000018 0x00000001 0x00000111 0x00000002 0x00000019 0x00000001 0x00000111 0x00000002 0x0000001a 0x00000001 0x00000111 0x00000002 0x0000001b 0x00000001 0x00000111 0x00000002 0x0000001c 0x00000001 0x00000111 0x00000002 0x0000001d 0x00000001 0x00000111 0x00000002 0x0000001e 0x00000001 0x00000111 0x00000002 0x0000001f 0x00000001 0x00000111 0x00000003 0x00000001 0x00000001 0x00000111 0x00000003 0x00000002 0x00000001 0x00000111 0x00000003 0x00000003 0x00000001 0x00000111 0x00000003 0x00000004 0x00000001 0x00000111 0x00000003 0x00000005 0x00000001 0x00000111 0x00000003 0x00000006 0x00000001 0x00000111 0x00000003 0x00000007 0x00000001 0x00000111 0x00000003 0x00000008 0x00000001 0x00000111 0x00000003 0x00000009 0x00000001 0x00000111 0x00000003 0x0000000a 0x00000001 0x00000111 0x00000003 0x0000000b 0x00000001 0x00000111 0x00000003 0x0000000c 0x00000001 0x00000111 0x00000003 0x0000000d 0x00000001 0x00000111 0x00000003 0x0000000e 0x00000001 0x00000111 0x00000003 0x0000000f 0x00000001 0x00000111 0x00000003 0x00000010 0x00000001 0x00000111 0x00000003 0x00000013 0x00000001 0x00000111 0x00000003 0x00000011 0x00000001 0x00000111 0x00000003 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000030>;
            };
        };
        pdm {
            pdmm1-clk1 {
                rockchip,pins = <0x00000004 0x00000000 0x00000004 0x00000111>;
                phandle = <0x000000c2>;
            };
            pdmm1-sdi1 {
                rockchip,pins = <0x00000004 0x00000001 0x00000004 0x00000111>;
                phandle = <0x000000c3>;
            };
            pdmm1-sdi2 {
                rockchip,pins = <0x00000004 0x00000002 0x00000005 0x00000111>;
                phandle = <0x000000c4>;
            };
            pdmm1-sdi3 {
                rockchip,pins = <0x00000004 0x00000003 0x00000005 0x00000111>;
                phandle = <0x000000c5>;
            };
        };
        pmic {
            pmic_int {
                rockchip,pins = <0x00000000 0x00000003 0x00000000 0x00000113>;
                phandle = <0x00000036>;
            };
            soc_slppin_gpio {
                rockchip,pins = <0x00000000 0x00000002 0x00000000 0x00000117>;
                phandle = <0x00000039>;
            };
            soc_slppin_slp {
                rockchip,pins = <0x00000000 0x00000002 0x00000001 0x00000111>;
                phandle = <0x00000037>;
            };
            soc_slppin_rst {
                rockchip,pins = <0x00000000 0x00000002 0x00000002 0x00000111>;
                phandle = <0x000001ca>;
            };
        };
        pwm0 {
            pwm0m0-pins {
                rockchip,pins = <0x00000000 0x0000000f 0x00000001 0x00000111>;
                phandle = <0x00000041>;
            };
        };
        pwm1 {
            pwm1m0-pins {
                rockchip,pins = <0x00000000 0x00000010 0x00000001 0x00000111>;
                phandle = <0x00000042>;
            };
        };
        pwm2 {
            pwm2m0-pins {
                rockchip,pins = <0x00000000 0x00000011 0x00000001 0x00000111>;
                phandle = <0x00000043>;
            };
        };
        pwm3 {
            pwm3-pins {
                rockchip,pins = <0x00000000 0x00000012 0x00000001 0x00000111>;
                phandle = <0x00000044>;
            };
        };
        pwm4 {
            pwm4-pins {
                rockchip,pins = <0x00000000 0x00000013 0x00000001 0x00000111>;
                phandle = <0x000000f5>;
            };
        };
        pwm5 {
            pwm5-pins {
                rockchip,pins = <0x00000000 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000f6>;
            };
        };
        pwm6 {
            pwm6-pins {
                rockchip,pins = <0x00000000 0x00000015 0x00000001 0x00000111>;
                phandle = <0x000000f7>;
            };
        };
        pwm7 {
            pwm7-pins {
                rockchip,pins = <0x00000000 0x00000016 0x00000001 0x00000111>;
                phandle = <0x000000f8>;
            };
        };
        pwm8 {
            pwm8m0-pins {
                rockchip,pins = <0x00000003 0x00000009 0x00000005 0x00000111>;
                phandle = <0x000000f9>;
            };
        };
        pwm9 {
            pwm9m0-pins {
                rockchip,pins = <0x00000003 0x0000000a 0x00000005 0x00000111>;
                phandle = <0x000000fa>;
            };
        };
        pwm10 {
            pwm10m0-pins {
                rockchip,pins = <0x00000003 0x0000000d 0x00000005 0x00000111>;
                phandle = <0x000000fb>;
            };
        };
        pwm11 {
            pwm11m0-pins {
                rockchip,pins = <0x00000003 0x0000000e 0x00000005 0x00000111>;
                phandle = <0x000000fc>;
            };
        };
        pwm12 {
            pwm12m0-pins {
                rockchip,pins = <0x00000003 0x0000000f 0x00000002 0x00000111>;
                phandle = <0x000000fd>;
            };
        };
        pwm13 {
            pwm13m0-pins {
                rockchip,pins = <0x00000003 0x00000010 0x00000002 0x00000111>;
                phandle = <0x000000fe>;
            };
        };
        pwm14 {
            pwm14m0-pins {
                rockchip,pins = <0x00000003 0x00000014 0x00000001 0x00000111>;
                phandle = <0x000000ff>;
            };
        };
        pwm15 {
            pwm15m0-pins {
                rockchip,pins = <0x00000003 0x00000015 0x00000001 0x00000111>;
                phandle = <0x00000100>;
            };
        };
        scr {
            scr-pins {
                rockchip,pins = <0x00000001 0x00000002 0x00000003 0x00000111 0x00000001 0x00000007 0x00000003 0x00000113 0x00000001 0x00000003 0x00000003 0x00000113 0x00000001 0x00000005 0x00000003 0x00000111>;
                phandle = <0x000000c9>;
            };
        };
        sdmmc0 {
            sdmmc0-bus4 {
                rockchip,pins = <0x00000001 0x0000001d 0x00000001 0x00000112 0x00000001 0x0000001e 0x00000001 0x00000112 0x00000001 0x0000001f 0x00000001 0x00000112 0x00000002 0x00000000 0x00000001 0x00000112>;
                phandle = <0x000000ad>;
            };
            sdmmc0-clk {
                rockchip,pins = <0x00000002 0x00000002 0x00000001 0x00000112>;
                phandle = <0x000000ae>;
            };
            sdmmc0-cmd {
                rockchip,pins = <0x00000002 0x00000001 0x00000001 0x00000112>;
                phandle = <0x000000af>;
            };
            sdmmc0-det {
                rockchip,pins = <0x00000000 0x00000004 0x00000001 0x00000113>;
                phandle = <0x000000b0>;
            };
        };
        sdmmc1 {
            sdmmc1-bus4 {
                rockchip,pins = <0x00000002 0x00000003 0x00000001 0x00000112 0x00000002 0x00000004 0x00000001 0x00000112 0x00000002 0x00000005 0x00000001 0x00000112 0x00000002 0x00000006 0x00000001 0x00000112>;
                phandle = <0x000000b2>;
            };
            sdmmc1-clk {
                rockchip,pins = <0x00000002 0x00000008 0x00000001 0x00000112>;
                phandle = <0x000000b4>;
            };
            sdmmc1-cmd {
                rockchip,pins = <0x00000002 0x00000007 0x00000001 0x00000112>;
                phandle = <0x000000b3>;
            };
        };
        spdif {
            spdifm0-tx {
                rockchip,pins = <0x00000001 0x00000004 0x00000004 0x00000111>;
                phandle = <0x000000c7>;
            };
        };
        spi0 {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000111 0x00000000 0x00000015 0x00000002 0x00000111 0x00000000 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000dd>;
            };
            spi0m0-cs0 {
                rockchip,pins = <0x00000000 0x00000016 0x00000002 0x00000111>;
                phandle = <0x000000db>;
            };
            spi0m0-cs1 {
                rockchip,pins = <0x00000000 0x00000014 0x00000002 0x00000111>;
                phandle = <0x000000dc>;
            };
        };
        spi1 {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000111 0x00000002 0x0000000e 0x00000003 0x00000111 0x00000002 0x0000000f 0x00000004 0x00000111>;
                phandle = <0x000000e1>;
            };
            spi1m0-cs0 {
                rockchip,pins = <0x00000002 0x00000010 0x00000004 0x00000111>;
                phandle = <0x000000df>;
            };
            spi1m0-cs1 {
                rockchip,pins = <0x00000002 0x00000016 0x00000003 0x00000111>;
                phandle = <0x000000e0>;
            };
        };
        spi2 {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000111 0x00000002 0x00000012 0x00000004 0x00000111 0x00000002 0x00000013 0x00000004 0x00000111>;
                phandle = <0x000000e5>;
            };
            spi2m0-cs0 {
                rockchip,pins = <0x00000002 0x00000014 0x00000004 0x00000111>;
                phandle = <0x000000e3>;
            };
            spi2m0-cs1 {
                rockchip,pins = <0x00000002 0x00000015 0x00000004 0x00000111>;
                phandle = <0x000000e4>;
            };
        };
        spi3 {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000111 0x00000004 0x00000008 0x00000004 0x00000111 0x00000004 0x0000000a 0x00000004 0x00000111>;
                phandle = <0x000000e9>;
            };
            spi3m0-cs0 {
                rockchip,pins = <0x00000004 0x00000006 0x00000004 0x00000111>;
                phandle = <0x000000e7>;
            };
            spi3m0-cs1 {
                rockchip,pins = <0x00000004 0x00000007 0x00000004 0x00000111>;
                phandle = <0x000000e8>;
            };
        };
        tsadc {
            tsadc-shutorg {
                rockchip,pins = <0x00000000 0x00000001 0x00000002 0x00000111>;
                phandle = <0x00000102>;
            };
        };
        uart0 {
            uart0-xfer {
                rockchip,pins = <0x00000000 0x00000010 0x00000003 0x00000113 0x00000000 0x00000011 0x00000003 0x00000113>;
                phandle = <0x00000040>;
            };
        };
        uart1 {
            uart1m0-xfer {
                rockchip,pins = <0x00000002 0x0000000b 0x00000002 0x00000113 0x00000002 0x0000000c 0x00000002 0x00000113>;
                phandle = <0x000000eb>;
            };
            uart1m0-ctsn {
                rockchip,pins = <0x00000002 0x0000000e 0x00000002 0x00000111>;
                phandle = <0x000000ec>;
            };
            uart1m0-rtsn {
                rockchip,pins = <0x00000002 0x0000000d 0x00000002 0x00000111>;
                phandle = <0x00000130>;
            };
        };
        uart2 {
            uart2m0-xfer {
                rockchip,pins = <0x00000000 0x00000018 0x00000001 0x00000113 0x00000000 0x00000019 0x00000001 0x00000113>;
                phandle = <0x000000ed>;
            };
        };
        uart3 {
            uart3m0-xfer {
                rockchip,pins = <0x00000001 0x00000000 0x00000002 0x00000113 0x00000001 0x00000001 0x00000002 0x00000113>;
                phandle = <0x000000ee>;
            };
        };
        uart4 {
            uart4m0-xfer {
                rockchip,pins = <0x00000001 0x00000004 0x00000002 0x00000113 0x00000001 0x00000006 0x00000002 0x00000113>;
                phandle = <0x000000ef>;
            };
        };
        uart5 {
            uart5m0-xfer {
                rockchip,pins = <0x00000002 0x00000001 0x00000003 0x00000113 0x00000002 0x00000002 0x00000003 0x00000113>;
                phandle = <0x000000f0>;
            };
        };
        uart6 {
            uart6m0-xfer {
                rockchip,pins = <0x00000002 0x00000003 0x00000003 0x00000113 0x00000002 0x00000004 0x00000003 0x00000113>;
                phandle = <0x000000f1>;
            };
        };
        uart7 {
            uart7m0-xfer {
                rockchip,pins = <0x00000002 0x00000005 0x00000003 0x00000113 0x00000002 0x00000006 0x00000003 0x00000113>;
                phandle = <0x000000f2>;
            };
        };
        uart8 {
            uart8m0-xfer {
                rockchip,pins = <0x00000002 0x00000016 0x00000002 0x00000113 0x00000002 0x00000015 0x00000003 0x00000113>;
                phandle = <0x000000f3>;
            };
        };
        uart9 {
            uart9m0-xfer {
                rockchip,pins = <0x00000002 0x00000007 0x00000003 0x00000113 0x00000002 0x00000008 0x00000003 0x00000113>;
                phandle = <0x000000f4>;
            };
        };
        spi0-hs {
            spi0m0-pins {
                rockchip,pins = <0x00000000 0x0000000d 0x00000002 0x00000118 0x00000000 0x00000015 0x00000002 0x00000118 0x00000000 0x0000000e 0x00000002 0x00000118>;
                phandle = <0x000000de>;
            };
        };
        spi1-hs {
            spi1m0-pins {
                rockchip,pins = <0x00000002 0x0000000d 0x00000003 0x00000118 0x00000002 0x0000000e 0x00000003 0x00000118 0x00000002 0x0000000f 0x00000004 0x00000118>;
                phandle = <0x000000e2>;
            };
        };
        spi2-hs {
            spi2m0-pins {
                rockchip,pins = <0x00000002 0x00000011 0x00000004 0x00000118 0x00000002 0x00000012 0x00000004 0x00000118 0x00000002 0x00000013 0x00000004 0x00000118>;
                phandle = <0x000000e6>;
            };
        };
        spi3-hs {
            spi3m0-pins {
                rockchip,pins = <0x00000004 0x0000000b 0x00000004 0x00000118 0x00000004 0x00000008 0x00000004 0x00000118 0x00000004 0x0000000a 0x00000004 0x00000118>;
                phandle = <0x000000ea>;
            };
        };
        gmac-txd-level3 {
            gmac1m0-tx-bus2-level3 {
                rockchip,pins = <0x00000003 0x0000000d 0x00000003 0x00000119 0x00000003 0x0000000e 0x00000003 0x00000119 0x00000003 0x0000000f 0x00000003 0x00000111>;
                phandle = <0x0000007d>;
            };
            gmac1m0-rgmii-bus-level3 {
                rockchip,pins = <0x00000003 0x00000004 0x00000003 0x00000111 0x00000003 0x00000005 0x00000003 0x00000111 0x00000003 0x00000002 0x00000003 0x00000119 0x00000003 0x00000003 0x00000003 0x00000119>;
                phandle = <0x00000080>;
            };
        };
        gmac-txc-level2 {
            gmac1m0-rgmii-clk-level2 {
                rockchip,pins = <0x00000003 0x00000007 0x00000003 0x00000111 0x00000003 0x00000006 0x00000003 0x00000114>;
                phandle = <0x0000007f>;
            };
        };
        gpio-func {
            tsadc-gpio-func {
                rockchip,pins = <0x00000000 0x00000001 0x00000000 0x00000111>;
                phandle = <0x00000101>;
            };
        };
        mxc6655xa {
            mxc6655xa_irq_gpio {
                rockchip,pins = <0x00000003 0x00000011 0x00000000 0x00000111>;
                phandle = <0x000000da>;
            };
        };
        touch {
            touch-gpio {
                rockchip,pins = <0x00000000 0x0000000d 0x00000000 0x00000113 0x00000000 0x0000000e 0x00000000 0x00000111>;
                phandle = <0x000000ce>;
            };
        };
        sdio-pwrseq {
            wifi-enable-h {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x0000012d>;
            };
        };
        usb {
            vcc5v0-host-en {
                rockchip,pins = <0x00000000 0x00000006 0x00000000 0x00000111>;
                phandle = <0x0000012a>;
            };
            vcc5v0-otg-en {
                rockchip,pins = <0x00000000 0x00000005 0x00000000 0x00000111>;
                phandle = <0x0000012b>;
            };
        };
        wireless-bluetooth {
            uart8-gpios {
                rockchip,pins = <0x00000002 0x00000009 0x00000000 0x00000111>;
                phandle = <0x000001cb>;
            };
            uart1-gpios {
                rockchip,pins = <0x00000002 0x0000000d 0x00000000 0x00000111>;
                phandle = <0x00000131>;
            };
        };
        headphone {
            hp-det {
                rockchip,pins = <0x00000004 0x0000000b 0x00000000 0x0000011a>;
                phandle = <0x00000132>;
            };
        };
        lcd0 {
            lcd-rst-gpio {
                rockchip,pins = <0x00000001 0x00000005 0x00000000 0x00000111>;
                phandle = <0x00000094>;
            };
        };
        lcd1 {
            lcd1-rst-gpio {
                rockchip,pins = <0x00000004 0x00000016 0x00000000 0x00000111>;
                phandle = <0x0000009d>;
            };
        };
        wireless-wlan {
            wifi-host-wake-irq {
                rockchip,pins = <0x00000002 0x0000000a 0x00000000 0x0000011a>;
                phandle = <0x0000012f>;
            };
        };
        fddis_ctr {
            dis-ctl {
                rockchip,pins = <0x00000000 0x0000000b 0x00000000 0x00000113 0x00000000 0x0000000c 0x00000000 0x00000113>;
                phandle = <0x0000010f>;
            };
        };
    };
    adc-keys {
        compatible = "adc-keys";
        io-channels = <0x0000011b 0x00000000>;
        io-channel-names = "buttons";
        keyup-threshold-microvolt = <0x001b7740>;
        poll-interval = <0x00000064>;
        phandle = <0x000001cc>;
        vol-up-key {
            label = "volume up";
            linux,code = <0x00000073>;
            press-threshold-microvolt = <0x000006d6>;
        };
        vol-down-key {
            label = "volume down";
            linux,code = <0x00000072>;
            press-threshold-microvolt = <0x00048a1c>;
        };
        menu-key {
            label = "menu";
            linux,code = <0x0000008b>;
            press-threshold-microvolt = <0x000ef420>;
        };
        back-key {
            label = "back";
            linux,code = <0x0000009e>;
            press-threshold-microvolt = <0x0013eb9c>;
        };
    };
    audiopwmout-diff {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,audiopwmout-diff";
        simple-audio-card,mclk-fs = <0x00000100>;
        simple-audio-card,bitclock-master = <0x0000011c>;
        simple-audio-card,frame-master = <0x0000011c>;
        phandle = <0x000001cd>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x0000011e>;
            phandle = <0x0000011c>;
        };
    };
    backlight {
        compatible = "pwm-backlight";
        pwms = <0x0000011f 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x00000091>;
    };
    backlight1 {
        compatible = "pwm-backlight";
        pwms = <0x00000120 0x00000000 0x000061a8 0x00000000>;
        brightness-levels = <0x00000000 0x00000014 0x00000014 0x00000015 0x00000015 0x00000016 0x00000016 0x00000017 0x00000017 0x00000018 0x00000018 0x00000019 0x00000019 0x0000001a 0x0000001a 0x0000001b 0x0000001b 0x0000001c 0x0000001c 0x0000001d 0x0000001d 0x0000001e 0x0000001e 0x0000001f 0x0000001f 0x00000020 0x00000020 0x00000021 0x00000021 0x00000022 0x00000022 0x00000023 0x00000023 0x00000024 0x00000024 0x00000025 0x00000025 0x00000026 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f 0x00000030 0x00000031 0x00000032 0x00000033 0x00000034 0x00000035 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x0000003e 0x0000003f 0x00000040 0x00000041 0x00000042 0x00000043 0x00000044 0x00000045 0x00000046 0x00000047 0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c 0x0000004d 0x0000004e 0x0000004f 0x00000050 0x00000051 0x00000052 0x00000053 0x00000054 0x00000055 0x00000056 0x00000057 0x00000058 0x00000059 0x0000005a 0x0000005b 0x0000005c 0x0000005d 0x0000005e 0x0000005f 0x00000060 0x00000061 0x00000062 0x00000063 0x00000064 0x00000065 0x00000066 0x00000067 0x00000068 0x00000069 0x0000006a 0x0000006b 0x0000006c 0x0000006d 0x0000006e 0x0000006f 0x00000070 0x00000071 0x00000072 0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000007a 0x0000007b 0x0000007c 0x0000007d 0x0000007e 0x0000007f 0x00000080 0x00000081 0x00000082 0x00000083 0x00000084 0x00000085 0x00000086 0x00000087 0x00000088 0x00000089 0x0000008a 0x0000008b 0x0000008c 0x0000008d 0x0000008e 0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094 0x00000095 0x00000096 0x00000097 0x00000098 0x00000099 0x0000009a 0x0000009b 0x0000009c 0x0000009d 0x0000009e 0x0000009f 0x000000a0 0x000000a1 0x000000a2 0x000000a3 0x000000a4 0x000000a5 0x000000a6 0x000000a7 0x000000a8 0x000000a9 0x000000aa 0x000000ab 0x000000ac 0x000000ad 0x000000ae 0x000000af 0x000000b0 0x000000b1 0x000000b2 0x000000b3 0x000000b4 0x000000b5 0x000000b6 0x000000b7 0x000000b8 0x000000b9 0x000000ba 0x000000bb 0x000000bc 0x000000bd 0x000000be 0x000000bf 0x000000c0 0x000000c1 0x000000c2 0x000000c3 0x000000c4 0x000000c5 0x000000c6 0x000000c7 0x000000c8 0x000000c9 0x000000ca 0x000000cb 0x000000cc 0x000000cd 0x000000ce 0x000000cf 0x000000d0 0x000000d1 0x000000d2 0x000000d3 0x000000d4 0x000000d5 0x000000d6 0x000000d7 0x000000d8 0x000000d9 0x000000da 0x000000db 0x000000dc 0x000000dd 0x000000de 0x000000df 0x000000e0 0x000000e1 0x000000e2 0x000000e3 0x000000e4 0x000000e5 0x000000e6 0x000000e7 0x000000e8 0x000000e9 0x000000ea 0x000000eb 0x000000ec 0x000000ed 0x000000ee 0x000000ef 0x000000f0 0x000000f1 0x000000f2 0x000000f3 0x000000f4 0x000000f5 0x000000f6 0x000000f7 0x000000f8 0x000000f9 0x000000fa 0x000000fb 0x000000fc 0x000000fd 0x000000fe 0x000000ff>;
        default-brightness-level = <0x000000c8>;
        phandle = <0x0000009a>;
    };
    dc-12v {
        compatible = "regulator-fixed";
        regulator-name = "dc_12v";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00b71b00>;
        regulator-max-microvolt = <0x00b71b00>;
        phandle = <0x00000129>;
    };
    hdmi-sound {
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,mclk-fs = <0x00000080>;
        simple-audio-card,name = "rockchip,hdmi";
        status = "okay";
        phandle = <0x000001ce>;
        simple-audio-card,cpu {
            sound-dai = <0x00000121>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000122>;
        };
    };
    dummy-codec {
        status = "disabled";
        compatible = "rockchip,dummy-codec";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000124>;
    };
    pdm-mic-array {
        status = "disabled";
        compatible = "simple-audio-card";
        simple-audio-card,name = "rockchip,pdm-mic-array";
        phandle = <0x000001cf>;
        simple-audio-card,cpu {
            sound-dai = <0x00000123>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000124>;
        };
    };
    rk809-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,format = "i2s";
        simple-audio-card,name = "rockchip,rk809-codec";
        simple-audio-card,mclk-fs = <0x00000100>;
        phandle = <0x000001d0>;
        simple-audio-card,cpu {
            sound-dai = <0x0000011d>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000125>;
        };
    };
    spdif-sound {
        status = "okay";
        compatible = "simple-audio-card";
        simple-audio-card,name = "ROCKCHIP,SPDIF";
        simple-audio-card,cpu {
            sound-dai = <0x00000126>;
        };
        simple-audio-card,codec {
            sound-dai = <0x00000127>;
        };
    };
    spdif-out {
        status = "okay";
        compatible = "linux,spdif-dit";
        #sound-dai-cells = <0x00000000>;
        phandle = <0x00000127>;
    };
    vad-sound {
        status = "disabled";
        compatible = "rockchip,multicodecs-card";
        rockchip,card-name = "rockchip,rk3568-vad";
        rockchip,cpu = <0x000000c6>;
        rockchip,codec = <0x00000125 0x00000128>;
        phandle = <0x000001d1>;
    };
    vcc3v3-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x00325aa0>;
        regulator-max-microvolt = <0x00325aa0>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003c>;
    };
    vcc5v0-sys {
        compatible = "regulator-fixed";
        regulator-name = "vcc5v0_sys";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <0x004c4b40>;
        regulator-max-microvolt = <0x004c4b40>;
        vin-supply = <0x00000129>;
        phandle = <0x0000003e>;
    };
    vcc5v0-host-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000006 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012a>;
        regulator-name = "vcc5v0_host";
        regulator-always-on;
        phandle = <0x0000010c>;
    };
    vcc5v0-otg-regulator {
        compatible = "regulator-fixed";
        enable-active-high;
        gpio = <0x00000035 0x00000005 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012b>;
        regulator-name = "vcc5v0_otg";
        phandle = <0x0000010d>;
    };
    vcc3v3-lcd0-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd0_n";
        regulator-boot-on;
        gpio = <0x00000035 0x00000010 0x00000000>;
        enable-active-high;
        phandle = <0x00000092>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    vcc3v3-lcd1-n {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_lcd1_n";
        regulator-boot-on;
        phandle = <0x0000009b>;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
    sdio-pwrseq {
        compatible = "mmc-pwrseq-simple";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012d>;
        post-power-on-delay-ms = <0x000000c8>;
        reset-gpios = <0x0000012e 0x00000009 0x00000001>;
        phandle = <0x000000b1>;
    };
    wireless-wlan {
        compatible = "wlan-platdata";
        rockchip,grf = <0x00000032>;
        wifi_chip_type = "ap6398s";
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <0x0000012f>;
        WIFI,host_wake_irq = <0x0000012e 0x0000000a 0x00000000>;
        phandle = <0x000001d2>;
    };
    wireless-bluetooth {
        compatible = "bluetooth-platdata";
        clocks = <0x0000012c 0x00000001>;
        clock-names = "ext_clock";
        uart_rts_gpios = <0x0000012e 0x0000000d 0x00000001>;
        pinctrl-names = "default", "rts_gpio";
        pinctrl-0 = <0x00000130>;
        pinctrl-1 = <0x00000131>;
        BT,reset_gpio = <0x0000012e 0x0000000f 0x00000000>;
        BT,wake_gpio = <0x0000012e 0x00000011 0x00000000>;
        BT,wake_host_irq = <0x0000012e 0x00000010 0x00000000>;
        status = "okay";
        phandle = <0x000001d3>;
    };
    test-power {
        status = "okay";
    };
    rk-headset {
        compatible = "rockchip_headset";
        headset_gpio = <0x0000009c 0x0000000b 0x00000001>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000132>;
        phandle = <0x000001d4>;
    };
    vcc3v3-vga {
        compatible = "regulator-fixed";
        regulator-name = "vcc3v3_vga";
        regulator-always-on;
        regulator-boot-on;
        gpio = <0x0000009c 0x0000000a 0x00000000>;
        enable-active-high;
        vin-supply = <0x0000003c>;
        phandle = <0x000001d5>;
    };
    vcc-camera-regulator {
        compatible = "regulator-fixed";
        gpio = <0x00000035 0x00000011 0x00000000>;
        pinctrl-names = "default";
        pinctrl-0 = <0x00000133>;
        regulator-name = "vcc_camera";
        enable-active-high;
        regulator-always-on;
        regulator-boot-on;
        phandle = <0x000001d6>;
    };
    chosen {
        bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0";
        phandle = <0x000001d7>;
    };
    fiq-debugger {
        compatible = "rockchip,fiq-debugger";
        rockchip,serial-id = <0x00000002>;
        rockchip,wake-irq = <0x00000000>;
        rockchip,irq-mode-enable = <0x00000001>;
        rockchip,baudrate = <0x0016e360>;
        interrupts = <0x00000000 0x000000fc 0x00000008>;
        pinctrl-names = "default";
        pinctrl-0 = <0x000000ed>;
        status = "okay";
    };
    debug@fd904000 {
        compatible = "rockchip,debug";
        reg = <0x00000000 0xfd904000 0x00000000 0x00001000 0x00000000 0xfd905000 0x00000000 0x00001000 0x00000000 0xfd906000 0x00000000 0x00001000 0x00000000 0xfd907000 0x00000000 0x00001000>;
        phandle = <0x000001d8>;
    };
    cspmu@fd90c000 {
        compatible = "rockchip,cspmu";
        reg = <0x00000000 0xfd90c000 0x00000000 0x00001000 0x00000000 0xfd90d000 0x00000000 0x00001000 0x00000000 0xfd90e000 0x00000000 0x00001000 0x00000000 0xfd90f000 0x00000000 0x00001000>;
        phandle = <0x000001d9>;
    };
    leds {
        compatible = "gpio-leds";
        power-green {
            gpios = <0x00000035 0x0000001b 0x00000001>;
            linux,default-trigger = "none";
            default-state = "off";
        };
        power-red {
            gpios = <0x00000035 0x0000001c 0x00000000>;
            linux,default-trigger = "none";
            default-state = "off";
        };
    };
    fddis_dev {
        compatible = "fddis_dev";
        fddis_gpio_clk = <0x00000035 0x0000000b 0x00000000>;
        fddis_gpio_dat = <0x00000035 0x0000000c 0x00000000>;
        status = "okay";
    };
    resume_reboot {
        compatible = "resume_reboot";
        status = "okay";
    };
    __symbols__ {
        ddr_timing = "/ddr_timing";
        cpu0 = "/cpus/cpu@0";
        cpu1 = "/cpus/cpu@100";
        cpu2 = "/cpus/cpu@200";
        cpu3 = "/cpus/cpu@300";
        CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
        cpu0_opp_table = "/cpu0-opp-table";
        display_subsystem = "/display-subsystem";
        route_dsi0 = "/display-subsystem/route/route-dsi0";
        route_dsi1 = "/display-subsystem/route/route-dsi1";
        route_edp = "/display-subsystem/route/route-edp";
        route_hdmi = "/display-subsystem/route/route-hdmi";
        route_lvds = "/display-subsystem/route/route-lvds";
        route_rgb = "/display-subsystem/route/route-rgb";
        optee = "/firmware/optee";
        scmi = "/firmware/scmi";
        scmi_clk = "/firmware/scmi/protocol@14";
        sdei = "/firmware/sdei";
        mpp_srv = "/mpp-srv";
        reserved_memory = "/reserved-memory";
        drm_logo = "/reserved-memory/drm-logo@00000000";
        drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000";
        ramoops = "/reserved-memory/ramoops@110000";
        rockchip_suspend = "/rockchip-suspend";
        rockchip_system_monitor = "/rockchip-system-monitor";
        thermal_zones = "/thermal-zones";
        soc_thermal = "/thermal-zones/soc-thermal";
        threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
        target = "/thermal-zones/soc-thermal/trips/trip-point-1";
        soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
        gpu_thermal = "/thermal-zones/gpu-thermal";
        gmac1_clkin = "/external-gmac1-clock";
        gmac1_xpcsclk = "/xpcs-gmac1-clock";
        i2s1_mclkin_rx = "/i2s1-mclkin-rx";
        i2s1_mclkin_tx = "/i2s1-mclkin-tx";
        i2s2_mclkin = "/i2s2-mclkin";
        i2s3_mclkin = "/i2s3-mclkin";
        mpll = "/mpll";
        xin24m = "/xin24m";
        xin32k = "/xin32k";
        scmi_shmem = "/scmi-shmem@10f000";
        sata1 = "/sata@fc400000";
        sata2 = "/sata@fc800000";
        usbdrd30 = "/usbdrd";
        usbdrd_dwc3 = "/usbdrd/dwc3@fcc00000";
        usbhost30 = "/usbhost";
        usbhost_dwc3 = "/usbhost/dwc3@fd000000";
        gic = "/interrupt-controller@fd400000";
        its = "/interrupt-controller@fd400000/interrupt-controller@fd440000";
        usb_host0_ehci = "/usb@fd800000";
        usb_host0_ohci = "/usb@fd840000";
        usb_host1_ehci = "/usb@fd880000";
        usb_host1_ohci = "/usb@fd8c0000";
        xpcs = "/syscon@fda00000";
        pmugrf = "/syscon@fdc20000";
        pmu_io_domains = "/syscon@fdc20000/io-domains";
        reboot_mode = "/syscon@fdc20000/reboot-mode";
        pipegrf = "/syscon@fdc50000";
        grf = "/syscon@fdc60000";
        io_domains = "/syscon@fdc60000/io-domains";
        lvds = "/syscon@fdc60000/lvds";
        lvds_in_vp1 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@1";
        lvds_in_vp2 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@2";
        rgb = "/syscon@fdc60000/rgb";
        rgb_in_vp2 = "/syscon@fdc60000/rgb/ports/port@0/endpoint@2";
        pipe_phy_grf0 = "/syscon@fdc70000";
        pipe_phy_grf1 = "/syscon@fdc80000";
        pipe_phy_grf2 = "/syscon@fdc90000";
        usb2phy0_grf = "/syscon@fdca0000";
        usb2phy1_grf = "/syscon@fdca8000";
        edp_phy = "/edp-phy@fdcb0000";
        sram = "/sram@fdcc0000";
        rkvdec_sram = "/sram@fdcc0000/rkvdec-sram@0";
        pmucru = "/clock-controller@fdd00000";
        cru = "/clock-controller@fdd20000";
        i2c0 = "/i2c@fdd40000";
        rk809 = "/i2c@fdd40000/pmic@20";
        pinctrl_rk8xx = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx";
        rk817_slppin_null = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_null";
        rk817_slppin_slp = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_slp";
        rk817_slppin_pwrdn = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_pwrdn";
        rk817_slppin_rst = "/i2c@fdd40000/pmic@20/pinctrl_rk8xx/rk817_slppin_rst";
        vdd_logic = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG1";
        vdd_gpu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG2";
        vcc_ddr = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG3";
        vdd_npu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG4";
        vdda0v9_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG1";
        vdda_0v9 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG2";
        vdda0v9_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG3";
        vccio_acodec = "/i2c@fdd40000/pmic@20/regulators/LDO_REG4";
        vccio_sd = "/i2c@fdd40000/pmic@20/regulators/LDO_REG5";
        vcc3v3_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG6";
        vcca_1v8 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG7";
        vcca1v8_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG8";
        vcca1v8_image = "/i2c@fdd40000/pmic@20/regulators/LDO_REG9";
        vcc_1v8 = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG5";
        vcc_3v3 = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG1";
        vcc3v3_sd = "/i2c@fdd40000/pmic@20/regulators/SWITCH_REG2";
        rk809_codec = "/i2c@fdd40000/pmic@20/codec";
        vdd_cpu = "/i2c@fdd40000/tcs4526@10";
        uart0 = "/serial@fdd50000";
        pwm0 = "/pwm@fdd70000";
        pwm1 = "/pwm@fdd70010";
        pwm2 = "/pwm@fdd70020";
        pwm3 = "/pwm@fdd70030";
        pmu = "/power-management@fdd90000";
        power = "/power-management@fdd90000/power-controller";
        rknpu = "/npu@fde40000";
        npu_opp_table = "/npu-opp-table";
        bus_npu = "/bus-npu";
        bus_npu_opp_table = "/bus-npu-opp-table";
        rknpu_mmu = "/iommu@fde4b000";
        gpu = "/gpu@fde60000";
        gpu_power_model = "/gpu@fde60000/power-model";
        gpu_opp_table = "/opp-table2";
        vdpu = "/vdpu@fdea0400";
        vdpu_mmu = "/iommu@fdea0800";
        rk_rga = "/rk_rga@fdeb0000";
        ebc = "/ebc@fdec0000";
        jpegd = "/jpegd@fded0000";
        jpegd_mmu = "/iommu@fded0480";
        vepu = "/vepu@fdee0000";
        vepu_mmu = "/iommu@fdee0800";
        iep = "/iep@fdef0000";
        iep_mmu = "/iommu@fdef0800";
        eink = "/eink@fdf00000";
        rkvenc = "/rkvenc@fdf40000";
        rkvenc_opp_table = "/rkvenc-opp-table";
        rkvenc_mmu = "/iommu@fdf40f00";
        rkvdec = "/rkvdec@fdf80200";
        rkvdec_mmu = "/iommu@fdf80800";
        mipi_csi2 = "/mipi-csi2@fdfb0000";
        rkcif = "/rkcif@fdfe0000";
        rkcif_mmu = "/iommu@fdfe0800";
        rkcif_dvp = "/rkcif_dvp";
        dvp_in_bcam = "/rkcif_dvp/port/endpoint";
        rkcif_dvp_sditf = "/rkcif_dvp_sditf";
        rkcif_mipi_lvds = "/rkcif_mipi_lvds";
        rkcif_mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf";
        rkisp = "/rkisp@fdff0000";
        rkisp_mmu = "/iommu@fdff1a00";
        rkisp_vir0 = "/rkisp-vir0";
        isp0_in = "/rkisp-vir0/port/endpoint@0";
        rkisp_vir1 = "/rkisp-vir1";
        gmac1 = "/ethernet@fe010000";
        mdio1 = "/ethernet@fe010000/mdio";
        rgmii_phy1 = "/ethernet@fe010000/mdio/phy@0";
        gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config";
        gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config";
        gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config";
        vop = "/vop@fe040000";
        vop_out = "/vop@fe040000/ports";
        vp0 = "/vop@fe040000/ports/port@0";
        vp0_out_dsi0 = "/vop@fe040000/ports/port@0/endpoint@0";
        vp0_out_dsi1 = "/vop@fe040000/ports/port@0/endpoint@1";
        vp0_out_edp = "/vop@fe040000/ports/port@0/endpoint@2";
        vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@3";
        vp1 = "/vop@fe040000/ports/port@1";
        vp1_out_dsi0 = "/vop@fe040000/ports/port@1/endpoint@0";
        vp1_out_dsi1 = "/vop@fe040000/ports/port@1/endpoint@1";
        vp1_out_edp = "/vop@fe040000/ports/port@1/endpoint@2";
        vp1_out_hdmi = "/vop@fe040000/ports/port@1/endpoint@3";
        vp1_out_lvds = "/vop@fe040000/ports/port@1/endpoint@4";
        vp2 = "/vop@fe040000/ports/port@2";
        vp2_out_lvds = "/vop@fe040000/ports/port@2/endpoint@0";
        vp2_out_rgb = "/vop@fe040000/ports/port@2/endpoint@1";
        vop_mmu = "/iommu@fe043e00";
        dsi0 = "/dsi@fe060000";
        dsi0_in = "/dsi@fe060000/ports/port@0";
        dsi0_in_vp0 = "/dsi@fe060000/ports/port@0/endpoint@0";
        dsi0_in_vp1 = "/dsi@fe060000/ports/port@0/endpoint@1";
        dsi_out_panel = "/dsi@fe060000/ports/port@1/endpoint";
        dsi0_panel = "/dsi@fe060000/panel@0";
        disp_timings0 = "/dsi@fe060000/panel@0/display-timings";
        dsi0_timing0 = "/dsi@fe060000/panel@0/display-timings/timing0";
        panel_in_dsi = "/dsi@fe060000/panel@0/ports/port@0/endpoint";
        dsi1 = "/dsi@fe070000";
        dsi1_in = "/dsi@fe070000/ports/port@0";
        dsi1_in_vp0 = "/dsi@fe070000/ports/port@0/endpoint@0";
        dsi1_in_vp1 = "/dsi@fe070000/ports/port@0/endpoint@1";
        dsi1_out_panel = "/dsi@fe070000/ports/port@1/endpoint";
        dsi1_panel = "/dsi@fe070000/panel@0";
        disp_timings1 = "/dsi@fe070000/panel@0/display-timings";
        dsi1_timing0 = "/dsi@fe070000/panel@0/display-timings/timing0";
        panel_in_dsi1 = "/dsi@fe070000/panel@0/ports/port@0/endpoint";
        hdmi = "/hdmi@fe0a0000";
        hdmi_in = "/hdmi@fe0a0000/ports/port";
        hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port/endpoint@0";
        hdmi_in_vp1 = "/hdmi@fe0a0000/ports/port/endpoint@1";
        edp = "/edp@fe0c0000";
        edp_in = "/edp@fe0c0000/ports/port@0";
        edp_in_vp0 = "/edp@fe0c0000/ports/port@0/endpoint@0";
        edp_in_vp1 = "/edp@fe0c0000/ports/port@0/endpoint@1";
        qos_gpu = "/qos@fe128000";
        qos_rkvenc_rd_m0 = "/qos@fe138080";
        qos_rkvenc_rd_m1 = "/qos@fe138100";
        qos_rkvenc_wr_m0 = "/qos@fe138180";
        qos_isp = "/qos@fe148000";
        qos_vicap0 = "/qos@fe148080";
        qos_vicap1 = "/qos@fe148100";
        qos_vpu = "/qos@fe150000";
        qos_ebc = "/qos@fe158000";
        qos_iep = "/qos@fe158100";
        qos_jpeg_dec = "/qos@fe158180";
        qos_jpeg_enc = "/qos@fe158200";
        qos_rga_rd = "/qos@fe158280";
        qos_rga_wr = "/qos@fe158300";
        qos_npu = "/qos@fe180000";
        qos_pcie2x1 = "/qos@fe190000";
        qos_sata1 = "/qos@fe190280";
        qos_sata2 = "/qos@fe190300";
        qos_usb3_0 = "/qos@fe190380";
        qos_usb3_1 = "/qos@fe190400";
        qos_rkvdec = "/qos@fe198000";
        qos_hdcp = "/qos@fe1a8000";
        qos_vop_m0 = "/qos@fe1a8080";
        qos_vop_m1 = "/qos@fe1a8100";
        sdmmc2 = "/dwmmc@fe000000";
        dfi = "/dfi@fe230000";
        dmc = "/dmc";
        dmc_opp_table = "/dmc-opp-table";
        pcie2x1 = "/pcie@fe260000";
        pcie2x1_intc = "/pcie@fe260000/legacy-interrupt-controller";
        sdmmc0 = "/dwmmc@fe2b0000";
        sdmmc1 = "/dwmmc@fe2c0000";
        sfc = "/sfc@fe300000";
        sdhci = "/sdhci@fe310000";
        nandc0 = "/nandc@fe330000";
        crypto = "/crypto@fe380000";
        rng = "/rng@fe388000";
        otp = "/otp@fe38c000";
        cpu_code = "/otp@fe38c000/cpu-code@2";
        otp_cpu_version = "/otp@fe38c000/cpu-version@8";
        mbist_vmin = "/otp@fe38c000/mbist-vmin@9";
        otp_id = "/otp@fe38c000/id@a";
        cpu_leakage = "/otp@fe38c000/cpu-leakage@1a";
        log_leakage = "/otp@fe38c000/log-leakage@1b";
        npu_leakage = "/otp@fe38c000/npu-leakage@1c";
        gpu_leakage = "/otp@fe38c000/gpu-leakage@1d";
        core_pvtm = "/otp@fe38c000/core-pvtm@2a";
        i2s0_8ch = "/i2s@fe400000";
        i2s1_8ch = "/i2s@fe410000";
        i2s2_2ch = "/i2s@fe420000";
        i2s3_2ch = "/i2s@fe430000";
        pdm = "/pdm@fe440000";
        vad = "/vad@fe450000";
        spdif_8ch = "/spdif@fe460000";
        audpwm = "/audpwm@fe470000";
        dig_acodec = "/codec-digital@fe478000";
        dmac0 = "/dmac@fe530000";
        dmac1 = "/dmac@fe550000";
        scr = "/rkscr@fe560000";
        can0 = "/can@fe570000";
        can1 = "/can@fe580000";
        can2 = "/can@fe590000";
        i2c1 = "/i2c@fe5a0000";
        gt1x = "/i2c@fe5a0000/gt1x@14";
        i2c2 = "/i2c@fe5b0000";
        gc2145 = "/i2c@fe5b0000/gc2145@3c";
        gc2145_out = "/i2c@fe5b0000/gc2145@3c/port/endpoint";
        ov5695 = "/i2c@fe5b0000/ov5695@36";
        ov5695_out = "/i2c@fe5b0000/ov5695@36/port/endpoint";
        gc8034 = "/i2c@fe5b0000/gc8034@37";
        gc8034_out = "/i2c@fe5b0000/gc8034@37/port/endpoint";
        i2c3 = "/i2c@fe5c0000";
        i2c4 = "/i2c@fe5d0000";
        i2c5 = "/i2c@fe5e0000";
        mxc6655xa = "/i2c@fe5e0000/mxc6655xa@15";
        rktimer = "/timer@fe5f0000";
        wdt = "/watchdog@fe600000";
        spi0 = "/spi@fe610000";
        spi1 = "/spi@fe620000";
        spi2 = "/spi@fe630000";
        spi3 = "/spi@fe640000";
        uart1 = "/serial@fe650000";
        uart2 = "/serial@fe660000";
        uart3 = "/serial@fe670000";
        uart4 = "/serial@fe680000";
        uart5 = "/serial@fe690000";
        uart6 = "/serial@fe6a0000";
        uart7 = "/serial@fe6b0000";
        uart8 = "/serial@fe6c0000";
        uart9 = "/serial@fe6d0000";
        pwm4 = "/pwm@fe6e0000";
        pwm5 = "/pwm@fe6e0010";
        pwm6 = "/pwm@fe6e0020";
        pwm7 = "/pwm@fe6e0030";
        pwm8 = "/pwm@fe6f0000";
        pwm9 = "/pwm@fe6f0010";
        pwm10 = "/pwm@fe6f0020";
        pwm11 = "/pwm@fe6f0030";
        pwm12 = "/pwm@fe700000";
        pwm13 = "/pwm@fe700010";
        pwm14 = "/pwm@fe700020";
        pwm15 = "/pwm@fe700030";
        tsadc = "/tsadc@fe710000";
        saradc = "/saradc@fe720000";
        mailbox = "/mailbox@fe780000";
        combphy1_usq = "/phy@fe830000";
        combphy2_psq = "/phy@fe840000";
        mipi_dphy0 = "/mipi-dphy@fe850000";
        video_phy0 = "/video-phy@fe850000";
        mipi_dphy1 = "/mipi-dphy@fe860000";
        csi2_dphy_hw = "/csi2-dphy-hw@fe870000";
        csi2_dphy0 = "/csi2-dphy0";
        mipi_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1";
        mipi_in_ucam1 = "/csi2-dphy0/ports/port@0/endpoint@2";
        csidphy_out = "/csi2-dphy0/ports/port@1/endpoint@0";
        csi2_dphy1 = "/csi2-dphy1";
        csi2_dphy2 = "/csi2-dphy2";
        usb2phy0 = "/usb2-phy@fe8a0000";
        u2phy0_host = "/usb2-phy@fe8a0000/host-port";
        u2phy0_otg = "/usb2-phy@fe8a0000/otg-port";
        usb2phy1 = "/usb2-phy@fe8b0000";
        u2phy1_host = "/usb2-phy@fe8b0000/host-port";
        u2phy1_otg = "/usb2-phy@fe8b0000/otg-port";
        pinctrl = "/pinctrl";
        gpio0 = "/pinctrl/gpio@fdd60000";
        gpio1 = "/pinctrl/gpio@fe740000";
        gpio2 = "/pinctrl/gpio@fe750000";
        gpio3 = "/pinctrl/gpio@fe760000";
        gpio4 = "/pinctrl/gpio@fe770000";
        pcfg_pull_up = "/pinctrl/pcfg-pull-up";
        pcfg_pull_down = "/pinctrl/pcfg-pull-down";
        pcfg_pull_none = "/pinctrl/pcfg-pull-none";
        pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
        pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
        pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
        pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
        pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
        pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
        pcfg_output_low = "/pinctrl/pcfg-output-low";
        acodec_pins = "/pinctrl/acodec/acodec-pins";
        cam_clkout0 = "/pinctrl/cam/cam-clkout0";
        camera_pwr = "/pinctrl/cam/camera-pwr";
        can0m1_pins = "/pinctrl/can0/can0m1-pins";
        can1m1_pins = "/pinctrl/can1/can1m1-pins";
        can2m1_pins = "/pinctrl/can2/can2m1-pins";
        cif_clk = "/pinctrl/cif/cif-clk";
        cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
        cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
        clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
        ebc_pins = "/pinctrl/ebc/ebc-pins";
        gmac1m0_miim = "/pinctrl/gmac1/gmac1m0-miim";
        gmac1m0_rx_bus2 = "/pinctrl/gmac1/gmac1m0-rx-bus2";
        hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec";
        hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl";
        hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda";
        i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
        i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
        i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer";
        i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
        i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
        i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
        i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx";
        i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx";
        i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
        i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
        i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx";
        i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx";
        i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi";
        i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo";
        i2s3m1_lrck = "/pinctrl/i2s3/i2s3m1-lrck";
        i2s3m1_mclk = "/pinctrl/i2s3/i2s3m1-mclk";
        i2s3m1_sclk = "/pinctrl/i2s3/i2s3m1-sclk";
        i2s3m1_sdi = "/pinctrl/i2s3/i2s3m1-sdi";
        i2s3m1_sdo = "/pinctrl/i2s3/i2s3m1-sdo";
        lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl";
        pdmm1_clk1 = "/pinctrl/pdm/pdmm1-clk1";
        pdmm1_sdi1 = "/pinctrl/pdm/pdmm1-sdi1";
        pdmm1_sdi2 = "/pinctrl/pdm/pdmm1-sdi2";
        pdmm1_sdi3 = "/pinctrl/pdm/pdmm1-sdi3";
        pmic_int = "/pinctrl/pmic/pmic_int";
        soc_slppin_gpio = "/pinctrl/pmic/soc_slppin_gpio";
        soc_slppin_slp = "/pinctrl/pmic/soc_slppin_slp";
        soc_slppin_rst = "/pinctrl/pmic/soc_slppin_rst";
        pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
        pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
        pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
        pwm3_pins = "/pinctrl/pwm3/pwm3-pins";
        pwm4_pins = "/pinctrl/pwm4/pwm4-pins";
        pwm5_pins = "/pinctrl/pwm5/pwm5-pins";
        pwm6_pins = "/pinctrl/pwm6/pwm6-pins";
        pwm7_pins = "/pinctrl/pwm7/pwm7-pins";
        pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
        pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
        pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
        pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
        pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
        pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
        pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
        pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
        scr_pins = "/pinctrl/scr/scr-pins";
        sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4";
        sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk";
        sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd";
        sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det";
        sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4";
        sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk";
        sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd";
        spdifm0_tx = "/pinctrl/spdif/spdifm0-tx";
        spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
        spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
        spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
        spi1m0_pins = "/pinctrl/spi1/spi1m0-pins";
        spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0";
        spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1";
        spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
        spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
        spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
        spi3m0_pins = "/pinctrl/spi3/spi3m0-pins";
        spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0";
        spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1";
        tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg";
        uart0_xfer = "/pinctrl/uart0/uart0-xfer";
        uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer";
        uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn";
        uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn";
        uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
        uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
        uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
        uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
        uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer";
        uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer";
        uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
        uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer";
        spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins";
        spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins";
        spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins";
        spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins";
        gmac1m0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-tx-bus2-level3";
        gmac1m0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-rgmii-bus-level3";
        gmac1m0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m0-rgmii-clk-level2";
        tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func";
        mxc6655xa_irq_gpio = "/pinctrl/mxc6655xa/mxc6655xa_irq_gpio";
        touch_gpio = "/pinctrl/touch/touch-gpio";
        wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h";
        vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en";
        vcc5v0_otg_en = "/pinctrl/usb/vcc5v0-otg-en";
        uart8_gpios = "/pinctrl/wireless-bluetooth/uart8-gpios";
        uart1_gpios = "/pinctrl/wireless-bluetooth/uart1-gpios";
        hp_det = "/pinctrl/headphone/hp-det";
        lcd0_rst_gpio = "/pinctrl/lcd0/lcd-rst-gpio";
        lcd1_rst_gpio = "/pinctrl/lcd1/lcd1-rst-gpio";
        wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq";
        dis_ctl = "/pinctrl/fddis_ctr/dis-ctl";
        adc_keys = "/adc-keys";
        audiopwmout_diff = "/audiopwmout-diff";
        master = "/audiopwmout-diff/simple-audio-card,codec";
        backlight = "/backlight";
        backlight1 = "/backlight1";
        dc_12v = "/dc-12v";
        hdmi_sound = "/hdmi-sound";
        pdmics = "/dummy-codec";
        pdm_mic_array = "/pdm-mic-array";
        rk809_sound = "/rk809-sound";
        spdif_out = "/spdif-out";
        vad_sound = "/vad-sound";
        vcc3v3_sys = "/vcc3v3-sys";
        vcc5v0_sys = "/vcc5v0-sys";
        vcc5v0_host = "/vcc5v0-host-regulator";
        vcc5v0_otg = "/vcc5v0-otg-regulator";
        vcc3v3_lcd0_n = "/vcc3v3-lcd0-n";
        vcc3v3_lcd1_n = "/vcc3v3-lcd1-n";
        sdio_pwrseq = "/sdio-pwrseq";
        wireless_wlan = "/wireless-wlan";
        wireless_bluetooth = "/wireless-bluetooth";
        rk_headset = "/rk-headset";
        vcc3v3_vga = "/vcc3v3-vga";
        vcc_camera = "/vcc-camera-regulator";
        chosen = "/chosen";
        debug = "/debug@fd904000";
        cspmu = "/cspmu@fd90c000";
    };
};
 



 

Quote

 

Arquivo .conf
/home/ubuntu/armbian/build/config/boards
/home/ubuntu/armbian/build/cache/sources/u-boot/rk356x/configs/firefly-rk3566.config

Arquivo .Patch
/home/ubuntu/armbian/build/patch/kernel/archive/media-6.0

Arquivo .dtb
/home/ubuntu/armbian/build/cache/sources/u-boot/rk356x/arch/arm/dts
/home/ubuntu/armbian/build/cache/sources/linux-rockchip64/kernel-4.19/arch/arm64/boot/dts/rockchip
Arquivo .dts
/home/ubuntu/armbian/build/cache/sources/u-boot/rk356x/arch/arm/dts
/home/ubuntu/armbian/build/cache/sources/linux-rockchip64/kernel-4.19/arch/arm64/boot/dts/rockchip

 

 

Edited by hotnikq
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Hqnicolas

Hqnicolas

Posted
  • Author
Posted (edited)

When boot kernel, i found some problems over HDMi No driver support for vblank timestamp query

infinite loop Screen over HDMi with 4gb Cards and DTB1 file

Quote


[   62.034127] Video Port0: ACTIVE
[   62.037370]     Connector: HDMI-A-1
[   62.040638]  bus_format[2025]: YUV8_1X24
[   62.043939]  overlay_mode[1] output_mode[f]
[   62.043941]  color_space[3]
[   62.050606]     Display mode: 3840x2160p30
[   62.053992]  clk[297000] real_clk[297000] type[48] flag[5]
[   62.057434]  H: 3840 4016 4104 4400
[   62.060893]  V: 2160 2168 2178 2250
[   62.064324]     Smart1-win0: ACTIVE
[   62.067740]  win_id: 1
[   62.071162]  format: XR24 little-endian (0x34325258) SDR[0] color_space[0] glb_alpha[0xff]
[   62.074725]  rotate: xmirror: 0 ymirror: 0 rotate_90: 0 rotate_270: 0
[   62.078338]  csc: y2r[0] r2y[1] csc mode[1]
[   62.081973]  zpos: 1
[   62.085611]  src: pos[0, 0] rect[3840 x 2160]
[   62.089302]  dst: pos[0, 0] rect[3840 x 2160]
[   62.092994]  buf[0]: addr: 0x0000000000000000 pitch: 15360 offset: 0
[   62.096758] Video Port1: DISABLED
[   62.100540] rk_iommu fe043e00.iommu: Page fault at 0x00000000edf00000 of type read
[   62.104434] rk_iommu fe043e00.iommu: iova = 0x00000000edf00000: dte_index: 0x3b7 pte_index: 0x300 page_offset: 0x0
[   62.108433] rk_iommu fe043e00.iommu: mmu_dte_addr: 0x00000000e80cf000 dte@0x00000000e80cfedc: 0xe8256001 valid: 1 pte@0x00000000e8256c00: 0xe      df00006 valid: 0 page@0x0000000000000000 flags: 0x0
[   62.112652] [drm:rockchip_drm_fault_handler] *ERROR* iommu fault handler flags: 0x30b
 




Full Kernel Logon:

after that, just loop
 

Quote

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
[    0.000000] Linux version 4.19.219-station-p2 (root@ubuntu) (gcc version 8.3.                                                                                            0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)), GNU                                                                                             ld (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 2.                                                                                            32.0.20190321) #trunk SMP Wed Oct 26 07:02:21 -03 2022
[    0.000000] Machine model: Firefly RK3566-ROC-PC HDMI(Linux)
[    0.000000] Reserved memory: created CMA memory pool at 0x00000001f8000000, s                                                                                            ize 128 MiB
[    0.000000] OF: reserved mem: initialized node rknpu, compatible id shared-dm                                                                                            a-pool
[    0.000000] cma: Reserved 16 MiB at 0x00000000eec00000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 24 pages/cpu s60968 r8192 d29144 u98304
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: Virtualization Host Extensions
[    0.000000] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1027656
[    0.000000] Kernel command line: root=UUID=103cb11d-3ebe-4b1c-af2f-b0fc46bd3b                                                                                            25 console=ttyS02,1500000 console=tty0 rw no_console_suspend consoleblank=0 fsck                                                                                            .fix=yes fsck.repair=yes net.ifnames=0 bootsplash.bootfile=bootsplash.armbian
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes                                                                                            )
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0xe9f00000-0xedf00000] (64MB)
[    0.000000] Memory: 3823636K/4175872K available (17278K kernel code, 2466K rw                                                                                            data, 5600K rodata, 1792K init, 1031K bss, 204780K reserved, 147456K cma-reserve                                                                                            d)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] ftrace: allocating 58128 entries in 228 pages
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: no VLPI support, no direct LPI support
[    0.000000] ITS [mem 0xfd440000-0xfd45ffff]
[    0.000000] ITS@0x00000000fd440000: allocated 8192 Devices @ee810000 (indirec                                                                                            t, esz 8, psz 64K, shr 0)
[    0.000000] ITS@0x00000000fd440000: allocated 32768 Interrupt Collections @ee                                                                                            820000 (flat, esz 2, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GIC: using LPI property table @0x00000000ee830000
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000fd460000
[    0.000000] CPU0: using LPI pending table @0x00000000ee840000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] random: random: get_random_bytes called from start_kernel+0x35c/0                                                                                            x4dc with crng_init=0
[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles:                                                                                             0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000003] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 43980                                                                                            46511097ns
[    0.000847] Console: colour dummy device 80x25
[    0.001195] console [tty0] enabled
[    0.001230] Calibrating delay loop (skipped), value calculated using timer fr                                                                                            equency.. 48.00 BogoMIPS (lpj=80000)
[    0.001248] pid_max: default: 32768 minimum: 301
[    0.001368] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.001389] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.002591] ASID allocator initialised with 32768 entries
[    0.002702] rcu: Hierarchical SRCU implementation.
[    0.004548] Platform MSI: interrupt-controller@fd440000 domain created
[    0.004967] PCI/MSI: /interrupt-controller@fd400000/interrupt-controller@fd44                                                                                            0000 domain created
[    0.005525] smp: Bringing up secondary CPUs ...
[    0.006048] Detected VIPT I-cache on CPU1
[    0.006075] GICv3: CPU1: found redistributor 100 region 0:0x00000000fd480000
[    0.006114] CPU1: using LPI pending table @0x00000000ee850000
[    0.006158] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[    0.006783] Detected VIPT I-cache on CPU2
[    0.006803] GICv3: CPU2: found redistributor 200 region 0:0x00000000fd4a0000
[    0.006841] CPU2: using LPI pending table @0x00000000ee860000
[    0.006874] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
[    0.007391] Detected VIPT I-cache on CPU3
[    0.007409] GICv3: CPU3: found redistributor 300 region 0:0x00000000fd4c0000
[    0.007445] CPU3: using LPI pending table @0x00000000ee870000
[    0.007473] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
[    0.007550] smp: Brought up 1 node, 4 CPUs
[    0.007649] SMP: Total of 4 processors activated.
[    0.007659] CPU features: detected: GIC system register CPU interface
[    0.007668] CPU features: detected: Privileged Access Never
[    0.007677] CPU features: detected: LSE atomic instructions
[    0.007685] CPU features: detected: User Access Override
[    0.007694] CPU features: detected: 32-bit EL0 Support
[    0.007702] CPU features: detected: RAS Extension Support
[    0.007803] CPU: All CPU(s) started at EL2
[    0.007830] alternatives: patching kernel code
[    0.013517] devtmpfs: initialized
[    0.030968] Registered cp15_barrier emulation handler
[    0.030998] Registered setend emulation handler
[    0.031247] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ma                                                                                            x_idle_ns: 6370867519511994 ns
[    0.031272] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.031738] xor: measuring software checksum speed
[    0.062945]    8regs     :  3249.600 MB/sec
[    0.096325]    8regs_prefetch:  2965.200 MB/sec
[    0.129705]    32regs    :  4141.200 MB/sec
[    0.163089]    32regs_prefetch:  3693.600 MB/sec
[    0.163101] xor: using function: 32regs (4141.200 MB/sec)
[    0.163116] pinctrl core: initialized pinctrl subsystem
[    0.163886] NET: Registered protocol family 16
[    0.164404] audit: initializing netlink subsys (disabled)
[    0.164581] audit: type=2000 audit(0.159:1): state=initialized audit_enabled=                                                                                            0 res=1
[    0.166696] cpuidle: using governor menu
[    0.166736] Registered FIQ tty driver
[    0.167106] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.167848] DMA: preallocated 256 KiB pool for atomic allocations
[    0.170296] console [pstore-1] enabled
[    0.170314] pstore: Registered ramoops as persistent store backend
[    0.170326] ramoops: attached 0xf0000@0x110000, ecc: 0/0
[    0.174116] platform fde40000.npu: assigned reserved memory node rknpu
[    0.190782] rockchip-gpio fdd60000.gpio: probed gpio0 (fdd60000.gpio)
[    0.191233] rockchip-gpio fe740000.gpio: probed gpio1 (fe740000.gpio)
[    0.191633] rockchip-gpio fe750000.gpio: probed gpio2 (fe750000.gpio)
[    0.192028] rockchip-gpio fe760000.gpio: probed gpio3 (fe760000.gpio)
[    0.192419] rockchip-gpio fe770000.gpio: probed gpio4 (fe770000.gpio)
[    0.192498] rockchip-pinctrl pinctrl: probed pinctrl
[    0.202418] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.202589] cryptd: max_cpu_qlen set to 1000
[    0.256634] raid6: int64x1  gen()   283 MB/s
[    0.313361] raid6: int64x1  xor()   391 MB/s
[    0.370134] raid6: int64x2  gen()   521 MB/s
[    0.426811] raid6: int64x2  xor()   719 MB/s
[    0.483542] raid6: int64x4  gen()   820 MB/s
[    0.540312] raid6: int64x4  xor()   874 MB/s
[    0.597036] raid6: int64x8  gen()   863 MB/s
[    0.653758] raid6: int64x8  xor()   836 MB/s
[    0.710576] raid6: neonx1   gen()   539 MB/s
[    0.767224] raid6: neonx1   xor()   945 MB/s
[    0.823979] raid6: neonx2   gen()   914 MB/s
[    0.880698] raid6: neonx2   xor()  1282 MB/s
[    0.937437] raid6: neonx4   gen()  1408 MB/s
[    0.994156] raid6: neonx4   xor()  1676 MB/s
[    1.050889] raid6: neonx8   gen()  1441 MB/s
[    1.107640] raid6: neonx8   xor()  1633 MB/s
[    1.107653] raid6: using algorithm neonx8 gen() 1441 MB/s
[    1.107663] raid6: .... xor() 1633 MB/s, rmw enabled
[    1.107674] raid6: using neon recovery algorithm
[    1.107875] fbcon: Taking over console
[    1.109446] console [ttyFIQ0] enabled
[    1.109639] Registered fiq debugger ttyFIQ0
[    1.110325] vcc3v3_sys: supplied by dc_12v
[    1.110612] vcc5v0_sys: supplied by dc_12v
[    1.111655] vcc2v5-sys: supplied by vcc3v3_sys
[    1.111960] vcc3v3_vga: supplied by vcc3v3_sys
[    1.112240] pcie30_avdd0v9: supplied by vcc3v3_sys
[    1.112522] pcie30_avdd1v8: supplied by vcc3v3_sys
[    1.112812] vcc3v3_bu: supplied by vcc5v0_sys
[    1.113915] rk_iommu fdea0800.iommu: version = 2
[    1.114388] rk_iommu fded0480.iommu: version = 2
[    1.114761] rk_iommu fdee0800.iommu: version = 2
[    1.115058] rk_iommu fdef0800.iommu: version = 2
[    1.115304] rk_iommu fdf40f00.iommu: version = 2
[    1.115624] rk_iommu fdf80800.iommu: version = 2
[    1.115904] rk_iommu fdff1a00.iommu: version = 2
[    1.116179] rk_iommu fe043e00.iommu: version = 2
[    1.116854] SCSI subsystem initialized
[    1.117068] usbcore: registered new interface driver usbfs
[    1.117129] usbcore: registered new interface driver hub
[    1.117234] usbcore: registered new device driver usb
[    1.117322] media: Linux media interface: v0.10
[    1.117366] videodev: Linux video capture interface: v2.00
[    1.117439] pps_core: LinuxPPS API ver. 1 registered
[    1.117458] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giome                                                                                            tti <giometti@linux.it>
[    1.117491] PTP clock support registered
[    1.117760] arm-scmi firmware:scmi: SCMI Protocol v2.0 'rockchip:' Firmware v                                                                                            ersion 0x0
[    1.119464] Advanced Linux Sound Architecture Driver Initialized.
[    1.119946] Bluetooth: Core ver 2.22
[    1.119995] NET: Registered protocol family 31
[    1.120013] Bluetooth: HCI device and connection manager initialized
[    1.120041] Bluetooth: HCI socket layer initialized
[    1.120062] Bluetooth: L2CAP socket layer initialized
[    1.120101] Bluetooth: SCO socket layer initialized
[    1.120492] rockchip-cpuinfo cpuinfo: SoC            : 35662000
[    1.120515] rockchip-cpuinfo cpuinfo: Serial         : baedc7b8eb5ab5fa
[    1.121280] clocksource: Switched to clocksource arch_sys_counter
[    1.205723] VFS: Disk quotas dquot_6.6.0
[    1.205822] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.205954] FS-Cache: Loaded
[    1.213811] thermal thermal_zone1: power_allocator: sustainable_power will be                                                                                             estimated
[    1.214131] NET: Registered protocol family 2
[    1.214334] IP idents hash table entries: 65536 (order: 7, 524288 bytes)
[    1.215685] tcp_listen_portaddr_hash hash table entries: 2048 (order: 4, 8192                                                                                            0 bytes)
[    1.215781] TCP established hash table entries: 32768 (order: 6, 262144 bytes                                                                                            )
[    1.215934] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes)
[    1.216716] TCP: Hash tables configured (established 32768 bind 32768)
[    1.216938] UDP hash table entries: 2048 (order: 5, 196608 bytes)
[    1.217140] UDP-Lite hash table entries: 2048 (order: 5, 196608 bytes)
[    1.217508] NET: Registered protocol family 1
[    1.218078] RPC: Registered named UNIX socket transport module.
[    1.218103] RPC: Registered udp transport module.
[    1.218119] RPC: Registered tcp transport module.
[    1.218135] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.219279] Trying to unpack rootfs image as initramfs...
[    1.598300] Freeing initrd memory: 14008K
[    1.599289] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters av                                                                                            ailable
[    1.599817] kvm [1]: 16-bit VMID
[    1.599848] kvm [1]: GICv3: no GICV resource entry
[    1.599866] kvm [1]: disabling GICv2 emulation
[    1.599881] kvm [1]: GIC system register CPU interface enabled
[    1.599988] kvm [1]: vgic interrupt IRQ1
[    1.600123] kvm [1]: VHE mode initialized successfully
[    1.601870] Initialise system trusted keyrings
[    1.602072] workingset: timestamp_bits=45 max_order=20 bucket_order=0
[    1.608375] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    1.609001] NFS: Registering the id_resolver key type
[    1.609043] Key type id_resolver registered
[    1.609061] Key type id_legacy registered
[    1.609534] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[    1.610170] JFS: nTxBlock = 8192, nTxLock = 65536
[    1.615839] SGI XFS with ACLs, security attributes, realtime, no debug enable                                                                                            d
[    1.617526] ocfs2: Registered cluster interface o2cb
[    1.617755] OCFS2 User DLM kernel interface loaded
[    1.619086] gfs2: GFS2 installed
[    1.620839] NET: Registered protocol family 38
[    1.620884] Key type asymmetric registered
[    1.620900] Asymmetric key parser 'x509' registered
[    1.620947] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 2                                                                                            44)
[    1.621084] io scheduler noop registered
[    1.621105] io scheduler deadline registered
[    1.621235] io scheduler cfq registered (default)
[    1.621258] io scheduler mq-deadline registered
[    1.621316] io scheduler kyber registered
[    1.622328] rockchip-csi2-dphy csi2-dphy0: csi2 dphy0 probe successfully!
[    1.622472] rockchip-csi2-dphy-hw fe870000.csi2-dphy-hw: csi2 dphy hw probe s                                                                                            uccessfully!
[    1.624130] phy phy-fe8a0000.usb2-phy.0: Linked as a consumer to regulator.4
[    1.624338] phy phy-fe8a0000.usb2-phy.1: No vbus specified for otg port
[    1.625576] extcon extcon1: failed to create extcon usb2-phy link
[    1.625706] phy phy-fe8b0000.usb2-phy.2: Linked as a consumer to regulator.4
[    1.625852] phy phy-fe8b0000.usb2-phy.3: Linked as a consumer to regulator.4
[    1.625957] phy phy-fe8b0000.usb2-phy.3: No vbus specified for otg port
[    1.631782] rk-pcie 3c0000000.pcie: Linked as a consumer to regulator.12
[    1.632029] rk-pcie 3c0000000.pcie: missing legacy IRQ resource
[    1.632065] rk-pcie 3c0000000.pcie: Missing *config* reg space
[    1.632090] rk-pcie 3c0000000.pcie: host bridge /pcie@fe260000 ranges:
[    1.632123] rk-pcie 3c0000000.pcie:   err 0x300000000..0x3007fffff -> 0x00000                                                                                            000
[    1.632152] rk-pcie 3c0000000.pcie:    IO 0x300800000..0x3008fffff -> 0x00800                                                                                            000
[    1.632156] mpp_service mpp-srv: 7c0cdae4b6 author: balbes150 2022-01-16 v202                                                                                            20116
[    1.632159] mpp_service mpp-srv: probe start
[    1.632188] rk-pcie 3c0000000.pcie:   MEM 0x300900000..0x33fffffff -> 0x00900                                                                                            000
[    1.632872] iommu: Adding device fdf40000.rkvenc to group 4
[    1.632914] mpp_rkvenc fdf40000.rkvenc: Linked as a consumer to fdf40f00.iomm                                                                                            u
[    1.633095] mpp_rkvenc fdf40000.rkvenc: probing start
[    1.633516] mpp_rkvenc fdf40000.rkvenc: venc regulator not ready, retry
[    1.633539] rkvenc_init:1199: failed to add venc devfreq
[    1.633835] mpp_rkvenc fdf40000.rkvenc: probing finish
[    1.634749] iommu: Adding device fdea0400.vdpu to group 0
[    1.634786] mpp_vdpu2 fdea0400.vdpu: Linked as a consumer to fdea0800.iommu
[    1.634941] mpp_vdpu2 fdea0400.vdpu: probe device
[    1.635445] mpp_vdpu2 fdea0400.vdpu: probing finish
[    1.635907] iommu: Adding device fdee0000.vepu to group 2
[    1.635947] mpp_vepu2 fdee0000.vepu: Linked as a consumer to fdee0800.iommu
[    1.636108] mpp_vepu2 fdee0000.vepu: probe device
[    1.636579] mpp_vepu2 fdee0000.vepu: probing finish
[    1.637041] iommu: Adding device fdef0000.iep to group 3
[    1.637080] mpp-iep2 fdef0000.iep: Linked as a consumer to fdef0800.iommu
[    1.637208] mpp-iep2 fdef0000.iep: probe device
[    1.637610] mpp-iep2 fdef0000.iep: allocate roi buffer failed
[    1.637755] mpp-iep2 fdef0000.iep: probing finish
[    1.638257] iommu: Adding device fded0000.jpegd to group 1
[    1.638302] mpp_jpgdec fded0000.jpegd: Linked as a consumer to fded0480.iommu
[    1.638429] mpp_jpgdec fded0000.jpegd: probe device
[    1.638908] mpp_jpgdec fded0000.jpegd: probing finish
[    1.639395] iommu: Adding device fdf80200.rkvdec to group 5
[    1.639437] mpp_rkvdec2 fdf80200.rkvdec: Linked as a consumer to fdf80800.iom                                                                                            mu
[    1.639646] mpp_rkvdec2 fdf80200.rkvdec: probing start
[    1.639775] mpp_rkvdec2 fdf80200.rkvdec: 16 task capacity link mode detected
[    1.640073] mpp_rkvdec2 fdf80200.rkvdec: shared_niu_a is not found!
[    1.640097] rkvdec2_init:661: No niu aclk reset resource define
[    1.640118] mpp_rkvdec2 fdf80200.rkvdec: shared_niu_h is not found!
[    1.640136] rkvdec2_init:664: No niu hclk reset resource define
[    1.640295] mpp_rkvdec2 fdf80200.rkvdec: sram_start 0x00000000fdcc0000
[    1.640319] mpp_rkvdec2 fdf80200.rkvdec: rcb_iova 0x0000000010000000
[    1.640338] mpp_rkvdec2 fdf80200.rkvdec: sram_size 45056
[    1.640355] mpp_rkvdec2 fdf80200.rkvdec: rcb_size 65536
[    1.640373] mpp_rkvdec2 fdf80200.rkvdec: min_width 512
[    1.640431] mpp_rkvdec2 fdf80200.rkvdec: link mode probe finish
[    1.640507] mpp_rkvdec2 fdf80200.rkvdec: probing finish
[    1.640794] mpp_service mpp-srv: probe success
[    1.645358] dma-pl330 fe530000.dmac: Loaded driver for PL330 DMAC-241330
[    1.645396] dma-pl330 fe530000.dmac:         DBUFF-128x8bytes Num_Chans-8 Num                                                                                            _Peri-32 Num_Events-16
[    1.647386] dma-pl330 fe550000.dmac: Loaded driver for PL330 DMAC-241330
[    1.647422] dma-pl330 fe550000.dmac:         DBUFF-128x8bytes Num_Chans-8 Num                                                                                            _Peri-32 Num_Events-16
[    1.648493] rockchip-system-monitor rockchip-system-monitor: system monitor p                                                                                            robe
[    1.649318] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    1.650028] fe650000.serial: ttyS1 at MMIO 0xfe650000 (irq = 60, base_baud =                                                                                             1500000) is a 16550A
[    1.652384] random: fast init done
[    1.652687] random: crng init done
[    1.652891] iommu: Adding device fe040000.vop to group 7
[    1.652935] rockchip-vop2 fe040000.vop: Linked as a consumer to fe043e00.iomm                                                                                            u
[    1.656410] rockchip-drm display-subsystem: Linked as a consumer to fe040000.                                                                                            vop
[    1.657192] rockchip-drm display-subsystem: Linked as a consumer to fe0a0000.                                                                                            hdmi
[    1.658496] rockchip-drm display-subsystem: dmc is disabled
[    1.658764] rockchip-vop2 fe040000.vop: [drm:vop2_bind] vp0 assign plane mask                                                                                            : 0x2a, primary plane phy id: 5
[    1.658798] rockchip-vop2 fe040000.vop: [drm:vop2_bind] vp1 assign plane mask                                                                                            : 0x15, primary plane phy id: 4
[    1.658827] rockchip-vop2 fe040000.vop: [drm:vop2_bind] vp2 assign plane mask                                                                                            : 0x0, primary plane phy id: -1
[    1.659025] [drm] unsupported AFBC format[3432564e]
[    1.659077] [drm] failed to init overlay plane Cluster0-win1
[    1.659147] [drm] failed to init overlay plane Cluster1-win1
[    1.659278] rockchip-drm display-subsystem: bound fe040000.vop (ops 0xffffff8                                                                                            0092854c8)
[    1.659488] dwhdmi-rockchip fe0a0000.hdmi: Detected HDMI TX controller v2.11a                                                                                             with HDCP (DWC HDMI 2.0 TX PHY)
[    1.660066] dwhdmi-rockchip fe0a0000.hdmi: registered DesignWare HDMI I2C bus                                                                                             driver
[    1.660590] rockchip-drm display-subsystem: bound fe0a0000.hdmi (ops 0xffffff                                                                                            8009288ee0)
[    1.660620] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    1.660639] [drm] No driver support for vblank timestamp query.
** 21386 printk messages dropped **
[    2.051110] 00000080: 00000000 00000000 000000a4 00000000
[    2.051113] 00000090: 00000000 00000000 00000000 00000000
** 1 printk messages dropped **
[    2.051119] 000000b0: 00000000 00000000 00000000 00000000
[    2.051122] 000000c0: 00000000 00000000 00000000 00000000
[    2.051125] 000000d0: 00000010 00000000 00000000 00000000
[    2.051128] 000000e0: 00000000 00000000 00000000 00000000
[    2.051131] 000000f0: 00000000 00000000 00000000 00000000
[    2.051135] 00000100: 00000000 00000000 00000000 00000000
[    2.051135] Cluster1:
[    2.051155] 00000000: 00000000 00000000 000000e6 00000000
[    2.051158] 00000010: 00000000 00000000 00000000 00000000
[    2.051161] 00000020: 00000000 00000000 00000000 00000000
[    2.051164] 00000030: 00000000 00000000 00000000 00000000
[    2.051167] 00000040: 00000000 00000000 00000000 00000000
[    2.051170] 00000050: 00000010 00000000 00000000 00000000
[    2.051173] 00000060: 00000000 00000000 00000000 00000000
[    2.051176] 00000070: 00000000 00000000 00000000 00000000
[    2.051179] 00000080: 00000000 00000000 00000128 00000000
[    2.051182] 00000090: 00000000 00000000 00000000 00000000
[    2.051186] 000000a0: 00000000 00000000 00000000 00000000
[    2.051188] 000000b0: 00000000 00000000 00000000 00000000
[    2.051191] 000000c0: 00000000 00000000 00000000 00000000
[    2.051195] 000000d0: 00000010 00000000 00000000 00000000
[    2.051198] 000000e0: 00000000 00000000 00000000 00000000
[    2.051200] 000000f0: 00000000 00000000 00000000 00000000
[    2.051204] 00000100: 00000000 00000000 00000000 00000000
[    2.051205] Esmart0:
[    2.051224] 00000000: 00000000 0000b0a0 00000000 00000000
[    2.051228] 00000010: 00000000 00000000 00000000 00000000
[    2.051230] 00000020: 00000000 00000000 00000000 00000000
[    2.051234] 00000030: 00000000 10001000 10001000 00000000
[    2.051237] 00000040: 00000000 00000000 00000000 00000000
[    2.051240] 00000050: 00000000 00000000 00000000 00000000
[    2.051243] 00000060: 00000000 10001000 10001000 00000000
[    2.051246] 00000070: 00000000 00000000 00000000 00000000
[    2.051249] 00000080: 00000000 00000000 00000000 00000000
[    2.051252] 00000090: 00000000 10001000 10001000 00000000
[    2.051255] 000000a0: 00000000 00000000 00000000 00000000
[    2.051258] 000000b0: 00000000 00000000 00000000 00000000
[    2.051261] 000000c0: 00000000 10001000 10001000 00000000
[    2.051264] 000000d0: 00000000 00000000 00000000 00000000
[    2.051267] 000000e0: 00000000 00000000 00000000 00000000
[    2.051270] 000000f0: 00000000 00000000 00000000 00000000
[    2.051273] 00000100: 00000000 00000000 00000000 00000000
[    2.051274] Esmart1:
[    2.051294] 00000000: 00000000 0000b0a0 00000000 00000000
[    2.051297] 00000010: 00000000 00000000 00000000 00000000
[    2.051300] 00000020: 00000000 00000000 00000000 00000000
[    2.051303] 00000030: 00000000 10001000 10001000 00000000
[    2.051306] 00000040: 00000000 00000000 00000000 00000000
[    2.051309] 00000050: 00000000 00000000 00000000 00000000
[    2.051312] 00000060: 00000000 10001000 10001000 00000000
[    2.051315] 00000070: 00000000 00000000 00000000 00000000
[    2.051318] 00000080: 00000000 00000000 00000000 00000000
[    2.051321] 00000090: 00000000 10001000 10001000 00000000
[    2.051324] 000000a0: 00000000 00000000 00000000 00000000
[    2.051327] 000000b0: 00000000 00000000 00000000 00000000
[    2.051331] 000000c0: 00000000 10001000 10001000 00000000
[    2.051334] 000000d0: 00000000 00000000 00000000 00000000
[    2.051337] 000000e0: 00000000 00000000 00000000 00000000
[    2.051340] 000000f0: 00000000 00000000 00000000 00000000
[    2.051343] 00000100: 00000000 00000000 00000000 00000000
[    2.051344] Smart0:
[    2.051363] 00000000: 00000004 0000d0c0 00000000 00000000
[    2.051367] 00000010: 00000003 edf00036 00000000 000005a0
[    2.051370] 00000020: 0437077f 04370437 01a40000 00000000
[    2.051373] 00000030: 00000046 00001c74 10001000 00000000
[    2.051376] 00000040: 00000000 00000000 00000000 00000000
[    2.051379] 00000050: 00000000 00000000 00000000 00000000
[    2.051382] 00000060: 00000000 10001000 10001000 00000000
[    2.051385] 00000070: 00000000 00000000 00000000 00000000
[    2.051388] 00000080: 00000000 00000000 00000000 00000000
[    2.051391] 00000090: 00000000 10001000 10001000 00000000
[    2.051394] 000000a0: 00000000 00000000 00000000 00000000
[    2.051397] 000000b0: 00000000 00000000 00000000 00000000
[    2.051401] 000000c0: 00000000 10001000 10001000 00000000
[    2.051403] 000000d0: 00000000 00000000 00000000 00000000
[    2.051407] 000000e0: 00000000 00000000 00000000 00000000
[    2.051410] 000000f0: 00000000 00000000 00000000 00000000
[    2.051413] 00000100: 00000000 00000000 00000000 00000000
[    2.051414] Smart1:
[    2.051433] 00000000: 00000006 0000d0c0 00000000 00000000
[    2.051437] 00000010: 00000001 00000000 00000000 00000f00
[    2.051440] 00000020: 086f0eff 086f0eff 00000000 00000000
 

 

Edited by hotnikq
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Hqnicolas

Hqnicolas

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Posted (edited)

i found a solution to DTS HDMI  DRM Support
is a kernel patch for Quartz64-a

need to include dt-bindings display configuration on kernel includes

I'm compiling a 5 kernel and I'll make everything available soon

 

Quartz-a Dsi Adaptado para H96 MAX Board Type 2.zip

 

Quartz-a Dsi Adaptado para H96 MAX.zip


Quartz-a_Dsi_Adaptado_para_H96_MAX_Board_Type_2.zip
Quartz-a_Dsi_Adaptado_para_H96_MAX.zip

 

Edited by hotnikq
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Hqnicolas

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Posted (edited)

if You flash the wrong type of board "1 or 2" it will return a Power Model error
i'ts caused by the difference on DTB Files used to compile Kernel

Board Type 1

Quote

        sti8070@40 {
            compatible = "silergy,syr827";
            reg = <0x00000040>;
            vin-supply = <0x0000003e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x00100590>;
            regulator-max-microvolt = <0x001535b0>;
            regulator-ramp-delay = <0x000008fc>;
            fcs,suspend-voltage-selector = <0x00000001>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x00000005>;
            regulator-state-mem {
                regulator-off-in-suspend;
            };



Board Type 2

Quote

      tcs4526@10 {
            compatible = "tcs,tcs452x";
            reg = <0x00000010>;
            vin-supply = <0x0000003e>;
            regulator-compatible = "fan53555-reg";
            regulator-name = "vdd_cpu";
            regulator-min-microvolt = <0x00100590>;
            regulator-max-microvolt = <0x001535b0>;
            regulator-ramp-delay = <0x000008fc>;
            fcs,suspend-voltage-selector = <0x00000001>;
            regulator-boot-on;
            regulator-always-on;
            phandle = <0x00000005>;
            regulator-state-mem {
                regulator-off-in-suspend;
            };



The Different types of boardconfig to call FAN53555 Regulators
 

Quote

Fairchild Semiconductor FAN53555 regulator

The FAN53555 is a step-down switching voltage regulator that delivers a

digitally programmable output from an input voltage supply of 2.5 V to 5.5 V.

The output voltage is programmed through an I2C interface capable of operating

up to 3.4 MHz.

The fan53555 interface is via I2C bus.

Required Properties:

- compatible: Must be "fairchild,fan53555-regulator".

- reg: The device 8-bit I2C address.

- fairchild,backup-vsel: Register ID of backup register.

Supported values are 0 or 1.

The voltage selection ID used while the system

is active will be the other option not used

during running.

- regulator-min-microvolt: Minimum voltage in microvolts supported by this

regulator.

- regulator-max-microvolt: Maximum voltage in microvolts supported by this

regulator.

- regulator-ramp-delay: The slew rate of the regulator, in uV/us.

Optional Properties:

- fairchild,vsel-gpio: Present: GPIO connects to the VSEL pin and set

the output.

Not Present: No GPIO is connected to vsel pin.

- pinctrl-names: The state name of the VSEL pin configuration.

Only support: "default"

- pinctrl-0: The phandles of the pin configuration node in

pinctrl for VSEL pin.

For details of pinctrl properties, please refer to:

"Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"

- fairchild,restore-reg: Present: Restore vsel register from backup

register.

Not Present: No restore.

- fairchild,disable-suspend: Present: Disable regulator suspend method.

Not Present: Do not disable regulator suspend

method.

Example:

i2c_0 {

fan53555-regulator@60 {

compatible = "fairchild,fan53555-regulator";

reg = <0x60>;

fairchild,backup-vsel = <1>;

regulator-min-microvolt = <1050000>;

regulator-max-microvolt = <1350000>;

regulator-ramp-delay = <8000>;

pintrl-names = "default";

pinctrl-0 = <&ext_buck_vsel_default>;

fairchild,vsel-gpio = <&msmgpio 2 1>;

fairchild,restore-reg;

fairchild,disable-suspend;

};

};




Wrong Board Type flash

Quote

DDR Version V1.06 20210326
ln
LP4 MR14:0x5d
PHY drv:clk:36,ca:36,DQ:29,odt:60
PHY drv:clk:0x1a,0x1a,ca:0x1a,0x1a,DQ:0x1e,0x1e,odt:0x0,0xa
vrefinner:0x66, vrefout:0x100
dram drv:40,odt:0
ddrconfig:0
LPDDR4X, 324MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
wrlvl:clk skew:0x80,0x80
tdqss_skew:
cs 0 dqs 0: 10
cs 0 dqs 1: 5
cs 0 dqs 2: 7
cs 0 dqs 3: 3
cs 0 dqs 4: 0
cs 0 dqs 0: 241ps
cs 0 dqs 1: 120ps
cs 0 dqs 2: 168ps
cs 0 dqs 3: 72ps
tdqss.min:72,mid:156,max:241
change to: 324MHz
PHY drv:clk:36,ca:36,DQ:29,odt:60
PHY drv:clk:0x1a,0x1a,ca:0x1a,0x1a,DQ:0x1e,0x1e,odt:0x0,0xa
vrefinner:0x66, vrefout:0x100
dram drv:40,odt:0
PWRCTL:0x40,stat:0x303
vref_ca:0000004A
minca:0x7f,ck:0x80,ab:0x80,0x80, min_ck:0x1
get_clk_dqs_def_val: tdqs2dq:0
clk:0x5a, clk_delta:-38,max_freq:780
skew.dqs[0][0]:0x63
skew.dqs[0][1]:0x5e
skew.dqs[0][2]:0x60
skew.dqs[0][3]:0x5c
PWRCTL:0x0,stat:0x1
cs 0:
the read training result:
DQS0:0x6e:
DQ0:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ1:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ2:min:0x0,mid:0x3f,max:0x7e,range:0x7e
DQ3:min:0x0,mid:0x3d,max:0x7a,range:0x7a
DQ4:min:0x0,mid:0x37,max:0x6e,range:0x6e
DQ5:min:0x0,mid:0x38,max:0x70,range:0x70
DQ6:min:0x0,mid:0x37,max:0x6f,range:0x6f
DQ7:min:0x0,mid:0x38,max:0x70,range:0x70

DQS1:0x73:
DQ8:min:0x0,mid:0x3d,max:0x7b,range:0x7b
DQ9:min:0x0,mid:0x3e,max:0x7d,range:0x7d
DQ10:min:0x0,mid:0x3b,max:0x76,range:0x76
DQ11:min:0x0,mid:0x3a,max:0x75,range:0x75
DQ12:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ13:min:0x0,mid:0x3d,max:0x7a,range:0x7a
DQ14:min:0x0,mid:0x3d,max:0x7b,range:0x7b
DQ15:min:0x0,mid:0x3c,max:0x79,range:0x79

DQS2:0x6f:
DQ16:min:0x0,mid:0x3e,max:0x7d,range:0x7d
DQ17:min:0x0,mid:0x3e,max:0x7d,range:0x7d
DQ18:min:0x0,mid:0x3c,max:0x78,range:0x78
DQ19:min:0x0,mid:0x3b,max:0x76,range:0x76
DQ20:min:0x0,mid:0x37,max:0x6f,range:0x6f
DQ21:min:0x0,mid:0x36,max:0x6d,range:0x6d
DQ22:min:0x0,mid:0x35,max:0x6b,range:0x6b
DQ23:min:0x0,mid:0x38,max:0x70,range:0x70

DQS3:0x6e:
DQ24:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ25:min:0x0,mid:0x3d,max:0x7a,range:0x7a
DQ26:min:0x0,mid:0x3b,max:0x76,range:0x76
DQ27:min:0x0,mid:0x39,max:0x72,range:0x72
DQ28:min:0x0,mid:0x3e,max:0x7d,range:0x7d
DQ29:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ30:min:0x0,mid:0x3c,max:0x79,range:0x79
DQ31:min:0x0,mid:0x3e,max:0x7c,range:0x7c

the write training result:
DQS0:0x63:
DQ0:min:0x58,mid:0x77,max:0x96,range:0x3e
DQ1:min:0x59,mid:0x78,max:0x97,range:0x3e
DQ2:min:0x59,mid:0x78,max:0x97,range:0x3e
DQ3:min:0x58,mid:0x77,max:0x96,range:0x3e
DQ4:min:0x55,mid:0x74,max:0x93,range:0x3e
DQ5:min:0x55,mid:0x74,max:0x93,range:0x3e
DQ6:min:0x56,mid:0x75,max:0x94,range:0x3e
DQ7:min:0x57,mid:0x75,max:0x94,range:0x3d
DM0:min:0x57,mid:0x75,max:0x94,range:0x3d

DQS1:0x5e:
DQ8:min:0x50,mid:0x6e,max:0x8d,range:0x3d
DQ9:min:0x51,mid:0x6f,max:0x8d,range:0x3c
DQ10:min:0x4f,mid:0x6d,max:0x8c,range:0x3d
DQ11:min:0x4f,mid:0x6d,max:0x8c,range:0x3d
DQ12:min:0x52,mid:0x70,max:0x8e,range:0x3c
DQ13:min:0x52,mid:0x70,max:0x8e,range:0x3c
DQ14:min:0x52,mid:0x70,max:0x8e,range:0x3c
DQ15:min:0x51,mid:0x6f,max:0x8d,range:0x3c
DM1:min:0x50,mid:0x6e,max:0x8c,range:0x3c

DQS2:0x60:
DQ16:min:0x55,mid:0x74,max:0x93,range:0x3e
DQ17:min:0x55,mid:0x74,max:0x93,range:0x3e
DQ18:min:0x54,mid:0x73,max:0x92,range:0x3e
DQ19:min:0x54,mid:0x73,max:0x92,range:0x3e
DQ20:min:0x52,mid:0x70,max:0x8f,range:0x3d
DQ21:min:0x52,mid:0x70,max:0x8e,range:0x3c
DQ22:min:0x52,mid:0x70,max:0x8f,range:0x3d
DQ23:min:0x53,mid:0x71,max:0x90,range:0x3d
DM2:min:0x53,mid:0x71,max:0x90,range:0x3d

DQS3:0x5c:
DQ24:min:0x50,mid:0x6e,max:0x8d,range:0x3d
DQ25:min:0x4f,mid:0x6d,max:0x8c,range:0x3d
DQ26:min:0x4e,mid:0x6c,max:0x8b,range:0x3d
DQ27:min:0x4e,mid:0x6c,max:0x8b,range:0x3d
DQ28:min:0x51,mid:0x6f,max:0x8e,range:0x3d
DQ29:min:0x51,mid:0x6f,max:0x8e,range:0x3d
DQ30:min:0x50,mid:0x6e,max:0x8c,range:0x3c
DQ31:min:0x51,mid:0x6f,max:0x8e,range:0x3d
DM3:min:0x4e,mid:0x6c,max:0x8b,range:0x3d

CA Training result:
clk_a:0x5a, clk_b:0x5a
reg0x26c:0x0, 0x0
cs0 chA ca0 min: 0x3d, mid:0x84 max:0xcc, range:0x8f
cs0 chA ca1 min: 0x4e, mid:0x84 max:0xbb, range:0x6d
cs0 chA ca2 min: 0x3a, mid:0x81 max:0xc9, range:0x8f
cs0 chA ca3 min: 0x4a, mid:0x81 max:0xb8, range:0x6e
cs0 chA ca4 min: 0x39, mid:0x80 max:0xc8, range:0x8f
cs0 chA ca5 min: 0x4a, mid:0x81 max:0xb8, range:0x6e
cs0 chA  CS min: 0x3c, mid:0x74 max:0xac, range:0x70
cs0 chB ca0 min: 0x3c, mid:0x84 max:0xcc, range:0x90
cs0 chB ca1 min: 0x4c, mid:0x83 max:0xba, range:0x6e
cs0 chB ca2 min: 0x39, mid:0x80 max:0xc8, range:0x8f
cs0 chB ca3 min: 0x4a, mid:0x80 max:0xb7, range:0x6d
cs0 chB ca4 min: 0x3a, mid:0x81 max:0xc8, range:0x8e
cs0 chB ca5 min: 0x48, mid:0x7f max:0xb7, range:0x6f
cs0 chB  CS min: 0x3c, mid:0x74 max:0xac, range:0x70
RX DQS Train result:
cs0, DQS0:cyc:1,oph:7,dll:26
cs0, DQS1:cyc:1,oph:7,dll:29
cs0, DQS2:cyc:1,oph:7,dll:25
cs0, DQS3:cyc:1,oph:7,dll:29
get tdqqs2dq:458 ps
change to: 528MHz
PHY drv:clk:36,ca:36,DQ:29,odt:60
PHY drv:clk:0x1a,0x1a,ca:0x1a,0x1a,DQ:0x1e,0x1e,odt:0x0,0xa
vrefinner:0x66, vrefout:0x100
dram drv:40,odt:0
PWRCTL:0x40,stat:0x303
vref_ca:0000004A
minca:0x7f,ck:0x80,ab:0x80,0x80, min_ck:0x1
get_clk_dqs_def_val: tdqs2dq:458
clk:0x82, clk_delta:2,max_freq:780
skew.dqs[0][0]:0x92
skew.dqs[0][1]:0x8a
skew.dqs[0][2]:0x8d
skew.dqs[0][3]:0x86
PWRCTL:0x0,stat:0x1
cs 0:
the read training result:
DQS0:0x6e:
DQ0:min:0x0,mid:0x3e,max:0x7d,range:0x7d
DQ1:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ2:min:0x0,mid:0x3f,max:0x7e,range:0x7e
DQ3:min:0x0,mid:0x3d,max:0x7a,range:0x7a
DQ4:min:0x0,mid:0x37,max:0x6e,range:0x6e
DQ5:min:0x0,mid:0x38,max:0x71,range:0x71
DQ6:min:0x0,mid:0x38,max:0x70,range:0x70
DQ7:min:0x0,mid:0x38,max:0x70,range:0x70

DQS1:0x73:
DQ8:min:0x0,mid:0x3d,max:0x7b,range:0x7b
DQ9:min:0x0,mid:0x3f,max:0x7e,range:0x7e
DQ10:min:0x0,mid:0x3b,max:0x76,range:0x76
DQ11:min:0x0,mid:0x3b,max:0x76,range:0x76
DQ12:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ13:min:0x0,mid:0x3d,max:0x7a,range:0x7a
DQ14:min:0x0,mid:0x3d,max:0x7b,range:0x7b
DQ15:min:0x0,mid:0x3d,max:0x7a,range:0x7a

DQS2:0x6f:
DQ16:min:0x0,mid:0x3f,max:0x7e,range:0x7e
DQ17:min:0x0,mid:0x3f,max:0x7e,range:0x7e
DQ18:min:0x0,mid:0x3c,max:0x78,range:0x78
DQ19:min:0x0,mid:0x3b,max:0x77,range:0x77
DQ20:min:0x0,mid:0x38,max:0x70,range:0x70
DQ21:min:0x0,mid:0x36,max:0x6d,range:0x6d
DQ22:min:0x0,mid:0x35,max:0x6b,range:0x6b
DQ23:min:0x0,mid:0x38,max:0x70,range:0x70

DQS3:0x6e:
DQ24:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ25:min:0x0,mid:0x3c,max:0x79,range:0x79
DQ26:min:0x0,mid:0x3b,max:0x76,range:0x76
DQ27:min:0x0,mid:0x39,max:0x72,range:0x72
DQ28:min:0x0,mid:0x3f,max:0x7e,range:0x7e
DQ29:min:0x0,mid:0x3e,max:0x7c,range:0x7c
DQ30:min:0x0,mid:0x3d,max:0x7a,range:0x7a
DQ31:min:0x0,mid:0x3e,max:0x7c,range:0x7c

the write training result:
DQS0:0x92:
DQ0:min:0x91,mid:0xaf,max:0xce,range:0x3d
DQ1:min:0x93,mid:0xb1,max:0xcf,range:0x3c
DQ2:min:0x93,mid:0xb1,max:0xd0,range:0x3d
DQ3:min:0x91,mid:0xaf,max:0xce,range:0x3d
DQ4:min:0x8c,mid:0xaa,max:0xc9,range:0x3d
DQ5:min:0x8c,mid:0xaa,max:0xc9,range:0x3d
DQ6:min:0x8e,mid:0xac,max:0xcb,range:0x3d
DQ7:min:0x8f,mid:0xac,max:0xca,range:0x3b
DM0:min:0x8e,mid:0xac,max:0xca,range:0x3c

DQS1:0x8a:
DQ8:min:0x87,mid:0xa5,max:0xc4,range:0x3d
DQ9:min:0x87,mid:0xa5,max:0xc4,range:0x3d
DQ10:min:0x85,mid:0xa3,max:0xc2,range:0x3d
DQ11:min:0x84,mid:0xa2,max:0xc0,range:0x3c
DQ12:min:0x89,mid:0xa7,max:0xc6,range:0x3d
DQ13:min:0x89,mid:0xa7,max:0xc5,range:0x3c
DQ14:min:0x8a,mid:0xa8,max:0xc6,range:0x3c
DQ15:min:0x88,mid:0xa6,max:0xc5,range:0x3d
DM1:min:0x86,mid:0xa4,max:0xc3,range:0x3d

DQS2:0x8d:
DQ16:min:0x8d,mid:0xac,max:0xcb,range:0x3e
DQ17:min:0x8d,mid:0xab,max:0xca,range:0x3d
DQ18:min:0x8a,mid:0xa8,max:0xc7,range:0x3d
DQ19:min:0x8a,mid:0xa9,max:0xc9,range:0x3f
DQ20:min:0x87,mid:0xa5,max:0xc4,range:0x3d
DQ21:min:0x86,mid:0xa4,max:0xc2,range:0x3c
DQ22:min:0x87,mid:0xa4,max:0xc2,range:0x3b
DQ23:min:0x8a,mid:0xa7,max:0xc5,range:0x3b
DM2:min:0x89,mid:0xa7,max:0xc6,range:0x3d

DQS3:0x86:
DQ24:min:0x87,mid:0xa5,max:0xc3,range:0x3c
DQ25:min:0x85,mid:0xa3,max:0xc2,range:0x3d
DQ26:min:0x83,mid:0xa2,max:0xc1,range:0x3e
DQ27:min:0x82,mid:0xa0,max:0xbf,range:0x3d
DQ28:min:0x88,mid:0xa6,max:0xc5,range:0x3d
DQ29:min:0x88,mid:0xa6,max:0xc5,range:0x3d
DQ30:min:0x86,mid:0xa4,max:0xc2,range:0x3c
DQ31:min:0x88,mid:0xa6,max:0xc5,range:0x3d
DM3:min:0x84,mid:0xa2,max:0xc0,range:0x3c

CA Training result:
clk_a:0x82, clk_b:0x82
reg0x26c:0x0, 0x0
cs0 chA ca0 min: 0x3a, mid:0x86 max:0xd3, range:0x99
cs0 chA ca1 min: 0x57, mid:0x87 max:0xb8, range:0x61
cs0 chA ca2 min: 0x34, mid:0x81 max:0xce, range:0x9a
cs0 chA ca3 min: 0x50, mid:0x81 max:0xb2, range:0x62
cs0 chA ca4 min: 0x34, mid:0x81 max:0xce, range:0x9a
cs0 chA ca5 min: 0x50, mid:0x81 max:0xb2, range:0x62
cs0 chA  CS min: 0x39, mid:0x76 max:0xb3, range:0x7a
cs0 chB ca0 min: 0x38, mid:0x85 max:0xd3, range:0x9b
cs0 chB ca1 min: 0x54, mid:0x84 max:0xb5, range:0x61
cs0 chB ca2 min: 0x34, mid:0x80 max:0xcd, range:0x99
cs0 chB ca3 min: 0x50, mid:0x80 max:0xb1, range:0x61
cs0 chB ca4 min: 0x34, mid:0x80 max:0xcd, range:0x99
cs0 chB ca5 min: 0x4d, mid:0x7f max:0xb1, range:0x64
cs0 chB  CS min: 0x3a, mid:0x76 max:0xb3, range:0x79
RX DQS Train result:
cs0, DQS0:cyc:2,oph:3,dll:0
cs0, DQS1:cyc:2,oph:3,dll:2
cs0, DQS2:cyc:2,oph:3,dll:0
cs0, DQS3:cyc:2,oph:3,dll:4
change to: 780MHz
PHY drv:clk:36,ca:36,DQ:29,odt:60
PHY drv:clk:0x1a,0x1a,ca:0x1a,0x1a,DQ:0x1e,0x1e,odt:0x0,0xa
vrefinner:0x66, vrefout:0x100
dram drv:40,odt:0
PWRCTL:0x40,stat:0x303
vref_ca:0000004A
minca:0x7e,ck:0x80,ab:0x80,0x80, min_ck:0x2
get_clk_dqs_def_val: tdqs2dq:458
clk:0x6b, clk_delta:-21,max_freq:780
skew.dqs[0][0]:0x83
skew.dqs[0][1]:0x76
skew.dqs[0][2]:0x7b
skew.dqs[0][3]:0x72
PWRCTL:0x0,stat:0x1
cs 0:
the read training result:
DQS0:0x54:
DQ0:min:0xd,mid:0x38,max:0x63,range:0x56
DQ1:min:0xf,mid:0x39,max:0x63,range:0x54
DQ2:min:0xd,mid:0x38,max:0x64,range:0x57
DQ3:min:0xe,mid:0x36,max:0x5f,range:0x51
DQ4:min:0x2,mid:0x2b,max:0x54,range:0x52
DQ5:min:0x2,mid:0x2c,max:0x57,range:0x55
DQ6:min:0x7,mid:0x2f,max:0x57,range:0x50
DQ7:min:0x2,mid:0x2c,max:0x56,range:0x54

DQS1:0x55:
DQ8:min:0x8,mid:0x32,max:0x5c,range:0x54
DQ9:min:0x9,mid:0x34,max:0x5f,range:0x56
DQ10:min:0x3,mid:0x2d,max:0x58,range:0x55
DQ11:min:0x1,mid:0x2c,max:0x57,range:0x56
DQ12:min:0xa,mid:0x33,max:0x5d,range:0x53
DQ13:min:0x9,mid:0x32,max:0x5c,range:0x53
DQ14:min:0xa,mid:0x33,max:0x5c,range:0x52
DQ15:min:0x6,mid:0x30,max:0x5b,range:0x55

DQS2:0x5a:
DQ16:min:0x10,mid:0x3c,max:0x69,range:0x59
DQ17:min:0x11,mid:0x3c,max:0x68,range:0x57
DQ18:min:0xc,mid:0x37,max:0x63,range:0x57
DQ19:min:0xc,mid:0x37,max:0x62,range:0x56
DQ20:min:0x4,mid:0x2f,max:0x5a,range:0x56
DQ21:min:0x1,mid:0x2c,max:0x58,range:0x57
DQ22:min:0x3,mid:0x2c,max:0x56,range:0x53
DQ23:min:0x5,mid:0x30,max:0x5c,range:0x57

DQS3:0x53:
DQ24:min:0xb,mid:0x36,max:0x61,range:0x56
DQ25:min:0x8,mid:0x33,max:0x5e,range:0x56
DQ26:min:0x6,mid:0x31,max:0x5c,range:0x56
DQ27:min:0x1,mid:0x2b,max:0x56,range:0x55
DQ28:min:0xd,mid:0x38,max:0x63,range:0x56
DQ29:min:0xa,mid:0x35,max:0x61,range:0x57
DQ30:min:0x9,mid:0x33,max:0x5e,range:0x55
DQ31:min:0xb,mid:0x35,max:0x60,range:0x55

the write training result:
DQS0:0x83:
DQ0:min:0x91,mid:0xaf,max:0xce,range:0x3d
DQ1:min:0x93,mid:0xb1,max:0xcf,range:0x3c
DQ2:min:0x94,mid:0xb2,max:0xd0,range:0x3c
DQ3:min:0x92,mid:0xb0,max:0xce,range:0x3c
DQ4:min:0x8b,mid:0xa7,max:0xc3,range:0x38
DQ5:min:0x8b,mid:0xa8,max:0xc5,range:0x3a
DQ6:min:0x8e,mid:0xab,max:0xc8,range:0x3a
DQ7:min:0x90,mid:0xab,max:0xc6,range:0x36
DM0:min:0x8e,mid:0xa9,max:0xc5,range:0x37

DQS1:0x76:
DQ8:min:0x8b,mid:0xa7,max:0xc3,range:0x38
DQ9:min:0x8d,mid:0xa7,max:0xc1,range:0x34
DQ10:min:0x8a,mid:0xa4,max:0xbf,range:0x35
DQ11:min:0x89,mid:0xa4,max:0xbf,range:0x36
DQ12:min:0x8f,mid:0xa9,max:0xc4,range:0x35
DQ13:min:0x8d,mid:0xa7,max:0xc2,range:0x35
DQ14:min:0x91,mid:0xaa,max:0xc3,range:0x32
DQ15:min:0x8f,mid:0xa9,max:0xc3,range:0x34
DM1:min:0x8b,mid:0xa5,max:0xbf,range:0x34

DQS2:0x7b:
DQ16:min:0x8f,mid:0xad,max:0xcc,range:0x3d
DQ17:min:0x8e,mid:0xac,max:0xca,range:0x3c
DQ18:min:0x8b,mid:0xa8,max:0xc5,range:0x3a
DQ19:min:0x8a,mid:0xa8,max:0xc7,range:0x3d
DQ20:min:0x89,mid:0xa4,max:0xbf,range:0x36
DQ21:min:0x87,mid:0xa0,max:0xba,range:0x33
DQ22:min:0x88,mid:0xa2,max:0xbd,range:0x35
DQ23:min:0x8c,mid:0xa5,max:0xbf,range:0x33
DM2:min:0x8b,mid:0xa5,max:0xc0,range:0x35

DQS3:0x72:
DQ24:min:0x8b,mid:0xa6,max:0xc2,range:0x37
DQ25:min:0x8a,mid:0xa4,max:0xbf,range:0x35
DQ26:min:0x88,mid:0xa3,max:0xbe,range:0x36
DQ27:min:0x87,mid:0xa2,max:0xbe,range:0x37
DQ28:min:0x8f,mid:0xa9,max:0xc3,range:0x34
DQ29:min:0x8e,mid:0xa8,max:0xc2,range:0x34
DQ30:min:0x8d,mid:0xa6,max:0xbf,range:0x32
DQ31:min:0x8f,mid:0xa9,max:0xc3,range:0x34
DM3:min:0x89,mid:0xa4,max:0xbf,range:0x36

CA Training result:
clk_a:0x6b, clk_b:0x6b
reg0x26c:0x0, 0x0
cs0 chA ca0 min: 0x36, mid:0x89 max:0xdc, range:0xa6
cs0 chA ca1 min: 0x60, mid:0x8a max:0xb4, range:0x54
cs0 chA ca2 min: 0x2f, mid:0x82 max:0xd5, range:0xa6
cs0 chA ca3 min: 0x57, mid:0x81 max:0xac, range:0x55
cs0 chA ca4 min: 0x2e, mid:0x81 max:0xd4, range:0xa6
cs0 chA ca5 min: 0x58, mid:0x82 max:0xac, range:0x54
cs0 chA  CS min: 0x0, mid:0x7f max:0xff, range:0xff
cs0 chB ca0 min: 0x34, mid:0x87 max:0xdb, range:0xa7
cs0 chB ca1 min: 0x5c, mid:0x86 max:0xb0, range:0x54
cs0 chB ca2 min: 0x2d, mid:0x7f max:0xd2, range:0xa5
cs0 chB ca3 min: 0x57, mid:0x80 max:0xa9, range:0x52
cs0 chB ca4 min: 0x2e, mid:0x80 max:0xd2, range:0xa4
cs0 chB ca5 min: 0x53, mid:0x7e max:0xa9, range:0x56
cs0 chB  CS min: 0x0, mid:0x7f max:0xff, range:0xff
RX DQS Train result:
cs0, DQS0:cyc:2,oph:4,dll:26
cs0, DQS1:cyc:2,oph:5,dll:0
cs0, DQS2:cyc:2,oph:4,dll:22
cs0, DQS3:cyc:2,oph:5,dll:0
change to: 780MHz(final freq)
PHY drv:clk:36,ca:36,DQ:29,odt:60
PHY drv:clk:0x1a,0x1a,ca:0x1a,0x1a,DQ:0x1e,0x1e,odt:0x0,0xa
vrefinner:0x66, vrefout:0x100
dram drv:40,odt:0
PWRCTL:0x40,stat:0x303
vref_ca:0000004A
minca:0x7d,ck:0x80,ab:0x80,0x80, min_ck:0x3
get_clk_dqs_def_val: tdqs2dq:458
clk:0x6b, clk_delta:-21,max_freq:780
skew.dqs[0][0]:0x83
skew.dqs[0][1]:0x76
skew.dqs[0][2]:0x7b
skew.dqs[0][3]:0x72
PWRCTL:0x0,stat:0x1
cs 0:
the read training result:
DQS0:0x54:
DQ0:min:0xc,mid:0x37,max:0x63,range:0x57
DQ1:min:0xf,mid:0x39,max:0x63,range:0x54
DQ2:min:0xd,mid:0x38,max:0x64,range:0x57
DQ3:min:0xe,mid:0x37,max:0x60,range:0x52
DQ4:min:0x2,mid:0x2b,max:0x54,range:0x52
DQ5:min:0x2,mid:0x2c,max:0x57,range:0x55
DQ6:min:0x7,mid:0x2f,max:0x57,range:0x50
DQ7:min:0x2,mid:0x2c,max:0x56,range:0x54

DQS1:0x55:
DQ8:min:0x8,mid:0x32,max:0x5c,range:0x54
DQ9:min:0x9,mid:0x34,max:0x5f,range:0x56
DQ10:min:0x3,mid:0x2d,max:0x58,range:0x55
DQ11:min:0x1,mid:0x2c,max:0x57,range:0x56
DQ12:min:0x9,mid:0x33,max:0x5d,range:0x54
DQ13:min:0x9,mid:0x32,max:0x5c,range:0x53
DQ14:min:0xa,mid:0x33,max:0x5d,range:0x53
DQ15:min:0x6,mid:0x30,max:0x5b,range:0x55

DQS2:0x5a:
DQ16:min:0x10,mid:0x3c,max:0x69,range:0x59
DQ17:min:0x11,mid:0x3c,max:0x68,range:0x57
DQ18:min:0xc,mid:0x37,max:0x62,range:0x56
DQ19:min:0xc,mid:0x37,max:0x62,range:0x56
DQ20:min:0x4,mid:0x2f,max:0x5a,range:0x56
DQ21:min:0x1,mid:0x2c,max:0x58,range:0x57
DQ22:min:0x3,mid:0x2c,max:0x56,range:0x53
DQ23:min:0x5,mid:0x30,max:0x5c,range:0x57

DQS3:0x53:
DQ24:min:0xb,mid:0x36,max:0x62,range:0x57
DQ25:min:0x8,mid:0x33,max:0x5e,range:0x56
DQ26:min:0x6,mid:0x31,max:0x5c,range:0x56
DQ27:min:0x1,mid:0x2b,max:0x56,range:0x55
DQ28:min:0xd,mid:0x38,max:0x63,range:0x56
DQ29:min:0xa,mid:0x35,max:0x61,range:0x57
DQ30:min:0x9,mid:0x33,max:0x5e,range:0x55
DQ31:min:0xc,mid:0x36,max:0x61,range:0x55

the write training result:
DQS0:0x83:
DQ0:min:0x92,mid:0xb0,max:0xce,range:0x3c
DQ1:min:0x93,mid:0xb1,max:0xcf,range:0x3c
DQ2:min:0x93,mid:0xb1,max:0xd0,range:0x3d
DQ3:min:0x92,mid:0xb0,max:0xce,range:0x3c
DQ4:min:0x8c,mid:0xa7,max:0xc3,range:0x37
DQ5:min:0x8b,mid:0xa8,max:0xc5,range:0x3a
DQ6:min:0x8e,mid:0xab,max:0xc8,range:0x3a
DQ7:min:0x91,mid:0xab,max:0xc6,range:0x35
DM0:min:0x8e,mid:0xa9,max:0xc5,range:0x37

DQS1:0x76:
DQ8:min:0x8b,mid:0xa6,max:0xc2,range:0x37
DQ9:min:0x8e,mid:0xa7,max:0xc1,range:0x33
DQ10:min:0x8a,mid:0xa4,max:0xbf,range:0x35
DQ11:min:0x88,mid:0xa3,max:0xbf,range:0x37
DQ12:min:0x90,mid:0xaa,max:0xc4,range:0x34
DQ13:min:0x8d,mid:0xa7,max:0xc2,range:0x35
DQ14:min:0x91,mid:0xa9,max:0xc2,range:0x31
DQ15:min:0x8f,mid:0xa9,max:0xc3,range:0x34
DM1:min:0x8b,mid:0xa5,max:0xc0,range:0x35

DQS2:0x7b:
DQ16:min:0x8f,mid:0xad,max:0xcb,range:0x3c
DQ17:min:0x8e,mid:0xac,max:0xca,range:0x3c
DQ18:min:0x8b,mid:0xa8,max:0xc5,range:0x3a
DQ19:min:0x8b,mid:0xa9,max:0xc7,range:0x3c
DQ20:min:0x8a,mid:0xa4,max:0xbf,range:0x35
DQ21:min:0x88,mid:0xa1,max:0xba,range:0x32
DQ22:min:0x89,mid:0xa2,max:0xbc,range:0x33
DQ23:min:0x8d,mid:0xa6,max:0xbf,range:0x32
DM2:min:0x8b,mid:0xa5,max:0xc0,range:0x35

DQS3:0x72:
DQ24:min:0x8c,mid:0xa7,max:0xc2,range:0x36
DQ25:min:0x8b,mid:0xa5,max:0xbf,range:0x34
DQ26:min:0x88,mid:0xa3,max:0xbe,range:0x36
DQ27:min:0x87,mid:0xa2,max:0xbe,range:0x37
DQ28:min:0x90,mid:0xa9,max:0xc3,range:0x33
DQ29:min:0x8e,mid:0xa8,max:0xc2,range:0x34
DQ30:min:0x8d,mid:0xa6,max:0xbf,range:0x32
DQ31:min:0x8f,mid:0xa9,max:0xc3,range:0x34
DM3:min:0x89,mid:0xa4,max:0xbf,range:0x36

CA Training result:
clk_a:0x6b, clk_b:0x6b
reg0x26c:0x0, 0x0
cs0 chA ca0 min: 0x35, mid:0x88 max:0xdc, range:0xa7
cs0 chA ca1 min: 0x60, mid:0x8a max:0xb4, range:0x54
cs0 chA ca2 min: 0x2f, mid:0x82 max:0xd5, range:0xa6
cs0 chA ca3 min: 0x57, mid:0x81 max:0xac, range:0x55
cs0 chA ca4 min: 0x2e, mid:0x81 max:0xd4, range:0xa6
cs0 chA ca5 min: 0x57, mid:0x81 max:0xac, range:0x55
cs0 chA  CS min: 0x0, mid:0x7f max:0xff, range:0xff
cs0 chB ca0 min: 0x34, mid:0x87 max:0xdb, range:0xa7
cs0 chB ca1 min: 0x5b, mid:0x85 max:0xaf, range:0x54
cs0 chB ca2 min: 0x2d, mid:0x7f max:0xd2, range:0xa5
cs0 chB ca3 min: 0x57, mid:0x80 max:0xa9, range:0x52
cs0 chB ca4 min: 0x2e, mid:0x80 max:0xd2, range:0xa4
cs0 chB ca5 min: 0x52, mid:0x7d max:0xa9, range:0x57
cs0 chB  CS min: 0x0, mid:0x7f max:0xff, range:0xff
RX DQS Train result:
cs0, DQS0:cyc:2,oph:4,dll:25
cs0, DQS1:cyc:2,oph:5,dll:0
cs0, DQS2:cyc:2,oph:4,dll:23
cs0, DQS3:cyc:2,oph:5,dll:0
out
U-Boot SPL board init
U-Boot SPL 2017.09-gc613b7ea04-210315 #zzz (Mar 15 2021 - 18:08:14)
unknown raw ID phN
unrecognized JEDEC id bytes: 00, 00, 00
Trying to boot from MMC2
MMC error: The cmd index is 1, ret is -110
Card did not respond to voltage select!
mmc_init: -95, time 10
spl: mmc init failed with error: -95
Trying to boot from MMC1
SPL: A/B-slot: _a, successful: 0, tries-remain: 7
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256+ OK
## Checking uboot 0x00a00000 ... sha256+ OK
## Checking fdt 0x00b22130 ... sha256+ OK
## Checking atf-2 0xfdcc9000 ... sha256+ OK
## Checking atf-3 0xfdcd0000 ... sha256+ OK
## Checking optee 0x00200000 ... sha256+ OK
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 218.465 ms

INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-110-g8504c6c97-dirty:xsf
NOTICE:  BL31: Built : 14:50:05, Mar 26 2021
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    pmu v1 is valid
INFO:    dfs DDR fsp_param[0].freq_mhz= 780MHz
INFO:    dfs DDR fsp_param[1].freq_mhz= 324MHz
INFO:    dfs DDR fsp_param[2].freq_mhz= 528MHz
INFO:    dfs DDR fsp_param[3].freq_mhz= 780MHz
INFO:    Using opteed sec cpu_context!
INFO:    boot cpu mask: 0
INFO:    BL31: Initializing runtime services
INFO:    BL31: Initializing BL32
I/TC:
I/TC: Start rockchip platform init
I/TC: Rockchip release version: 1.0
I/TC: OP-TEE version: 3.6.0-293-g2b112e40 #102 Thu Feb  4 10:50:04 UTC 2021 aarc                                                                                         h64
I/TC: Initialized
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9


U-Boot 2017.09-g32ed8ff-210328-dirty #pc (Apr 21 2021 - 20:51:20 +0800)

Model: Rockchip RK3568 Evaluation Board
PreSerial: 2, raw, 0xfe660000
DRAM:  2 GiB
Sysmem: init
Relocation Offset: 7d39f000, fdt: 7b9f8e18
Using default environment

dwmmc@fe2b0000: 1, dwmmc@fe2c0000: 2, sdhci@fe310000: 0
Bootdev(atags): mmc 0
MMC0: HS200, 200Mhz
PartType: EFI
boot mode: recovery (misc)
DTB: rk-kernel.dtb
FIT: no signed, no conf required
HASH(c): OK
I2c0 speed: 100000Hz
PMIC:  RK8090 (on=0x40, off=0x00)
vdd_logic init 900000 uV
vdd_gpu init 900000 uV
vdd_npu init 900000 uV
io-domain: OK
Model: Rockchip RK3566 EVB3 DDR3 V10 Board
Rockchip UBOOT DRM driver version: v1.0.1
Using display timing dts
Detailed mode clock 132000 kHz, flags[8000000a]
    H: 1080 1095 1097 1127
    V: 1920 1935 1937 1952
bus_format: 100e
final DSI-Link bandwidth: 880 Mbps x 4
PHY is not locked
generic write fifo is full
failed to write cmd0: -110
failed to send on cmds: -110
CLK: (sync kernel. arm: enter 816000 KHz, init 816000 KHz, kernel 0N/A)
  apll 816000 KHz
  dpll 390000 KHz
  gpll 1188000 KHz
  cpll 1000000 KHz
  npll 1200000 KHz
  vpll 660000 KHz
  hpll 24000 KHz
  ppll 200000 KHz
  armclk 816000 KHz
  aclk_bus 150000 KHz
  pclk_bus 100000 KHz
  aclk_top_high 500000 KHz
  aclk_top_low 400000 KHz
  hclk_top 150000 KHz
  pclk_top 100000 KHz
  aclk_perimid 300000 KHz
  hclk_perimid 150000 KHz
  pclk_pmu 100000 KHz
Net:   eth1: ethernet@fe010000
Hit key to stop autoboot('CTRL+C'):  0
## Booting FIT Image at 0x799aba00 with size 0x01e4c400
Fdt Ramdisk skip relocation
## Loading kernel from FIT Image at 799aba00 ...
   Using 'conf' configuration
optee api revision: 2.0
TEEC: Waring: Could not find security partition
## Verified-boot: 0
   Trying 'kernel' kernel subimage
     Description:  unavailable
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x799cc600
     Data Size:    24678408 Bytes = 23.5 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x00a80000
     Entry Point:  0x00a80000
     Hash algo:    sha256
     Hash value:   c60e0578949ef5570e6d6279b81e254d743ca8924765418eb245647a5607f                                                                                         d9a
   Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk from FIT Image at 799aba00 ...
   Using 'conf' configuration
   Trying 'ramdisk' ramdisk subimage
     Description:  unavailable
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x7b155800
     Data Size:    6956263 Bytes = 6.6 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x0a200000
     Entry Point:  unavailable
     Hash algo:    sha256
     Hash value:   848757f81587ca00f60eeb52788b237c9cde5bb2b94663176b2393ad70038                                                                                         702
   Verifying Hash Integrity ... sha256+ OK
   Loading ramdisk from 0x7b155800 to 0x0a200000
## Loading fdt from FIT Image at 799aba00 ...
   Using 'conf' configuration
   Trying 'fdt' fdt subimage
     Description:  unavailable
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x799ac200
     Data Size:    131591 Bytes = 128.5 KiB
     Architecture: AArch64
     Load Address: 0x0a100000
     Hash algo:    sha256
     Hash value:   cb4280385739d3d722744ec712dccd4f454f458752617694c3ac4c6a1bdf8                                                                                         45c
   Verifying Hash Integrity ... sha256+ OK
   Loading fdt from 0x0a100000 to 0x0a100000
   Booting using the fdt blob at 0x0a100000
   Loading Kernel Image from 0x799cc600 to 0x00a80000 ... OK
  'reserved-memory' linux,cma: addr=10000000 size=800000
  'reserved-memory' ramoops@110000: addr=110000 size=f0000
   Using Device Tree in place at 000000000a100000, end 000000000a123206
Adding bank: 0x00a00000 - 0x80000000 (size: 0x7f600000)
Total: 1075.626 ms

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
[    0.000000] Linux version 4.19.232 (ubuntu@ubuntu) ((no: 330e82b263990b121882                                                                                         0d784f5a01e9c471f037) (sdk version: rk356x_linux_bsp_release_20220726_v1.3.0a.xm                                                                                         l) (gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05), GNU ld (Linaro_Binutils                                                                                         -2017.05) 2.27.0.20161019) #1 SMP Fri Oct 28 12:30:06 -03 2022
[    0.000000] Machine model: Rockchip RK3566 EVB3 DDR3 V10 Board
[    0.000000] earlycon: uart8250 at MMIO32 0x00000000fe660000 (options '')
[    0.000000] bootconsole [uart8250] enabled
[    0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'drm-                                                                                         cubic-lut@00000000': base 0x0000000000000000, size 0 MiB
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000010000000, s                                                                                         ize 8 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id share                                                                                         d-dma-pool
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 24 pages/cpu s60136 r8192 d29976 u98304
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: Virtualization Host Extensions
[    0.000000] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 513576
[    0.000000] Kernel command line: storagemedia=emmc androidboot.storagemedia=e                                                                                         mmc androidboot.mode=normal  earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Memory: 2007908K/2086912K available (15166K kernel code, 1956K rw                                                                                         data, 5324K rodata, 1600K init, 598K bss, 70812K reserved, 8192K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] ftrace: allocating 54438 entries in 213 pages
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: no VLPI support, no direct LPI support
[    0.000000] ITS [mem 0xfd440000-0xfd45ffff]
[    0.000000] ITS@0x00000000fd440000: allocated 8192 Devices @7f580000 (indirec                                                                                         t, esz 8, psz 64K, shr 0)
[    0.000000] ITS@0x00000000fd440000: allocated 32768 Interrupt Collections @7f                                                                                         590000 (flat, esz 2, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GIC: using LPI property table @0x000000007f5a0000
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000fd460000
[    0.000000] CPU0: using LPI pending table @0x000000007f5b0000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] random: random: get_random_bytes called from start_kernel+0x36c/0                                                                                         x514 with crng_init=0
[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles:                                                                                          0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000006] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 43980                                                                                         46511097ns
[    0.002305] Console: colour dummy device 80x25
[    0.002769] Calibrating delay loop (skipped), value calculated using timer fr                                                                                         equency.. 48.00 BogoMIPS (lpj=80000)
[    0.003720] pid_max: default: 32768 minimum: 301
[    0.004311] Security Framework initialized
[    0.004707] AppArmor: AppArmor disabled by boot time parameter
[    0.005305] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.005973] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.008786] ASID allocator initialised with 32768 entries
[    0.009524] rcu: Hierarchical SRCU implementation.
[    0.013210] Platform MSI: interrupt-controller@fd440000 domain created
[    0.014387] PCI/MSI: /interrupt-controller@fd400000/interrupt-controller@fd44                                                                                         0000 domain created
[    0.016137] smp: Bringing up secondary CPUs ...
[    0.017439] Detected VIPT I-cache on CPU1
[    0.017485] GICv3: CPU1: found redistributor 100 region 0:0x00000000fd480000
[    0.017546] CPU1: using LPI pending table @0x000000007f740000
[    0.017614] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[    0.018602] Detected VIPT I-cache on CPU2
[    0.018638] GICv3: CPU2: found redistributor 200 region 0:0x00000000fd4a0000
[    0.018693] CPU2: using LPI pending table @0x000000007f7a0000
[    0.018745] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
[    0.019751] Detected VIPT I-cache on CPU3
[    0.019783] GICv3: CPU3: found redistributor 300 region 0:0x00000000fd4c0000
[    0.019842] CPU3: using LPI pending table @0x000000007f7c0000
[    0.019893] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
[    0.020033] smp: Brought up 1 node, 4 CPUs
[    0.026950] SMP: Total of 4 processors activated.
[    0.027387] CPU features: detected: GIC system register CPU interface
[    0.027981] CPU features: detected: Privileged Access Never
[    0.028491] CPU features: detected: LSE atomic instructions
[    0.029005] CPU features: detected: User Access Override
[    0.029497] CPU features: detected: 32-bit EL0 Support
[    0.029971] CPU features: detected: RAS Extension Support
[    0.030683] CPU: All CPU(s) started at EL2
[    0.031096] alternatives: patching kernel code
[    0.039900] devtmpfs: initialized
[    0.070070] Registered cp15_barrier emulation handler
[    0.070567] Registered setend emulation handler
[    0.071382] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ma                                                                                         x_idle_ns: 6370867519511994 ns
[    0.072354] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.073231] pinctrl core: initialized pinctrl subsystem
[    0.074900] NET: Registered protocol family 16
[    0.076033] audit: initializing netlink subsys (disabled)
[    0.076826] audit: type=2000 audit(0.069:1): state=initialized audit_enabled=                                                                                         0 res=1
[    0.080732] cpuidle: using governor menu
[    0.081138] Registered FIQ tty driver
[    0.081996] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.082960] DMA: preallocated 256 KiB pool for atomic allocations
[    0.087894] console [pstore-1] enabled
[    0.088289] pstore: Registered ramoops as persistent store backend
[    0.088867] ramoops: attached 0xf0000@0x110000, ecc: 0/0
[    0.126783] rockchip-gpio fdd60000.gpio: probed gpio0 (fdd60000.gpio)
[    0.128124] rockchip-gpio fe740000.gpio: probed gpio1 (fe740000.gpio)
[    0.129491] rockchip-gpio fe750000.gpio: probed gpio2 (fe750000.gpio)
[    0.130784] rockchip-gpio fe760000.gpio: probed gpio3 (fe760000.gpio)
[    0.132084] rockchip-gpio fe770000.gpio: probed gpio4 (fe770000.gpio)
[    0.132827] rockchip-pinctrl pinctrl: probed pinctrl
[    0.150993] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.151897] cryptd: max_cpu_qlen set to 1000
[[    0.154501] console [ttyFIQ0] enabled
    0.154501] console [ttyFIQ0] enabled
[    0.155214] bootconsole [uart8250] disabled
[    0.155214] bootconsole [uart8250] disabled
[    0.155908] Registered fiq debugger ttyFIQ0
[    0.157064] vcc3v3_sys: supplied by dc_12v
[    0.157572] vcc5v0_sys: supplied by dc_12v
[    0.159938] vcc3v3_vga: supplied by vcc3v3_sys
[    0.161886] rk_iommu fde4b000.iommu: version = 2
[    0.162736] rk_iommu fdea0800.iommu: version = 2
[    0.163271] rk_iommu fded0480.iommu: version = 2
[    0.163666] rk_iommu fdee0800.iommu: version = 2
[    0.164037] rk_iommu fdef0800.iommu: version = 2
[    0.164406] rk_iommu fdf40f00.iommu: version = 2
[    0.164858] rk_iommu fdf80800.iommu: version = 2
[    0.165298] rk_iommu fdff1a00.iommu: version = 2
[    0.165652] rk_iommu fe043e00.iommu: version = 2
[    0.166780] SCSI subsystem initialized
[    0.167156] usbcore: registered new interface driver usbfs
[    0.167250] usbcore: registered new interface driver hub
[    0.167331] usbcore: registered new device driver usb
[    0.167469] media: Linux media interface: v0.10
[    0.167538] videodev: Linux video capture interface: v2.00
[    0.167692] pps_core: LinuxPPS API ver. 1 registered
[    0.167718] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giome                                                                                         tti <giometti@linux.it>
[    0.167762] PTP clock support registered
[    0.168206] arm-scmi firmware:scmi: SCMI Protocol v2.0 'rockchip:' Firmware v                                                                                         ersion 0x0
[    0.171308] Advanced Linux Sound Architecture Driver Initialized.
[    0.172060] Bluetooth: Core ver 2.22
[    0.172144] NET: Registered protocol family 31
[    0.172170] Bluetooth: HCI device and connection manager initialized
[    0.172200] Bluetooth: HCI socket layer initialized
[    0.172232] Bluetooth: L2CAP socket layer initialized
[    0.172342] Bluetooth: SCO socket layer initialized
[    0.174968] rockchip-cpuinfo cpuinfo: SoC            : 35662000
[    0.175007] rockchip-cpuinfo cpuinfo: Serial         : baedc7b8eb5ab5fa
[    0.176198] clocksource: Switched to clocksource arch_sys_counter
[    0.283486] thermal thermal_zone1: power_allocator: sustainable_power will be                                                                                          estimated
[    0.283979] NET: Registered protocol family 2
[    0.284221] IP idents hash table entries: 32768 (order: 6, 262144 bytes)
[    0.285975] tcp_listen_portaddr_hash hash table entries: 1024 (order: 3, 4096                                                                                         0 bytes)
[    0.286067] TCP established hash table entries: 16384 (order: 5, 131072 bytes                                                                                         )
[    0.286342] TCP bind hash table entries: 16384 (order: 7, 524288 bytes)
[    0.286910] TCP: Hash tables configured (established 16384 bind 16384)
[    0.287153] UDP hash table entries: 1024 (order: 4, 98304 bytes)
[    0.287304] UDP-Lite hash table entries: 1024 (order: 4, 98304 bytes)
[    0.287705] NET: Registered protocol family 1
[    0.289785] Trying to unpack rootfs image as initramfs...
[    0.695797] Freeing initrd memory: 6792K
[    0.697353] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters av                                                                                         ailable
[    0.698220] kvm [1]: 16-bit VMID
[    0.698263] kvm [1]: GICv3: no GICV resource entry
[    0.698277] kvm [1]: disabling GICv2 emulation
[    0.698289] kvm [1]: GIC system register CPU interface enabled
[    0.698469] kvm [1]: vgic interrupt IRQ1
[    0.698707] kvm [1]: VHE mode initialized successfully
[    0.701401] Initialise system trusted keyrings
[    0.701690] workingset: timestamp_bits=45 max_order=19 bucket_order=0
[    0.712121] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.712590] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[    0.713089] fuse init (API version 7.27)
[    0.713756] SGI XFS with security attributes, no debug enabled
[    0.717880] NET: Registered protocol family 38
[    0.717966] Key type asymmetric registered
[    0.717994] Asymmetric key parser 'x509' registered
[    0.718065] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 2                                                                                         44)
[    0.718285] io scheduler noop registered
[    0.718311] io scheduler deadline registered
[    0.718517] io scheduler cfq registered (default)
[    0.718546] io scheduler mq-deadline registered
[    0.718567] io scheduler kyber registered
[    0.720005] rockchip-csi2-dphy csi2-dphy0: csi2 dphy0 probe successfully!
[    0.720243] rockchip-csi2-dphy-hw fe870000.csi2-dphy-hw: csi2 dphy hw probe s                                                                                         uccessfully!
[    0.723025] phy phy-fe8a0000.usb2-phy.0: Linked as a consumer to regulator.4
[    0.723449] phy phy-fe8a0000.usb2-phy.1: Linked as a consumer to regulator.5
[    0.725330] extcon extcon1: failed to create extcon usb2-phy link
[    0.725521] phy phy-fe8b0000.usb2-phy.2: Linked as a consumer to regulator.4
[    0.725764] phy phy-fe8b0000.usb2-phy.3: Linked as a consumer to regulator.4
[    0.725939] phy phy-fe8b0000.usb2-phy.3: No vbus specified for otg port
[    0.730752] rockchip-edpphy-naneng fdcb0000.edp-phy: failed to get grf: -22
[    0.730824] rockchip-edpphy-naneng: probe of fdcb0000.edp-phy failed with error -22
[    0.735541] pwm-backlight backlight: backlight supply power not found, using dummy regulator
[    0.735675] pwm-backlight backlight: Linked as a consumer to regulator.0
[    0.736030] pwm-backlight backlight1: backlight1 supply power not found, using dummy regulator
[    0.736126] pwm-backlight backlight1: Linked as a consumer to regulator.0
[    0.736523] mpp_service mpp-srv: 17e24d4a84af author: Ding Wei 2022-05-05 video: rockchip: mpp: rkvdec2: task->irq_status set for link mode
[    0.736556] mpp_service mpp-srv: probe start
[    0.737798] iommu: Adding device fdf40000.rkvenc to group 5
[    0.737854] mpp_rkvenc fdf40000.rkvenc: Linked as a consumer to fdf40f00.iommu
[    0.738142] mpp_rkvenc fdf40000.rkvenc: probing start
[    0.738804] mpp_rkvenc fdf40000.rkvenc: venc regulator not ready, retry
[    0.738835] rkvenc_init:1199: failed to add venc devfreq
[    0.739330] mpp_rkvenc fdf40000.rkvenc: probing finish
[    0.740840] iommu: Adding device fdea0400.vdpu to group 1
[    0.740901] mpp_vdpu2 fdea0400.vdpu: Linked as a consumer to fdea0800.iommu
[    0.741151] mpp_vdpu2 fdea0400.vdpu: probe device
[    0.742001] mpp_vdpu2 fdea0400.vdpu: probing finish
[    0.742782] iommu: Adding device fdee0000.vepu to group 3
[    0.742840] mpp_vepu2 fdee0000.vepu: Linked as a consumer to fdee0800.iommu
[    0.743171] mpp_vepu2 fdee0000.vepu: probe device
[    0.743965] mpp_vepu2 fdee0000.vepu: probing finish
[    0.744724] iommu: Adding device fdef0000.iep to group 4
[    0.744783] mpp-iep2 fdef0000.iep: Linked as a consumer to fdef0800.iommu
[    0.745003] mpp-iep2 fdef0000.iep: probe device
[    0.745667] mpp-iep2 fdef0000.iep: allocate roi buffer failed
[    0.745909] mpp-iep2 fdef0000.iep: probing finish
[    0.746690] iommu: Adding device fded0000.jpegd to group 2
[    0.746748] mpp_jpgdec fded0000.jpegd: Linked as a consumer to fded0480.iommu
[    0.747020] mpp_jpgdec fded0000.jpegd: probe device
[    0.747821] mpp_jpgdec fded0000.jpegd: probing finish
[    0.748595] iommu: Adding device fdf80200.rkvdec to group 6
[    0.748652] mpp_rkvdec2 fdf80200.rkvdec: Linked as a consumer to fdf80800.iommu
[    0.748975] mpp_rkvdec2 fdf80200.rkvdec: probing start
[    0.749641] mpp_rkvdec2 fdf80200.rkvdec: shared_niu_a is not found!
[    0.749672] rkvdec2_init:661: No niu aclk reset resource define
[    0.749700] mpp_rkvdec2 fdf80200.rkvdec: shared_niu_h is not found!
[    0.749720] rkvdec2_init:664: No niu hclk reset resource define
[    0.749954] mpp_rkvdec2 fdf80200.rkvdec: sram_start 0x00000000fdcc0000
[    0.749983] mpp_rkvdec2 fdf80200.rkvdec: rcb_iova 0x0000000010000000
[    0.750006] mpp_rkvdec2 fdf80200.rkvdec: sram_size 45056
[    0.750027] mpp_rkvdec2 fdf80200.rkvdec: rcb_size 65536
[    0.750050] mpp_rkvdec2 fdf80200.rkvdec: min_width 512
[    0.750076] mpp_rkvdec2 fdf80200.rkvdec: link mode resource not found
[    0.750400] mpp_rkvdec2 fdf80200.rkvdec: probing finish
[    0.750921] mpp_service mpp-srv: probe success
[    0.756707] dma-pl330 fe530000.dmac: Loaded driver for PL330 DMAC-241330
[    0.756736] dma-pl330 fe530000.dmac:         DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[    0.760082] dma-pl330 fe550000.dmac: Loaded driver for PL330 DMAC-241330
[    0.760125] dma-pl330 fe550000.dmac:         DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[    0.761875] rockchip-system-monitor rockchip-system-monitor: system monitor probe
[    0.763313] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    0.764524] fe650000.serial: ttyS1 at MMIO 0xfe650000 (irq = 56, base_baud = 1500000) is a 16550A
[    0.768139] random: fast init done
[    0.768494] random: crng init done
[    0.768798] iommu: Adding device fe040000.vop to group 8
[    0.768862] rockchip-vop2 fe040000.vop: Linked as a consumer to fe043e00.iommu
[    0.772945] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    0.775787] rockchip-drm display-subsystem: Linked as a consumer to fe040000.vop
[    0.776690] rockchip-drm display-subsystem: Linked as a consumer to fe0c0000.edp
[    0.777413] rockchip-drm display-subsystem: Linked as a consumer to fe0a0000.hdmi
[    0.778010] rockchip-drm display-subsystem: Linked as a consumer to fe060000.dsi
[    0.784627] mali fde60000.gpu: Kernel DDK version g7p1-01bet0
[    0.784706] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    0.784802] mali fde60000.gpu: Device initialization Deferred
[    0.785920] brd: module loaded
[    0.797007] loop: module loaded
[    0.797731] zram: Added device: zram0
[    0.797927] lkdtm: No crash points registered, enable through debugfs
[    0.801414] register firefly_spi_init spi return v = :0
[    0.801859] CAN device driver interface
[    0.804409] rk_gmac-dwmac fe010000.ethernet: no regulator found
[    0.804458] rk_gmac-dwmac fe010000.ethernet: clock input or output? (output).
[    0.804477] rk_gmac-dwmac fe010000.ethernet: TX delay(0x41).
[    0.804493] rk_gmac-dwmac fe010000.ethernet: RX delay(0x2e).
[    0.804515] rk_gmac-dwmac fe010000.ethernet: integrated PHY? (no).
[    0.809610] rk_gmac-dwmac fe010000.ethernet: init for RGMII
[    0.809993] rk_gmac-dwmac fe010000.ethernet: User ID: 0x30, Synopsys ID: 0x51
[    0.810025] rk_gmac-dwmac fe010000.ethernet:         DWMAC4/5
[    0.810052] rk_gmac-dwmac fe010000.ethernet: DMA HW capability register supported
[    0.810076] rk_gmac-dwmac fe010000.ethernet: RX Checksum Offload Engine supported
[    0.810097] rk_gmac-dwmac fe010000.ethernet: TX Checksum insertion supported
[    0.810116] rk_gmac-dwmac fe010000.ethernet: Wake-Up On Lan supported
[    0.810181] rk_gmac-dwmac fe010000.ethernet: TSO supported
[    0.810197] rk_gmac-dwmac fe010000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    0.810222] rk_gmac-dwmac fe010000.ethernet: TSO feature enabled
[    0.949762] usbcore: registered new interface driver rndis_wlan
[    0.949878] usbcore: registered new interface driver rtl8150
[    0.949962] usbcore: registered new interface driver r8152
[    0.950045] usbcore: registered new interface driver asix
[    0.950130] usbcore: registered new interface driver ax88179_178a
[    0.950208] usbcore: registered new interface driver cdc_ether
[    0.950285] usbcore: registered new interface driver rndis_host
[    0.950387] usbcore: registered new interface driver cdc_ncm
[    0.950480] usbcore: registered new interface driver qmi_wwan_q
[    0.950560] usbcore: registered new interface driver qmi_wwan
[    0.950627] usbcore: registered new interface driver cdc_mbim
[    0.952321] dwc3 fcc00000.dwc3: Failed to get clk 'ref': -2
[    0.955920] dwc3 fd000000.dwc3: Failed to get clk 'ref': -2
[    0.961132] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    0.961183] ehci-pci: EHCI PCI platform driver
[    0.961294] ehci-platform: EHCI generic platform driver
[    0.961790] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    0.961832] ohci-platform: OHCI generic platform driver
[    0.963337] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    0.963664] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[    0.963912] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x0000001002010010
[    0.964018] xhci-hcd xhci-hcd.0.auto: irq 68, io mem 0xfcc00000
[    0.964529] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
[    0.964561] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.964587] usb usb1: Product: xHCI Host Controller
[    0.964609] usb usb1: Manufacturer: Linux 4.19.232 xhci-hcd
[    0.964630] usb usb1: SerialNumber: xhci-hcd.0.auto
[    0.965360] hub 1-0:1.0: USB hub found
[    0.965438] hub 1-0:1.0: 1 port detected
[    0.965991] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    0.966313] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[    0.966360] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
[    0.966522] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[    0.966740] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
[    0.966771] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.966787] usb usb2: Product: xHCI Host Controller
[    0.966802] usb usb2: Manufacturer: Linux 4.19.232 xhci-hcd
[    0.966824] usb usb2: SerialNumber: xhci-hcd.0.auto
[    0.967473] hub 2-0:1.0: USB hub found
[    0.967546] hub 2-0:1.0: 1 port detected
[    0.968343] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[    0.968644] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 3
[    0.968888] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x0000011002010010
[    0.968991] xhci-hcd xhci-hcd.1.auto: irq 69, io mem 0xfd000000
[    0.969483] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
[    0.969553] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.969582] usb usb3: Product: xHCI Host Controller
[    0.969597] usb usb3: Manufacturer: Linux 4.19.232 xhci-hcd
[    0.969611] usb usb3: SerialNumber: xhci-hcd.1.auto
[    0.970282] hub 3-0:1.0: USB hub found
[    0.970359] hub 3-0:1.0: 1 port detected
[    0.970882] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[    0.971133] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 4
[    0.971177] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
[    0.971303] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
[    0.971531] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
[    0.971562] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.971586] usb usb4: Product: xHCI Host Controller
[    0.971608] usb usb4: Manufacturer: Linux 4.19.232 xhci-hcd
[    0.971623] usb usb4: SerialNumber: xhci-hcd.1.auto
[    0.972249] hub 4-0:1.0: USB hub found
[    0.972321] hub 4-0:1.0: 1 port detected
[    0.973108] usbcore: registered new interface driver cdc_acm
[    0.973138] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
[    0.973227] usbcore: registered new interface driver cdc_wdm
[    0.973591] usbcore: registered new interface driver uas
[    0.973767] usbcore: registered new interface driver usb-storage
[    0.973937] usbcore: registered new interface driver usbserial_generic
[    0.973998] usbserial: USB Serial support registered for generic
[    0.974083] usbcore: registered new interface driver cp210x
[    0.974140] usbserial: USB Serial support registered for cp210x
[    0.974264] usbcore: registered new interface driver ftdi_sio
[    0.974320] usbserial: USB Serial support registered for FTDI USB Serial Device
[    0.974575] usbcore: registered new interface driver keyspan
[    0.974639] usbserial: USB Serial support registered for Keyspan - (without firmware)
[    0.974695] usbserial: USB Serial support registered for Keyspan 1 port adapter
[    0.974752] usbserial: USB Serial support registered for Keyspan 2 port adapter
[    0.974807] usbserial: USB Serial support registered for Keyspan 4 port adapter
[    0.974897] usbcore: registered new interface driver option
[    0.974952] usbserial: USB Serial support registered for GSM modem (1-port)
[    0.975305] usbcore: registered new interface driver oti6858
[    0.975361] usbserial: USB Serial support registered for oti6858
[    0.975445] usbcore: registered new interface driver pl2303
[    0.975496] usbserial: USB Serial support registered for pl2303
[    0.975595] usbcore: registered new interface driver qcserial
[    0.975652] usbserial: USB Serial support registered for Qualcomm USB modem
[    0.975764] usbcore: registered new interface driver sierra
[    0.975819] usbserial: USB Serial support registered for Sierra USB modem
[    0.977665] usbcore: registered new interface driver usbtouchscreen
[    0.977738] ============ himax_hx83102_init 1742 jjlook ==========
[    0.977755] ============ himax_hx83102_probe 1725 jjlook ==========
[    0.977854] cyttsp5_loader_init: Parade TTSP FW Loader Driver (Built TTDA.03.08.874312) rc=0
[    0.977882] cyttsp5_device_access_init: Parade TTSP Device Access Driver (Built TTDA.03.08.874312) rc=0
[    0.978165] .. rk pwm remotectl v2.0 init
[    0.978621] input: fdd70030.pwm as /devices/platform/fdd70030.pwm/input/input0
[    0.979155] remotectl-pwm fdd70030.pwm: pwm version is 0x2130000
[    0.979199] remotectl-pwm fdd70030.pwm: cannot find PWR IRQ
[    0.979226] remotectl-pwm fdd70030.pwm: pwm sip wakeup config error!!
[    0.979245] remotectl-pwm fdd70030.pwm: Donot support ATF Wakeup
[    0.980372] i2c /dev entries driver
[    0.982820] rk808 0-0020: chip id: 0x8090
[    0.982934] rk808 0-0020: No cache defaults, reading back from HW
[    1.006774] rk808 0-0020: source: on=0x40, off=0x00
[    1.006815] rk808 0-0020: support dcdc3 fb mode:-22, 63
[    1.006835] rk808 0-0020: support pmic reset mode:0,0
[    1.013794] rk808-regulator rk808-regulator: there is no dvs0 gpio
[    1.013871] rk808-regulator rk808-regulator: there is no dvs1 gpio
[    1.014375] vdd_logic: supplied by vcc3v3_sys
[    1.015310] vdd_gpu: supplied by vcc3v3_sys
[    1.015820] vcc_ddr: supplied by vcc3v3_sys
[    1.016371] vdd_npu: supplied by vcc3v3_sys
[    1.017242] vcc_1v8: supplied by vcc3v3_sys
[    1.017747] vdda0v9_image: supplied by vcc3v3_sys
[    1.018566] vdda_0v9: supplied by vcc3v3_sys
[    1.019046] vdda0v9_pmu: supplied by vcc3v3_sys
[    1.019556] vccio_acodec: supplied by vcc3v3_sys
[    1.020391] vccio_sd: supplied by vcc3v3_sys
[    1.020886] vcc3v3_pmu: supplied by vcc3v3_sys
[    1.021726] vcca_1v8: supplied by vcc3v3_sys
[    1.022221] vcca1v8_pmu: supplied by vcc3v3_sys
[    1.022712] vcca1v8_image: supplied by vcc3v3_sys
[    1.023609] vcc_3v3: supplied by vcc3v3_sys
[    1.024418] vcc3v3_sd: supplied by vcc3v3_sys
[    1.025072] rk817-battery rk817-battery: Failed to find matching dt id
[    1.025432] rk817-charger rk817-charger: Failed to find matching dt id
[    1.028870] input: rk805 pwrkey as /devices/platform/fdd40000.i2c/i2c-0/0-0020/rk805-pwrkey/input/input1
[    1.035678] rk808-rtc rk808-rtc: registered as rtc0
[    1.037472] rk808-rtc rk808-rtc: setting system clock to 2017-08-04 09:00:03 UTC (1501837203)
[    1.038724] fan53555-regulator 0-0040: Failed to get chip ID!
[    1.041086] rockchip-pinctrl pinctrl: pin gpio3-11 already requested by fe010000.ethernet; cannot claim for fe5e0000.i2c
[    1.041128] rockchip-pinctrl pinctrl: pin-107 (fe5e0000.i2c) status -22
[    1.041147] rockchip-pinctrl pinctrl: could not request pin 107 (gpio3-11) from group i2c5m0-xfer  on device rockchip-pinctrl
[    1.041162] rk3x-i2c fe5e0000.i2c: Error applying setting, reverse things back
[    1.041194] rk3x-i2c: probe of fe5e0000.i2c failed with error -22
[    1.043758] rkcifhw fdfe0000.rkcif: iommu is disabled, using non-iommu buffers
[    1.043806] rkcifhw fdfe0000.rkcif: No reserved memory region assign to CIF
[    1.044085] rkcif rkcif_dvp: rkcif driver version: v00.01.0a
[    1.044168] rkcif rkcif_dvp: attach to cif hw node
[    1.044197] rkcif rkcif_dvp: rkcif wait line 0
[    1.048381] iommu: Adding device fdff0000.rkisp to group 7
[    1.048448] rkisp_hw fdff0000.rkisp: Linked as a consumer to fdff1a00.iommu
[    1.048709] rkisp_hw fdff0000.rkisp: is_thunderboot: 0
[    1.048732] rkisp_hw fdff0000.rkisp: max input:0x0@0fps
[    1.048783] rkisp_hw fdff0000.rkisp: can't request region for resource [mem 0xfdff0000-0xfdffffff]
[    1.049996] rkisp rkisp-vir0: rkisp driver version: v01.08.00
[    1.050409] rkisp rkisp-vir0: Entity type for entity rkisp-isp-subdev was not initialized!
[    1.050452] rkisp rkisp-vir0: Entity type for entity rkisp-csi-subdev was not initialized!
[    1.053354] usbcore: registered new interface driver uvcvideo
[    1.053386] USB Video Class driver (1.1.1)
[    1.053787] rockchip-iodomain fdc20000.syscon:io-domains: Linked as a consumer to regulator.20
[    1.053852] rockchip-iodomain fdc20000.syscon:io-domains: pmuio1(3300000 uV) supplied by vcc3v3_pmu
[    1.054030] rockchip-iodomain fdc20000.syscon:io-domains: pmuio2(3300000 uV) supplied by vcc3v3_pmu
[    1.054197] rockchip-iodomain fdc20000.syscon:io-domains: Linked as a consumer to regulator.18
[    1.054259] rockchip-iodomain fdc20000.syscon:io-domains: vccio1(3300000 uV) supplied by vccio_acodec
[    1.054459] rockchip-iodomain fdc20000.syscon:io-domains: Linked as a consumer to regulator.19
[    1.054518] rockchip-iodomain fdc20000.syscon:io-domains: vccio3(3300000 uV) supplied by vccio_sd
[    1.054656] rockchip-iodomain fdc20000.syscon:io-domains: Linked as a consumer to regulator.14
[    1.054711] rockchip-iodomain fdc20000.syscon:io-domains: vccio4(1800000 uV) supplied by vcc_1v8
[    1.054872] rockchip-iodomain fdc20000.syscon:io-domains: Linked as a consumer to regulator.24
[    1.054936] rockchip-iodomain fdc20000.syscon:io-domains: vccio5(3300000 uV) supplied by vcc_3v3
[    1.055081] rockchip-iodomain fdc20000.syscon:io-domains: vccio6(1800000 uV) supplied by vcc_1v8
[    1.055246] rockchip-iodomain fdc20000.syscon:io-domains: vccio7(3300000 uV) supplied by vcc_3v3
[    1.059644] rockchip-thermal fe710000.tsadc: tsadc is probed successfully!
[    1.061345] Bluetooth: HCI UART driver ver 2.3
[    1.061379] Bluetooth: HCI UART protocol H4 registered
[    1.061399] Bluetooth: HCI UART protocol ATH3K registered
[    1.061694] Bluetooth: HCI UART protocol Broadcom registered
[    1.061822] usbcore: registered new interface driver bfusb
[    1.061925] usbcore: registered new interface driver btusb
[    1.062309] cpu cpu0: leakage=30
[    1.062375] cpu cpu0: pvtm = 89970, from nvmem
[    1.062413] cpu cpu0: pvtm-volt-sel=1
[    1.064750] sdhci: Secure Digital Host Controller Interface driver
[    1.064786] sdhci: Copyright(c) Pierre Ossman
[    1.064806] Synopsys Designware Multimedia Card Interface Driver
[    1.066102] dwmmc_rockchip fe2b0000.dwmmc: IDMAC supports 32-bit address mode.
[    1.066248] dwmmc_rockchip fe2b0000.dwmmc: Using internal DMA controller.
[    1.066284] dwmmc_rockchip fe2b0000.dwmmc: Version ID is 270a
[    1.066376] dwmmc_rockchip fe2b0000.dwmmc: DW MMC controller at irq 41,32 bit host data width,256 deep fifo
[    1.066603] dwmmc_rockchip fe2b0000.dwmmc: Linked as a consumer to regulator.25
[    1.066730] dwmmc_rockchip fe2b0000.dwmmc: Linked as a consumer to regulator.19
[    1.080153] mmc_host mmc0: Bus speed (slot 0) = 375000Hz (slot req 400000Hz, actual 375000HZ div = 0)
[    1.093797] dwmmc_rockchip fe2c0000.dwmmc: IDMAC supports 32-bit address mode.
[    1.093906] dwmmc_rockchip fe2c0000.dwmmc: Using internal DMA controller.
[    1.093929] dwmmc_rockchip fe2c0000.dwmmc: Version ID is 270a
[    1.094016] dwmmc_rockchip fe2c0000.dwmmc: DW MMC controller at irq 42,32 bit host data width,256 deep fifo
[    1.094303] dwmmc_rockchip fe2c0000.dwmmc: allocated mmc-pwrseq
[    1.094339] mmc_host mmc1: card is non-removable.
[    1.313488] mmc_host mmc1: Bus speed (slot 0) = 375000Hz (slot req 400000Hz, actual 375000HZ div = 0)
[    1.326672] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.328320] mmc2: Unknown controller version (5). You may experience problems.
[    1.359643] mmc2: SDHCI controller on fe310000.sdhci [fe310000.sdhci] using ADMA
[    1.362078] mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
[    1.363523] hidraw: raw HID events driver (C) Jiri Kosina
[    1.364204] usbcore: registered new interface driver usbhid
[    1.364234] usbhid: USB HID core driver
[    1.365137] rockchip,bus bus-npu: Linked as a consumer to regulator.10
[    1.365187] rockchip,bus bus-npu: Failed to get leakage
[    1.365276] rockchip,bus bus-npu: pvtm = 89970, from nvmem
[    1.365315] rockchip,bus bus-npu: pvtm-volt-sel=1
[    1.365642] rockchip,bus bus-npu: avs=0
[    1.366006] mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
[    1.367827] mmc1: queuing unknown CIS tuple 0x80 (3 bytes)
[    1.369648] rockchip-saradc fe720000.saradc: Linked as a consumer to regulator.21
[    1.370809] rksfc_base v1.1 2016-01-08
[    1.371678] rksfc fe300000.sfc: rksfc_probe clk rate = 99000000
[    1.371811] rkflash_dev_init enter
[    1.371838] sfc nor id: 0 0 0
[    1.371853] rkflash[1] is invalid
[    1.371856] rkflash_dev_init enter
[    1.371895] sfc_nand id: 0 0 0
[    1.371914] rkflash[2] is invalid
[    1.373214] usbcore: registered new interface driver snd-usb-audio
[    1.376326] rk817-codec rk817-codec: DMA mask not set
[    1.377074] rk817_codec_parse_dt_property: rk809 have no io-channels defined
[    1.377119] invalid rk817->hp_det_gpio: -2
[    1.377141] invalid gpio: -2
[    1.386609] NET: Registered protocol family 10
[    1.388103] Segment Routing with IPv6
[    1.388222] NET: Registered protocol family 17
[    1.388250] can: controller area network core (rev 20170425 abi 9)
[    1.388499] NET: Registered protocol family 29
[    1.388534] can: raw protocol (rev 20170425)
[    1.388559] can: broadcast manager protocol (rev 20170425 t)
[    1.388590] can: netlink gateway (rev 20170425) max_hops=1
[    1.389036] Bluetooth: RFCOMM socket layer initialized
[    1.389101] Bluetooth: RFCOMM ver 1.11
[    1.389138] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    1.389161] Bluetooth: HIDP socket layer initialized
[    1.389184] [BT_RFKILL]: Enter rfkill_rk_init
[    1.389203] [WLAN_RFKILL]: Enter rfkill_wlan_init
[    1.390081] [WLAN_RFKILL]: Enter rfkill_wlan_probe
[    1.390166] [WLAN_RFKILL]: wlan_platdata_parse_dt: wifi_chip_type = ap6398s
[    1.390193] [WLAN_RFKILL]: wlan_platdata_parse_dt: enable wifi power control.
[    1.390214] [WLAN_RFKILL]: wlan_platdata_parse_dt: wifi power controled by gpio.
[    1.390294] [WLAN_RFKILL]: wlan_platdata_parse_dt: WIFI,host_wake_irq = 74, flags = 0.
[    1.390330] [WLAN_RFKILL]: wlan_platdata_parse_dt: The ref_wifi_clk not found !
[    1.390344] [WLAN_RFKILL]: rfkill_wlan_probe: init gpio
[    1.390363] [WLAN_RFKILL]: rfkill_set_wifi_bt_power: 1
[    1.390386] [WLAN_RFKILL]: Exit rfkill_wlan_probe
[    1.391312] [BT_RFKILL]: bluetooth_platdata_parse_dt: get property: uart_rts_gpios = 77.
[    1.391376] [BT_RFKILL]: bluetooth_platdata_parse_dt: get property: BT,reset_gpio = 79.
[    1.391406] [BT_RFKILL]: bluetooth_platdata_parse_dt: get property: BT,wake_gpio = 81.
[    1.391432] [BT_RFKILL]: bluetooth_platdata_parse_dt: get property: BT,wake_host_irq = 80.
[    1.391534] [BT_RFKILL]: Request irq for bt wakeup host
[    1.391688] [BT_RFKILL]: ** disable irq
[    1.391910] [BT_RFKILL]: bt_default device registered.
[    1.392185] Key type dns_resolver registered
[    1.392739] flash vendor_init_thread!
[    1.392756] flash vendor storage:20170308 ret = -1
[    1.392909] mmc2: new HS200 MMC card at address 0001
[    1.394497] mmcblk2: mmc2:0001 032G00 29.1 GiB
[    1.394686] ov5695 2-0036: driver version: 00.01.04
[    1.395015] ov5695 2-0036: 2-0036 supply avdd not found, using dummy regulator
[    1.395293] ov5695 2-0036: Linked as a consumer to regulator.0
[    1.395452] ov5695 2-0036: 2-0036 supply dovdd not found, using dummy regulator
[    1.395592] mmcblk2boot0: mmc2:0001 032G00 partition 1 8.00 MiB
[    1.395646] ov5695 2-0036: 2-0036 supply dvdd not found, using dummy regulator
[    1.396779] mmcblk2boot1: mmc2:0001 032G00 partition 2 8.00 MiB
[    1.397200] mmcblk2rpmb: mmc2:0001 032G00 partition 3 4.00 MiB, chardev (239:0)
[    1.397688] ov5695 2-0036: Unexpected sensor id(000000), ret(-5)
[    1.399230] gc8034 2-0037: driver version: 00.01.06
[    1.399451] gc8034 2-0037: Failed to get power-gpios, maybe no use
[    1.399812] gc8034 2-0037: 2-0037 supply avdd not found, using dummy regulator
[    1.400034] gc8034 2-0037: Linked as a consumer to regulator.0
[    1.400235] gc8034 2-0037: 2-0037 supply dovdd not found, using dummy regulator
[    1.400373] gc8034 2-0037: 2-0037 supply dvdd not found, using dummy regulator
[    1.400485] gc8034 2-0037: lane_num(4)  pixel_rate(319887360)
[    1.400548] gc8034 2-0037: could not get default pinstate
[    1.400573] gc8034 2-0037: could not get sleep pinstate
[    1.401742]  mmcblk2: p1 p2 p3 p4 p5 p6 p7
[    1.405826] gc8034 2-0037: gc8034 read reg:0xf0 failed !
[    1.406047] gc8034 2-0037: gc8034 read reg:0xf1 failed !
[    1.406078] gc8034 2-0037: Unexpected sensor id(000000), ret(-6)
[    1.408250] Loading compiled-in X.509 certificates
[    1.409240] pstore: Using compression: deflate
[    1.411050] rga2: Driver loaded successfully ver:3.2.63318
[    1.411633] rga2: Module initialized.
[    1.442411] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0)
[    1.454097] dwmmc_rockchip fe2c0000.dwmmc: Successfully tuned phase to 135
[    1.459181] mmc1: new ultra high speed SDR104 SDIO card at address 0001
[    1.472265] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.474069] mali fde60000.gpu: Kernel DDK version g7p1-01bet0
[    1.474184] input: adc-keys as /devices/platform/adc-keys/input/input2
[    1.474380] mali fde60000.gpu: Linked as a consumer to regulator.11
[    1.474665] mali fde60000.gpu: dev_pm_opp_set_regulators: no regulator (shadercores) found: -19
[    1.474817] mali fde60000.gpu: leakage=8
[    1.474896] mali fde60000.gpu: pvtm = 89970, from nvmem
[    1.475795] mali fde60000.gpu: avs=0
[    1.475847] W : [File] : drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c; [Line] : 112; [Func] : kbase_platform_rk_init(); power-off-delay-ms not available.
[    1.476471] mali fde60000.gpu: GPU identified as 0x2 arch 7.4.0 r1p0 status 0
[    1.476657] mali fde60000.gpu: No priority control manager is configured
[    1.476691] mali fde60000.gpu: No memory group manager is configured
[    1.477645] rk817-codec rk817-codec: rk817_probe: chip_name:0x80, chip_ver:0x94
[    1.478003] mali fde60000.gpu: l=-2147483648 h=2147483647 hyst=0 l_limit=0 h_limit=0 h_table=0
[    1.479252] mali fde60000.gpu: Probed as mali0
[    1.482531] asoc-simple-card rk809-sound: rk817-hifi <-> fe430000.i2s mapping ok
[    1.485694] asoc-simple-card spdif-sound: dit-hifi <-> fe460000.spdif mapping ok
[    1.487767] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.490059] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.492361] register spi return v = :0
[    1.492404] dhd_module_init: in Dongle Host Driver, version 100.10.545.9 (r826445-20200316-8)
[    1.492422] ======== dhd_wlan_init_plat_data ========
[    1.492434] [WLAN_RFKILL]: rockchip_wifi_get_oob_irq: Enter
[    1.492532] dhd_wlan_init_gpio: WL_HOST_WAKE=-1, oob_irq=96, oob_irq_flags=0x414
[    1.492556] dhd_wlan_init_gpio: WL_REG_ON=-1
[    1.492575] dhd_wifi_platform_load: Enter
[    1.492595] Power-up adapter 'DHD generic adapter'
[    1.493076] wifi_platform_set_power = 1, delay: 200 msec
[    1.493109] ======== PULL WL_REG_ON(-1) HIGH! ========
[    1.493130] [WLAN_RFKILL]: rockchip_wifi_power: 1
[    1.493150] [WLAN_RFKILL]: rockchip_wifi_power: toggle = false
[    1.493168] [WLAN_RFKILL]: wifi turn on power [GPIO-1-0]
[    1.516610] vendor storage:20190527 ret = 0
[    1.580668] devfreq fde60000.gpu: Couldn't update frequency transition information.
[    1.594383] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.822974] wifi_platform_bus_enumerate device present 1
[    1.823012] ======== Card detection to detect SDIO card! ========
[    1.823025] mmc1:mmc host rescan start!
[    1.839277] bcmsdh_register: register client driver
[    1.839584] bcmsdh_sdmmc_probe: Enter num=1
[    1.840549] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.840555] bcmsdh_sdmmc_probe: Enter num=2
[    1.840564] bus num (host idx)=1, slot num (rca)=1
[    1.840607] found adapter info 'DHD generic adapter'
[    1.840718] sdioh_attach: set sd_f2_blocksize 256
[    1.840818] sdioh_attach: sd clock rate = 0
[    1.841335] dhdsdio_probe : no mutex held. set lock
[    1.841564] F1 signature read @0x18000000=0x16024335
[    1.849273] F1 signature OK, socitype:0x1 chip:0x4339 rev:0x1 pkg:0x0
[    1.850588] DHD: dongle ram size is set to 786432(orig 786432) at 0x180000
[    1.850782] [dhd] dhd_conf_set_chiprev : chip=0x4339, chiprev=1
[    1.852213] [dhd] CFG80211-ERROR) wl_cfg80211_netdev_notifier_call : wdev null. Do nothing
[    1.852250] [dhd] CFG80211-ERROR) wl_cfg80211_netdev_notifier_call : wdev null. Do nothing
[    1.852726] dhd_log_dump_init: kernel log buf size = 256KB; logdump_prsrv_tailsize = 80KB; limit prsrv tail size to = 38KB
[    1.854520] dhd_attach(): thread:dhd_watchdog_thread:5f started
[    1.854817] dhd_attach(): thread:dhd_dpc:60 started
[    1.855090] dhd_attach(): thread:dhd_rxf:61 started
[    1.855125] dhd_deferred_work_init: work queue initialized
[    1.855154] dhd_tcpack_suppress_set: TCP ACK Suppress mode 0 -> mode 2
[    1.855317] get_mem_val_from_file: File [/data/misc/wifi/.memdump.info] doesn't exist
[    1.855350] dhd_get_memdump_info: MEMDUMP ENABLED = 3
[    1.855380] sdioh_cis_read: func_cis_ptr[0]=0x10ac
[    1.864278] dhdsdio_probe_init: making DHD_BUS_DOWN
[    1.864496] Dongle Host Driver, version 100.10.545.9 (r826445-20200316-8)
[    1.865425] Register interface [wlan0]  MAC: f0:25:b7:4c:b3:57
[    1.865425]
[    1.865621] dhd_dbg_detach_pkt_monitor, 2100
[    1.865653] dhd_bus_devreset: == Power OFF ==
[    1.865948] dhd_bus_stop: making DHD_BUS_DOWN
[    1.866024] bcmsdh_oob_intr_unregister: Enter
[    1.866047] bcmsdh_oob_intr_unregister: irq is not registered
[    1.866073] dhd_bus_devreset: making dhdpub up FALSE
[    1.866091] dhd_txglom_enable: enable 0
[    1.866105] dhd_bus_devreset: making DHD_BUS_DOWN
[    1.866128] dhd_bus_devreset:  WLAN OFF DONE
[    1.866236] wifi_platform_set_power = 0, delay: 0 msec
[    1.866271] ======== PULL WL_REG_ON(-1) LOW! ========
[    1.866292] [WLAN_RFKILL]: rockchip_wifi_power: 0
[    1.866328] [WLAN_RFKILL]: rockchip_wifi_power: toggle = false
[    1.866341] [WLAN_RFKILL]: rockchip_wifi_power: toggle = false
[    1.866359] [WLAN_RFKILL]: wifi shut off power [GPIO-1-1]
[    1.866381] dhdsdio_probe : the lock is released.
[    1.867465] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.868950] dhd_module_init: Exit err=0
[    1.869621] ==gsl_ts_init==
[    1.869745] ret=0
[    1.870179] rkcif rkcif_dvp: clear unready subdev num: 1
[    1.870211] rkcif_dvp: get_remote_sensor: remote pad is null
[    1.870232] rkcif_dvp: rkcif_update_sensor_info: stream[0] get remote sensor_sd failed!
[    1.870250] rkcif_dvp: Async subdev notifier completed
[    1.871957] iommu: Adding device fde40000.npu to group 0
[    1.872021] RKNPU fde40000.npu: Linked as a consumer to fde4b000.iommu
[    1.872810] RKNPU fde40000.npu: RKNPU: rknpu iommu is enabled, using iommu mode
[    1.873132] RKNPU fde40000.npu: Linked as a consumer to regulator.13
[    1.873243] RKNPU fde40000.npu: can't request region for resource [mem 0xfde40000-0xfde4ffff]
[    1.874157] [drm] Initialized rknpu 0.7.2 20220428 for fde40000.npu on minor 0
[    1.874315] RKNPU fde40000.npu: leakage=4
[    1.874394] RKNPU fde40000.npu: pvtm = 89970, from nvmem
[    1.875356] RKNPU fde40000.npu: avs=0
[    1.876149] RKNPU fde40000.npu: l=0 h=2147483647 hyst=5000 l_limit=0 h_limit=0 h_table=0
[    1.876286] RKNPU fde40000.npu: failed to find power_model node
[    1.876318] RKNPU fde40000.npu: RKNPU: failed to initialize power model
[    1.876341] RKNPU fde40000.npu: RKNPU: failed to get dynamic-coefficient
[    1.877969] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.880151] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    1.888123] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    1.889835] rockchip-pm rockchip-suspend: not set pwm-regulator-config
[    1.891003] I : [File] : drivers/gpu/arm/mali400/mali/linux/mali_kernel_linux.c; [Line] : 417; [Func] : mali_module_init(); svn_rev_string_from_arm of this mali_ko is '', rk_ko_ver is '5', built at '12:43:19', on 'Oct 28 2022'.
[    1.891693] Mali:
[    1.891696] Mali device driver loaded
[    1.891852] rkisp rkisp-vir0: clear unready subdev num: 2
[    1.891884] rockchip-csi2-dphy0: No link between dphy and sensor
[    1.892764] rockchip-csi2-dphy0: No link between dphy and sensor
[    1.892796] rkisp-vir0: update sensor failed
[    1.893249] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_probe] *ERROR* failed to get mipi dphy: -517
[    1.895009] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    1.895045] cfg80211: failed to load regulatory.db
v▒   1.901034]

 

Edited by hotnikq
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Hqnicolas

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First, Make a Full backup of your board!


H96 MAX Board Type 1
Kernel 4.19
RK3566
Linux FIT Image
Ubuntu 20.04 LTS
This image has been compiled without any standardization and should be used for experimental purposes only,
there is no guarantee of compatibility with your device

RK firmware is the firmware packaged in Rockchip’s proprietary format, and can be flashed to eMMC or SD card with the tools provided by Rockchip
(Note: If there is no special instruction, the firmware mentioned on WIKI defaults to RK firmware) .

 

Edited by Hqnicolas
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Hqnicolas

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H96 Max V56 Android 12
1) I am wondering if it does have the AV1 codec?
2) How's the performance? Any glitches or lags?
Hoping for some answers soon.
Gpu:
Mali g52 2ee
H.264 decoder And encoder
Vc1 decoder only
H265 decoder only

I Will Release an Linux kernel 4.19 in a feel weeks

Enviado de meu Mi 9T usando o Tapatalk

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Carol

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 But if you look into this video  around at the point of 11.12 showing the codec - it lists AV01 decoder. Since you actually have the physical unit, would you mind checking it out just to confirm it has the AV1 decoder, please. thanks

 

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Hqnicolas

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Today i was debuging some dts from android against linux and found swiotlb buffer is full (sz: 16384 bytes)

Original:
reg = <0x0 0xfe310000 0x0 0x10000>;  (sz: 16384 bytes)
Update:
reg = <0x0 0xfe310000 0x0 0x100000>   (sz: 1048576 bytes)

the difference betwin linux and android reserved memory

Quote

    sdhci@fe310000 {
        compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
        reg = <0x0 0xfe310000 0x0 0x10000>;
        interrupts = <0x0 0x13 0x4>;
        assigned-clocks = <0x1f 0x7b 0x1f 0x7d>;
        assigned-clock-rates = <0xbebc200 0x16e3600>;
        clocks = <0x1f 0x7c 0x1f 0x7a 0x1f 0x79 0x1f 0x7b 0x1f 0x7d>;
        clock-names = "core", "bus", "axi", "block", "timer";
        status = "okay";
        bus-width = <0x8>;
        supports-emmc;
        non-removable;
                                
        max-frequency = <0xbebc200>;
        phandle = <0x198>;
    };


 

Cause a buffer bug

Quote

'.
[    1.395517] Mali:
[    1.395518] Mali device driver loaded
[    1.395545] rkisp rkisp-vir0: clear unready subdev num: 2
[    1.395560] rockchip-csi2-dphy0: No link between dphy and sensor
[    1.396070] rockchip-csi2-dphy0: No link between dphy and sensor
[    1.396088] rkisp0: update sensor failed
[    1.396246] ALSA device list:
[    1.396258]   #0: rockchip,hdmi
[    1.396268]   #1: ROCKCHIP,SPDIF
[    1.396708] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    1.396729] cfg80211: failed to load regulatory.db
[    1.398199] Freeing unused kernel memory: 1536K
[    1.421743] Run /init as init process
NAME=Buildroot
VERSION=2018.02-rc3-02965-gfee6bd30e3
ID=buildroot
VERSION_ID=2018.02-rc3
PRETTY_NAME="Buildroot 2018.02-rc3"
Starting logging: OK
Populating /dev using udev: [    1.460321] udevd[130]: starting version 3.2.7
[    1.462494] udevd[130]: specified group 'kvm' unknown
[    1.466719] udevd[131]: starting eudev-3.2.7
[    1.489294] devfreq fde60000.gpu: Couldn't update frequency transition information.
[    1.505094] dwmmc_rockchip fe2c0000.dwmmc: Successfully tuned phase to 186
[    1.508523] mmc1: new ultra high speed SDR104 SDIO card at address 0001
[    1.607750] sdhci-dwcmshc fe310000.sdhci: swiotlb buffer is full (sz: 65536 bytes)
[    1.624894] rockchip-vop2 fe040000.vop: [drm:vop2_crtc_atomic_enable] Update mode to 3840x2160p30, type: 11 for                                                   vp0
[    1.625517] rockchip-vop2 fe040000.vop: [drm:vop2_crtc_atomic_enable] Update mode to 1080x1920p60, type: 16 for                                                   vp1
[    1.634340] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_encoder_enable] final DSI-Link bandwidth: 880 x 4 Mbps
[    1.637637] dw-mipi-dsi fe060000.dsi: [drm:dw_mipi_dsi_pre_enable] *ERROR* PHY is not locked
[    1.659053] sdhci-dwcmshc fe310000.sdhci: swiotlb buffer is full (sz: 16384 bytes)
[    1.659210] sdhci-dwcmshc fe310000.sdhci: swiotlb buffer is full (sz: 16384 bytes)
[    1.659231] ------------[ cut here ]------------
 

 

Edited by hotnikq
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Hqnicolas

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The development kit that works with this board is that of Quartz64,

as it has the patches corresponding to the use of Mali Panfrost gpu  quartz64-model-A_bsp Linux.tar.gz  (mirror)

 

i adapted the dts files to work on linux you can compare the modifications
H96_MAX_DTS_DTB_Release_Linux_4LTS_Board_Type_1

H96_MAX_DTS_DTB_Release_Linux_4LTS_Board_Type_2

H96 MAX DTS DTB Release Linux 4LTS Board Type 1.7z H96 MAX DTS DTB Release Linux 4LTS Board Type 2.7z

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Update on Kernel DEF CONFIG

how to extract linux_defconfig From android Kernel file
H96 MAX RK3566 KERNEL AND SCRIPT


File from /build/kernel/arch/arm64/configs

Quote

CONFIG_DEFAULT_HOSTNAME="localhost"
#
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=60301
CONFIG_CLANG_VERSION=0
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
# CONFIG_AUDITSYSCALL is not set

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_SCHED_AVG_IRQ=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
# CONFIG_PSI_DEFAULT_DISABLED is not set
CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_BUILD_BIN2C=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_IKHEADERS=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_SWAP_ENABLED=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
# CONFIG_DEBUG_BLK_CGROUP is not set
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_CFS_BANDWIDTH is not set
# CONFIG_RT_GROUP_SCHED is not set
# CONFIG_CGROUP_PIDS is not set
# CONFIG_CGROUP_RDMA is not set
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
# CONFIG_CGROUP_DEVICE is not set
CONFIG_CGROUP_CPUACCT=y
# CONFIG_CGROUP_PERF is not set
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_SCHED_AUTOGROUP is not set
CONFIG_SCHED_TUNE=y
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_INITRD_ASYNC=y
# CONFIG_ROCKCHIP_ONE_INITRD is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_FHANDLE is not set
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT_ALWAYS_ON=y
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_SYSFS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
CONFIG_SLUB_CPU_PARTIAL=y
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA32=y
CONFIG_HAVE_GENERIC_GUP=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BRCMSTB is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LAYERSCAPE is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_STRATIX10 is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set

#
# Bus support
#
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
# CONFIG_PCIEAER_INJECT is not set
# CONFIG_PCIE_ECRC is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEBUG is not set
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_DPC is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_HOST is not set
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
# CONFIG_ROCKCHIP_PCIE_DMA_OBJ is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_DW_ROCKCHIP=y
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
# CONFIG_ARM64_ERRATUM_826319 is not set
# CONFIG_ARM64_ERRATUM_827319 is not set
# CONFIG_ARM64_ERRATUM_824069 is not set
# CONFIG_ARM64_ERRATUM_819472 is not set
# CONFIG_ARM64_ERRATUM_832075 is not set
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
# CONFIG_CAVIUM_ERRATUM_22375 is not set
# CONFIG_CAVIUM_ERRATUM_23154 is not set
# CONFIG_CAVIUM_ERRATUM_27456 is not set
# CONFIG_CAVIUM_ERRATUM_30115 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
# CONFIG_HISILICON_ERRATUM_161600802 is not set
# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
CONFIG_ARCH_NR_GPIO=256
# CONFIG_NUMA is not set
CONFIG_HOLES_IN_ZONE=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
# CONFIG_ARM64_DMA_USE_IOMMU is not set
CONFIG_SECCOMP=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDEN_EL2_VECTORS=y
CONFIG_ARM64_SSBD=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y
CONFIG_ARM64_SW_TTBR0_PAN=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_VHE=y

#
# ARMv8.2 architectural features
#
CONFIG_ARM64_UAO=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_RELOCATABLE=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y

#
# Boot options
#
CONFIG_CMDLINE=""
# CONFIG_EFI is not set
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_HAS_WAKELOCK=y
CONFIG_WAKELOCK=y
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_DPM_WATCHDOG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_DT_IDLE_STATES=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_CPUIDLE=y

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_TIMES=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_CPUFREQ_DUMMY is not set
# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
# CONFIG_ARM_SCMI_CPUFREQ is not set
# CONFIG_QORIQ_CPUFREQ is not set

#
# Firmware Drivers
#
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_FIRMWARE_MEMMAP is not set
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_ROCKCHIP_SIP=y
CONFIG_HAVE_ARM_SMCCC=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# Tegra firmware driver
#
# CONFIG_VIRTUALIZATION is not set
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA256_ARM64=y
# CONFIG_CRYPTO_SHA512_ARM64 is not set
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
# CONFIG_CRYPTO_SHA512_ARM64_CE is not set
# CONFIG_CRYPTO_SHA3_ARM64 is not set
# CONFIG_CRYPTO_SM3_ARM64_CE is not set
# CONFIG_CRYPTO_SM4_ARM64_CE is not set
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRC32_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
# CONFIG_CRYPTO_CHACHA20_NEON is not set
# CONFIG_CRYPTO_POLY1305_NEON is not set
# CONFIG_CRYPTO_AES_ARM64_BS is not set

#
# General architecture-dependent options
#
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_THINLTO=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_REFCOUNT_FULL=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_HAS_RELR=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_PLUGIN_HOSTCC=""
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
# CONFIG_BLK_DEV_ZONED is not set
# CONFIG_BLK_DEV_THROTTLING is not set
CONFIG_BLK_CMDLINE_PARSER=y
# CONFIG_BLK_WBT is not set
# CONFIG_BLK_CGROUP_IOLATENCY is not set
CONFIG_BLK_DEBUG_FS=y
# CONFIG_BLK_SED_OPAL is not set
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_CFQ_GROUP_IOSCHED=y
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
# CONFIG_GKI_HIDDEN_DRM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_REGMAP_CONFIGS is not set
# CONFIG_GKI_HIDDEN_CRYPTO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_SOC_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPIO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_VIRTUAL_CONFIGS is not set
# CONFIG_GKI_LEGACY_WEXT_ALLCONFIG is not set
# CONFIG_GKI_HIDDEN_SOC_PM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_VIDEOBUF2_CONFIGS is not set
# CONFIG_GKI_HIDDEN_USB_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SOC_BUS_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPU_CONFIGS is not set
# CONFIG_GKI_HIDDEN_IRQ_CONFIGS is not set
# CONFIG_GKI_HACKS_TO_FIX is not set
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
# CONFIG_BINFMT_MISC is not set
CONFIG_COREDUMP=y

#
# Memory Management options
#
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_NO_BOOTMEM=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
# CONFIG_TRANSPARENT_HUGEPAGE is not set
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_AREAS=7
# CONFIG_ZPOOL is not set
# CONFIG_ZBUD is not set
CONFIG_ZSMALLOC=y
# CONFIG_PGTABLE_MAPPING is not set
# CONFIG_ZSMALLOC_STAT is not set
# CONFIG_MM_EVENT_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_FRAME_VECTOR=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_TLS is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=y
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
# CONFIG_XDP_SOCKETS is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
# CONFIG_IP_ROUTE_MULTIPATH is not set
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IP_TUNNEL=y
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=y
CONFIG_NET_UDP_TUNNEL=y
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
# CONFIG_INET_ESP_OFFLOAD is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
# CONFIG_INET_RAW_DIAG is not set
CONFIG_INET_DIAG_DESTROY=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
# CONFIG_INET6_ESP_OFFLOAD is not set
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=y
# CONFIG_IPV6_ILA is not set
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_INET6_XFRM_MODE_TRANSPORT=y
CONFIG_INET6_XFRM_MODE_TUNNEL=y
CONFIG_INET6_XFRM_MODE_BEET=y
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
CONFIG_IPV6_VTI=y
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
# CONFIG_IPV6_GRE is not set
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
# CONFIG_IPV6_MROUTE is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_NETLABEL is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=y

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
# CONFIG_NETFILTER_NETLINK_ACCT is not set
CONFIG_NETFILTER_NETLINK_QUEUE=y
CONFIG_NETFILTER_NETLINK_LOG=y
# CONFIG_NETFILTER_NETLINK_OSF is not set
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_COMMON=y
# CONFIG_NF_LOG_NETDEV is not set
CONFIG_NETFILTER_CONNCOUNT=y
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_SECMARK=y
# CONFIG_NF_CONNTRACK_ZONES is not set
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
# CONFIG_NF_CONNTRACK_LABELS is not set
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_H323=y
CONFIG_NF_CONNTRACK_IRC=y
CONFIG_NF_CONNTRACK_BROADCAST=y
CONFIG_NF_CONNTRACK_NETBIOS_NS=y
# CONFIG_NF_CONNTRACK_SNMP is not set
CONFIG_NF_CONNTRACK_PPTP=y
CONFIG_NF_CONNTRACK_SANE=y
# CONFIG_NF_CONNTRACK_SIP is not set
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set
CONFIG_NF_NAT=y
CONFIG_NF_NAT_NEEDED=y
CONFIG_NF_NAT_PROTO_DCCP=y
CONFIG_NF_NAT_PROTO_UDPLITE=y
CONFIG_NF_NAT_PROTO_SCTP=y
CONFIG_NF_NAT_AMANDA=y
CONFIG_NF_NAT_FTP=y
CONFIG_NF_NAT_IRC=y
CONFIG_NF_NAT_TFTP=y
CONFIG_NF_NAT_REDIRECT=y
# CONFIG_NF_TABLES is not set
CONFIG_NETFILTER_XTABLES=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y

#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_CT=y
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
# CONFIG_NETFILTER_XT_TARGET_HL is not set
# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
# CONFIG_NETFILTER_XT_TARGET_LED is not set
CONFIG_NETFILTER_XT_TARGET_LOG=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_NAT=y
CONFIG_NETFILTER_XT_TARGET_NETMAP=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
# CONFIG_NETFILTER_XT_TARGET_TEE is not set
CONFIG_NETFILTER_XT_TARGET_TPROXY=y
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set

#
# Xtables matches
#
# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
CONFIG_NETFILTER_XT_MATCH_BPF=y
# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
# CONFIG_NETFILTER_XT_MATCH_CPU is not set
# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
CONFIG_NETFILTER_XT_MATCH_ECN=y
# CONFIG_NETFILTER_XT_MATCH_ESP is not set
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
CONFIG_NETFILTER_XT_MATCH_HELPER=y
CONFIG_NETFILTER_XT_MATCH_HL=y
# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
CONFIG_NETFILTER_XT_MATCH_L2TP=y
CONFIG_NETFILTER_XT_MATCH_LENGTH=y
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
# CONFIG_NETFILTER_XT_MATCH_OSF is not set
CONFIG_NETFILTER_XT_MATCH_OWNER=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
CONFIG_NETFILTER_XT_MATCH_QUOTA=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
# CONFIG_NETFILTER_XT_MATCH_REALM is not set
# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
CONFIG_NETFILTER_XT_MATCH_SOCKET=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
CONFIG_NETFILTER_XT_MATCH_STRING=y
# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
CONFIG_NETFILTER_XT_MATCH_TIME=y
CONFIG_NETFILTER_XT_MATCH_U32=y
# CONFIG_IP_SET is not set
# CONFIG_IP_VS is not set

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=y
CONFIG_NF_TPROXY_IPV4=y
# CONFIG_NF_DUP_IPV4 is not set
# CONFIG_NF_LOG_ARP is not set
CONFIG_NF_LOG_IPV4=y
CONFIG_NF_REJECT_IPV4=y
CONFIG_NF_NAT_IPV4=y
CONFIG_NF_NAT_MASQUERADE_IPV4=y
CONFIG_NF_NAT_PROTO_GRE=y
CONFIG_NF_NAT_PPTP=y
CONFIG_NF_NAT_H323=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=y
CONFIG_IP_NF_MATCH_ECN=y
CONFIG_IP_NF_MATCH_RPFILTER=y
CONFIG_IP_NF_MATCH_TTL=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
# CONFIG_IP_NF_TARGET_SYNPROXY is not set
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
CONFIG_IP_NF_MANGLE=y
# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
# CONFIG_IP_NF_TARGET_ECN is not set
# CONFIG_IP_NF_TARGET_TTL is not set
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_SECURITY=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=y
CONFIG_NF_TPROXY_IPV6=y
# CONFIG_NF_DUP_IPV6 is not set
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
# CONFIG_NF_NAT_IPV6 is not set
CONFIG_IP6_NF_IPTABLES=y
# CONFIG_IP6_NF_MATCH_AH is not set
# CONFIG_IP6_NF_MATCH_EUI64 is not set
# CONFIG_IP6_NF_MATCH_FRAG is not set
# CONFIG_IP6_NF_MATCH_OPTS is not set
# CONFIG_IP6_NF_MATCH_HL is not set
# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
# CONFIG_IP6_NF_MATCH_MH is not set
CONFIG_IP6_NF_MATCH_RPFILTER=y
# CONFIG_IP6_NF_MATCH_RT is not set
# CONFIG_IP6_NF_MATCH_SRH is not set
# CONFIG_IP6_NF_TARGET_HL is not set
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
CONFIG_IP6_NF_MANGLE=y
CONFIG_IP6_NF_RAW=y
# CONFIG_IP6_NF_SECURITY is not set
# CONFIG_IP6_NF_NAT is not set
CONFIG_NF_DEFRAG_IPV6=y
CONFIG_BRIDGE_NF_EBTABLES=y
CONFIG_BRIDGE_EBT_BROUTE=y
# CONFIG_BRIDGE_EBT_T_FILTER is not set
# CONFIG_BRIDGE_EBT_T_NAT is not set
# CONFIG_BRIDGE_EBT_802_3 is not set
# CONFIG_BRIDGE_EBT_AMONG is not set
# CONFIG_BRIDGE_EBT_ARP is not set
# CONFIG_BRIDGE_EBT_IP is not set
# CONFIG_BRIDGE_EBT_IP6 is not set
# CONFIG_BRIDGE_EBT_LIMIT is not set
# CONFIG_BRIDGE_EBT_MARK is not set
# CONFIG_BRIDGE_EBT_PKTTYPE is not set
# CONFIG_BRIDGE_EBT_STP is not set
# CONFIG_BRIDGE_EBT_VLAN is not set
# CONFIG_BRIDGE_EBT_ARPREPLY is not set
# CONFIG_BRIDGE_EBT_DNAT is not set
# CONFIG_BRIDGE_EBT_MARK_T is not set
# CONFIG_BRIDGE_EBT_REDIRECT is not set
# CONFIG_BRIDGE_EBT_SNAT is not set
# CONFIG_BRIDGE_EBT_LOG is not set
# CONFIG_BRIDGE_EBT_NFLOG is not set
# CONFIG_BPFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
CONFIG_L2TP=y
# CONFIG_L2TP_DEBUGFS is not set
# CONFIG_L2TP_V3 is not set
CONFIG_STP=y
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_HAVE_NET_DSA=y
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
CONFIG_LLC=y
# CONFIG_LLC2 is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
# CONFIG_IEEE802154 is not set
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
# CONFIG_NET_SCH_CBQ is not set
CONFIG_NET_SCH_HTB=y
# CONFIG_NET_SCH_HFSC is not set
CONFIG_NET_SCH_PRIO=y
# CONFIG_NET_SCH_MULTIQ is not set
# CONFIG_NET_SCH_RED is not set
# CONFIG_NET_SCH_SFB is not set
# CONFIG_NET_SCH_SFQ is not set
# CONFIG_NET_SCH_TEQL is not set
# CONFIG_NET_SCH_TBF is not set
# CONFIG_NET_SCH_CBS is not set
# CONFIG_NET_SCH_ETF is not set
# CONFIG_NET_SCH_GRED is not set
# CONFIG_NET_SCH_DSMARK is not set
CONFIG_NET_SCH_NETEM=y
# CONFIG_NET_SCH_DRR is not set
# CONFIG_NET_SCH_MQPRIO is not set
# CONFIG_NET_SCH_SKBPRIO is not set
# CONFIG_NET_SCH_CHOKE is not set
# CONFIG_NET_SCH_QFQ is not set
# CONFIG_NET_SCH_CODEL is not set
# CONFIG_NET_SCH_FQ_CODEL is not set
# CONFIG_NET_SCH_CAKE is not set
# CONFIG_NET_SCH_FQ is not set
# CONFIG_NET_SCH_HHF is not set
# CONFIG_NET_SCH_PIE is not set
CONFIG_NET_SCH_INGRESS=y
# CONFIG_NET_SCH_PLUG is not set
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
# CONFIG_NET_CLS_BASIC is not set
# CONFIG_NET_CLS_TCINDEX is not set
# CONFIG_NET_CLS_ROUTE4 is not set
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
# CONFIG_CLS_U32_PERF is not set
CONFIG_CLS_U32_MARK=y
# CONFIG_NET_CLS_RSVP is not set
# CONFIG_NET_CLS_RSVP6 is not set
CONFIG_NET_CLS_FLOW=y
# CONFIG_NET_CLS_CGROUP is not set
CONFIG_NET_CLS_BPF=y
# CONFIG_NET_CLS_FLOWER is not set
# CONFIG_NET_CLS_MATCHALL is not set
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=y
CONFIG_NET_EMATCH_NBYTE=y
CONFIG_NET_EMATCH_U32=y
CONFIG_NET_EMATCH_META=y
CONFIG_NET_EMATCH_TEXT=y
# CONFIG_NET_EMATCH_IPT is not set
CONFIG_NET_CLS_ACT=y
# CONFIG_NET_ACT_POLICE is not set
# CONFIG_NET_ACT_GACT is not set
# CONFIG_NET_ACT_MIRRED is not set
# CONFIG_NET_ACT_SAMPLE is not set
# CONFIG_NET_ACT_IPT is not set
# CONFIG_NET_ACT_NAT is not set
# CONFIG_NET_ACT_PEDIT is not set
# CONFIG_NET_ACT_SIMP is not set
# CONFIG_NET_ACT_SKBEDIT is not set
# CONFIG_NET_ACT_CSUM is not set
# CONFIG_NET_ACT_VLAN is not set
# CONFIG_NET_ACT_BPF is not set
# CONFIG_NET_ACT_CONNMARK is not set
# CONFIG_NET_ACT_SKBMOD is not set
# CONFIG_NET_ACT_IFE is not set
# CONFIG_NET_ACT_TUNNEL_KEY is not set
# CONFIG_NET_CLS_IND is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
# CONFIG_DNS_RESOLVER is not set
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
# CONFIG_NET_SWITCHDEV is not set
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_STREAM_PARSER is not set
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
CONFIG_BT=y
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
CONFIG_BT_HS=y
CONFIG_BT_LE=y
# CONFIG_BT_LEDS is not set
# CONFIG_BT_SELFTEST is not set
CONFIG_BT_DEBUGFS=y

#
# Bluetooth device drivers
#
# CONFIG_BT_HCIBTUSB is not set
# CONFIG_BT_HCIBTSDIO is not set
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_BCSP is not set
# CONFIG_BT_HCIUART_ATH3K is not set
# CONFIG_BT_HCIUART_INTEL is not set
# CONFIG_BT_HCIUART_AG6XX is not set
# CONFIG_BT_HCIUART_MRVL is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BT_MRVL is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_WEXT is not set
CONFIG_MAC80211=y
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_MINSTREL_HT=y
# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
# CONFIG_MAC80211_LEDS is not set
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
# CONFIG_RFKILL_INPUT is not set
# CONFIG_RFKILL_GPIO is not set
CONFIG_RFKILL_RK=y
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
# CONFIG_NET_DEVLINK is not set
CONFIG_MAY_USE_DEVLINK=y
# CONFIG_FAILOVER is not set
CONFIG_HAVE_EBPF_JIT=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
# CONFIG_FW_CACHE is not set
CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_MALI_MEMORY_GROUP_MANAGER=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_DMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=16
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
CONFIG_GENERIC_ARCH_TOPOLOGY=y

#
# Bus devices
#
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_SIMPLE_PM_BUS is not set
# CONFIG_VEXPRESS_CONFIG is not set
# CONFIG_CONNECTOR is not set
# CONFIG_GNSS is not set
# CONFIG_MTD is not set
CONFIG_DTC=y
CONFIG_OF=y
CONFIG_DTC_SYMBOLS=y
# CONFIG_DTC_OMIT_DISABLED is not set
# CONFIG_DTC_OMIT_EMPTY is not set
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
CONFIG_OF_RESERVED_MEM=y
# CONFIG_OF_OVERLAY is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=y
# CONFIG_ZRAM_WRITEBACK is not set
# CONFIG_ZRAM_MEMORY_TRACKING is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=16
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SKD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TARGET is not set

#
# Misc devices
#
# CONFIG_ROCKCHIP_SCR is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_PCI_ENDPOINT_TEST is not set
CONFIG_UID_SYS_STATS=y
# CONFIG_UID_SYS_STATS_DEBUG is not set
# CONFIG_PIR_ASCHIP is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_CB710_CORE is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set

#
# Intel MIC & related support
#

#
# Intel MIC Bus Driver
#

#
# SCIF Bus Driver
#

#
# VOP Bus Driver
#

#
# Intel MIC Host Driver
#

#
# Intel MIC Card Driver
#

#
# SCIF Driver
#

#
# Intel MIC Coprocessor State Management (COSM) Drivers
#

#
# VOP Driver
#
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_MISC_RTSX_PCI is not set
# CONFIG_MISC_RTSX_USB is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_MQ_DEFAULT=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
CONFIG_CHR_DEV_SG=y
CONFIG_CHR_DEV_SCH=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
# CONFIG_AHCI_CEVA is not set
# CONFIG_AHCI_QORIQ is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
# CONFIG_ATA_SFF is not set
CONFIG_MD=y
# CONFIG_BLK_DEV_MD is not set
# CONFIG_BCACHE is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
# CONFIG_DM_MQ_DEFAULT is not set
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=y
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=y
CONFIG_DM_DEFAULT_KEY=y
CONFIG_DM_SNAPSHOT=y
# CONFIG_DM_THIN_PROVISIONING is not set
# CONFIG_DM_CACHE is not set
# CONFIG_DM_WRITECACHE is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_MIRROR is not set
# CONFIG_DM_RAID is not set
# CONFIG_DM_ZERO is not set
# CONFIG_DM_MULTIPATH is not set
# CONFIG_DM_DELAY is not set
CONFIG_DM_UEVENT=y
# CONFIG_DM_FLAKEY is not set
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_AVB=y
CONFIG_DM_VERITY_FEC=y
# CONFIG_DM_SWITCH is not set
# CONFIG_DM_LOG_WRITES is not set
# CONFIG_DM_INTEGRITY is not set
CONFIG_DM_BOW=y
CONFIG_DM_ANDROID_VERITY_AT_MOST_ONCE_DEFAULT_ENABLED=y
CONFIG_DM_USER=y
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
CONFIG_DUMMY=y
# CONFIG_WIREGUARD is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_FC is not set
# CONFIG_IFB is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_IPVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_GTP is not set
# CONFIG_MACSEC is not set
# CONFIG_NETCONSOLE is not set
CONFIG_TUN=y
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=y
# CONFIG_NLMON is not set
# CONFIG_ARCNET is not set

#
# CAIF transport drivers
#

#
# Distributed Switch Architecture drivers
#
CONFIG_ETHERNET=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_AURORA is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_BROCADE is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_JME is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
# CONFIG_DWMAC_DWC_QOS_ETH is not set
# CONFIG_DWMAC_GENERIC is not set
CONFIG_DWMAC_ROCKCHIP=y
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
# CONFIG_MDIO_BCM_UNIMAC is not set
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_THUNDER is not set
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_ICPLUS_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
# CONFIG_SMSC_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=y
CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
CONFIG_SLIP=y
CONFIG_SLHC=y
CONFIG_SLIP_COMPRESSED=y
# CONFIG_SLIP_SMART is not set
CONFIG_SLIP_MODE_SLIP6=y
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=y
CONFIG_USB_KAWETH=y
CONFIG_USB_PEGASUS=y
CONFIG_USB_RTL8150=y
CONFIG_USB_RTL8152=y
# CONFIG_USB_LAN78XX is not set
CONFIG_USB_USBNET=y
CONFIG_USB_NET_AX8817X=y
CONFIG_USB_NET_AX88179_178A=y
CONFIG_USB_NET_CDCETHER=y
CONFIG_USB_NET_CDC_EEM=y
CONFIG_USB_NET_CDC_NCM=y
# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
CONFIG_USB_NET_CDC_MBIM=y
CONFIG_USB_NET_DM9601=y
# CONFIG_USB_NET_SR9700 is not set
# CONFIG_USB_NET_SR9800 is not set
CONFIG_USB_NET_SMSC75XX=y
CONFIG_USB_NET_SMSC95XX=y
CONFIG_USB_NET_GL620A=y
CONFIG_USB_NET_NET1080=y
CONFIG_USB_NET_PLUSB=y
CONFIG_USB_NET_MCS7830=y
CONFIG_USB_NET_RNDIS_HOST=y
CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
CONFIG_USB_NET_CDC_SUBSET=y
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=y
CONFIG_USB_NET_CX82310_ETH=y
CONFIG_USB_NET_KALMIA=y
CONFIG_USB_NET_QMI_WWAN=y
CONFIG_USB_HSO=y
CONFIG_USB_NET_INT51X1=y
CONFIG_USB_IPHETH=y
CONFIG_USB_SIERRA_NET=y
# CONFIG_USB_VL600 is not set
# CONFIG_USB_NET_CH9200 is not set
CONFIG_WLAN=y
# CONFIG_WIRELESS_WDS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_WL_ROCKCHIP=y
CONFIG_WIFI_BUILD_MODULE=y
# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set
# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set
CONFIG_BCMDHD=y
CONFIG_AP6XXX=m
# CONFIG_AP6XXX_WIFI6 is not set
# CONFIG_AP6XXX_INDEP_POWER is not set
CONFIG_BCMDHD_FW_PATH="/vendor/etc/firmware/fw_bcmdhd.bin"
CONFIG_BCMDHD_NVRAM_PATH="/vendor/etc/firmware/nvram.txt"
# CONFIG_BCMDHD_STATIC_IF is not set
CONFIG_RTL_WIRELESS_SOLUTION=y
# CONFIG_RTL8188EU is not set
# CONFIG_RTL8188FU is not set
# CONFIG_RTL8189FS is not set
CONFIG_RTL8723CS=m
# CONFIG_RTL8723DS is not set
CONFIG_RTL8821CS=m
CONFIG_RTL8822BS=m
# CONFIG_MVL88W8977 is not set
# CONFIG_CYW_BCMDHD is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_VIRT_WIFI is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_VMXNET3 is not set
CONFIG_LTE=y
CONFIG_LTE_RM310=y
# CONFIG_NETDEVSIM is not set
# CONFIG_NET_FAILOVER is not set
# CONFIG_ISDN is not set
# CONFIG_NVM is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_POLLDEV=y
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
# CONFIG_JOYSTICK_GRIP_MP is not set
# CONFIG_JOYSTICK_GUILLEMOT is not set
# CONFIG_JOYSTICK_INTERACT is not set
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
# CONFIG_JOYSTICK_IFORCE is not set
# CONFIG_JOYSTICK_WARRIOR is not set
# CONFIG_JOYSTICK_MAGELLAN is not set
# CONFIG_JOYSTICK_SPACEORB is not set
# CONFIG_JOYSTICK_SPACEBALL is not set
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_TWIDJOY is not set
# CONFIG_JOYSTICK_ZHENHUA is not set
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=y
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
# CONFIG_JOYSTICK_PXRC is not set
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=y
CONFIG_TABLET_USB_AIPTEK=y
CONFIG_TABLET_USB_GTCO=y
CONFIG_TABLET_USB_HANWANG=y
CONFIG_TABLET_USB_KBTAB=y
# CONFIG_TABLET_USB_PEGASUS is not set
# CONFIG_TABLET_SERIAL_WACOM4 is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CY8C40XX is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
CONFIG_TOUCHSCREEN_GSLX6801=y
# CONFIG_TOUCHSCREEN_GSLX680A is not set
# CONFIG_TOUCHSCREEN_GSLX680_D708 is not set
CONFIG_TOUCHSCREEN_GSLX680_PAD=y
CONFIG_TOUCHSCREEN_GSLX680_VR=y
# CONFIG_TOUCHSCREEN_GSLX680_FIREFLY is not set
CONFIG_TOUCHSCREEN_GSL3673=y
CONFIG_TOUCHSCREEN_GSL3673_800X1280=y
CONFIG_TOUCHSCREEN_GSL3676=y
CONFIG_TOUCHSCREEN_GT9XX=y
# CONFIG_TOUCHSCREEN_HIDEEP is not set
CONFIG_TOUCHSCREEN_HYN_CST2XX=y
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
CONFIG_TOUCHSCREEN_WACOM_W9013=y
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_VTL_CT36X is not set
CONFIG_TOUCHSCREEN_GT1X=y
CONFIG_TOUCHSCREEN_FTS=y
# CONFIG_TOUCHSCREEN_FT5436 is not set
CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5=y
CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_DEVICETREE_SUPPORT=y
CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_I2C=y
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_SPI is not set
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_MT_A is not set
CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_MT_B=y
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_BUTTON is not set
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_PROXIMITY is not set
CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_DEVICE_ACCESS=y
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_DEVICE_ACCESS_API is not set
CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_LOADER=y
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_PLATFORM_FW_UPGRADE is not set
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_BINARY_FW_UPGRADE is not set
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_PLATFORM_TTCONFIG_UPGRADE is not set
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_MANUAL_TTCONFIG_UPGRADE is not set
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5_DEBUG_MDL is not set
CONFIG_ROCKCHIP_REMOTECTL=y
CONFIG_ROCKCHIP_REMOTECTL_PWM=y

#
# handle all sensors
#
CONFIG_SENSOR_DEVICE=y
# CONFIG_ANGLE_DEVICE is not set
CONFIG_GSENSOR_DEVICE=y
CONFIG_GS_MMA8452=y
# CONFIG_STK8BAXX_ACC is not set
CONFIG_MPU6880_ACC=y
CONFIG_MPU6500_ACC=y
# CONFIG_GS_KXTIK is not set
CONFIG_GS_KXTJ9=y
CONFIG_GS_LIS3DH=y
CONFIG_GS_MMA7660=y
CONFIG_GS_MC3230=y
CONFIG_GS_SC7660=y
CONFIG_GS_SC7A20=y
CONFIG_GS_SC7A30=y
# CONFIG_GS_MXC6225 is not set
CONFIG_GS_MXC6655XA=y
# CONFIG_GS_DMT10 is not set
CONFIG_GS_LSM303D=y
# CONFIG_GS_BMA023 is not set
CONFIG_LSM330_ACC=y
CONFIG_BMA2XX_ACC=y
CONFIG_GS_DA223=y
# CONFIG_ICM2060X_ACC is not set
CONFIG_COMPASS_DEVICE=y
CONFIG_COMPASS_AK8975=y
CONFIG_COMPASS_AK8963=y
# CONFIG_COMPASS_AK09911 is not set
# CONFIG_COMPASS_AK09918 is not set
CONFIG_GYROSCOPE_DEVICE=y
CONFIG_GYRO_L3G4200D=y
# CONFIG_GYRO_K3G is not set
CONFIG_GYRO_L3G20D=y
CONFIG_GYRO_EWTSA=y
CONFIG_GYRO_MPU6500=y
CONFIG_GYRO_MPU6880=y
CONFIG_GYRO_LSM330=y
# CONFIG_GYRO_ICM2060X is not set
CONFIG_LIGHT_DEVICE=y
CONFIG_LS_CM3217=y
CONFIG_LS_CM3218=y
# CONFIG_LS_CM3232 is not set
# CONFIG_LS_AL3006 is not set
# CONFIG_LS_STK3171 is not set
# CONFIG_LS_ISL29023 is not set
# CONFIG_LS_AP321XX is not set
# CONFIG_LS_US5152 is not set
CONFIG_LS_STK3410=y
# CONFIG_LS_EM3071X is not set
CONFIG_PROXIMITY_DEVICE=y
# CONFIG_PS_AL3006 is not set
# CONFIG_PS_STK3171 is not set
# CONFIG_PS_AP321XX is not set
CONFIG_PS_STK3410=y
# CONFIG_PS_EM3071X is not set
# CONFIG_TEMPERATURE_DEVICE is not set
# CONFIG_PRESSURE_DEVICE is not set
CONFIG_HALL_DEVICE=y
# CONFIG_HS_OCH165T is not set
CONFIG_HS_MH248=y
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
# CONFIG_INPUT_GP2A is not set
# CONFIG_INPUT_GPIO_BEEPER is not set
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_PWM_BEEPER is not set
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
# CONFIG_RMI4_CORE is not set

#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_TTY=y
# CONFIG_VT is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
CONFIG_LDISC_AUTOLOAD=y
# CONFIG_DEVMEM is not set

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=10
CONFIG_SERIAL_8250_RUNTIME_UARTS=10
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
# CONFIG_SERIAL_8250_MOXA is not set
# CONFIG_SERIAL_OF_PLATFORM is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
# CONFIG_SERIAL_AMBA_PL011 is not set
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_MSM_GENI_HALF_SAMPLING is not set
# CONFIG_SERIAL_MSM_GENI_EARLY_CONSOLE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
# CONFIG_HVC_DCC is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_CAVIUM is not set
CONFIG_HW_RANDOM_ROCKCHIP=y
# CONFIG_APPLICOM is not set

#
# PCMCIA character devices
#
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_DEVPORT is not set
# CONFIG_XILLYBUS is not set
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set

#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_MUX_GPIO is not set
# CONFIG_I2C_MUX_GPMUX is not set
# CONFIG_I2C_MUX_LTC4306 is not set
# CONFIG_I2C_MUX_PCA9541 is not set
# CONFIG_I2C_MUX_PCA954x is not set
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_MUX_REG is not set
# CONFIG_I2C_DEMUX_PINCTRL is not set
# CONFIG_I2C_MUX_MLXCPLD is not set
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
# CONFIG_SPI_MEM is not set

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX is not set
CONFIG_SPI_ROCKCHIP=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PINCTRL=y
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_MCP23S08 is not set
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_RK628=y
CONFIG_PINCTRL_RK805=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_PL061 is not set
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XGENE is not set
# CONFIG_GPIO_XILINX is not set

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADP5588 is not set
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set

#
# MFD GPIO expanders
#

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set

#
# USB GPIO expanders
#
# CONFIG_W1 is not set
CONFIG_POWER_AVS=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
# CONFIG_POWER_RESET_GPIO_RESTART is not set
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_XGENE is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
CONFIG_TEST_POWER=y
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_LEGO_EV3 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LTC3651 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
CONFIG_CHARGER_BQ25700=y
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_CHARGER_RT9455 is not set
CONFIG_BATTERY_CW2015=y
# CONFIG_BATTERY_RK816 is not set
CONFIG_BATTERY_RK817=y
CONFIG_CHARGER_RK817=y
CONFIG_BATTERY_RK818=y
CONFIG_CHARGER_RK818=y
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ARM_SCMI is not set
# CONFIG_SENSORS_ASPEED is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_PWM_FAN is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
# CONFIG_CLOCK_THERMAL is not set
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_QORIQ_THERMAL is not set
CONFIG_ROCKCHIP_THERMAL=y
# CONFIG_RK_VIRTUAL_THERMAL is not set
CONFIG_RK3368_THERMAL=y

#
# ACPI INT340X thermal drivers
#
# CONFIG_GENERIC_ADC_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
# CONFIG_WATCHDOG_SYSFS is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK618=y
CONFIG_MFD_RK628=y
CONFIG_MFD_RK630=y
CONFIG_MFD_RK630_I2C=y
# CONFIG_MFD_RK630_SPI is not set
CONFIG_MFD_RK808=y
CONFIG_MFD_RK1000=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
CONFIG_FUSB_30X=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_PROXY_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
CONFIG_REGULATOR_ACT8865=y
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ANATOP is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
CONFIG_REGULATOR_LP8752=y
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
CONFIG_REGULATOR_MP8865=y
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS549B22 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
CONFIG_REGULATOR_TPS65132=y
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_REGULATOR_VCTRL is not set
CONFIG_REGULATOR_XZ3216=y
CONFIG_REGULATOR_DIO5632=y
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
# CONFIG_RC_CORE is not set
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_V4L2=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
# CONFIG_VIDEO_PCI_SKELETON is not set
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=m
# CONFIG_USB_M5602 is not set
# CONFIG_USB_STV06XX is not set
# CONFIG_USB_GL860 is not set
# CONFIG_USB_GSPCA_BENQ is not set
# CONFIG_USB_GSPCA_CONEX is not set
# CONFIG_USB_GSPCA_CPIA1 is not set
# CONFIG_USB_GSPCA_DTCS033 is not set
# CONFIG_USB_GSPCA_ETOMS is not set
# CONFIG_USB_GSPCA_FINEPIX is not set
# CONFIG_USB_GSPCA_JEILINJ is not set
# CONFIG_USB_GSPCA_JL2005BCD is not set
# CONFIG_USB_GSPCA_KINECT is not set
# CONFIG_USB_GSPCA_KONICA is not set
# CONFIG_USB_GSPCA_MARS is not set
# CONFIG_USB_GSPCA_MR97310A is not set
# CONFIG_USB_GSPCA_NW80X is not set
# CONFIG_USB_GSPCA_OV519 is not set
# CONFIG_USB_GSPCA_OV534 is not set
# CONFIG_USB_GSPCA_OV534_9 is not set
# CONFIG_USB_GSPCA_PAC207 is not set
# CONFIG_USB_GSPCA_PAC7302 is not set
# CONFIG_USB_GSPCA_PAC7311 is not set
# CONFIG_USB_GSPCA_SE401 is not set
# CONFIG_USB_GSPCA_SN9C2028 is not set
# CONFIG_USB_GSPCA_SN9C20X is not set
# CONFIG_USB_GSPCA_SONIXB is not set
# CONFIG_USB_GSPCA_SONIXJ is not set
# CONFIG_USB_GSPCA_SPCA500 is not set
# CONFIG_USB_GSPCA_SPCA501 is not set
# CONFIG_USB_GSPCA_SPCA505 is not set
# CONFIG_USB_GSPCA_SPCA506 is not set
# CONFIG_USB_GSPCA_SPCA508 is not set
# CONFIG_USB_GSPCA_SPCA561 is not set
# CONFIG_USB_GSPCA_SPCA1528 is not set
# CONFIG_USB_GSPCA_SQ905 is not set
# CONFIG_USB_GSPCA_SQ905C is not set
# CONFIG_USB_GSPCA_SQ930X is not set
# CONFIG_USB_GSPCA_STK014 is not set
# CONFIG_USB_GSPCA_STK1135 is not set
# CONFIG_USB_GSPCA_STV0680 is not set
# CONFIG_USB_GSPCA_SUNPLUS is not set
# CONFIG_USB_GSPCA_T613 is not set
# CONFIG_USB_GSPCA_TOPRO is not set
# CONFIG_USB_GSPCA_TOUPTEK is not set
# CONFIG_USB_GSPCA_TV8532 is not set
# CONFIG_USB_GSPCA_VC032X is not set
# CONFIG_USB_GSPCA_VICAM is not set
# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
# CONFIG_USB_GSPCA_ZC3XX is not set
# CONFIG_USB_PWC is not set
# CONFIG_VIDEO_CPIA2 is not set
# CONFIG_USB_ZR364XX is not set
# CONFIG_USB_STKWEBCAM is not set
# CONFIG_USB_S2255 is not set
# CONFIG_VIDEO_USBTV is not set

#
# Webcam, TV (analog/digital) USB devices
#
# CONFIG_VIDEO_EM28XX is not set

#
# USB HDMI CEC adapters
#
# CONFIG_USB_PULSE8_CEC is not set
# CONFIG_USB_RAINSHADOW_CEC is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_VIDEO_CAFE_CCIC is not set
# CONFIG_VIDEO_CADENCE is not set
# CONFIG_VIDEO_MUX is not set
# CONFIG_SOC_CAMERA is not set
# CONFIG_VIDEO_XILINX is not set
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y
# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set
CONFIG_VIDEO_ROCKCHIP_ISP1=y
CONFIG_VIDEO_ROCKCHIP_ISP=y
# CONFIG_VIDEO_ROCKCHIP_ISPP is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_CEC_PLATFORM_DRIVERS is not set

#
# Supported MMC/SDIO adapters
#
# CONFIG_CYPRESS_FIRMWARE is not set
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=y

#
# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
#
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set

#
# I2C Encoders, decoders, sensors and other helper chips
#

#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TDA1997X is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
# CONFIG_VIDEO_MSP3400 is not set
# CONFIG_VIDEO_CS3308 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_TLV320AIC23B is not set
# CONFIG_VIDEO_UDA1342 is not set
# CONFIG_VIDEO_WM8775 is not set
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set
# CONFIG_VIDEO_SONY_BTF_MPX is not set

#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_ADV748X is not set
# CONFIG_VIDEO_ADV7604 is not set
# CONFIG_VIDEO_ADV7842 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_AD5820 is not set
# CONFIG_VIDEO_AK7375 is not set
CONFIG_VIDEO_DW9714=y
# CONFIG_VIDEO_DW9718 is not set
# CONFIG_VIDEO_DW9807_VCM is not set
# CONFIG_VIDEO_FP5510 is not set
# CONFIG_VIDEO_GT9760S is not set
CONFIG_VIDEO_VM149C=y
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_TC358743 is not set
CONFIG_VIDEO_TC35874X=y
CONFIG_VIDEO_RK628_CSI=y
# CONFIG_VIDEO_TECHPOINT is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_TW2804 is not set
# CONFIG_VIDEO_TW9903 is not set
# CONFIG_VIDEO_TW9906 is not set
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_CX25840 is not set

#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_ADV7511 is not set
# CONFIG_VIDEO_AD9389B is not set
# CONFIG_VIDEO_AK881X is not set
# CONFIG_VIDEO_THS8200 is not set

#
# Camera sensor devices
#
# CONFIG_VIDEO_IMX178 is not set
# CONFIG_VIDEO_IMX219 is not set
# CONFIG_VIDEO_IMX258 is not set
# CONFIG_VIDEO_IMX274 is not set
# CONFIG_VIDEO_IMX307 is not set
# CONFIG_VIDEO_IMX317 is not set
# CONFIG_VIDEO_IMX323 is not set
# CONFIG_VIDEO_IMX327 is not set
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
# CONFIG_VIDEO_IMX347 is not set
# CONFIG_VIDEO_IMX378 is not set
# CONFIG_VIDEO_IMX415 is not set
# CONFIG_VIDEO_IMX462 is not set
# CONFIG_VIDEO_IMX464 is not set
# CONFIG_VIDEO_OS02G10 is not set
# CONFIG_VIDEO_OS04A10 is not set
# CONFIG_VIDEO_OS04C10 is not set
# CONFIG_VIDEO_OS05A20 is not set
# CONFIG_VIDEO_OS08A10 is not set
# CONFIG_VIDEO_OV02B10 is not set
# CONFIG_VIDEO_OV02K10 is not set
# CONFIG_VIDEO_OV2640 is not set
# CONFIG_VIDEO_OV2659 is not set
CONFIG_VIDEO_OV2680=y
# CONFIG_VIDEO_OV2685 is not set
# CONFIG_VIDEO_OV2718 is not set
# CONFIG_VIDEO_OV2735 is not set
# CONFIG_VIDEO_OV2775 is not set
# CONFIG_VIDEO_OV4686 is not set
# CONFIG_VIDEO_OV4688 is not set
# CONFIG_VIDEO_OV4689 is not set
# CONFIG_VIDEO_OV5640 is not set
# CONFIG_VIDEO_OV5645 is not set
# CONFIG_VIDEO_OV5647 is not set
CONFIG_VIDEO_OV5648=y
# CONFIG_VIDEO_OV5670 is not set
CONFIG_VIDEO_OV5695=y
# CONFIG_VIDEO_OV6650 is not set
# CONFIG_VIDEO_OV7251 is not set
# CONFIG_VIDEO_OV772X is not set
# CONFIG_VIDEO_OV7640 is not set
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV7740 is not set
# CONFIG_VIDEO_OV7750 is not set
CONFIG_VIDEO_OV8858=y
# CONFIG_VIDEO_OV9281 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV9750 is not set
# CONFIG_VIDEO_OV12D2Q is not set
CONFIG_VIDEO_OV13850=y
# CONFIG_VIDEO_OV13858 is not set
# CONFIG_VIDEO_PREISP_DUMMY_SENSOR is not set
# CONFIG_VIDEO_VS6624 is not set
# CONFIG_VIDEO_MT9M032 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
# CONFIG_VIDEO_MT9T001 is not set
# CONFIG_VIDEO_MT9T112 is not set
# CONFIG_VIDEO_MT9V011 is not set
# CONFIG_VIDEO_MT9V032 is not set
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_AR0230 is not set
# CONFIG_VIDEO_SR030PC30 is not set
# CONFIG_VIDEO_NOON010PC30 is not set
# CONFIG_VIDEO_M5MOLS is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5K6AA is not set
# CONFIG_VIDEO_S5K6A3 is not set
# CONFIG_VIDEO_S5KGM1SP is not set
# CONFIG_VIDEO_S5K4H7YX is not set
# CONFIG_VIDEO_S5K4ECGX is not set
# CONFIG_VIDEO_S5K5BAF is not set
# CONFIG_VIDEO_SMIAPP is not set
# CONFIG_VIDEO_ET8EK8 is not set
# CONFIG_VIDEO_S5C73M3 is not set
# CONFIG_VIDEO_GC02M2 is not set
CONFIG_VIDEO_GC0312=y
# CONFIG_VIDEO_GC0329 is not set
CONFIG_VIDEO_GC032A=y
# CONFIG_VIDEO_GC0403 is not set
# CONFIG_VIDEO_GC2035 is not set
# CONFIG_VIDEO_GC2053 is not set
# CONFIG_VIDEO_GC2093 is not set
CONFIG_VIDEO_GC2145=y
# CONFIG_VIDEO_GC2155 is not set
CONFIG_VIDEO_GC2355=y
# CONFIG_VIDEO_GC2375H is not set
CONFIG_VIDEO_GC2385=y
# CONFIG_VIDEO_GC4663 is not set
CONFIG_VIDEO_GC4C33=y
# CONFIG_VIDEO_GC5024 is not set
# CONFIG_VIDEO_GC5025 is not set
# CONFIG_VIDEO_GC5035 is not set
CONFIG_VIDEO_GC8034=y
# CONFIG_VIDEO_BF3925 is not set
# CONFIG_VIDEO_JX_F37 is not set
# CONFIG_VIDEO_JX_H62 is not set
# CONFIG_VIDEO_JX_H65 is not set
# CONFIG_VIDEO_JX_K04 is not set
# CONFIG_VIDEO_SC031GS is not set
# CONFIG_VIDEO_SC035HGS is not set
# CONFIG_VIDEO_SC132GS is not set
# CONFIG_VIDEO_SC200AI is not set
# CONFIG_VIDEO_SC210IOT is not set
# CONFIG_VIDEO_SC2232 is not set
# CONFIG_VIDEO_SC2239 is not set
# CONFIG_VIDEO_SC2310 is not set
# CONFIG_VIDEO_SC2335 is not set
# CONFIG_VIDEO_SC401AI is not set
# CONFIG_VIDEO_SC4238 is not set
# CONFIG_VIDEO_SC430CS is not set
# CONFIG_VIDEO_SC500AI is not set
# CONFIG_VIDEO_SC8220 is not set
# CONFIG_VIDEO_SP250A is not set
# CONFIG_VIDEO_HYNIX_HI556 is not set
# CONFIG_VIDEO_HYNIX_HI846 is not set

#
# Flash devices
#
# CONFIG_VIDEO_ADP1653 is not set
# CONFIG_VIDEO_LM3560 is not set
# CONFIG_VIDEO_LM3646 is not set
CONFIG_VIDEO_SGM3784=y

#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set

#
# Audio/Video compression chips
#
# CONFIG_VIDEO_SAA6752HS is not set

#
# SDR tuner chips
#

#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_I2C is not set
# CONFIG_VIDEO_NVP6158 is not set
# CONFIG_VIDEO_NVP6188 is not set
# CONFIG_VIDEO_NVP6324 is not set
# CONFIG_VIDEO_HALL_DC_MOTOR is not set
# CONFIG_VIDEO_RK_IRCUT is not set
# CONFIG_VIDEO_MP6507 is not set

#
# Sensors used on soc_camera driver
#

#
# SPI helper chips
#
# CONFIG_VIDEO_GS1662 is not set
# CONFIG_VIDEO_MS41908 is not set
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set

#
# Media SPI Adapters
#

#
# Customise DVB Frontends
#

#
# Tools to develop new frontends
#

#
# Graphics support
#
# CONFIG_VGA_ARB is not set
CONFIG_DRM=y
CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_GEM_CMA_HELPER=y

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set

#
# ACP (Audio CoProcessor) Configuration
#

#
# AMD Library routines
#
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_DRM_TVE=y
CONFIG_ROCKCHIP_RGB=y
# CONFIG_DRM_ROCKCHIP_VVOP is not set
# CONFIG_ROCKCHIP_EBC_DEV is not set
CONFIG_DRM_ROCKCHIP_RK618=y
CONFIG_DRM_ROCKCHIP_RK628=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_QXL is not set
# CONFIG_DRM_BOCHS is not set
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_LVDS is not set
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_SIMPLE_OF_ONLY is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_DUMB_VGA_DAC is not set
# CONFIG_DRM_LVDS_ENCODER is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
CONFIG_DRM_RK630_TVE=y
CONFIG_DRM_RK1000_TVE=y
# CONFIG_DRM_SIL_SII8620 is not set
CONFIG_DRM_SII902X=y
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TI_TFP410 is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_I2C_ADV7511 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=y
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_TINYDRM is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_MALI400=y
CONFIG_MALI450=y
# CONFIG_MALI470 is not set
# CONFIG_MALI400_DEBUG is not set
# CONFIG_MALI400_PROFILING is not set
# CONFIG_MALI400_UMP is not set
CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
CONFIG_MALI_SHARED_INTERRUPTS=y
# CONFIG_MALI_PMU_PARALLEL_POWER_UP is not set
CONFIG_MALI_DT=y
CONFIG_MALI_DEVFREQ=y
# CONFIG_MALI_QUIET is not set
CONFIG_MALI_MIDGARD_FOR_ANDROID=y
# CONFIG_MALI_MIDGARD_FOR_LINUX is not set
CONFIG_MALI_MIDGARD=y
# CONFIG_MALI_GATOR_SUPPORT is not set
# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set
# CONFIG_MALI_DMA_FENCE is not set
CONFIG_MALI_EXPERT=y
# CONFIG_MALI_CORESTACK is not set
# CONFIG_MALI_PRFCNT_SET_SECONDARY is not set
# CONFIG_MALI_PLATFORM_FAKE is not set
# CONFIG_MALI_PLATFORM_DEVICETREE is not set
CONFIG_MALI_PLATFORM_THIRDPARTY=y
CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="rk"
CONFIG_MALI_DEBUG=y
CONFIG_MALI_FENCE_DEBUG=y
# CONFIG_MALI_NO_MALI is not set
# CONFIG_MALI_TRACE_TIMELINE is not set
# CONFIG_MALI_SYSTEM_TRACE is not set
# CONFIG_MALI_GPU_MMU_AARCH64 is not set
CONFIG_MALI_PWRSOFT_765=y
# CONFIG_MALI_KUTF is not set
CONFIG_MALI_BIFROST_FOR_ANDROID=y
# CONFIG_MALI_BIFROST_FOR_LINUX is not set
CONFIG_MALI_BIFROST=y
# CONFIG_MALI_BIFROST_GATOR_SUPPORT is not set
CONFIG_MALI_BIFROST_ENABLE_TRACE=y
CONFIG_MALI_BIFROST_DEVFREQ=y
# CONFIG_MALI_BIFROST_DMA_FENCE is not set
CONFIG_MALI_PLATFORM_NAME="rk"
# CONFIG_MALI_ARBITER_SUPPORT is not set
CONFIG_MALI_BIFROST_EXPERT=y
CONFIG_MALI_BIFROST_DEBUG=y
CONFIG_MALI_BIFROST_FENCE_DEBUG=y
# CONFIG_MALI_BIFROST_NO_MALI is not set
CONFIG_MALI_REAL_HW=y
CONFIG_MALI_BIFROST_SYSTEM_TRACE=y
# CONFIG_MALI_2MB_ALLOC is not set
# CONFIG_MALI_MEMORY_FULLY_BACKED is not set
# CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND is not set
# CONFIG_MALI_DMA_BUF_LEGACY_COMPAT is not set
# CONFIG_MALI_HW_ERRATA_1485982_NOT_AFFECTED is not set
# CONFIG_MALI_HW_ERRATA_1485982_USE_CLOCK_ALTERNATIVE is not set
# CONFIG_MALI_GEM5_BUILD is not set
# CONFIG_MALI_JOB_DUMP is not set
# CONFIG_MALI_BIFROST_PRFCNT_SET_SECONDARY is not set
# CONFIG_MALI_PRFCNT_SET_SECONDARY_VIA_DEBUG_FS is not set

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_PM8941_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set

#
# Rockchip Misc Video driver
#

#
# RGA
#
# CONFIG_ROCKCHIP_RGA is not set

#
# RGA2
#
CONFIG_ROCKCHIP_RGA2=y

#
# IEP
#
CONFIG_IEP=y
# CONFIG_IEP_MMU is not set
CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y
CONFIG_ROCKCHIP_MPP_VEPU2=y
CONFIG_ROCKCHIP_MPP_IEP2=y
CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
# CONFIG_LOGO is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
# CONFIG_SND_HRTIMER is not set
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
CONFIG_SND_VERBOSE_PRINTK=y
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA_PREALLOC_SIZE=64
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=y
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_BCD2000 is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_VARIAX is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_DESIGNWARE_I2S is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_PREALLOC_BUFFER_SIZE=512
# CONFIG_SND_SOC_ROCKCHIP_AUDIO_PWM is not set
CONFIG_SND_SOC_ROCKCHIP_I2S=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
# CONFIG_SND_SOC_ROCKCHIP_VAD is not set
# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
CONFIG_SND_SOC_ROCKCHIP_RT5651=y
# CONFIG_SND_SOC_ROCKCHIP_RT5651_RK628 is not set
# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set

#
# STMicroelectronics STM32 SOC audio support
#
# CONFIG_SND_SOC_XTFPGA_I2S is not set
# CONFIG_ZX_TDM is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
# CONFIG_SND_SOC_AC97_CODEC is not set
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_BD28623 is not set
CONFIG_SND_SOC_BT_SCO=y
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
CONFIG_SND_SOC_CX2072X=y
CONFIG_SND_SOC_DUMMY_CODEC=y
CONFIG_SND_SOC_HDMI_CODEC=y
# CONFIG_SND_SOC_ES7134 is not set
CONFIG_SND_SOC_ES7202=y
CONFIG_SND_SOC_ES7210=y
# CONFIG_SND_SOC_ES7241 is not set
CONFIG_SND_SOC_ES7243E=y
CONFIG_SND_SOC_ES8311=y
CONFIG_SND_SOC_ES8316=y
# CONFIG_SND_SOC_ES8323 is not set
# CONFIG_SND_SOC_ES8328_I2C is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
CONFIG_SND_SOC_ES8396=y
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_INNO_RK3036 is not set
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
# CONFIG_SND_SOC_MAX98927 is not set
# CONFIG_SND_SOC_MAX98373 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3168A_I2C is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK1000 is not set
# CONFIG_SND_SOC_RK312X is not set
# CONFIG_SND_SOC_RK3228 is not set
# CONFIG_SND_SOC_RK3308 is not set
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RL6231=y
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5651=y
# CONFIG_SND_SOC_SGTL5000 is not set
# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
CONFIG_SND_SOC_SPDIF=y
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X is not set
# CONFIG_SND_SOC_TS3A227E is not set
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731 is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
# CONFIG_SND_SOC_ZX_AUD96P22 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
# CONFIG_SND_SIMPLE_SCU_CARD is not set
# CONFIG_SND_AUDIO_GRAPH_CARD is not set
# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set

#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
# CONFIG_HID_ACCUTOUCH is not set
CONFIG_HID_ACRUX=y
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=y
CONFIG_HID_APPLEIR=y
# CONFIG_HID_ASUS is not set
CONFIG_HID_AUREAL=y
CONFIG_HID_BELKIN=y
# CONFIG_HID_BETOP_FF is not set
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_COUGAR is not set
CONFIG_HID_PRODIKEYS=y
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CP2112 is not set
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=y
# CONFIG_HID_ELAN is not set
CONFIG_HID_ELECOM=y
# CONFIG_HID_ELO is not set
CONFIG_HID_EZKEY=y
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
CONFIG_HID_HOLTEK=y
# CONFIG_HOLTEK_FF is not set
# CONFIG_HID_GOOGLE_HAMMER is not set
# CONFIG_HID_GT683R is not set
CONFIG_HID_KEYTOUCH=y
CONFIG_HID_KYE=y
CONFIG_HID_UCLOGIC=y
CONFIG_HID_WALTOP=y
CONFIG_HID_GYRATION=y
CONFIG_HID_ICADE=y
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
CONFIG_HID_TWINHAN=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LED=y
CONFIG_HID_LENOVO=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_LOGITECH_DJ=y
CONFIG_HID_LOGITECH_HIDPP=y
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=y
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_REDRAGON is not set
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NINTENDO=y
# CONFIG_HID_NTI is not set
CONFIG_HID_NTRIG=y
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
# CONFIG_HID_PENMOUNT is not set
CONFIG_HID_PETALYNX=y
CONFIG_HID_PICOLCD=y
# CONFIG_HID_PICOLCD_FB is not set
# CONFIG_HID_PICOLCD_BACKLIGHT is not set
# CONFIG_HID_PICOLCD_LEDS is not set
# CONFIG_HID_PLANTRONICS is not set
CONFIG_HID_PRIMAX=y
# CONFIG_HID_RETRODE is not set
CONFIG_HID_ROCCAT=y
CONFIG_HID_SAITEK=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_SONY_FF is not set
CONFIG_HID_SPEEDLINK=y
CONFIG_HID_STEAM=y
CONFIG_HID_STEELSERIES=y
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_RMI is not set
CONFIG_HID_GREENASIA=y
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THINGM=y
CONFIG_HID_THRUSTMASTER=y
# CONFIG_THRUSTMASTER_FF is not set
# CONFIG_HID_UDRAW_PS3 is not set
CONFIG_HID_WACOM=y
CONFIG_HID_WIIMOTE=y
# CONFIG_HID_XINMO is not set
CONFIG_HID_ZEROPLUS=y
# CONFIG_ZEROPLUS_FF is not set
CONFIG_HID_ZYDACRON=y
# CONFIG_HID_SENSOR_HUB is not set
CONFIG_HID_ALPS=y

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y

#
# I2C HID support
#
CONFIG_I2C_HID=y
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_MON=y
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
# CONFIG_USB_MAX3421_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_HCD_PCI is not set
CONFIG_USB_OHCI_HCD_PLATFORM=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=y
CONFIG_USB_WDM=y
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_USBAT=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_USB_STORAGE_ALAUDA=y
CONFIG_USB_STORAGE_ONETOUCH=y
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_STORAGE_ENE_UB6250=y
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_MUSB_HDRC is not set
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3_ROCKCHIP_INNO=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
# CONFIG_USB_SERIAL_CONSOLE is not set
CONFIG_USB_SERIAL_GENERIC=y
# CONFIG_USB_SERIAL_SIMPLE is not set
# CONFIG_USB_SERIAL_AIRCABLE is not set
# CONFIG_USB_SERIAL_ARK3116 is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_CH341 is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_CP210X is not set
# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
# CONFIG_USB_SERIAL_F81232 is not set
# CONFIG_USB_SERIAL_F8153X is not set
# CONFIG_USB_SERIAL_GARMIN is not set
# CONFIG_USB_SERIAL_IPW is not set
# CONFIG_USB_SERIAL_IUU is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_METRO is not set
# CONFIG_USB_SERIAL_MOS7720 is not set
# CONFIG_USB_SERIAL_MOS7840 is not set
# CONFIG_USB_SERIAL_MXUPORT is not set
# CONFIG_USB_SERIAL_NAVMAN is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_SERIAL_QCAUX is not set
# CONFIG_USB_SERIAL_QUALCOMM is not set
# CONFIG_USB_SERIAL_SPCP8X5 is not set
# CONFIG_USB_SERIAL_SAFE is not set
# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
# CONFIG_USB_SERIAL_SYMBOL is not set
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_XIRCOM is not set
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=y
# CONFIG_USB_SERIAL_OMNINET is not set
# CONFIG_USB_SERIAL_OPTICON is not set
# CONFIG_USB_SERIAL_XSENS_MT is not set
# CONFIG_USB_SERIAL_WISHBONE is not set
# CONFIG_USB_SERIAL_SSU100 is not set
# CONFIG_USB_SERIAL_QT2 is not set
# CONFIG_USB_SERIAL_UPD78F0730 is not set
# CONFIG_USB_SERIAL_DEBUG is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
CONFIG_USB_TRANCEVIBRATOR=y
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
# CONFIG_USB_CHAOSKEY is not set

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ULPI is not set
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
CONFIG_USB_GADGET_DEBUG_FILES=y
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_DUMMY_HCD is not set
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_F_UVC=y
CONFIG_USB_F_MIDI=y
CONFIG_USB_F_ACC=y
CONFIG_USB_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
# CONFIG_USB_CONFIGFS_SERIAL is not set
CONFIG_USB_CONFIGFS_ACM=y
# CONFIG_USB_CONFIGFS_OBEX is not set
# CONFIG_USB_CONFIGFS_NCM is not set
# CONFIG_USB_CONFIGFS_ECM is not set
# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
CONFIG_USB_CONFIGFS_RNDIS=y
# CONFIG_USB_CONFIGFS_EEM is not set
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
# CONFIG_USB_CONFIGFS_F_UAC1 is not set
# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
# CONFIG_USB_CONFIGFS_F_UAC2 is not set
CONFIG_USB_CONFIGFS_F_MIDI=y
# CONFIG_USB_CONFIGFS_F_HID is not set
CONFIG_USB_CONFIGFS_F_UVC=y
# CONFIG_USB_CONFIGFS_F_PRINTER is not set
# CONFIG_TYPEC is not set
# CONFIG_USB_ROLE_SWITCH is not set
# CONFIG_USB_LED_TRIG is not set
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_UWB is not set
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
CONFIG_MMC_CRYPTO=y
CONFIG_SDIO_KEEPALIVE=y

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
# CONFIG_MMC_SDHCI_OF_AT91 is not set
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
# CONFIG_MMC_SDHCI_CADENCE is not set
# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
CONFIG_MMC_CQHCI=y
# CONFIG_MMC_TOSHIBA_PCI is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_MMC_SDHCI_OMAP is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AAT1290 is not set
# CONFIG_LEDS_AS3645A is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_LM3601X is not set
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_LP5562 is not set
# CONFIG_LEDS_LP8501 is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_PWM is not set
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_KTD2692 is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set
CONFIG_LEDS_RGB13H=y

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
# CONFIG_LEDS_SYSCON is not set
# CONFIG_LEDS_MLXREG is not set
# CONFIG_LEDS_USER is not set

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
# CONFIG_LEDS_TRIGGER_DISK is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_GPIO is not set
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
# CONFIG_LEDS_TRIGGER_CAMERA is not set
# CONFIG_LEDS_TRIGGER_PANIC is not set
# CONFIG_LEDS_TRIGGER_NETDEV is not set

#
# FD628 support
#
CONFIG_RK_FD628=y
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABX80X is not set
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_FAKE is not set
# CONFIG_RTC_DRV_HYM8563 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RK_TIMER is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV8803 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RX6110 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
# CONFIG_RTC_DRV_PL031 is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_SNVS is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_AMBA_PL08X is not set
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
# CONFIG_DW_DMAC is not set
# CONFIG_DW_DMAC_PCI is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO_MENU=y
# CONFIG_VIRTIO_PCI is not set
# CONFIG_VIRTIO_MMIO is not set

#
# Microsoft Hyper-V guest support
#
CONFIG_STAGING=y
# CONFIG_PRISM2_USB is not set
# CONFIG_COMEDI is not set
# CONFIG_RTL8192U is not set
# CONFIG_RTLLIB is not set
# CONFIG_RTL8723BS is not set
# CONFIG_R8712U is not set
# CONFIG_R8188EU is not set
# CONFIG_R8822BE is not set
# CONFIG_RTS5208 is not set
# CONFIG_VT6655 is not set
# CONFIG_VT6656 is not set

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set

#
# Analog to digital converters
#
# CONFIG_AD7606 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7816 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7280 is not set

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# CONFIG_AD7152 is not set
# CONFIG_AD7746 is not set

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set

#
# Resolver to digital converters
#
# CONFIG_AD2S90 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_FB_SM750 is not set
# CONFIG_FB_XGI is not set

#
# Speakup console speech
#
# CONFIG_STAGING_MEDIA is not set

#
# Android
#
CONFIG_ASHMEM=y
# CONFIG_ANDROID_VSOC is not set
CONFIG_ION=y
# CONFIG_ION_PROTECTED_HEAP is not set
CONFIG_ION_SYSTEM_HEAP=y
# CONFIG_ION_CARVEOUT_HEAP is not set
# CONFIG_ION_CHUNK_HEAP is not set
CONFIG_ION_CMA_HEAP=y
CONFIG_ION_FORCE_DMA_SYNC=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
# CONFIG_FIQ_DEBUGGER_UART_OVERLAY is not set
CONFIG_RK_CONSOLE_THREAD=y
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_DGNC is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_FB_TFT is not set
# CONFIG_WILC1000_SDIO is not set
# CONFIG_WILC1000_SPI is not set
# CONFIG_MOST is not set
# CONFIG_KS7010 is not set
# CONFIG_GREYBUS is not set
# CONFIG_PI433 is not set
# CONFIG_MTK_MMC is not set

#
# Gasket devices
#
# CONFIG_STAGING_GASKET_FRAMEWORK is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_EROFS_FS is not set
CONFIG_POWERVR_ROGUE_N=y
# CONFIG_POWERVR_ROGUE_PDUMP is not set
# CONFIG_POWERVR_ROGUE_RESOURCE_INFO is not set
# CONFIG_POWERVR_ROGUE_DEVICEMEM_HISTORY is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
CONFIG_COMMON_CLK_DEBUGFS=y
# CONFIG_COMMON_CLK_PROCFS is not set
# CONFIG_COMMON_CLK_VERSATILE is not set
# CONFIG_CLK_HSDK is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_CLK_QORIQ is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_ROCKCHIP_CLK_COMPENSATION is not set
CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=y
CONFIG_CLK_RK618=y
CONFIG_CLK_RK628=y
# CONFIG_HWSPINLOCK is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
# CONFIG_ARM_TIMER_SP804 is not set
CONFIG_MAILBOX=y
# CONFIG_ARM_MHU is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_ROCKCHIP_MBOX is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_RK3368_MBOX=y
CONFIG_RK3368_SCPI_PROTOCOL=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_IOMMU_IOVA=y
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_ROCKCHIP_IOMMU=y
# CONFIG_ARM_SMMU is not set
# CONFIG_ARM_SMMU_V3 is not set

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set

#
# Rpmsg drivers
#
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RPMSG_VIRTIO is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set

#
# NXP/Freescale QorIQ SoC drivers
#

#
# i.MX SoC drivers
#

#
# Qualcomm SoC drivers
#

#
# Rockchip CPU selection
#
CONFIG_CPU_PX30=y
# CONFIG_CPU_RK1808 is not set
# CONFIG_CPU_RK3308 is not set
CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3368=y
CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3568=y
CONFIG_ANDROID_VERSION=0x08000000
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_GRF=y
# CONFIG_ROCKCHIP_HW_DECOMPRESS is not set
CONFIG_ROCKCHIP_IPA=y
CONFIG_ROCKCHIP_OPP=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y
# CONFIG_ROCKCHIP_RAMDISK is not set
CONFIG_ROCKCHIP_SUSPEND_MODE=y
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y
CONFIG_ROCKCHIP_DEBUG=y
# CONFIG_ROCKCHIP_LOW_PERFORMANCE is not set
# CONFIG_ROCKCHIP_THUNDER_BOOT is not set
CONFIG_ROCKCHIP_SCHED_PERFORMANCE_BIAS=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
# CONFIG_DEVFREQ_GOV_PASSIVE is not set

#
# DEVFREQ Drivers
#
CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y
CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y
# CONFIG_ARM_ROCKCHIP_DMC_DEBUG is not set
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_MEMORY is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
CONFIG_IIO_KFIFO_BUF=y
# CONFIG_IIO_CONFIGFS is not set
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
# CONFIG_IIO_SW_DEVICE is not set
# CONFIG_IIO_SW_TRIGGER is not set

#
# Accelerometers
#
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_BMA180 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_ACCEL is not set
# CONFIG_DA280 is not set
# CONFIG_DA311 is not set
# CONFIG_DMARD06 is not set
# CONFIG_DMARD09 is not set
# CONFIG_DMARD10 is not set
# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
# CONFIG_KXSD9 is not set
# CONFIG_KXCJK1013 is not set
# CONFIG_MC3230 is not set
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMA7660 is not set
# CONFIG_MMA8452 is not set
# CONFIG_MMA9551 is not set
# CONFIG_MMA9553 is not set
# CONFIG_MXC4005 is not set
# CONFIG_MXC6255 is not set
# CONFIG_SCA3000 is not set
# CONFIG_STK8312 is not set
# CONFIG_STK8BA50 is not set

#
# Analog to digital converters
#
# CONFIG_AD7266 is not set
# CONFIG_AD7291 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD799X is not set
# CONFIG_CC10001_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_HI8435 is not set
# CONFIG_HX711 is not set
# CONFIG_INA2XX_ADC is not set
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1363 is not set
# CONFIG_MAX9611 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
# CONFIG_NAU7802 is not set
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_ROCKCHIP_SARADC_TEST_CHN is not set
# CONFIG_SD_ADC_MODULATOR is not set
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS1015 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_VF610_ADC is not set

#
# Analog Front Ends
#
# CONFIG_IIO_RESCALE is not set

#
# Amplifiers
#
# CONFIG_AD8366 is not set

#
# Chemical Sensors
#
# CONFIG_ATLAS_PH_SENSOR is not set
# CONFIG_BME680 is not set
# CONFIG_CCS811 is not set
# CONFIG_IAQCORE is not set
# CONFIG_VZ89X is not set

#
# Hid Sensor IIO Common
#

#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set

#
# Counters
#

#
# Digital to analog converters
#
# CONFIG_AD5064 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5380 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5446 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5593R is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_LTC2632 is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5696_I2C is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD8801 is not set
# CONFIG_DPOT_DAC is not set
# CONFIG_DS4424 is not set
# CONFIG_M62332 is not set
# CONFIG_MAX517 is not set
# CONFIG_MAX5821 is not set
# CONFIG_MCP4725 is not set
# CONFIG_MCP4922 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC5571 is not set
# CONFIG_VF610_DAC is not set

#
# IIO dummy driver
#

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
# CONFIG_AD9523 is not set

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
# CONFIG_ADF4350 is not set

#
# Digital gyroscope sensors
#
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_MPU3050_I2C is not set
# CONFIG_IIO_ST_GYRO_3AXIS is not set
# CONFIG_ITG3200 is not set

#
# Health Sensors
#

#
# Heart Rate Monitors
#
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
# CONFIG_MAX30100 is not set
# CONFIG_MAX30102 is not set

#
# Humidity sensors
#
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set

#
# Inertial measurement units
#
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_BMI160_I2C is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_KMX61 is not set
# CONFIG_INV_MPU6050_I2C is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_IIO_ST_LSM6DSX is not set

#
# Light sensors
#
# CONFIG_ADJD_S311 is not set
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
# CONFIG_CM3605 is not set
# CONFIG_CM36651 is not set
# CONFIG_GP2AP020A00F is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_ISL29125 is not set
# CONFIG_JSA1212 is not set
# CONFIG_RPR0521 is not set
# CONFIG_LTR501 is not set
# CONFIG_LV0104CS is not set
# CONFIG_MAX44000 is not set
# CONFIG_OPT3001 is not set
# CONFIG_PA12203001 is not set
# CONFIG_SI1133 is not set
# CONFIG_SI1145 is not set
# CONFIG_STK3310 is not set
# CONFIG_ST_UVIS25 is not set
# CONFIG_TCS3414 is not set
# CONFIG_TCS3472 is not set
# CONFIG_SENSORS_TSL2563 is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2772 is not set
# CONFIG_TSL4531 is not set
# CONFIG_US5182D is not set
# CONFIG_VCNL4000 is not set
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
# CONFIG_ZOPT2201 is not set

#
# Magnetometer sensors
#
# CONFIG_AK8974 is not set
# CONFIG_AK8975 is not set
# CONFIG_AK09911 is not set
# CONFIG_BMC150_MAGN_I2C is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_MAG3110 is not set
# CONFIG_MMC35240 is not set
# CONFIG_IIO_ST_MAGN_3AXIS is not set
# CONFIG_SENSORS_HMC5843_I2C is not set
# CONFIG_SENSORS_HMC5843_SPI is not set

#
# Multiplexers
#
# CONFIG_IIO_MUX is not set

#
# Inclinometer sensors
#

#
# Triggers - standalone
#
# CONFIG_IIO_INTERRUPT_TRIGGER is not set
# CONFIG_IIO_SYSFS_TRIGGER is not set

#
# Digital potentiometers
#
# CONFIG_AD5272 is not set
# CONFIG_DS1803 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MCP4018 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
# CONFIG_TPL0102 is not set

#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set

#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
# CONFIG_BMP280 is not set
# CONFIG_HP03 is not set
# CONFIG_MPL115_I2C is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MPL3115 is not set
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
# CONFIG_IIO_ST_PRESS is not set
# CONFIG_T5403 is not set
# CONFIG_HP206C is not set
# CONFIG_ZPA2326 is not set

#
# Lightning sensors
#
# CONFIG_AS3935 is not set

#
# Proximity and distance sensors
#
# CONFIG_ISL29501 is not set
# CONFIG_LIDAR_LITE_V2 is not set
# CONFIG_RFD77402 is not set
# CONFIG_SRF04 is not set
# CONFIG_SX9500 is not set
# CONFIG_SRF08 is not set

#
# Resolver to digital converters
#
# CONFIG_AD2S1200 is not set

#
# Temperature sensors
#
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MLX90614 is not set
# CONFIG_MLX90632 is not set
# CONFIG_TMP006 is not set
# CONFIG_TMP007 is not set
# CONFIG_TSYS01 is not set
# CONFIG_TSYS02D is not set
# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
# CONFIG_PWM_ROCKCHIP_ONESHOT is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_PARTITION_PERCPU=y
# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_FMC is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
# CONFIG_PHY_ROCKCHIP_DP is not set
CONFIG_PHY_ROCKCHIP_EMMC=y
# CONFIG_PHY_ROCKCHIP_INNO_COMBPHY is not set
CONFIG_PHY_ROCKCHIP_INNO_HDMI_PHY=y
CONFIG_PHY_ROCKCHIP_INNO_MIPI_DPHY=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y
# CONFIG_PHY_ROCKCHIP_INNO_VIDEO_PHY is not set
CONFIG_PHY_ROCKCHIP_MIPI_RX=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
# CONFIG_ARM_CCI_PMU is not set
# CONFIG_ARM_CCN is not set
CONFIG_ARM_PMU=y
# CONFIG_ARM_DSU_PMU is not set
# CONFIG_ARM_SPE_PMU is not set
CONFIG_RAS=y

#
# Android
#
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# CONFIG_LIBNVDIMM is not set
# CONFIG_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y

#
# TEE drivers
#
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_LEGACY_ENERGY_MODEL_DT is not set
# CONFIG_RK_FLASH is not set
CONFIG_RK_NAND=y

#
# Headset device support
#
CONFIG_RK_HEADSET=y

#
# RKNPU
#
CONFIG_ROCKCHIP_RKNPU=y

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
CONFIG_EXT4_FS_ENCRYPTION=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
CONFIG_F2FS_FS_ENCRYPTION=y
# CONFIG_F2FS_FAULT_INJECTION is not set
# CONFIG_F2FS_FS_COMPRESSION is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
CONFIG_FS_VERITY=y
# CONFIG_FS_VERITY_DEBUG is not set
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
# CONFIG_AUTOFS_FS is not set
CONFIG_FUSE_FS=y
# CONFIG_CUSE is not set
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
CONFIG_INCREMENTAL_FS=y

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROC_CHILDREN is not set
# CONFIG_PROC_UID is not set
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_HUGETLBFS is not set
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_SDCARD_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFLATE_COMPRESS=y
# CONFIG_PSTORE_LZO_COMPRESS is not set
# CONFIG_PSTORE_LZ4_COMPRESS is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
# CONFIG_PSTORE_842_COMPRESS is not set
# CONFIG_PSTORE_ZSTD_COMPRESS is not set
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_CONSOLE_FORCE is not set
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
# CONFIG_PSTORE_MCU_LOG is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
CONFIG_UNICODE=y
CONFIG_UNICODE_NORMALIZATION_SELFTEST=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DISCARD=y
# CONFIG_EXFAT_DELAYED_SYNC is not set
# CONFIG_EXFAT_KERNEL_DEBUG is not set
# CONFIG_EXFAT_DEBUG_MSG is not set
CONFIG_EXFAT_DEFAULT_CODEPAGE=437
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"

#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_COMPAT=y
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
# CONFIG_SECURITY_PATH is not set
CONFIG_LSM_MMAP_MIN_ADDR=4096
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_HARDENED_USERCOPY_FALLBACK=y
# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
# CONFIG_FORTIFY_SOURCE is not set
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STATIC_USERMODEHELPER_PATH=""
CONFIG_SECURITY_SELINUX=y
# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
CONFIG_TEE_SUPPORT=y
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_SELINUX=y
# CONFIG_DEFAULT_SECURITY_DAC is not set
CONFIG_DEFAULT_SECURITY="selinux"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_RSA=y
# CONFIG_CRYPTO_DH is not set
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_PCRYPT is not set
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=y
# CONFIG_CRYPTO_MCRYPTD is not set
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_SIMD=y
# CONFIG_CRYPTO_CURVE25519 is not set

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_AEGIS128L is not set
# CONFIG_CRYPTO_AEGIS256 is not set
# CONFIG_CRYPTO_MORUS640 is not set
# CONFIG_CRYPTO_MORUS1280 is not set
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
CONFIG_CRYPTO_XTS=y
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_ADIANTUM is not set

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
# CONFIG_CRYPTO_BLAKE2S is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
CONFIG_CRYPTO_GHASH=y
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_SHA3 is not set
CONFIG_CRYPTO_SM3=y
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_TEA is not set
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_842 is not set
CONFIG_CRYPTO_LZ4=y
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_ZSTD is not set

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
CONFIG_CRYPTO_HASH_INFO=y

#
# Crypto library routines
#
# CONFIG_CRYPTO_LIB_BLAKE2S is not set
# CONFIG_CRYPTO_LIB_CHACHA is not set
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
# CONFIG_CRYPTO_LIB_POLY1305 is not set
# CONFIG_CRYPTO_LIB_CURVE25519 is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=y
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
# CONFIG_INDIRECT_PIO is not set
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC64 is not set
# CONFIG_CRC4 is not set
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
# CONFIG_CRC8 is not set
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=y
CONFIG_TEXTSEARCH_BM=y
CONFIG_TEXTSEARCH_FSM=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_DMA_DIRECT_OPS=y
CONFIG_SWIOTLB=y
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER is not set
# CONFIG_PRINTK_PROCESS is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_GDB_SCRIPTS is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_PAGE_OWNER is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_DEBUG_KERNEL=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_VM is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_CC_HAS_KASAN_GENERIC=y
# CONFIG_KASAN is not set
CONFIG_KASAN_STACK=1
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Lockups and Hangs
#
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=5
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_STACK_END_CHECK=y
# CONFIG_DEBUG_TIMEKEEPING is not set
# CONFIG_DEBUG_PREEMPT is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_HAVE_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PI_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_PREEMPTIRQ_EVENTS is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
CONFIG_ENABLE_DEFAULT_TRACERS=y
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
CONFIG_TRACING_EVENTS_GPIO=y
# CONFIG_DMA_API_DEBUG is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_SORT is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_BITFIELD is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_MEMTEST is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
# CONFIG_DEBUG_WX is not set
# CONFIG_DEBUG_ALIGN_RODATA is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
 

 

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BUILD CUSTOM SDK - shaggy013 - 02-14-2022

Made this bsp/sdk because the beta wich is on the site don't makes a image wich you can flash and boot from sd/emmc
and while mainline is cool a working bsp/sdk makes it more complete for me

I looked how raxda and firefly made their bsp/sdk and made a custom one for the Quartz64
used some scripts of them and adjusted so they work to build a image
Most sources are from rockchip and the just 2 or 3 comes from other sources (from firefly: rawimg script, qsetting and camera_engine_rkaiq package)
So i tried to keep it some kind rockchip original and those packages were not on the rockhcip site or other open places so if it is a problem i can remove them

The bsp/sdk builds a buildroot ,debian or yocto distro wich you can flash on a sd/emmc or rockchip images to do it the difficult way
the hardest part was to get the right revisions to make some packages work

The bsp/sdk has 2 kernel options kernel 4.19.19 or 5.10.66 from rockchip sources

the 4.19 is common used kernel for the rk3566/68 bsp/sdk kernel and it has
working hdmi,lan,usb,wifi,gpu and npu

Quote

* 4.19.219-2022-01-18

the 5.10 is a newer(experimental) one it is for the coming rk3588 and proberly for the newer android 12 rk3566/68 no confirmation but saw some info
working hdmi,lan,usb,gpu



 

Quote

* 5.10.66-2022-01-18

!! keep in mind 5.10 is way from stable npu crash no video but hdmi works !!!

pcie and bluetooth not tested
not included lcd,touchscreen (just broke one)

 

Quote

*** ADDED ***
Added buildconfigs for other pine boards with a rk356x  PineNote ,Quartz64-b and Soquartz
!!! DTS files not included only added a pinenote dts the soquartz and quartz64-b are just quartz64-a dts !!
so if you got a dts for dowmstream kernel bards you can add them

so instead of

quartz64-rk3566-buildroot-k4.mk
 you do
quartz64b-rk3566-buildroot-k4.mk        For building a Quartz64-B image
or
pinenote-rk3566-buildroot-k4.mk         For Building a Pinenote image
or
soquartz-rk3566-buildroot-k4.mk         For building a Soquartz image

and same for

quartz64-rk3566-raw-k4.mk

quartz64b-rk3566-raw-k4.mk        For building a Quartz64-B  SD-image
or
pinenote-rk3566-raw-k4.mk         For Building a Pinenote SD-image
or
soquartz-rk3566-raw-k4.mk         For building a Soquartz SD-image


*Needed*

Time
Ubuntu 18.04 or 20.04
at least 200+GB of free space (yeah it likes to grow maybey more)

*Building*

#Packages Needed on pc

sudo apt-get install repo git ssh make gcc libssl-dev liblz4-tool \
expect g++ patchelf chrpath gawk texinfo chrpath diffstat binfmt-support \
qemu-user-static live-build bison flex fakeroot cmake gcc-multilib g++-multilib \
unzip device-tree-compiler python-pip ncurses-dev python-pyelftools

*Download BSP*

#make bsp/sdk folder

mkdir Quartz64

#go to Quartz64 folder

cd Quartz64

# make .repo folder

mkdir .repo

#go to .repo folder

cd .repo

#download repo

git clone https://github.com/rockchip-linux/repo
or
git clone https://gerrit.googlesource.com/git-repo repo

#make repo executable

chmod a+rx repo/repo

#go back

cd ..

# Download repo manifest

.repo/repo/repo init -u https://github.com/Shaggy013/manifests -b master -m rk356x_linux_custom_v1.2.8_20220309.xml

# Dowload bsp/sdk

.repo/repo/repo sync --no-clone-bundle

***** trouble ****
if it gives trouble about github account
https://elinux.org/Buildroot_how_to_contribute
configure section
**** only by trouble ****

Now you see that your Quartz64 folder is full with new folders and files
your Download is finished

*Building*

There are 4 distros you can build Buildroot,Debian,Ubuntu and Yocto
You can choose to make the distro against the 4.19 or 5.10 kernel

First you choose wich kernel

#for 4.19

./build.sh quartz64-rk3566-buildroot-k4.mk

#or 5.10

./build.sh quartz64-rk3566-buildroot-k5.mk

For the first time you have to do it twice the first time can give a error

you see something like this

***** example ****
processing option: quartz64-rk3566-buildroot-k4.mk
link kernel to proper kernel-directory
renew kernel to proper kernel-directory
link kernel 4
link Debian to proper Debian-distro
renew Debian to proper Debian-Distro
link debian to bullseye or buster
link kernel 4
switching to board: /home/thc013/corner/Quartz64-release/device/rockchip/rk356x/quartz64-rk3566-buildroot-k4.mk

****** example ****

so now you bsp is set to the right options

You have multiple options but you have to make a uboot,kernel and recovery and a rootfs so the best start is just as a base for the later buiding of distros

# build all (uboot,kernel,recovery,rootfs"buildroot",rockchip image) / AKA BUILDROOT

./build.sh

**Info**
For the 4.19 kernel you get after a few minutes a blue screen where you have to give the right voltage for the io-domains
watch carefull some domains are not asked
the domain info comes from the schematic or the dts file

pmuio1-supply = <&vcc3v3_pmu>; not asked
pmuio2-supply = <&vcc_3v3>;
vccio1-supply = <&vccio_acodec>; 3,3
vccio2-supply = <&vcc_1v8>; not asked
vccio3-supply = <&vccio_sd>; 3,3
vccio4-supply = <&vcca1v8_pmu>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc1v8_dvp>;
vccio7-supply = <&vcc_3v3>;
After that the buildroot will start the rest of the building
****

Depening on the speed of your pc it takes from a hour to ?
so after some coffee and some heat for the cold weather you get

Now it build a rockhip image DO NOT FLASH TO SD !!!!!!!!

Make buildroot image ok!
..../Quartz64/rockdev/pack/QUARTZ64-RK3566-BUILDROOT-K4-GPT-!DATE!-2137.img

Now it builds a rockhip image DO NOT FLASH TO SD !!!!!!!!

#change to the SD/EMMC IMAGE option

.#for 4.19

./build.sh quartz64-rk3566-raw-k4.mk

#or 5.10

./build.sh quartz64-rk3566-raw-k5.mk

#Build image

./build.sh rawimg

***Info ***
Make raw image ok!
..../Quartz64/rockdev/pack/QUARTZ64-RK3566-RAW-K4-GPT-!DATE!-2137.img

Now you can flash that image RAW to a sd or EMMC with your desired tool Etcher,dd etc

*****

Now you can build a Debian or a Yocto image

**** DEBIAN ******

#for 4.19

./build.sh quartz64-rk3566-buildroot-k4.mk

#or 5.10

./build.sh quartz64-rk3566-buildroot-k5.mk

!!
before building you have to install extra packages they differ from ubuntu and debian so you have to install or overwrite them first

sudo apt-get install binfmt-support qemu-user-static
sudo dpkg -i ubuntu-build-service/packages/*
sudo apt-get install -f


# build Debian rootfs

./build.sh debian

Now it build a rockhip image DO NOT FLASH TO SD !!!!!!!!

#change to the SD/EMMC IMAGE option

.#for 4.19

./build.sh quartz64-rk3566-raw-k4.mk

#or 5.10

./build.sh quartz64-rk3566-raw-k5.mk

#Build image

./build.sh rawimg

***Info ***
Make raw image ok!
..../Quartz64/rockdev/pack/QUARTZ64-RK3566-RAW-K4-GPT-!DATE!-2137.img

Now you can flash that image RAW to a sd or EMMC with your desired tool Etcher,dd etc

Same as rest /Quartz64/rockdev/pack/

**** Ubuntu ******

#for 4.19

./build.sh quartz64-rk3566-buildroot-k4.mk

#or 5.10

./build.sh quartz64-rk3566-buildroot-k5.mk

!!
before building you have to install extra packages they differ from ubuntu and debian so you have to install or overwrite them first

sudo apt-get install binfmt-support qemu-user-static
sudo dpkg -i ubuntu-build-service/packages/*
sudo apt-get install -f

# build Ubuntu rootfs

./build.sh ubuntu

*** This build option ask after a few minutes the keyboard and region settings ****

Now it build a rockhip image DO NOT FLASH TO SD !!!!!!!!

#change to the SD/EMMC IMAGE option

.#for 4.19

./build.sh quartz64-rk3566-raw-k4.mk

#or 5.10

./build.sh quartz64-rk3566-raw-k5.mk

#Build image

./build.sh rawimg

***Info ***
Make raw image ok!
..../Quartz64/rockdev/pack/QUARTZ64-RK3566-RAW-K4-GPT-!DATE!-2137.img

Now you can flash that image RAW to a sd or EMMC with your desired tool Etcher,dd etc

Same as rest /Quartz64/rockdev/pack/



***** YOCTO *****
!!! Yocto can take a time to build the toolchain has also clang etc included !!!

#for 4.19

./build.sh quartz64-rk3566-buildroot-k4.mk

#or 5.10

./build.sh quartz64-rk3566-buildroot-k5.mk

# build Debian rootfs

./build.sh yocto

Now it build a rockhip image DO NOT FLASH TO SD !!!!!!!!

#change to the SD/EMMC IMAGE option

.#for 4.19

./build.sh quartz64-rk3566-raw-k4.mk

#or 5.10

./build.sh quartz64-rk3566-raw-k5.mk

#Build image

./build.sh rawimg

***Info ***
Make raw image ok!
..../Quartz64/rockdev/pack/QUARTZ64-RK3566-RAW-K4-GPT-!DATE!-2137.img

Now you can flash that image RAW to a sd or EMMC with your desired tool Etcher,dd etc

Same as rest /Quartz64/rockdev/pack/

***** BUILD OPTIONS ****

Available options:

*.mk              -switch to specified board config
launch              -list current SDK boards and switch to specified board config
uboot              -build uboot
spl                -build spl
loader            -build loader
kernel            -build kernel"
modules            -build kernel modules
modules2          -build kernel modules to rockdev/pack/modules *added*
toolchain          -build toolchain
extboot            -build extlinux boot.img, boot from EFI partition
rootfs            -build default rootfs, currently build buildroot as default
buildroot          -build buildroot rootfs
ramboot            -build ramboot image
multi-npu_boot    -build boot image for multi-npu board
yocto              -build yocto rootfs
debian            -build debian 9 or 10 rootfs !! set in config !! !! only bullseye included
ubuntu            -build Ubuntu 20.04 rootfs !! set in config !! !! only focal included
pcba              -build pcba not tested
recovery          -build recovery
all                -build uboot, kernel, rootfs, recovery image
cleanall          -clean uboot, kernel, rootfs, recovery
firmware          -pack all the image we need to boot up system
updateimg          -pack update image not tested
rawimg            -pack raw image
otapackage        -pack ab update otapackage image (update_ota.img) not tested
sdpackage          -pack update sdcard package image (update_sdcard.img) not tested
save              -save images, patches, commands used to debug
allsave            -build all & firmware & updateimg & save
check              -check the environment of building
info              -see the current board building information
app/<pkg>          -build packages in the dir of app/*
external/<pkg>    -build packages in the dir of external/*

**** Examples ****

For if you made changes to uboot or the kernel
buildroot is another story

#u-boot

./build.sh uboot

#kernel

./build.sh kernel

#recovery

./build.sh recovery


***** Making modules from the kernel ****
it can be that you want to copy or have some kernel modules to copy to your image

./build.sh modules2

makes in the folder rockdev/pack/modules the kernel-modules

**********************************************************************************************************************

****** TESTS ******

the distros all contain a folder rockchip test with some simple demos and test even a benchmark

cd ~/rockchip_test

# some test options

./rockhip_test.sh

The npu video and gpu are most fun

********

ddr test :                  1 (memtester & stressapptest)
cpufreq test:              2 (cpufreq stresstest)
????flash stress test:          3
# not working # bluetooth test:      4 (bluetooth on&off test)
# not working # audio test:          5
recovery test:              6 (default wipe all)
suspend_resume test:        7 (suspend & resume)
wifi test:                  8
ethernet test:              9
auto reboot test:          10
ddr freq scaling test       11
#not working # npu test              12
npu2 test                  13 (rk356x or rk3588)
??? camera test                14 (use rkisp_demo)
video test                  15 (use gstreamer-wayland and app_demo)
gpu test                            16 (use glmark2)
# not working# chromium test          17 (chromium with video hardware acceleration)"
nand power lost test:       18

*****

************ Last Info ******

That is almost step for step i hope
it just started with a dts and boardconfig but got a little bigger
if i made any faults or i missed something please let me know
no debug program just plain doing diff,reading(there is a lot),copy paste and some simple adjustments to make it work for me
well it was something diffrent as making a custom limo os for the limo M1 360 from vodafone in 2009 (got first to root cdc_nand) gone glory
the sources and info you can all find them on google and github and gitlab

so no OFFICIAL ROCKCHIP or QUARTZ64 JUST !!CUSTOM!!


I will include download links with the images it compiles

and to make it work for another 3566 or 68 just make a boardconfig.mk in ?/Quartz64/device/rockchip/rk356x/
and make sure the defconfigs and dts are inthe right places
well at least it gets you on the way

SPECIAL THNX TO quartz64 chat , my free time ,a quartz64 too stay still alive ,ryzen 3700x+5700xt to keep me warm,20TB nas for the space,R.I.P sd (2),touchscreen,monitor and OPI4 (well the opi semi dead dont fuss with the fusb32 in uboot )

 

inside this SDK you will need to include this header to dts file

 

Quote

#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/rk3568-power.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/suspend/rockchip-rk3568.h>
#include <dt-bindings/thermal/thermal.h>
#include "rk3568-dram-default-timing.dtsi"
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/sensor-dev.h>
#include <dt-bindings/display/media-bus-format.h>
#include "rk3566-diff3.dtsi"

 

Edited by hotnikq
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@Walma This FIT image needs to be flashed on the internal storage, this board don't have SD CARD Reader.
 

Backup Rockchip Firmware emmc

Driver Assistant Download
RkDevTool Download

Upgrade Rockchip Firmware eemc
Maskrom mode

Loader mode


Install Drivers,
Just Press the RESET Button when connect male-male USB 2.0 (BLACK) to Desktop

MAKE A Backup
Rockchip boards are unbrikable
in a worse case  you need to short the EMMC CLK pin to GND on the other side of the board 
and upload the righ LoaderALL.bin File from a linux machine that you backup.
to connect the RK3566 on Desktop USB Maskrom Mode.

 

Edited by hotnikq
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@Walma when the Board Boot UP you will need to conect RJ45 LAN, Find the IP Addres on your PiHole Firewall or  Lan Router and SSH to the ubuntu.
User: ubuntu
Password: ubuntu



Partition Parameter.txt
 

Quote

FIRMWARE_VER: 1.0
MACHINE_MODEL: RK3568
MACHINE_ID: 007
MANUFACTURER: RK3568
MAGIC: 0x5041524B
ATAG: 0x00200800
MACHINE: 0xffffffff
CHECK_MASK: 0x80
PWR_HLD: 0,0,A,0,1
TYPE: GPT
CMDLINE: mtdparts=rk29xxnand:0x00002000@0x00004000(uboot),0x00002000@0x00006000(misc),0x00010000@0x00008000(boot),0x00010000@0x00018000(recovery),0x00010000@0x00028000(backup),-@0x00038000(rootfs:grow)
uuid:rootfs=614e0000-0000-4b53-8000-1d28000054a9

 

Edited by hotnikq
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Release Version v0.3BETA (DEPRECATED)
UPDATE: Partition " / " resized to FULL DISK 
+wifi 
+bluetooth
No Video out
No Virtualization
No Docker
H96 MAX Board Type 1
Kernel 4.19.219
RK3566
Linux FIT Image Rockchip EMMC
Ubuntu 20.04 LTS
This image has been compiled without any standardization and should be used for experimental purposes only,
there is no guarantee of compatibility with your device

Download Link: DELETED FILE DUE DEPRECATED KERNEL4


First BOOT COMANDS:
Partition " / " resized to FULL DISK  

$ df -h
$ sudo resize2fs /dev/mmcblk2p6
$ df -h



Base Parameters to build:
DTB + DTS + rockchip_defconfig +BT +WIFI

 

SDK 4.19.219 LINUX to RK3566 H96 MAX

 

Why it doesn't video output? >Problem< >Problem<

Solution: ????11/2022??? @Walma let's debug the video output?

Edited by hotnikq
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I already spent 30 days and more than 3240,00$ dollars man machine running this debug system, I will visit this topic only sometimes, I want another user to continue this project.

a Bad thing is that The kernel supplied by Rockchip 4.19 for the RK3566 is too crippled to run Docker.

here a screenshot of the USB HUB 3.0 on port 3.0

Ugreen 4 in 1 USB 3.0 Hub
2x SATA TO USB 3.0 CONVERTER


/dev/sda:
 Timing cached reads:   1816 MB in  2.00 seconds = 907.91 MB/sec
 Timing buffered disk reads: 576 MB in  3.00 seconds = 191.75 MB/sec
ubuntu@localhost:~$ sudo hdparm -tT /dev/sdb

/dev/sdb:
 Timing cached reads:   1840 MB in  2.00 seconds = 920.41 MB/sec
 Timing buffered disk reads: 532 MB in  3.01 seconds = 176.97 MB/sec

 



USBHUB-SATA.jpg886eb958-7588-4809-a7b3-f8f71e5f04fa.jpgWhats-App-Image-2022-11-11-at-13-11-29.j

 

 

Edited by hotnikq
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I have installed Jellyfin and enable Hardware Acceleration!

Extra Configuration VA-API hardware acceleration on Debian/Ubuntu
  

$ sudo apt install jellyfin-ffmpeg

  

$ apt install ffmpeg
$ ffmpeg -codecs


@carol

Codecs List:  

 D..... = Decoding supported
 .E.... = Encoding supported
 ..V... = Video codec
 ..A... = Audio codec
 ..S... = Subtitle codec
 ...I.. = Intra frame-only codec
 ....L. = Lossy compression
 .....S = Lossless compression

 DEV.L. h263                 H.263 / H.263-1996, H.263+ / H.263-1998 / H.263 version 2 (decoders: h263 h263_v4l2m2m ) (encoders: h263 h263_v4l2m2m )
 DEV.L. hevc                 H.265 / HEVC (High Efficiency Video Coding) (decoders: hevc hevc_v4l2m2m ) (encoders: libx265 hevc_v4l2m2m hevc_vaapi )
DEV.LS h264                 H.264 / AVC / MPEG-4 AVC / MPEG-4 part 10 (decoders: h264 h264_v4l2m2m ) (encoders: libx264 libx264rgb h264_omx h264_v4l2m2m h264_vaapi )
 DEV.L. mpeg1video           MPEG-1 video (decoders: mpeg1video mpeg1_v4l2m2m )
 DEV.L. mpeg2video           MPEG-2 video (decoders: mpeg2video mpegvideo mpeg2_v4l2m2m ) (encoders: mpeg2video mpeg2_vaapi )
 DEV.L. mpeg4                MPEG-4 part 2 (decoders: mpeg4 mpeg4_v4l2m2m ) (encoders: mpeg4 libxvid mpeg4_v4l2m2m )
 D.V.L. vc1                  SMPTE VC-1 (decoders: vc1 vc1_v4l2m2m )
 DEV.L. vp8                  On2 VP8 (decoders: vp8 vp8_v4l2m2m libvpx ) (encoders: libvpx vp8_v4l2m2m vp8_vaapi )
 DEV.L. vp9                  Google VP9 (decoders: vp9 vp9_v4l2m2m libvpx-vp9 ) (encoders: libvpx-vp9 vp9_vaapi )


rk3566-transcoder.jpg
 

Edited by hotnikq
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  • Werner changed the title to Efforts to develop firmware for H96 MAX V56 RK3566 4G/32G

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