DigitalDaz Posted August 8, 2022 Posted August 8, 2022 (edited) Firstly, I would like to say I know next to nothing about what I am doing at all. I'm trying to learn though! With the current shortage of decent SBCs at a reasonable price I thought being able to run Armbian on the above device would make it a very good deal. I am only interested in using the device as a server so I currently have no information on running it as a desktop though I can burn an image and post the results if anyone is interested. From reading the forums it seems many devices will try and boot from external storage of some sort before booting from emmc. This turned out not to be the case for this device. I blundered about for a while just writing random stuff to sd cards and trying to boot, nothing worked. I eventually connected a serial adapter to this board, there are holes on the board quite clearly marked, V,R,T and G. The baud rate is 1500000 Once I had done this, I realised how much earlier I should have done it, I now had a little light on what was going on. It appeared from using printenv that the boot targets are set on this device to go for emmc first. There is no saveenv so this left me wondering how I was going to ever get it to boot without needing the serial adapter. There appeared to be no option to boot from SD. What I did notice was that one of the boot targets was usb0 and so I wrote the Armbian_22.02.0-trunk_Station-m2_bullseye_legacy_4.19.219.img to a USB stick. I replaced the rk3566-firefly-roc-pc.dtb with the one attached which I extracted from the Android firmware. I then tried to boot from this by breaking into the boot sequence using ctrl-c and then used "run bootcmd_usb0". I saw that it was trying to boot but then was unable to find the root filesystem. I now thought that USB wasn't compiled in/loaded at this stage and this led me to believe that I may be able to get this working by now adding an SD card with the same image on it. This worked! I ended up with a login prompt and networking was working and I could SSH in. So how now do I get it to boot from my combo? I started by using fdisk and deleted all partitions on the emmc, this trashed everything and after restoring the android image back to the emmc using the rockchip recovery tool and a bit more reading, I could see that u-boot was on the second emmc partition. There were actually 15 partitions on the emmc. I now deleted all but the first two and issued the reboot command. I still have no explanation for what happened next. For some reason, the usb storage seemed no longer to be recognised but yet the first stage of the boot seemed to be happening but then it was crashing. I knew what the problem was from my earlier experimentation. When I wrote the SD card, I hadn't replaced the DTB as I believed I only needed the SD for the root filesystem. I quickly added the DTB so the SD and rebooted. This was now successful. I was now booting from the SD card, something I hadn't seemed to be able to do from the u-boot command line, that will just be some error of mine. I quickly added a partition to the emmc and copied the root filesystem there. I then updated the sd card extlinux to point to that emmc partition for the root filesystem and thats just about currently where I am at. |_ _/ _ \| ___| | _ \| |_ _ ___ | || (_) |___ \ | |_) | | | | / __| | | \__, |___) | | __/| | |_| \__ \ |_| /_/|____/ |_| |_|\__,_|___/ Welcome to Armbian 22.05.3 Bullseye with Linux 4.19.219-station-p2 System load: 2% Up time: 7:36 Memory usage: 13% of 7.50G IP: 192.168.50.29 CPU temp: 43°C Usage of /: 6% of 58G Last login: Sun Aug 7 23:34:24 2022 from 192.168.50.121 cat /proc/cpuinfo processor : 0 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 1 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 2 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 processor : 3 BogoMIPS : 48.00 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x2 CPU part : 0xd05 CPU revision : 0 Hardware : Rockchip RK3566 BOX DEMO V10 ANDROID Board Serial : 399eb13dd69295ae free total used free shared buff/cache available Mem: 7862464 1014552 6063900 61308 784012 6705776 Swap: 0 0 0 I really wish I could get the saveenv to work but I guess this means rebuilding u-boot and flashing that, then I could boot from emmc, I can already do that from the u-boot cli but I'm quite some reading and experimentation away from that. I conclude from this though that there will never be a way to get to this stage without hooking up to a serial adapter first as I can see no way to delete those emmc partitions without that and so it will always try and boot the android first. Maybe a custom firmware that only contains the u-boot? That too is much reading away. I hope this all helps someone in some way, I wouldn't be where I am with this now without the help of this forum. The box, by the way is this one: https://www.amazon.co.uk/gp/product/B098DY737L The replacement dtb is attached. I also managed to get Proxmox running on it t95plus.dtb Edited August 8, 2022 by DigitalDaz 1 Quote
maka Posted August 8, 2022 Posted August 8, 2022 It seems to me that you have not flashed Linux uboot to emmc so booting from there is not working. Booting from sd card is not a bad solution though. 0 Quote
pyroo Posted August 11, 2022 Posted August 11, 2022 Hi @DigitalDaz Looks great so far, just a few questions. Does it support 1gbe ? and is the 8gb accessible? Great effort awesome to see, i sent you a dm in regards to what you've got done here. 0 Quote
DigitalDaz Posted August 11, 2022 Author Posted August 11, 2022 Yes, its gigabit and yes, the 8GB is there too And coming very soon is a guide on how to get this all working without opening the box. It very easy once you know how. If you haven't got a USB A male to USB A male, get one. 0 Quote
DigitalDaz Posted August 11, 2022 Author Posted August 11, 2022 PS I like these so much I got another two, and got Proxmox running on them. 0 Quote
pyroo Posted August 11, 2022 Posted August 11, 2022 I already have one sat here, 4GB variant but haven't had any chance to delve into it yet. Im going to order a 8gb one now and i've got a few a to a cables from reflashing amlogic boxes. Sounds very promising 0 Quote
pyroo Posted August 11, 2022 Posted August 11, 2022 Does it look possible to burn to EMMC etc and boot from there or is this still a long way away in terms of work needed? 0 Quote
DigitalDaz Posted August 11, 2022 Author Posted August 11, 2022 I'm really struggling with the emmc boot at the moment, trying everything. My knowledge just isn't up to it. I'm doing a shed load of reading. What is very easy is to boot from and sdcard then have the root filesystem on emmc so basically its just loading the first part of the boot from sdcard then continues to boot from the emmc. Performance should be as good as having it installed on emmc. 0 Quote
DigitalDaz Posted August 11, 2022 Author Posted August 11, 2022 I'll have you a guide that will work fine and be easy by tomorrow. 0 Quote
DigitalDaz Posted August 11, 2022 Author Posted August 11, 2022 I can already boot from emmc by the way by using a serial cable and issuing a couple of commands in the u-boot There is a saveenv missing that would normally allow you to save the env variables to flash, then it would be easy. So yes, I can boot from flash but I don't currently have a way to save it. That's now I'm sure its just a matter of time 0 Quote
DigitalDaz Posted August 11, 2022 Author Posted August 11, 2022 I'm going to write up my progress here as I move forward: https://www.t95plus.com/ 1 Quote
jeffbouchard Posted September 27, 2022 Posted September 27, 2022 the H96 Max RK3566 8GB (the very first at 8GB) doesn't even have a SD slot, u-boot nor any uEnv.txt it's a DSU https://developer.android.com/topic/dsu dynamic software update that can be bypassed but it's totally alien to the solutions we (I) have thus far. I got them rooted though but replacing the OS is gonna be a tough candy I too made a station image but M-2 (rk3566) not P-2 (rk3568) with the build script, fingers crossed. The RK tools doesn't differenciate 3568 of 3566 in the config files. 1 Quote
Hefti Posted September 29, 2022 Posted September 29, 2022 For the reference, here is the device tree source of t95plus.dtb Spoiler /dts-v1/; / { compatible = "rockchip,rk3566-box-demo-v10\0rockchip,rk3566"; interrupt-parent = <0x01>; #address-cells = <0x02>; #size-cells = <0x02>; model = "Rockchip RK3566 BOX DEMO V10 ANDROID Board"; ddr_timing { compatible = "rockchip,ddr-timing"; ddr2_speed_bin = <0x00>; ddr3_speed_bin = <0x15>; ddr4_speed_bin = <0x0c>; pd_idle = <0x0d>; sr_idle = <0x5d>; sr_mc_gate_idle = <0x00>; srpd_lite_idle = <0x00>; standby_idle = <0x00>; auto_pd_dis_freq = <0x42a>; auto_sr_dis_freq = <0x320>; ddr2_dll_dis_freq = <0x12c>; ddr3_dll_dis_freq = <0x12c>; ddr4_dll_dis_freq = <0x271>; phy_dll_dis_freq = <0x190>; ddr2_odt_dis_freq = <0x64>; phy_ddr2_odt_dis_freq = <0x64>; ddr2_drv = <0x02>; ddr2_odt = <0x40>; phy_ddr2_ca_drv = <0x00>; phy_ddr2_ck_drv = <0x00>; phy_ddr2_dq_drv = <0x00>; phy_ddr2_odt = <0x00>; ddr3_odt_dis_freq = <0x14d>; phy_ddr3_odt_dis_freq = <0x14d>; ddr3_drv = <0x02>; ddr3_odt = <0x40>; phy_ddr3_ca_drv = <0x00>; phy_ddr3_ck_drv = <0x00>; phy_ddr3_dq_drv = <0x00>; phy_ddr3_odt = <0x00>; phy_lpddr2_odt_dis_freq = <0x14d>; lpddr2_drv = <0x02>; phy_lpddr2_ca_drv = <0x00>; phy_lpddr2_ck_drv = <0x00>; phy_lpddr2_dq_drv = <0x00>; phy_lpddr2_odt = <0x00>; lpddr3_odt_dis_freq = <0x14d>; phy_lpddr3_odt_dis_freq = <0x14d>; lpddr3_drv = <0x01>; lpddr3_odt = <0x02>; phy_lpddr3_ca_drv = <0x00>; phy_lpddr3_ck_drv = <0x00>; phy_lpddr3_dq_drv = <0x00>; phy_lpddr3_odt = <0x00>; lpddr4_odt_dis_freq = <0x14d>; phy_lpddr4_odt_dis_freq = <0x14d>; lpddr4_drv = <0x30>; lpddr4_dq_odt = <0x01>; lpddr4_ca_odt = <0x00>; phy_lpddr4_ca_drv = <0x00>; phy_lpddr4_ck_cs_drv = <0x00>; phy_lpddr4_dq_drv = <0x00>; phy_lpddr4_odt = <0x00>; ddr4_odt_dis_freq = <0x271>; phy_ddr4_odt_dis_freq = <0x271>; ddr4_drv = <0x00>; ddr4_odt = <0x200>; phy_ddr4_ca_drv = <0x00>; phy_ddr4_ck_drv = <0x00>; phy_ddr4_dq_drv = <0x00>; phy_ddr4_odt = <0x00>; phandle = <0x8e>; }; aliases { csi2dphy0 = "/csi2-dphy0"; csi2dphy1 = "/csi2-dphy1"; csi2dphy2 = "/csi2-dphy2"; dsi0 = "/dsi@fe060000"; dsi1 = "/dsi@fe070000"; ethernet1 = "/ethernet@fe010000"; gpio0 = "/pinctrl/gpio@fdd60000"; gpio1 = "/pinctrl/gpio@fe740000"; gpio2 = "/pinctrl/gpio@fe750000"; gpio3 = "/pinctrl/gpio@fe760000"; gpio4 = "/pinctrl/gpio@fe770000"; i2c0 = "/i2c@fdd40000"; i2c1 = "/i2c@fe5a0000"; i2c2 = "/i2c@fe5b0000"; i2c3 = "/i2c@fe5c0000"; i2c4 = "/i2c@fe5d0000"; i2c5 = "/i2c@fe5e0000"; mmc0 = "/dwmmc@fe2b0000"; mmc1 = "/dwmmc@fe2c0000"; mmc2 = "/sdhci@fe310000"; mmc3 = "/dwmmc@fe000000"; serial0 = "/serial@fdd50000"; serial1 = "/serial@fe650000"; serial2 = "/serial@fe660000"; serial3 = "/serial@fe670000"; serial4 = "/serial@fe680000"; serial5 = "/serial@fe690000"; serial6 = "/serial@fe6a0000"; serial7 = "/serial@fe6b0000"; serial8 = "/serial@fe6c0000"; serial9 = "/serial@fe6d0000"; spi0 = "/spi@fe610000"; spi1 = "/spi@fe620000"; spi2 = "/spi@fe630000"; spi3 = "/spi@fe640000"; }; cpus { #address-cells = <0x02>; #size-cells = <0x00>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x00>; enable-method = "psci"; clocks = <0x02 0x00>; operating-points-v2 = <0x03>; cpu-idle-states = <0x04>; #cooling-cells = <0x02>; dynamic-power-coefficient = <0xbb>; cpu-supply = <0x05>; phandle = <0x09>; power-model { compatible = "simple-power-model"; leakage-range = <0x0a 0x28>; ls = <0xffffdc14 0x18d8 0x00>; static-coefficient = <0x186a0>; ts = <0x1476e 0x3263d 0xffffef34 0x47>; thermal-zone = "soc-thermal"; }; }; cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x100>; enable-method = "psci"; clocks = <0x02 0x00>; operating-points-v2 = <0x03>; cpu-idle-states = <0x04>; phandle = <0x0a>; }; cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x200>; enable-method = "psci"; clocks = <0x02 0x00>; operating-points-v2 = <0x03>; cpu-idle-states = <0x04>; phandle = <0x0b>; }; cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x300>; enable-method = "psci"; clocks = <0x02 0x00>; operating-points-v2 = <0x03>; cpu-idle-states = <0x04>; phandle = <0x0c>; }; idle-states { entry-method = "psci"; cpu-sleep { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x10000>; entry-latency-us = <0x64>; exit-latency-us = <0x78>; min-residency-us = <0x3e8>; phandle = <0x04>; }; }; }; cpu0-opp-table { compatible = "operating-points-v2"; opp-shared; mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; nvmem-cells = <0x06 0x07 0x08>; nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; rockchip,pvtm-voltage-sel = <0x00 0x14050 0x00 0x14051 0x16b48 0x01 0x16b49 0x186a0 0x02>; rockchip,pvtm-freq = <0x639c0>; rockchip,pvtm-volt = <0xdbba0>; rockchip,pvtm-ch = <0x00 0x05>; rockchip,pvtm-sample-time = <0x3e8>; rockchip,pvtm-number = <0x0a>; rockchip,pvtm-error = <0x3e8>; rockchip,pvtm-ref-temp = <0x28>; rockchip,pvtm-temp-prop = <0x1a 0x1a>; rockchip,thermal-zone = "soc-thermal"; rockchip,temp-hysteresis = <0x1388>; rockchip,low-temp = <0x00>; rockchip,low-temp-adjust-volt = <0x00 0x648 0x124f8>; phandle = <0x03>; opp-408000000 { opp-hz = <0x00 0x18519600>; opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; clock-latency-ns = <0x9c40>; }; opp-600000000 { opp-hz = <0x00 0x23c34600>; opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; clock-latency-ns = <0x9c40>; }; opp-816000000 { opp-hz = <0x00 0x30a32c00>; opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; clock-latency-ns = <0x9c40>; opp-suspend; }; opp-1104000000 { opp-hz = <0x00 0x41cdb400>; opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; clock-latency-ns = <0x9c40>; }; opp-1416000000 { opp-hz = <0x00 0x54667200>; opp-microvolt = <0xe1d48 0xe1d48 0x118c30>; clock-latency-ns = <0x9c40>; }; opp-1608000000 { opp-hz = <0x00 0x5fd82200>; opp-microvolt = <0xf4240 0xf4240 0x118c30>; clock-latency-ns = <0x9c40>; }; opp-1800000000 { opp-hz = <0x00 0x6b49d200>; opp-microvolt = <0x100590 0x100590 0x118c30>; clock-latency-ns = <0x9c40>; }; }; arm-pmu { compatible = "arm,cortex-a55-pmu\0arm,armv8-pmuv3"; interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>; interrupt-affinity = <0x09 0x0a 0x0b 0x0c>; }; cpuinfo { compatible = "rockchip,cpuinfo"; nvmem-cells = <0x0d 0x0e 0x0f>; nvmem-cell-names = "id\0cpu-version\0cpu-code"; }; display-subsystem { compatible = "rockchip,display-subsystem"; memory-region = <0x10 0x11>; memory-region-names = "drm-logo\0drm-cubic-lut"; ports = <0x12>; devfreq = <0x13>; phandle = <0x10c>; route { route-dsi0 { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <0x14>; phandle = <0x10d>; }; route-dsi1 { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <0x15>; phandle = <0x10e>; }; route-edp { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <0x16>; phandle = <0x10f>; }; route-hdmi { status = "okay"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <0x17>; phandle = <0x110>; }; route-lvds { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <0x18>; phandle = <0x111>; }; route-rgb { status = "disabled"; logo,uboot = "logo.bmp"; logo,kernel = "logo_kernel.bmp"; logo,mode = "center"; charge_logo,mode = "center"; connect = <0x19>; phandle = <0x112>; }; }; }; firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; phandle = <0x113>; }; scmi { compatible = "arm,scmi-smc"; shmem = <0x1a>; arm,smc-id = <0x82000010>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x114>; protocol@14 { reg = <0x14>; #clock-cells = <0x01>; rockchip,clk-init = "Tfr"; phandle = <0x02>; }; }; sdei { compatible = "arm,sdei-1.0"; method = "smc"; phandle = <0x115>; }; }; mpp-srv { compatible = "rockchip,mpp-service"; rockchip,taskqueue-count = <0x06>; rockchip,resetgroup-count = <0x06>; status = "okay"; phandle = <0x5a>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; reserved-memory { #address-cells = <0x02>; #size-cells = <0x02>; ranges; phandle = <0x116>; drm-logo@00000000 { compatible = "rockchip,drm-logo"; reg = <0x00 0x00 0x00 0x00>; phandle = <0x10>; }; drm-cubic-lut@00000000 { compatible = "rockchip,drm-cubic-lut"; reg = <0x00 0x00 0x00 0x00>; phandle = <0x11>; }; rknpu { compatible = "shared-dma-pool"; inactive; reusable; size = <0x00 0x20000000>; alignment = <0x00 0x1000>; status = "disabled"; phandle = <0x52>; }; linux,cma { compatible = "shared-dma-pool"; inactive; reusable; reg = <0x00 0x10000000 0x00 0x800000>; linux,cma-default; }; ramoops@110000 { compatible = "ramoops"; reg = <0x00 0x110000 0x00 0xf0000>; record-size = <0x20000>; console-size = <0x80000>; ftrace-size = <0x00>; pmsg-size = <0x50000>; phandle = <0x117>; }; }; rockchip-suspend { compatible = "rockchip,pm-rk3568"; status = "okay"; rockchip,sleep-debug-en = <0x01>; rockchip,sleep-mode-config = <0x4e4>; rockchip,wakeup-config = <0x2001>; phandle = <0x118>; }; rockchip-system-monitor { compatible = "rockchip,system-monitor"; rockchip,thermal-zone = "soc-thermal"; phandle = <0x119>; }; thermal-zones { phandle = <0x11a>; soc-thermal { polling-delay-passive = <0x14>; polling-delay = <0x3e8>; sustainable-power = <0x5c3>; thermal-sensors = <0x1b 0x00>; phandle = <0x11b>; trips { trip-point-0 { temperature = <0x11170>; hysteresis = <0x7d0>; type = "passive"; phandle = <0x11c>; }; trip-point-1 { temperature = <0x14c08>; hysteresis = <0x7d0>; type = "passive"; phandle = <0x1c>; }; soc-crit { temperature = <0x1c138>; hysteresis = <0x7d0>; type = "critical"; phandle = <0x11d>; }; }; cooling-maps { map0 { trip = <0x1c>; cooling-device = <0x09 0xffffffff 0xffffffff>; contribution = <0x400>; }; map1 { trip = <0x1c>; cooling-device = <0x1d 0xffffffff 0xffffffff>; contribution = <0x400>; }; }; }; gpu-thermal { polling-delay-passive = <0x14>; polling-delay = <0x3e8>; thermal-sensors = <0x1b 0x01>; phandle = <0x11e>; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; arm,no-tick-in-suspend; }; external-gmac1-clock { compatible = "fixed-clock"; clock-frequency = <0x7735940>; clock-output-names = "gmac1_clkin"; #clock-cells = <0x00>; phandle = <0x6e>; }; xpcs-gmac1-clock { compatible = "fixed-clock"; clock-frequency = <0x7735940>; clock-output-names = "clk_gmac1_xpcs_mii"; #clock-cells = <0x00>; phandle = <0x11f>; }; i2s1-mclkin-rx { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0xbb8000>; clock-output-names = "i2s1_mclkin_rx"; phandle = <0x120>; }; i2s1-mclkin-tx { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0xbb8000>; clock-output-names = "i2s1_mclkin_tx"; phandle = <0x121>; }; i2s2-mclkin { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0xbb8000>; clock-output-names = "i2s2_mclkin"; phandle = <0x122>; }; i2s3-mclkin { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0xbb8000>; clock-output-names = "i2s3_mclkin"; phandle = <0x123>; }; mpll { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x2faf0800>; clock-output-names = "mpll"; phandle = <0x124>; }; xin24m { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <0x16e3600>; clock-output-names = "xin24m"; phandle = <0x125>; }; xin32k { compatible = "fixed-clock"; clock-frequency = <0x8000>; clock-output-names = "xin32k"; #clock-cells = <0x00>; pinctrl-names = "default"; pinctrl-0 = <0x1e>; phandle = <0x126>; }; scmi-shmem@10f000 { compatible = "arm,scmi-shmem"; reg = <0x00 0x10f000 0x00 0x100>; phandle = <0x1a>; }; sata@fc400000 { compatible = "snps,dwc-ahci"; reg = <0x00 0xfc400000 0x00 0x1000>; clocks = <0x1f 0x9b 0x1f 0x9c 0x1f 0x9d>; clock-names = "sata\0pmalive\0rxoob"; interrupts = <0x00 0x5f 0x04>; interrupt-names = "hostc"; phys = <0x20 0x01>; phy-names = "sata-phy"; ports-implemented = <0x01>; power-domains = <0x21 0x0f>; status = "disabled"; phandle = <0x127>; }; sata@fc800000 { compatible = "snps,dwc-ahci"; reg = <0x00 0xfc800000 0x00 0x1000>; clocks = <0x1f 0xa0 0x1f 0xa1 0x1f 0xa2>; clock-names = "sata\0pmalive\0rxoob"; interrupts = <0x00 0x60 0x04>; interrupt-names = "hostc"; phys = <0x22 0x01>; phy-names = "sata-phy"; ports-implemented = <0x01>; power-domains = <0x21 0x0f>; status = "okay"; phandle = <0x128>; }; usbdrd { compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3"; clocks = <0x1f 0xa6 0x1f 0xa7 0x1f 0xa5 0x1f 0x7f>; clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk"; #address-cells = <0x02>; #size-cells = <0x02>; ranges; status = "okay"; phandle = <0x129>; dwc3@fcc00000 { compatible = "snps,dwc3"; reg = <0x00 0xfcc00000 0x00 0x400000>; interrupts = <0x00 0xa9 0x04>; dr_mode = "otg"; phys = <0x23>; phy-names = "usb2-phy"; phy_type = "utmi_wide"; power-domains = <0x21 0x0f>; resets = <0x1f 0x94>; reset-names = "usb3-otg"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; snps,xhci-trb-ent-quirk; status = "okay"; extcon = <0x24>; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; phandle = <0x12a>; }; }; usbhost { compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3"; clocks = <0x1f 0xa9 0x1f 0xaa 0x1f 0xa8 0x1f 0x7f>; clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk"; #address-cells = <0x02>; #size-cells = <0x02>; ranges; status = "okay"; phandle = <0x12b>; dwc3@fd000000 { compatible = "snps,dwc3"; reg = <0x00 0xfd000000 0x00 0x400000>; interrupts = <0x00 0xaa 0x04>; dr_mode = "host"; phys = <0x25 0x20 0x04>; phy-names = "usb2-phy\0usb3-phy"; phy_type = "utmi_wide"; power-domains = <0x21 0x0f>; resets = <0x1f 0x95>; reset-names = "usb3-host"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; snps,xhci-trb-ent-quirk; status = "okay"; phandle = <0x12c>; }; }; interrupt-controller@fd400000 { compatible = "arm,gic-v3"; #interrupt-cells = <0x03>; #address-cells = <0x02>; #size-cells = <0x02>; ranges; interrupt-controller; reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>; interrupts = <0x01 0x09 0x04>; phandle = <0x01>; interrupt-controller@fd440000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <0x01>; reg = <0x00 0xfd440000 0x00 0x20000>; phandle = <0x91>; }; }; usb@fd800000 { compatible = "generic-ehci"; reg = <0x00 0xfd800000 0x00 0x40000>; interrupts = <0x00 0x82 0x04>; clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x26>; clock-names = "usbhost\0arbiter\0pclk\0utmi"; phys = <0x27>; phy-names = "usb2-phy"; status = "disabled"; phandle = <0x12d>; }; usb@fd840000 { compatible = "generic-ohci"; reg = <0x00 0xfd840000 0x00 0x40000>; interrupts = <0x00 0x83 0x04>; clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x26>; clock-names = "usbhost\0arbiter\0pclk\0utmi"; phys = <0x27>; phy-names = "usb2-phy"; status = "disabled"; phandle = <0x12e>; }; usb@fd880000 { compatible = "generic-ehci"; reg = <0x00 0xfd880000 0x00 0x40000>; interrupts = <0x00 0x85 0x04>; clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x26>; clock-names = "usbhost\0arbiter\0pclk\0utmi"; phys = <0x28>; phy-names = "usb2-phy"; status = "disabled"; phandle = <0x12f>; }; usb@fd8c0000 { compatible = "generic-ohci"; reg = <0x00 0xfd8c0000 0x00 0x40000>; interrupts = <0x00 0x86 0x04>; clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x26>; clock-names = "usbhost\0arbiter\0pclk\0utmi"; phys = <0x28>; phy-names = "usb2-phy"; status = "disabled"; phandle = <0x130>; }; syscon@fda00000 { compatible = "rockchip,rk3568-xpcs\0syscon"; reg = <0x00 0xfda00000 0x00 0x200000>; status = "disabled"; phandle = <0x131>; }; syscon@fdc20000 { compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; reg = <0x00 0xfdc20000 0x00 0x10000>; phandle = <0x30>; io-domains { compatible = "rockchip,rk3568-pmu-io-voltage-domain"; status = "okay"; pmuio2-supply = <0x29>; vccio1-supply = <0x29>; vccio3-supply = <0x29>; vccio4-supply = <0x2a>; vccio5-supply = <0x29>; vccio6-supply = <0x2a>; vccio7-supply = <0x29>; phandle = <0x132>; }; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x200>; mode-bootloader = <0x5242c301>; mode-charge = <0x5242c30b>; mode-fastboot = <0x5242c309>; mode-loader = <0x5242c301>; mode-normal = <0x5242c300>; mode-recovery = <0x5242c303>; mode-ums = <0x5242c30c>; mode-panic = <0x5242c307>; mode-watchdog = <0x5242c308>; phandle = <0x133>; }; }; syscon@fdc50000 { compatible = "rockchip,rk3568-pipegrf\0syscon"; reg = <0x00 0xfdc50000 0x00 0x1000>; phandle = <0xe2>; }; syscon@fdc60000 { compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; reg = <0x00 0xfdc60000 0x00 0x10000>; phandle = <0x2f>; io-domains { compatible = "rockchip,rk3568-io-voltage-domain"; status = "disabled"; phandle = <0x134>; }; lvds { compatible = "rockchip,rk3568-lvds"; phys = <0x2b>; phy-names = "phy"; status = "disabled"; phandle = <0x135>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; endpoint@1 { reg = <0x01>; remote-endpoint = <0x18>; status = "disabled"; phandle = <0x7f>; }; endpoint@2 { reg = <0x02>; remote-endpoint = <0x2c>; status = "disabled"; phandle = <0x80>; }; }; }; }; rgb { compatible = "rockchip,rk3568-rgb"; pinctrl-names = "default"; pinctrl-0 = <0x2d>; status = "disabled"; phandle = <0x136>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; endpoint@2 { reg = <0x02>; remote-endpoint = <0x19>; status = "disabled"; phandle = <0x81>; }; }; }; }; }; syscon@fdc70000 { compatible = "rockchip,pipe-phy-grf\0syscon"; reg = <0x00 0xfdc70000 0x00 0x1000>; phandle = <0x137>; }; syscon@fdc80000 { compatible = "rockchip,pipe-phy-grf\0syscon"; reg = <0x00 0xfdc80000 0x00 0x1000>; phandle = <0xe3>; }; syscon@fdc90000 { compatible = "rockchip,pipe-phy-grf\0syscon"; reg = <0x00 0xfdc90000 0x00 0x1000>; phandle = <0xe4>; }; syscon@fdca0000 { compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; reg = <0x00 0xfdca0000 0x00 0x8000>; phandle = <0xe9>; }; syscon@fdca8000 { compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; reg = <0x00 0xfdca8000 0x00 0x8000>; phandle = <0xec>; }; edp-phy@fdcb0000 { compatible = "rockchip,rk3568-edp-phy"; reg = <0x00 0xfdcb0000 0x00 0x8000>; clocks = <0x2e 0x29 0x1f 0x192>; clock-names = "refclk\0pclk"; resets = <0x1f 0x1d6>; reset-names = "apb"; #phy-cells = <0x00>; status = "disabled"; phandle = <0x8a>; }; sram@fdcc0000 { compatible = "mmio-sram"; reg = <0x00 0xfdcc0000 0x00 0xb000>; #address-cells = <0x01>; #size-cells = <0x01>; ranges = <0x00 0x00 0xfdcc0000 0xb000>; phandle = <0x138>; rkvdec-sram@0 { reg = <0x00 0xb000>; phandle = <0x62>; }; }; clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x00 0xfdd00000 0x00 0x1000>; rockchip,grf = <0x2f>; rockchip,pmugrf = <0x30>; #clock-cells = <0x01>; #reset-cells = <0x01>; assigned-clocks = <0x2e 0x32>; assigned-clock-parents = <0x2e 0x05>; phandle = <0x2e>; }; clock-controller@fdd20000 { compatible = "rockchip,rk3568-cru"; reg = <0x00 0xfdd20000 0x00 0x1000>; rockchip,grf = <0x2f>; #clock-cells = <0x01>; #reset-cells = <0x01>; assigned-clocks = <0x2e 0x05 0x1f 0x106 0x1f 0x10b 0x2e 0x01 0x2e 0x2b 0x1f 0x03 0x1f 0x19b 0x1f 0x09 0x1f 0x19c 0x1f 0x19d 0x1f 0x1a1 0x1f 0x19e 0x1f 0x19f 0x1f 0x1a0 0x1f 0x04 0x1f 0x10d 0x1f 0x10e 0x1f 0x173 0x1f 0x174 0x1f 0x175 0x1f 0x176 0x1f 0xc9 0x1f 0xca 0x1f 0x06 0x1f 0x7e 0x1f 0x7f 0x1f 0x3d 0x1f 0x41 0x1f 0x45 0x1f 0x49 0x1f 0x4d 0x1f 0x4d 0x1f 0x55 0x1f 0x51 0x1f 0x5d 0x1f 0xdd>; assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>; assigned-clock-parents = <0x2e 0x08 0x1f 0x04 0x1f 0x04>; phandle = <0x1f>; }; i2c@fdd40000 { compatible = "rockchip,rk3399-i2c"; reg = <0x00 0xfdd40000 0x00 0x1000>; clocks = <0x2e 0x07 0x2e 0x2d>; clock-names = "i2c\0pclk"; interrupts = <0x00 0x2e 0x04>; pinctrl-names = "default"; pinctrl-0 = <0x31>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x139>; }; serial@fdd50000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfdd50000 0x00 0x100>; interrupts = <0x00 0x74 0x04>; clocks = <0x2e 0x0b 0x2e 0x2c>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x00 0x32 0x01>; pinctrl-names = "default"; pinctrl-0 = <0x33>; status = "disabled"; phandle = <0x13a>; }; pwm@fdd70000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfdd70000 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0x34>; clocks = <0x2e 0x0d 0x2e 0x30>; clock-names = "pwm\0pclk"; status = "okay"; phandle = <0xfe>; }; pwm@fdd70010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfdd70010 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0x35>; clocks = <0x2e 0x0d 0x2e 0x30>; clock-names = "pwm\0pclk"; status = "okay"; phandle = <0xff>; }; pwm@fdd70020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfdd70020 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0x36>; clocks = <0x2e 0x0d 0x2e 0x30>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x13b>; }; pwm@fdd70030 { compatible = "rockchip,remotectl-pwm"; reg = <0x00 0xfdd70030 0x00 0x10>; interrupts = <0x00 0x52 0x04 0x00 0x56 0x04>; #pwm-cells = <0x03>; pinctrl-names = "default"; pinctrl-0 = <0x37>; clocks = <0x2e 0x0d 0x2e 0x30>; clock-names = "pwm\0pclk"; status = "okay"; remote_pwm_id = <0x03>; handle_cpu_id = <0x01>; remote_support_psci = <0x00>; phandle = <0x13c>; ir_key1 { rockchip,usercode = <0xfe01>; rockchip,key_table = <0xec 0xe8 0xe6 0x9e 0xe9 0x67 0xe5 0x6c 0xae 0x69 0xaf 0x6a 0xee 0x66 0xe7 0x73 0xef 0x72 0xbf 0x74 0xbe 0x75 0xb3 0x8b 0xbd 0x0e 0xbc 0xda 0xf0 0x8c 0xff 0x184 0xb1 0x02 0xf2 0x03 0xf3 0x04 0xb5 0x05 0xf6 0x06 0xf7 0x07 0xb9 0x08 0xfa 0x09 0xfb 0x0a 0xb4 0xb2 0xb0 0xb3 0xfd 0xb7 0xdb 0xb4 0xde 0xa9 0xf8 0xb6 0xda 0x1d2 0xfe 0x0b>; }; ir_key2 { rockchip,usercode = <0xfe02>; rockchip,key_table = <0xec 0xe8 0xe6 0x9e 0xe9 0x67 0xe5 0x6c 0xae 0x69 0xaf 0x6a 0xee 0x66 0xe7 0x73 0xef 0x72 0xbf 0x74 0xbe 0x75 0xff 0x8b 0xbd 0x0e 0xbc 0xda 0xf0 0x8c 0xb3 0x184 0xb1 0x02 0xf2 0x03 0xf3 0x04 0xb5 0x05 0xf6 0x06 0xf7 0x07 0xb9 0x08 0xfa 0x09 0xfb 0x0a 0xb4 0xb2 0xb0 0xb3 0xfd 0xb7 0xdb 0xb4 0xd9 0xb5 0xf8 0xb6 0xfe 0x0b>; }; ir_key3 { rockchip,usercode = <0x1608>; rockchip,key_table = <0x4d 0xe8 0x74 0x9e 0x7b 0x67 0x72 0x6c 0x44 0x69 0x71 0x6a 0xb0 0x66 0x76 0x73 0x4a 0x72 0x78 0x74 0xa4 0x71 0x99 0x3e 0xba 0x3f 0xb9 0x41 0x0a 0x42 0xb7 0x40 0xb5 0x0e>; }; }; power-management@fdd90000 { compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd"; reg = <0x00 0xfdd90000 0x00 0x1000>; phandle = <0x13d>; power-controller { compatible = "rockchip,rk3568-power-controller"; #power-domain-cells = <0x01>; #address-cells = <0x01>; #size-cells = <0x00>; status = "okay"; phandle = <0x21>; pd_npu@6 { reg = <0x06>; clocks = <0x1f 0x27 0x1f 0x25 0x1f 0x26>; pm_qos = <0x38>; }; pd_gpu@7 { reg = <0x07>; clocks = <0x1f 0x19 0x1f 0x1a>; pm_qos = <0x39>; }; pd_vi@8 { reg = <0x08>; clocks = <0x1f 0xcc 0x1f 0xcd>; pm_qos = <0x3a 0x3b 0x3c>; }; pd_vo@9 { reg = <0x09>; clocks = <0x1f 0xda 0x1f 0xdb 0x1f 0xdc>; pm_qos = <0x3d 0x3e 0x3f>; }; pd_rga@10 { reg = <0x0a>; clocks = <0x1f 0xf1 0x1f 0xf2>; pm_qos = <0x40 0x41 0x42 0x43 0x44 0x45>; }; pd_vpu@11 { reg = <0x0b>; clocks = <0x1f 0xed>; pm_qos = <0x46>; }; pd_rkvdec@13 { clocks = <0x1f 0x107>; reg = <0x0d>; pm_qos = <0x47>; }; pd_rkvenc@14 { reg = <0x0e>; clocks = <0x1f 0x102>; pm_qos = <0x48 0x49 0x4a>; }; pd_pipe@15 { reg = <0x0f>; clocks = <0x1f 0x7f>; pm_qos = <0x4b 0x4c 0x4d 0x4e 0x4f>; }; }; }; pvtm@fde00000 { compatible = "rockchip,rk3568-core-pvtm"; reg = <0x00 0xfde00000 0x00 0x100>; #address-cells = <0x01>; #size-cells = <0x00>; pvtm@0 { reg = <0x00>; clocks = <0x1f 0x13 0x1f 0x1c2>; clock-names = "clk\0pclk"; resets = <0x1f 0x1a 0x1f 0x19>; reset-names = "rts\0rst-p"; thermal-zone = "soc-thermal"; }; }; npu@fde40000 { compatible = "rockchip,rknpu"; reg = <0x00 0xfde40000 0x00 0x10000>; interrupts = <0x00 0x97 0x04>; clocks = <0x02 0x02 0x1f 0x23 0x1f 0x28 0x1f 0x29>; clock-names = "scmi_clk\0clk\0aclk\0hclk"; assigned-clocks = <0x1f 0x23>; assigned-clock-rates = <0x23c34600>; resets = <0x1f 0x2b 0x1f 0x2c>; reset-names = "srst_a\0srst_h"; power-domains = <0x21 0x06>; operating-points-v2 = <0x50>; iommus = <0x51>; status = "okay"; memory-region = <0x52>; rknpu-supply = <0x53>; phandle = <0x13e>; }; npu-opp-table { compatible = "operating-points-v2"; mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; nvmem-cells = <0x54 0x07 0x08>; nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; rockchip,temp-hysteresis = <0x1388>; rockchip,low-temp = <0x00>; rockchip,low-temp-adjust-volt = <0x00 0x2bc 0xc350>; phandle = <0x50>; opp-200000000 { opp-hz = <0x00 0xbebc200>; opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; }; opp-300000000 { opp-hz = <0x00 0x11b3dc40>; opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; }; opp-400000000 { opp-hz = <0x00 0x17d78400>; opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; }; opp-600000000 { opp-hz = <0x00 0x23c34600>; opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; }; opp-700000000 { opp-hz = <0x00 0x29b92700>; opp-microvolt = <0xcf850 0xcf850 0xf4240>; }; opp-800000000 { opp-hz = <0x00 0x2faf0800>; opp-microvolt = <0xd59f8 0xd59f8 0xf4240>; }; opp-900000000 { opp-hz = <0x00 0x35a4e900>; opp-microvolt = <0xe1d48 0xe1d48 0xf4240>; }; opp-1000000000 { opp-hz = <0x00 0x3b9aca00>; opp-microvolt = <0xf4240 0xf4240 0xf4240>; status = "disabled"; }; }; bus-npu { compatible = "rockchip,rk3568-bus"; rockchip,busfreq-policy = "clkfreq"; clocks = <0x02 0x02>; clock-names = "bus"; operating-points-v2 = <0x55>; status = "okay"; bus-supply = <0x56>; pvtm-supply = <0x05>; phandle = <0x13f>; }; bus-npu-opp-table { compatible = "operating-points-v2"; opp-shared; nvmem-cells = <0x07>; nvmem-cell-names = "pvtm"; rockchip,pvtm-voltage-sel = <0x00 0x14050 0x00 0x14051 0x16b48 0x01 0x16b49 0x186a0 0x02>; rockchip,pvtm-ch = <0x00 0x05>; phandle = <0x55>; opp-1000000000 { opp-hz = <0x00 0x3b9aca00>; opp-microvolt = <0xe7ef0>; opp-microvolt-L0 = <0xe7ef0>; opp-microvolt-L1 = <0xe1d48>; opp-microvolt-L2 = <0x00>; }; opp-900000000 { opp-hz = <0x00 0x35a4e900>; opp-microvolt = <0x00>; }; }; iommu@fde4b000 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfde4b000 0x00 0x40>; interrupts = <0x00 0x97 0x04>; interrupt-names = "rknpu_mmu"; clocks = <0x1f 0x28 0x1f 0x29>; clock-names = "aclk\0iface"; power-domains = <0x21 0x06>; #iommu-cells = <0x00>; status = "disabled"; phandle = <0x51>; }; gpu@fde60000 { compatible = "arm,mali-bifrost"; reg = <0x00 0xfde60000 0x00 0x4000>; interrupts = <0x00 0x27 0x04 0x00 0x29 0x04 0x00 0x28 0x04>; interrupt-names = "GPU\0MMU\0JOB"; upthreshold = <0x28>; downdifferential = <0x0a>; clocks = <0x02 0x01 0x1f 0x1b>; clock-names = "clk_mali\0clk_gpu"; power-domains = <0x21 0x07>; #cooling-cells = <0x02>; operating-points-v2 = <0x57>; status = "okay"; mali-supply = <0x53>; phandle = <0x1d>; power-model { compatible = "simple-power-model"; leakage-range = <0x05 0x0f>; ls = <0xffffa23e 0x5927 0x00>; static-coefficient = <0x186a0>; dynamic-coefficient = <0x3b9>; ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>; thermal-zone = "gpu-thermal"; phandle = <0x140>; }; }; opp-table2 { compatible = "operating-points-v2"; mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; nvmem-cells = <0x58 0x07 0x08>; nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; phandle = <0x57>; opp-200000000 { opp-hz = <0x00 0xbebc200>; opp-microvolt = <0xc96a8>; }; opp-300000000 { opp-hz = <0x00 0x11e1a300>; opp-microvolt = <0xc96a8>; }; opp-400000000 { opp-hz = <0x00 0x17d78400>; opp-microvolt = <0xc96a8>; }; opp-600000000 { opp-hz = <0x00 0x23c34600>; opp-microvolt = <0xc96a8>; }; opp-700000000 { opp-hz = <0x00 0x29b92700>; opp-microvolt = <0xdbba0>; }; }; pvtm@fde80000 { compatible = "rockchip,rk3568-gpu-pvtm"; reg = <0x00 0xfde80000 0x00 0x100>; #address-cells = <0x01>; #size-cells = <0x00>; pvtm@1 { reg = <0x01>; clocks = <0x1f 0x1e 0x1f 0x1d>; clock-names = "clk\0pclk"; resets = <0x1f 0x24 0x1f 0x23>; reset-names = "rts\0rst-p"; thermal-zone = "gpu-thermal"; }; }; pvtm@fde90000 { compatible = "rockchip,rk3568-npu-pvtm"; reg = <0x00 0xfde90000 0x00 0x100>; #address-cells = <0x01>; #size-cells = <0x00>; pvtm@2 { reg = <0x02>; clocks = <0x1f 0x2b 0x1f 0x2a 0x1f 0x25>; clock-names = "clk\0pclk\0hclk"; resets = <0x1f 0x2e 0x1f 0x2d>; reset-names = "rts\0rst-p"; thermal-zone = "soc-thermal"; }; }; vdpu@fdea0400 { compatible = "rockchip,vpu-decoder-v2"; reg = <0x00 0xfdea0400 0x00 0x400>; interrupts = <0x00 0x8b 0x04>; interrupt-names = "irq_dec"; clocks = <0x1f 0xee 0x1f 0xef>; clock-names = "aclk_vcodec\0hclk_vcodec"; resets = <0x1f 0x11a 0x1f 0x11b>; reset-names = "video_a\0video_h"; iommus = <0x59>; power-domains = <0x21 0x0b>; rockchip,srv = <0x5a>; rockchip,taskqueue-node = <0x00>; rockchip,resetgroup-node = <0x00>; status = "okay"; phandle = <0x141>; }; iommu@fdea0800 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfdea0800 0x00 0x40>; interrupts = <0x00 0x8a 0x04>; interrupt-names = "vdpu_mmu"; clock-names = "aclk\0iface"; clocks = <0x1f 0xee 0x1f 0xef>; power-domains = <0x21 0x0b>; #iommu-cells = <0x00>; status = "okay"; phandle = <0x59>; }; rk_rga@fdeb0000 { compatible = "rockchip,rga2"; reg = <0x00 0xfdeb0000 0x00 0x1000>; interrupts = <0x00 0x5a 0x04>; clocks = <0x1f 0xf3 0x1f 0xf4 0x1f 0xf5>; clock-names = "aclk_rga\0hclk_rga\0clk_rga"; power-domains = <0x21 0x0a>; status = "okay"; phandle = <0x142>; }; ebc@fdec0000 { compatible = "rockchip,rk3568-ebc-tcon"; reg = <0x00 0xfdec0000 0x00 0x5000>; interrupts = <0x00 0x11 0x04>; clocks = <0x1f 0xf9 0x1f 0xfa>; clock-names = "hclk\0dclk"; power-domains = <0x21 0x0a>; rockchip,grf = <0x2f>; pinctrl-names = "default"; pinctrl-0 = <0x5b>; status = "disabled"; phandle = <0x143>; }; jpegd@fded0000 { compatible = "rockchip,rkv-jpeg-decoder-v1"; reg = <0x00 0xfded0000 0x00 0x400>; interrupts = <0x00 0x3e 0x04>; clocks = <0x1f 0xfb 0x1f 0xfc>; clock-names = "aclk_vcodec\0hclk_vcodec"; rockchip,disable-auto-freq; resets = <0x1f 0x12c 0x1f 0x12d>; reset-names = "video_a\0video_h"; iommus = <0x5c>; rockchip,srv = <0x5a>; rockchip,taskqueue-node = <0x01>; rockchip,resetgroup-node = <0x01>; power-domains = <0x21 0x0a>; status = "okay"; phandle = <0x144>; }; iommu@fded0480 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfded0480 0x00 0x40>; interrupts = <0x00 0x3d 0x04>; interrupt-names = "jpegd_mmu"; clock-names = "aclk\0iface"; clocks = <0x1f 0xfb 0x1f 0xfc>; power-domains = <0x21 0x0a>; #iommu-cells = <0x00>; status = "okay"; phandle = <0x5c>; }; vepu@fdee0000 { compatible = "rockchip,vpu-encoder-v2"; reg = <0x00 0xfdee0000 0x00 0x400>; interrupts = <0x00 0x40 0x04>; clocks = <0x1f 0xfd 0x1f 0xfe>; clock-names = "aclk_vcodec\0hclk_vcodec"; rockchip,disable-auto-freq; resets = <0x1f 0x12e 0x1f 0x12f>; reset-names = "video_a\0video_h"; iommus = <0x5d>; rockchip,srv = <0x5a>; rockchip,taskqueue-node = <0x02>; rockchip,resetgroup-node = <0x02>; power-domains = <0x21 0x0a>; status = "okay"; phandle = <0x145>; }; iommu@fdee0800 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfdee0800 0x00 0x40>; interrupts = <0x00 0x3f 0x04>; interrupt-names = "vepu_mmu"; clock-names = "aclk\0iface"; clocks = <0x1f 0xfd 0x1f 0xfe>; power-domains = <0x21 0x0a>; #iommu-cells = <0x00>; status = "okay"; phandle = <0x5d>; }; iep@fdef0000 { compatible = "rockchip,iep-v2"; reg = <0x00 0xfdef0000 0x00 0x500>; interrupts = <0x00 0x38 0x04>; clocks = <0x1f 0xf6 0x1f 0xf7 0x1f 0xf8>; clock-names = "aclk\0hclk\0sclk"; resets = <0x1f 0x127 0x1f 0x128 0x1f 0x129>; reset-names = "rst_a\0rst_h\0rst_s"; power-domains = <0x21 0x0a>; rockchip,srv = <0x5a>; rockchip,taskqueue-node = <0x05>; rockchip,resetgroup-node = <0x05>; iommus = <0x5e>; status = "okay"; phandle = <0x146>; }; iommu@fdef0800 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfdef0800 0x00 0x100>; interrupts = <0x00 0x38 0x04>; interrupt-names = "iep_mmu"; clocks = <0x1f 0xf6 0x1f 0xf7>; clock-names = "aclk\0iface"; #iommu-cells = <0x00>; power-domains = <0x21 0x0a>; status = "okay"; phandle = <0x5e>; }; eink@fdf00000 { compatible = "rockchip,rk3568-eink-tcon"; reg = <0x00 0xfdf00000 0x00 0x74>; interrupts = <0x00 0xb2 0x04>; clocks = <0x1f 0xff 0x1f 0x100>; clock-names = "pclk\0hclk"; status = "disabled"; phandle = <0x147>; }; rkvenc@fdf40000 { compatible = "rockchip,rkv-encoder-v1"; reg = <0x00 0xfdf40000 0x00 0x400>; interrupts = <0x00 0x8c 0x04>; interrupt-names = "irq_enc"; clocks = <0x1f 0x103 0x1f 0x104 0x1f 0x105>; clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40>; resets = <0x1f 0x133 0x1f 0x134 0x1f 0x135>; reset-names = "video_a\0video_h\0video_core"; assigned-clocks = <0x1f 0x103 0x1f 0x105>; assigned-clock-rates = <0x11b3dc40 0x11b3dc40>; iommus = <0x5f>; node-name = "rkvenc"; rockchip,srv = <0x5a>; rockchip,taskqueue-node = <0x03>; rockchip,resetgroup-node = <0x03>; power-domains = <0x21 0x0e>; operating-points-v2 = <0x60>; status = "okay"; phandle = <0x148>; }; rkvenc-opp-table { compatible = "operating-points-v2"; nvmem-cells = <0x07>; nvmem-cell-names = "pvtm"; rockchip,pvtm-voltage-sel = <0x00 0x14050 0x00 0x14051 0x16b48 0x01 0x16b49 0x186a0 0x02>; rockchip,pvtm-ch = <0x00 0x05>; phandle = <0x60>; opp-297000000 { opp-hz = <0x00 0x11b3dc40>; opp-microvolt = <0x00>; }; opp-400000000 { opp-hz = <0x00 0x17d78400>; opp-microvolt = <0xe7ef0>; opp-microvolt-L0 = <0xe7ef0>; opp-microvolt-L1 = <0xe1d48>; opp-microvolt-L2 = <0x00>; }; }; iommu@fdf40f00 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfdf40f00 0x00 0x40 0x00 0xfdf40f40 0x00 0x40>; interrupts = <0x00 0x8d 0x04 0x00 0x8e 0x04>; interrupt-names = "rkvenc_mmu0\0rkvenc_mmu1"; clocks = <0x1f 0x103 0x1f 0x104>; clock-names = "aclk\0iface"; rockchip,disable-mmu-reset; rockchip,enable-cmd-retry; #iommu-cells = <0x00>; power-domains = <0x21 0x0e>; status = "okay"; phandle = <0x5f>; }; rkvdec@fdf80200 { compatible = "rockchip,rkv-decoder-v2"; reg = <0x00 0xfdf80200 0x00 0x400>; interrupts = <0x00 0x5b 0x04>; interrupt-names = "irq_dec"; clocks = <0x1f 0x108 0x1f 0x109 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>; clock-names = "aclk_vcodec\0hclk_vcodec\0clk_cabac\0clk_core\0clk_hevc_cabac"; rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40 0x11b3dc40 0x23c34600>; rockchip,advanced-rates = <0x179a7b00 0x00 0x179a7b00 0x179a7b00 0x23c34600>; rockchip,default-max-load = <0x1fe000>; resets = <0x1f 0x142 0x1f 0x143 0x1f 0x144 0x1f 0x145 0x1f 0x146>; assigned-clocks = <0x1f 0x108 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>; assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>; reset-names = "video_a\0video_h\0video_cabac\0video_core\0video_hevc_cabac"; power-domains = <0x21 0x0d>; iommus = <0x61>; rockchip,srv = <0x5a>; rockchip,taskqueue-node = <0x04>; rockchip,resetgroup-node = <0x04>; rockchip,sram = <0x62>; rockchip,rcb-iova = <0x10000000 0x10000>; rockchip,rcb-min-width = <0x200>; status = "okay"; phandle = <0x149>; }; iommu@fdf80800 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfdf80800 0x00 0x40 0x00 0xfdf80840 0x00 0x40>; interrupts = <0x00 0x5c 0x04>; interrupt-names = "rkvdec_mmu"; clocks = <0x1f 0x108 0x1f 0x109>; clock-names = "aclk\0iface"; power-domains = <0x21 0x0d>; #iommu-cells = <0x00>; status = "okay"; phandle = <0x61>; }; mipi-csi2@fdfb0000 { compatible = "rockchip,rk3568-mipi-csi2"; reg = <0x00 0xfdfb0000 0x00 0x10000>; reg-names = "csihost_regs"; interrupts = <0x00 0x08 0x04 0x00 0x09 0x04>; interrupt-names = "csi-intr1\0csi-intr2"; clocks = <0x1f 0xd5>; clock-names = "pclk_csi2host"; resets = <0x1f 0xff>; reset-names = "srst_csihost_p"; status = "disabled"; phandle = <0x14a>; }; rkcif@fdfe0000 { compatible = "rockchip,rk3568-cif"; reg = <0x00 0xfdfe0000 0x00 0x8000>; reg-names = "cif_regs"; interrupts = <0x00 0x92 0x04>; interrupt-names = "cif-intr"; clocks = <0x1f 0xce 0x1f 0xcf 0x1f 0xd0 0x1f 0xd1>; clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_cif_g"; resets = <0x1f 0xf7 0x1f 0xf8 0x1f 0xf9 0x1f 0xfb 0x1f 0xfa>; reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_p\0rst_cif_i"; assigned-clocks = <0x1f 0xd0>; assigned-clock-rates = <0x11e1a300>; power-domains = <0x21 0x08>; rockchip,grf = <0x2f>; iommus = <0x63>; status = "disabled"; phandle = <0x64>; }; iommu@fdfe0800 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfdfe0800 0x00 0x100>; interrupts = <0x00 0x92 0x04>; interrupt-names = "cif_mmu"; clocks = <0x1f 0xce 0x1f 0xcf>; clock-names = "aclk\0iface"; power-domains = <0x21 0x08>; rockchip,disable-mmu-reset; #iommu-cells = <0x00>; status = "disabled"; phandle = <0x63>; }; rkcif_dvp { compatible = "rockchip,rkcif-dvp"; rockchip,hw = <0x64>; status = "disabled"; phandle = <0x65>; }; rkcif_dvp_sditf { compatible = "rockchip,rkcif-sditf"; rockchip,cif = <0x65>; status = "disabled"; phandle = <0x14b>; }; rkcif_mipi_lvds { compatible = "rockchip,rkcif-mipi-lvds"; rockchip,hw = <0x64>; status = "disabled"; phandle = <0x66>; }; rkcif_mipi_lvds_sditf { compatible = "rockchip,rkcif-sditf"; rockchip,cif = <0x66>; status = "disabled"; phandle = <0x14c>; }; rkisp@fdff0000 { compatible = "rockchip,rk3568-rkisp"; reg = <0x00 0xfdff0000 0x00 0x10000>; interrupts = <0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3c 0x04>; interrupt-names = "mipi_irq\0mi_irq\0isp_irq"; clocks = <0x1f 0xd2 0x1f 0xd3 0x1f 0xd4>; clock-names = "aclk_isp\0hclk_isp\0clk_isp"; resets = <0x1f 0xfd 0x1f 0xfc>; reset-names = "isp\0isp-h"; rockchip,grf = <0x2f>; power-domains = <0x21 0x08>; iommus = <0x67>; rockchip,iq-feature = <0x3fb 0xf7fe67ff>; status = "okay"; phandle = <0x68>; }; iommu@fdff1a00 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfdff1a00 0x00 0x100>; interrupts = <0x00 0x3b 0x04>; interrupt-names = "isp_mmu"; clocks = <0x1f 0xd2 0x1f 0xd3>; clock-names = "aclk\0iface"; power-domains = <0x21 0x08>; #iommu-cells = <0x00>; rockchip,disable-mmu-reset; status = "okay"; phandle = <0x67>; }; rkisp-vir0 { compatible = "rockchip,rkisp-vir"; rockchip,hw = <0x68>; status = "okay"; phandle = <0x14d>; port { #address-cells = <0x01>; #size-cells = <0x00>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x69>; phandle = <0xe8>; }; }; }; rkisp-vir1 { compatible = "rockchip,rkisp-vir"; rockchip,hw = <0x68>; status = "disabled"; phandle = <0x14e>; }; ethernet@fe010000 { compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; reg = <0x00 0xfe010000 0x00 0x10000>; interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>; interrupt-names = "macirq\0eth_wake_irq"; rockchip,grf = <0x2f>; clocks = <0x1f 0x186 0x1f 0x189 0x1f 0x189 0x1f 0xc7 0x1f 0xc3 0x1f 0xc4 0x1f 0x189 0x1f 0xc8 0x1f 0xac>; clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs"; resets = <0x1f 0xec>; reset-names = "stmmaceth"; snps,mixed-burst; snps,tso; snps,axi-config = <0x6a>; snps,mtl-rx-config = <0x6b>; snps,mtl-tx-config = <0x6c>; status = "okay"; phy-mode = "rgmii"; clock_in_out = "input"; snps,reset-gpio = <0x6d 0x12 0x01>; snps,reset-active-low; snps,reset-delays-us = <0x00 0x4e20 0x186a0>; assigned-clocks = <0x1f 0x189 0x1f 0x186>; assigned-clock-parents = <0x1f 0x187 0x6e>; pinctrl-names = "default"; pinctrl-0 = <0x6f 0x70 0x71 0x72 0x73 0x74>; tx_delay = <0x4f>; rx_delay = <0x2d>; phy-handle = <0x75>; phandle = <0x14f>; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x150>; phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x00>; phandle = <0x75>; }; }; stmmac-axi-config { snps,wr_osr_lmt = <0x04>; snps,rd_osr_lmt = <0x08>; snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; phandle = <0x6a>; }; rx-queues-config { snps,rx-queues-to-use = <0x01>; phandle = <0x6b>; queue0 { }; }; tx-queues-config { snps,tx-queues-to-use = <0x01>; phandle = <0x6c>; queue0 { }; }; }; vop@fe040000 { compatible = "rockchip,rk3568-vop"; reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>; reg-names = "regs\0gamma_lut"; rockchip,grf = <0x2f>; interrupts = <0x00 0x94 0x04>; clocks = <0x1f 0xdd 0x1f 0xde 0x1f 0xdf 0x1f 0xe0 0x1f 0xe1>; clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2"; iommus = <0x76>; power-domains = <0x21 0x09>; status = "okay"; assigned-clocks = <0x1f 0xe0>; assigned-clock-parents = <0x1f 0x05>; support-multi-area; phandle = <0x151>; ports { #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x12>; port@0 { #address-cells = <0x01>; #size-cells = <0x00>; reg = <0x00>; phandle = <0x152>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x77>; phandle = <0x14>; }; endpoint@1 { reg = <0x01>; remote-endpoint = <0x78>; phandle = <0x15>; }; endpoint@2 { reg = <0x02>; remote-endpoint = <0x79>; phandle = <0x16>; }; endpoint@3 { reg = <0x03>; remote-endpoint = <0x7a>; phandle = <0x17>; }; }; port@1 { #address-cells = <0x01>; #size-cells = <0x00>; reg = <0x01>; phandle = <0x153>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x7b>; phandle = <0x83>; }; endpoint@1 { reg = <0x01>; remote-endpoint = <0x7c>; phandle = <0x85>; }; endpoint@2 { reg = <0x02>; remote-endpoint = <0x7d>; phandle = <0x8b>; }; endpoint@3 { reg = <0x03>; remote-endpoint = <0x7e>; phandle = <0x89>; }; endpoint@4 { reg = <0x04>; remote-endpoint = <0x7f>; phandle = <0x18>; }; }; port@2 { #address-cells = <0x01>; #size-cells = <0x00>; reg = <0x02>; phandle = <0x154>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x80>; phandle = <0x2c>; }; endpoint@1 { reg = <0x01>; remote-endpoint = <0x81>; phandle = <0x19>; }; }; }; }; iommu@fe043e00 { compatible = "rockchip,iommu-v2"; reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>; interrupts = <0x00 0x94 0x04>; interrupt-names = "vop_mmu"; clocks = <0x1f 0xdd 0x1f 0xde>; clock-names = "aclk\0iface"; #iommu-cells = <0x00>; status = "okay"; phandle = <0x76>; }; dsi@fe060000 { compatible = "rockchip,rk3568-mipi-dsi"; reg = <0x00 0xfe060000 0x00 0x10000>; interrupts = <0x00 0x44 0x04>; clocks = <0x1f 0xe8 0x1f 0xda 0x82>; clock-names = "pclk\0hclk\0hs_clk"; resets = <0x1f 0x110>; reset-names = "apb"; phys = <0x82>; phy-names = "mipi_dphy"; power-domains = <0x21 0x09>; rockchip,grf = <0x2f>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x155>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x156>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x14>; status = "disabled"; phandle = <0x77>; }; endpoint@1 { reg = <0x01>; remote-endpoint = <0x83>; status = "disabled"; phandle = <0x7b>; }; }; }; }; dsi@fe070000 { compatible = "rockchip,rk3568-mipi-dsi"; reg = <0x00 0xfe070000 0x00 0x10000>; interrupts = <0x00 0x45 0x04>; clocks = <0x1f 0xe9 0x1f 0xda 0x84>; clock-names = "pclk\0hclk\0hs_clk"; resets = <0x1f 0x111>; reset-names = "apb"; phys = <0x84>; phy-names = "mipi_dphy"; power-domains = <0x21 0x09>; rockchip,grf = <0x2f>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x157>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x158>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x15>; status = "disabled"; phandle = <0x78>; }; endpoint@1 { reg = <0x01>; remote-endpoint = <0x85>; status = "disabled"; phandle = <0x7c>; }; }; }; }; hdmi@fe0a0000 { compatible = "rockchip,rk3568-dw-hdmi"; reg = <0x00 0xfe0a0000 0x00 0x20000>; interrupts = <0x00 0x2d 0x04>; clocks = <0x1f 0xe6 0x1f 0xe7 0x1f 0x193 0x2e 0x02 0x1f 0xde>; clock-names = "iahb\0isfr\0cec\0ref\0hclk"; power-domains = <0x21 0x09>; reg-io-width = <0x04>; rockchip,grf = <0x2f>; #sound-dai-cells = <0x00>; pinctrl-names = "default"; pinctrl-0 = <0x86 0x87 0x88>; status = "okay"; rockchip,phy-table = <0x58834d4 0x8009 0x00 0x270 0x9d5b340 0x800b 0x00 0x26d 0xb1069a8 0x800b 0x00 0x1ed 0x11b3dc40 0x800b 0x00 0x1ad 0x2367b880 0x8029 0x00 0x88 0x00 0x00 0x00 0x00>; phandle = <0xf9>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x159>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x17>; status = "okay"; phandle = <0x7a>; }; endpoint@1 { reg = <0x01>; remote-endpoint = <0x89>; status = "disabled"; phandle = <0x7e>; }; }; }; }; edp@fe0c0000 { compatible = "rockchip,rk3568-edp"; reg = <0x00 0xfe0c0000 0x00 0x10000>; interrupts = <0x00 0x12 0x04>; clocks = <0x2e 0x29 0x1f 0xea 0x1f 0xeb 0x1f 0xda>; clock-names = "dp\0pclk\0spdif\0hclk"; resets = <0x1f 0x113 0x1f 0x112>; reset-names = "dp\0apb"; phys = <0x8a>; phy-names = "dp"; power-domains = <0x21 0x09>; status = "disabled"; phandle = <0x15a>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x15b>; endpoint@0 { reg = <0x00>; remote-endpoint = <0x16>; status = "disabled"; phandle = <0x79>; }; endpoint@1 { reg = <0x01>; remote-endpoint = <0x8b>; status = "disabled"; phandle = <0x7d>; }; }; }; }; qos@fe128000 { compatible = "syscon"; reg = <0x00 0xfe128000 0x00 0x20>; phandle = <0x39>; }; qos@fe138080 { compatible = "syscon"; reg = <0x00 0xfe138080 0x00 0x20>; phandle = <0x48>; }; qos@fe138100 { compatible = "syscon"; reg = <0x00 0xfe138100 0x00 0x20>; phandle = <0x49>; }; qos@fe138180 { compatible = "syscon"; reg = <0x00 0xfe138180 0x00 0x20>; phandle = <0x4a>; }; qos@fe148000 { compatible = "syscon"; reg = <0x00 0xfe148000 0x00 0x20>; phandle = <0x3a>; }; qos@fe148080 { compatible = "syscon"; reg = <0x00 0xfe148080 0x00 0x20>; phandle = <0x3b>; }; qos@fe148100 { compatible = "syscon"; reg = <0x00 0xfe148100 0x00 0x20>; phandle = <0x3c>; }; qos@fe150000 { compatible = "syscon"; reg = <0x00 0xfe150000 0x00 0x20>; phandle = <0x46>; }; qos@fe158000 { compatible = "syscon"; reg = <0x00 0xfe158000 0x00 0x20>; phandle = <0x40>; }; qos@fe158100 { compatible = "syscon"; reg = <0x00 0xfe158100 0x00 0x20>; phandle = <0x41>; }; qos@fe158180 { compatible = "syscon"; reg = <0x00 0xfe158180 0x00 0x20>; phandle = <0x42>; }; qos@fe158200 { compatible = "syscon"; reg = <0x00 0xfe158200 0x00 0x20>; phandle = <0x43>; }; qos@fe158280 { compatible = "syscon"; reg = <0x00 0xfe158280 0x00 0x20>; phandle = <0x44>; }; qos@fe158300 { compatible = "syscon"; reg = <0x00 0xfe158300 0x00 0x20>; phandle = <0x45>; }; qos@fe180000 { compatible = "syscon"; reg = <0x00 0xfe180000 0x00 0x20>; phandle = <0x38>; }; qos@fe190000 { compatible = "syscon"; reg = <0x00 0xfe190000 0x00 0x20>; phandle = <0x4b>; }; qos@fe190280 { compatible = "syscon"; reg = <0x00 0xfe190280 0x00 0x20>; phandle = <0x4c>; }; qos@fe190300 { compatible = "syscon"; reg = <0x00 0xfe190300 0x00 0x20>; phandle = <0x4d>; }; qos@fe190380 { compatible = "syscon"; reg = <0x00 0xfe190380 0x00 0x20>; phandle = <0x4e>; }; qos@fe190400 { compatible = "syscon"; reg = <0x00 0xfe190400 0x00 0x20>; phandle = <0x4f>; }; qos@fe198000 { compatible = "syscon"; reg = <0x00 0xfe198000 0x00 0x20>; phandle = <0x47>; }; qos@fe1a8000 { compatible = "syscon"; reg = <0x00 0xfe1a8000 0x00 0x20>; phandle = <0x3d>; }; qos@fe1a8080 { compatible = "syscon"; reg = <0x00 0xfe1a8080 0x00 0x20>; phandle = <0x3e>; }; qos@fe1a8100 { compatible = "syscon"; reg = <0x00 0xfe1a8100 0x00 0x20>; phandle = <0x3f>; }; dwmmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; reg = <0x00 0xfe000000 0x00 0x4000>; interrupts = <0x00 0x64 0x04>; max-frequency = <0x8f0d180>; clocks = <0x1f 0xc1 0x1f 0xc2 0x1f 0x18e 0x1f 0x18f>; clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; fifo-depth = <0x100>; resets = <0x1f 0xeb>; reset-names = "reset"; status = "disabled"; phandle = <0x15c>; }; dfi@fe230000 { reg = <0x00 0xfe230000 0x00 0x400>; compatible = "rockchip,rk3568-dfi"; rockchip,pmugrf = <0x30>; status = "okay"; phandle = <0x8c>; }; dmc { compatible = "rockchip,rk3568-dmc"; interrupts = <0x00 0x0a 0x04>; interrupt-names = "complete"; devfreq-events = <0x8c>; clocks = <0x1f 0x1a2>; clock-names = "dmc_clk"; operating-points-v2 = <0x8d>; ddr_timing = <0x8e>; vop-bw-dmc-freq = <0x00 0x1f9 0x4f1a0 0x1fa 0x1869f 0x80e80>; upthreshold = <0x28>; downdifferential = <0x14>; system-status-freq = <0x01 0xbe6e0 0x08 0x101d00 0x02 0x4f1a0 0x10 0xbe6e0 0x10000 0xbe6e0 0x1000 0x101d00 0x4000 0x101d00 0x2000 0x101d00 0xc00 0x101d00>; auto-min-freq = <0x4f1a0>; auto-freq-en = <0x00>; #cooling-cells = <0x02>; status = "okay"; center-supply = <0x53>; phandle = <0x13>; }; dmc-opp-table { compatible = "operating-points-v2"; mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; nvmem-cells = <0x8f 0x07 0x08>; nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; rockchip,temp-hysteresis = <0x1388>; rockchip,low-temp = <0x00>; rockchip,low-temp-adjust-volt = <0x00 0x618 0x61a8>; rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>; phandle = <0x8d>; opp-324000000 { opp-hz = <0x00 0x134fd900>; opp-microvolt = <0xdbba0>; opp-microvolt-L0 = <0xdbba0>; opp-microvolt-L1 = <0xcf850>; }; opp-528000000 { opp-hz = <0x00 0x1f78a400>; opp-microvolt = <0xdbba0>; opp-microvolt-L0 = <0xdbba0>; opp-microvolt-L1 = <0xcf850>; }; opp-780000000 { opp-hz = <0x00 0x2e7ddb00>; opp-microvolt = <0xdbba0>; opp-microvolt-L0 = <0xdbba0>; opp-microvolt-L1 = <0xcf850>; }; opp-920000000 { opp-hz = <0x00 0x36d61600>; opp-microvolt = <0xdbba0>; opp-microvolt-L0 = <0xdbba0>; opp-microvolt-L1 = <0xcf850>; status = "disabled"; }; opp-1056000000 { opp-hz = <0x00 0x3ef14800>; opp-microvolt = <0xdbba0>; opp-microvolt-L0 = <0xdbba0>; opp-microvolt-L1 = <0xcf850>; }; }; pcie@fe260000 { compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; #address-cells = <0x03>; #size-cells = <0x02>; bus-range = <0x00 0x0f>; clocks = <0x1f 0x81 0x1f 0x82 0x1f 0x83 0x1f 0x84 0x1f 0x85>; clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; device_type = "pci"; interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>; interrupt-names = "sys\0pmc\0msg\0legacy\0err"; #interrupt-cells = <0x01>; interrupt-map-mask = <0x00 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x90 0x00 0x00 0x00 0x00 0x02 0x90 0x01 0x00 0x00 0x00 0x03 0x90 0x02 0x00 0x00 0x00 0x04 0x90 0x03>; linux,pci-domain = <0x00>; num-ib-windows = <0x06>; num-ob-windows = <0x02>; max-link-speed = <0x02>; msi-map = <0x00 0x91 0x00 0x1000>; num-lanes = <0x01>; phys = <0x22 0x02>; phy-names = "pcie-phy"; power-domains = <0x21 0x0f>; ranges = <0x800 0x00 0x00 0x03 0x00 0x00 0x800000 0x81000000 0x00 0x800000 0x03 0x800000 0x00 0x100000 0x83000000 0x00 0x900000 0x03 0x900000 0x00 0x3f700000>; reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000>; reg-names = "pcie-dbi\0pcie-apb"; resets = <0x1f 0xa1>; reset-names = "pipe"; status = "disabled"; phandle = <0x15d>; legacy-interrupt-controller { interrupt-controller; #address-cells = <0x00>; #interrupt-cells = <0x01>; interrupt-parent = <0x01>; interrupts = <0x00 0x48 0x01>; phandle = <0x90>; }; }; dwmmc@fe2b0000 { compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; reg = <0x00 0xfe2b0000 0x00 0x4000>; interrupts = <0x00 0x62 0x04>; max-frequency = <0x2faf080>; clocks = <0x1f 0xb0 0x1f 0xb1 0x1f 0x18a 0x1f 0x18b>; clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; fifo-depth = <0x100>; resets = <0x1f 0xd4>; reset-names = "reset"; status = "okay"; supports-sd; bus-width = <0x04>; cap-mmc-highspeed; cap-sd-highspeed; disable-wp; vmmc-supply = <0x92>; pinctrl-names = "default"; pinctrl-0 = <0x93 0x94 0x95 0x96>; phandle = <0x15e>; }; dwmmc@fe2c0000 { compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; reg = <0x00 0xfe2c0000 0x00 0x4000>; interrupts = <0x00 0x63 0x04>; max-frequency = <0x2faf080>; clocks = <0x1f 0xb2 0x1f 0xb3 0x1f 0x18c 0x1f 0x18d>; clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; fifo-depth = <0x100>; resets = <0x1f 0xd6>; reset-names = "reset"; status = "okay"; supports-sdio; bus-width = <0x04>; disable-wp; cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; non-removable; mmc-pwrseq = <0x97>; pinctrl-names = "default"; pinctrl-0 = <0x98 0x99 0x9a>; sd-uhs-sdr104; phandle = <0x15f>; }; sfc@fe300000 { compatible = "rockchip,sfc"; reg = <0x00 0xfe300000 0x00 0x4000>; interrupts = <0x00 0x65 0x04>; clocks = <0x1f 0x78 0x1f 0x76>; clock-names = "clk_sfc\0hclk_sfc"; assigned-clocks = <0x1f 0x78>; assigned-clock-rates = <0x5f5e100>; status = "okay"; phandle = <0x160>; }; sdhci@fe310000 { compatible = "rockchip,dwcmshc-sdhci\0snps,dwcmshc-sdhci"; reg = <0x00 0xfe310000 0x00 0x10000>; interrupts = <0x00 0x13 0x04>; assigned-clocks = <0x1f 0x7b 0x1f 0x7d>; assigned-clock-rates = <0xbebc200 0x16e3600>; clocks = <0x1f 0x7c 0x1f 0x7a 0x1f 0x79 0x1f 0x7b 0x1f 0x7d>; clock-names = "core\0bus\0axi\0block\0timer"; status = "okay"; bus-width = <0x08>; supports-emmc; non-removable; phandle = <0x161>; }; nandc@fe330000 { compatible = "rockchip,rk-nandc-v9"; reg = <0x00 0xfe330000 0x00 0x4000>; interrupts = <0x00 0x46 0x04>; nandc_id = <0x00>; clocks = <0x1f 0x75 0x1f 0x74>; clock-names = "clk_nandc\0hclk_nandc"; status = "disabled"; phandle = <0x162>; }; crypto@fe380000 { compatible = "rockchip,rk3568-crypto"; reg = <0x00 0xfe380000 0x00 0x4000>; interrupts = <0x00 0x04 0x04>; clocks = <0x1f 0x6a 0x1f 0x6b 0x1f 0x6c 0x1f 0x6d>; clock-names = "aclk\0hclk\0sclk\0apb_pclk"; assigned-clocks = <0x1f 0x6c>; assigned-clock-rates = <0xbebc200>; resets = <0x1f 0x69>; reset-names = "crypto-rst"; status = "disabled"; phandle = <0x163>; }; rng@fe388000 { compatible = "rockchip,cryptov2-rng"; reg = <0x00 0xfe388000 0x00 0x2000>; clocks = <0x1f 0x70 0x1f 0x6f>; clock-names = "clk_trng\0hclk_trng"; resets = <0x1f 0x6d>; reset-names = "reset"; status = "okay"; phandle = <0x164>; }; otp@fe38c000 { compatible = "rockchip,rk3568-otp"; reg = <0x00 0xfe38c000 0x00 0x4000>; #address-cells = <0x01>; #size-cells = <0x01>; clocks = <0x1f 0x73 0x1f 0x72 0x1f 0x71 0x1f 0x181>; clock-names = "usr\0sbpi\0apb\0phy"; resets = <0x1f 0x1cf>; reset-names = "otp_phy"; phandle = <0x165>; cpu-code@2 { reg = <0x02 0x02>; phandle = <0x0f>; }; cpu-version@8 { reg = <0x08 0x01>; bits = <0x03 0x03>; phandle = <0x0e>; }; mbist-vmin@9 { reg = <0x09 0x01>; bits = <0x00 0x04>; phandle = <0x08>; }; id@a { reg = <0x0a 0x10>; phandle = <0x0d>; }; cpu-leakage@1a { reg = <0x1a 0x01>; phandle = <0x06>; }; log-leakage@1b { reg = <0x1b 0x01>; phandle = <0x8f>; }; npu-leakage@1c { reg = <0x1c 0x01>; phandle = <0x54>; }; gpu-leakage@1d { reg = <0x1d 0x01>; phandle = <0x58>; }; core-pvtm@2a { reg = <0x2a 0x02>; phandle = <0x07>; }; }; i2s@fe400000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe400000 0x00 0x1000>; interrupts = <0x00 0x34 0x04>; clocks = <0x1f 0x3f 0x1f 0x43 0x1f 0x39>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x9b 0x00>; dma-names = "tx"; resets = <0x1f 0x50 0x1f 0x51>; reset-names = "tx-m\0rx-m"; rockchip,cru = <0x1f>; rockchip,grf = <0x2f>; rockchip,playback-only; #sound-dai-cells = <0x00>; status = "okay"; phandle = <0xf8>; }; i2s@fe410000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe410000 0x00 0x1000>; interrupts = <0x00 0x35 0x04>; clocks = <0x1f 0x47 0x1f 0x4b 0x1f 0x3a>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x9b 0x02 0x9b 0x03>; dma-names = "tx\0rx"; resets = <0x1f 0x52 0x1f 0x53>; reset-names = "tx-m\0rx-m"; rockchip,cru = <0x1f>; rockchip,grf = <0x2f>; #sound-dai-cells = <0x00>; pinctrl-names = "default"; pinctrl-0 = <0x9c 0x9d 0x9e 0x9f>; status = "okay"; rockchip,clk-trcm = <0x01>; phandle = <0x166>; }; i2s@fe420000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe420000 0x00 0x1000>; interrupts = <0x00 0x36 0x04>; clocks = <0x1f 0x4f 0x1f 0x4f 0x1f 0x3b>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x9b 0x04 0x9b 0x05>; dma-names = "tx\0rx"; rockchip,cru = <0x1f>; rockchip,grf = <0x2f>; rockchip,clk-trcm = <0x01>; #sound-dai-cells = <0x00>; pinctrl-names = "default"; pinctrl-0 = <0xa0 0xa1 0xa2 0xa3>; status = "disabled"; phandle = <0x167>; }; i2s@fe430000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe430000 0x00 0x1000>; interrupts = <0x00 0x37 0x04>; clocks = <0x1f 0x53 0x1f 0x57 0x1f 0x3c>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x9b 0x06 0x9b 0x07>; dma-names = "tx\0rx"; resets = <0x1f 0x55 0x1f 0x56>; reset-names = "tx-m\0rx-m"; rockchip,cru = <0x1f>; rockchip,grf = <0x2f>; rockchip,clk-trcm = <0x01>; #sound-dai-cells = <0x00>; pinctrl-names = "default"; pinctrl-0 = <0xa4 0xa5 0xa6 0xa7>; status = "disabled"; phandle = <0x168>; }; pdm@fe440000 { compatible = "rockchip,rk3568-pdm\0rockchip,pdm"; reg = <0x00 0xfe440000 0x00 0x1000>; clocks = <0x1f 0x5a 0x1f 0x59>; clock-names = "pdm_clk\0pdm_hclk"; dmas = <0x9b 0x09>; dma-names = "rx"; pinctrl-names = "default"; pinctrl-0 = <0xa8 0xa9 0xaa 0xab 0xac 0xad>; #sound-dai-cells = <0x00>; status = "disabled"; phandle = <0x169>; }; vad@fe450000 { compatible = "rockchip,rk3568-vad"; reg = <0x00 0xfe450000 0x00 0x10000>; reg-names = "vad"; clocks = <0x1f 0x5b>; clock-names = "hclk"; interrupts = <0x00 0x89 0x04>; rockchip,audio-src = <0x00>; rockchip,det-channel = <0x00>; rockchip,mode = <0x00>; #sound-dai-cells = <0x00>; status = "disabled"; phandle = <0x16a>; }; spdif@fe460000 { compatible = "rockchip,rk3568-spdif"; reg = <0x00 0xfe460000 0x00 0x1000>; interrupts = <0x00 0x66 0x04>; dmas = <0x9b 0x01>; dma-names = "tx"; clock-names = "mclk\0hclk"; clocks = <0x1f 0x5f 0x1f 0x5c>; #sound-dai-cells = <0x00>; pinctrl-names = "default"; pinctrl-0 = <0xae>; status = "okay"; phandle = <0xfa>; }; audpwm@fe470000 { compatible = "rockchip,rk3568-audio-pwm\0rockchip,audio-pwm-v1"; reg = <0x00 0xfe470000 0x00 0x1000>; clocks = <0x1f 0x63 0x1f 0x60>; clock-names = "clk\0hclk"; dmas = <0x9b 0x08>; dma-names = "tx"; #sound-dai-cells = <0x00>; rockchip,sample-width-bits = <0x0b>; rockchip,interpolat-points = <0x01>; status = "disabled"; phandle = <0x16b>; }; codec-digital@fe478000 { compatible = "rockchip,rk3568-codec-digital\0rockchip,codec-digital-v1"; reg = <0x00 0xfe478000 0x00 0x1000>; clocks = <0x1f 0x67 0x1f 0x66 0x1f 0x65 0x1f 0x64>; clock-names = "adc\0dac\0i2c\0pclk"; pinctrl-names = "default"; pinctrl-0 = <0xaf>; resets = <0x1f 0x5f>; reset-names = "reset"; rockchip,grf = <0x2f>; #sound-dai-cells = <0x00>; status = "disabled"; phandle = <0x16c>; }; dmac@fe530000 { compatible = "arm,pl330\0arm,primecell"; reg = <0x00 0xfe530000 0x00 0x4000>; interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04>; clocks = <0x1f 0x10d>; clock-names = "apb_pclk"; #dma-cells = <0x01>; arm,pl330-periph-burst; phandle = <0x32>; }; dmac@fe550000 { compatible = "arm,pl330\0arm,primecell"; reg = <0x00 0xfe550000 0x00 0x4000>; interrupts = <0x00 0x10 0x04 0x00 0x0f 0x04>; clocks = <0x1f 0x10d>; clock-names = "apb_pclk"; #dma-cells = <0x01>; arm,pl330-periph-burst; phandle = <0x9b>; }; rkscr@fe560000 { compatible = "rockchip-scr"; reg = <0x00 0xfe560000 0x00 0x10000>; interrupts = <0x00 0x61 0x04>; pinctrl-names = "default"; pinctrl-0 = <0xb0>; clocks = <0x1f 0x114>; clock-names = "g_pclk_sim_card"; status = "disabled"; phandle = <0x16d>; }; can@fe570000 { compatible = "rockchip,canfd-1.0"; reg = <0x00 0xfe570000 0x00 0x1000>; interrupts = <0x00 0x01 0x04>; clocks = <0x1f 0x141 0x1f 0x140>; clock-names = "baudclk\0apb_pclk"; resets = <0x1f 0x155 0x1f 0x154>; reset-names = "can\0can-apb"; tx-fifo-depth = <0x01>; rx-fifo-depth = <0x06>; status = "disabled"; phandle = <0x16e>; }; can@fe580000 { compatible = "rockchip,canfd-1.0"; reg = <0x00 0xfe580000 0x00 0x1000>; interrupts = <0x00 0x02 0x04>; clocks = <0x1f 0x143 0x1f 0x142>; clock-names = "baudclk\0apb_pclk"; resets = <0x1f 0x157 0x1f 0x156>; reset-names = "can\0can-apb"; tx-fifo-depth = <0x01>; rx-fifo-depth = <0x06>; status = "disabled"; phandle = <0x16f>; }; can@fe590000 { compatible = "rockchip,canfd-1.0"; reg = <0x00 0xfe590000 0x00 0x1000>; interrupts = <0x00 0x03 0x04>; clocks = <0x1f 0x145 0x1f 0x144>; clock-names = "baudclk\0apb_pclk"; resets = <0x1f 0x159 0x1f 0x158>; reset-names = "can\0can-apb"; tx-fifo-depth = <0x01>; rx-fifo-depth = <0x06>; status = "disabled"; phandle = <0x170>; }; i2c@fe5a0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x00 0xfe5a0000 0x00 0x1000>; clocks = <0x1f 0x148 0x1f 0x147>; clock-names = "i2c\0pclk"; interrupts = <0x00 0x2f 0x04>; pinctrl-names = "default"; pinctrl-0 = <0xb1>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x171>; }; i2c@fe5b0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x00 0xfe5b0000 0x00 0x1000>; clocks = <0x1f 0x14a 0x1f 0x149>; clock-names = "i2c\0pclk"; interrupts = <0x00 0x30 0x04>; pinctrl-names = "default"; pinctrl-0 = <0xb2>; #address-cells = <0x01>; #size-cells = <0x00>; status = "okay"; phandle = <0x172>; gc8034@37 { status = "okay"; compatible = "galaxycore,gc8034"; reg = <0x37>; clocks = <0x1f 0xd6>; clock-names = "xvclk"; power-domains = <0x21 0x08>; pinctrl-names = "default"; pinctrl-0 = <0xb3>; reset-gpios = <0xb4 0x1d 0x01>; pwdn-gpios = <0x6d 0x0a 0x01>; rockchip,camera-module-index = <0x00>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "RK-CMK-8M-2-v1"; rockchip,camera-module-lens-name = "CK8401"; phandle = <0x173>; port { endpoint { remote-endpoint = <0xb5>; data-lanes = <0x01 0x02 0x03 0x04>; phandle = <0xe7>; }; }; }; gc4c33@29 { status = "okay"; compatible = "galaxycore,gc4c33"; reg = <0x29>; clocks = <0x1f 0xd6>; clock-names = "xvclk"; power-domains = <0x21 0x08>; pinctrl-names = "default"; pinctrl-0 = <0xb3>; reset-gpios = <0xb4 0x1d 0x00>; pwdn-gpios = <0x6d 0x0a 0x00>; rockchip,camera-module-index = <0x00>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "PCORW0009A"; rockchip,camera-module-lens-name = "40IRC-4M"; phandle = <0x174>; port { endpoint { remote-endpoint = <0xb6>; data-lanes = <0x01 0x02>; phandle = <0xe6>; }; }; }; }; i2c@fe5c0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x00 0xfe5c0000 0x00 0x1000>; clocks = <0x1f 0x14c 0x1f 0x14b>; clock-names = "i2c\0pclk"; interrupts = <0x00 0x31 0x04>; pinctrl-names = "default"; pinctrl-0 = <0xb7>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x175>; }; i2c@fe5d0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x00 0xfe5d0000 0x00 0x1000>; clocks = <0x1f 0x14e 0x1f 0x14d>; clock-names = "i2c\0pclk"; interrupts = <0x00 0x32 0x04>; pinctrl-names = "default"; pinctrl-0 = <0xb8>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x176>; }; i2c@fe5e0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x00 0xfe5e0000 0x00 0x1000>; clocks = <0x1f 0x150 0x1f 0x14f>; clock-names = "i2c\0pclk"; interrupts = <0x00 0x33 0x04>; pinctrl-names = "default"; pinctrl-0 = <0xb9>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x177>; }; timer@fe5f0000 { compatible = "rockchip,rk3568-timer\0rockchip,rk3288-timer"; reg = <0x00 0xfe5f0000 0x00 0x1000>; interrupts = <0x00 0x6d 0x04>; clocks = <0x1f 0x16c 0x1f 0x16d>; clock-names = "pclk\0timer"; phandle = <0x178>; }; watchdog@fe600000 { compatible = "snps,dw-wdt"; reg = <0x00 0xfe600000 0x00 0x100>; clocks = <0x1f 0x116 0x1f 0x115>; clock-names = "tclk\0pclk"; interrupts = <0x00 0x95 0x04>; status = "okay"; phandle = <0x179>; }; spi@fe610000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe610000 0x00 0x1000>; interrupts = <0x00 0x67 0x04>; #address-cells = <0x01>; #size-cells = <0x00>; clocks = <0x1f 0x152 0x1f 0x151>; clock-names = "spiclk\0apb_pclk"; dmas = <0x32 0x14 0x32 0x15>; dma-names = "tx\0rx"; pinctrl-names = "default\0high_speed"; pinctrl-0 = <0xba 0xbb 0xbc>; pinctrl-1 = <0xba 0xbb 0xbd>; status = "disabled"; phandle = <0x17a>; }; spi@fe620000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe620000 0x00 0x1000>; interrupts = <0x00 0x68 0x04>; #address-cells = <0x01>; #size-cells = <0x00>; clocks = <0x1f 0x154 0x1f 0x153>; clock-names = "spiclk\0apb_pclk"; dmas = <0x32 0x16 0x32 0x17>; dma-names = "tx\0rx"; pinctrl-names = "default\0high_speed"; pinctrl-0 = <0xbe 0xbf 0xc0>; pinctrl-1 = <0xbe 0xbf 0xc1>; status = "disabled"; phandle = <0x17b>; }; spi@fe630000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe630000 0x00 0x1000>; interrupts = <0x00 0x69 0x04>; #address-cells = <0x01>; #size-cells = <0x00>; clocks = <0x1f 0x156 0x1f 0x155>; clock-names = "spiclk\0apb_pclk"; dmas = <0x32 0x18 0x32 0x19>; dma-names = "tx\0rx"; pinctrl-names = "default\0high_speed"; pinctrl-0 = <0xc2 0xc3 0xc4>; pinctrl-1 = <0xc2 0xc3 0xc5>; status = "disabled"; phandle = <0x17c>; }; spi@fe640000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe640000 0x00 0x1000>; interrupts = <0x00 0x6a 0x04>; #address-cells = <0x01>; #size-cells = <0x00>; clocks = <0x1f 0x158 0x1f 0x157>; clock-names = "spiclk\0apb_pclk"; dmas = <0x32 0x1a 0x32 0x1b>; dma-names = "tx\0rx"; pinctrl-names = "default\0high_speed"; pinctrl-0 = <0xc6 0xc7 0xc8>; pinctrl-1 = <0xc6 0xc7 0xc9>; status = "disabled"; phandle = <0x17d>; }; serial@fe650000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe650000 0x00 0x100>; interrupts = <0x00 0x75 0x04>; clocks = <0x1f 0x11f 0x1f 0x11c>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x02 0x32 0x03>; pinctrl-names = "default"; pinctrl-0 = <0xca 0xcb>; status = "okay"; phandle = <0x17e>; }; serial@fe660000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe660000 0x00 0x100>; interrupts = <0x00 0x76 0x04>; clocks = <0x1f 0x123 0x1f 0x120>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x04 0x32 0x05>; pinctrl-names = "default"; pinctrl-0 = <0xcc>; status = "disabled"; phandle = <0x17f>; }; serial@fe670000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe670000 0x00 0x100>; interrupts = <0x00 0x77 0x04>; clocks = <0x1f 0x127 0x1f 0x124>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x06 0x32 0x07>; pinctrl-names = "default"; pinctrl-0 = <0xcd>; status = "disabled"; phandle = <0x180>; }; serial@fe680000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe680000 0x00 0x100>; interrupts = <0x00 0x78 0x04>; clocks = <0x1f 0x12b 0x1f 0x128>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x08 0x32 0x09>; pinctrl-names = "default"; pinctrl-0 = <0xce>; status = "disabled"; phandle = <0x181>; }; serial@fe690000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe690000 0x00 0x100>; interrupts = <0x00 0x79 0x04>; clocks = <0x1f 0x12f 0x1f 0x12c>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x0a 0x32 0x0b>; pinctrl-names = "default"; pinctrl-0 = <0xcf>; status = "disabled"; phandle = <0x182>; }; serial@fe6a0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6a0000 0x00 0x100>; interrupts = <0x00 0x7a 0x04>; clocks = <0x1f 0x133 0x1f 0x130>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x0c 0x32 0x0d>; pinctrl-names = "default"; pinctrl-0 = <0xd0>; status = "disabled"; phandle = <0x183>; }; serial@fe6b0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6b0000 0x00 0x100>; interrupts = <0x00 0x7b 0x04>; clocks = <0x1f 0x137 0x1f 0x134>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x0e 0x32 0x0f>; pinctrl-names = "default"; pinctrl-0 = <0xd1>; status = "disabled"; phandle = <0x184>; }; serial@fe6c0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6c0000 0x00 0x100>; interrupts = <0x00 0x7c 0x04>; clocks = <0x1f 0x13b 0x1f 0x138>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x10 0x32 0x11>; pinctrl-names = "default"; pinctrl-0 = <0xd2>; status = "disabled"; phandle = <0x185>; }; serial@fe6d0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6d0000 0x00 0x100>; interrupts = <0x00 0x7d 0x04>; clocks = <0x1f 0x13f 0x1f 0x13c>; clock-names = "baudclk\0apb_pclk"; reg-shift = <0x02>; reg-io-width = <0x04>; dmas = <0x32 0x12 0x32 0x13>; pinctrl-names = "default"; pinctrl-0 = <0xd3>; status = "disabled"; phandle = <0x186>; }; pwm@fe6e0000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0000 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xd4>; clocks = <0x1f 0x15a 0x1f 0x159>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x187>; }; pwm@fe6e0010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0010 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xd5>; clocks = <0x1f 0x15a 0x1f 0x159>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x188>; }; pwm@fe6e0020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0020 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xd6>; clocks = <0x1f 0x15a 0x1f 0x159>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x189>; }; pwm@fe6e0030 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0030 0x00 0x10>; interrupts = <0x00 0x53 0x04 0x00 0x57 0x04>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xd7>; clocks = <0x1f 0x15a 0x1f 0x159>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x18a>; }; pwm@fe6f0000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0000 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xd8>; clocks = <0x1f 0x15d 0x1f 0x15c>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x18b>; }; pwm@fe6f0010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0010 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xd9>; clocks = <0x1f 0x15d 0x1f 0x15c>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x18c>; }; pwm@fe6f0020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0020 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xda>; clocks = <0x1f 0x15d 0x1f 0x15c>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x18d>; }; pwm@fe6f0030 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0030 0x00 0x10>; interrupts = <0x00 0x54 0x04 0x00 0x58 0x04>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xdb>; clocks = <0x1f 0x15d 0x1f 0x15c>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x18e>; }; pwm@fe700000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700000 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xdc>; clocks = <0x1f 0x160 0x1f 0x15f>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x18f>; }; pwm@fe700010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700010 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xdd>; clocks = <0x1f 0x160 0x1f 0x15f>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x190>; }; pwm@fe700020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700020 0x00 0x10>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xde>; clocks = <0x1f 0x160 0x1f 0x15f>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x191>; }; pwm@fe700030 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700030 0x00 0x10>; interrupts = <0x00 0x55 0x04 0x00 0x59 0x04>; #pwm-cells = <0x03>; pinctrl-names = "active"; pinctrl-0 = <0xdf>; clocks = <0x1f 0x160 0x1f 0x15f>; clock-names = "pwm\0pclk"; status = "disabled"; phandle = <0x192>; }; tsadc@fe710000 { compatible = "rockchip,rk3568-tsadc"; reg = <0x00 0xfe710000 0x00 0x100>; interrupts = <0x00 0x73 0x04>; rockchip,grf = <0x2f>; clocks = <0x1f 0x111 0x1f 0x10f>; clock-names = "tsadc\0apb_pclk"; assigned-clocks = <0x1f 0x110 0x1f 0x111>; assigned-clock-rates = <0x1036640 0xaae60>; resets = <0x1f 0x182 0x1f 0x181 0x1f 0x1d7>; reset-names = "tsadc\0tsadc-apb\0tsadc-phy"; #thermal-sensor-cells = <0x01>; rockchip,hw-tshut-temp = <0x1d4c0>; rockchip,hw-tshut-mode = <0x00>; rockchip,hw-tshut-polarity = <0x00>; pinctrl-names = "gpio\0otpout"; pinctrl-0 = <0xe0>; pinctrl-1 = <0xe1>; status = "okay"; phandle = <0x1b>; }; saradc@fe720000 { compatible = "rockchip,rk3568-saradc\0rockchip,rk3399-saradc"; reg = <0x00 0xfe720000 0x00 0x100>; interrupts = <0x00 0x5d 0x04>; #io-channel-cells = <0x01>; clocks = <0x1f 0x113 0x1f 0x112>; clock-names = "saradc\0apb_pclk"; resets = <0x1f 0x180>; reset-names = "saradc-apb"; status = "okay"; vref-supply = <0x2a>; phandle = <0xf7>; }; mailbox@fe780000 { compatible = "rockchip,rk3568-mailbox\0rockchip,rk3368-mailbox"; reg = <0x00 0xfe780000 0x00 0x1000>; interrupts = <0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04>; clocks = <0x1f 0x11b>; clock-names = "pclk_mailbox"; #mbox-cells = <0x01>; status = "disabled"; phandle = <0x193>; }; phy@fe830000 { compatible = "rockchip,rk3568-naneng-combphy"; reg = <0x00 0xfe830000 0x00 0x100>; #phy-cells = <0x01>; clocks = <0x2e 0x22 0x1f 0x17d 0x1f 0x7f>; clock-names = "refclk\0apbclk\0pipe_clk"; assigned-clocks = <0x2e 0x22>; assigned-clock-rates = <0x5f5e100>; resets = <0x1f 0x1c6 0x1f 0x1c7>; reset-names = "combphy-apb\0combphy"; rockchip,pipe-grf = <0xe2>; rockchip,pipe-phy-grf = <0xe3>; status = "okay"; phandle = <0x20>; }; phy@fe840000 { compatible = "rockchip,rk3568-naneng-combphy"; reg = <0x00 0xfe840000 0x00 0x100>; #phy-cells = <0x01>; clocks = <0x2e 0x25 0x1f 0x17e 0x1f 0x7f>; clock-names = "refclk\0apbclk\0pipe_clk"; assigned-clocks = <0x2e 0x25>; assigned-clock-rates = <0x5f5e100>; resets = <0x1f 0x1c8 0x1f 0x1c9>; reset-names = "combphy-apb\0combphy"; rockchip,pipe-grf = <0xe2>; rockchip,pipe-phy-grf = <0xe4>; status = "okay"; phandle = <0x22>; }; mipi-dphy@fe850000 { compatible = "rockchip,rk3568-mipi-dphy"; reg = <0x00 0xfe850000 0x00 0x10000>; clocks = <0x2e 0x17 0x1f 0x17a>; clock-names = "ref\0pclk"; clock-output-names = "mipi_dphy_pll"; #clock-cells = <0x00>; resets = <0x1f 0x1bb>; reset-names = "apb"; power-domains = <0x21 0x09>; #phy-cells = <0x00>; rockchip,grf = <0x2f>; status = "okay"; phandle = <0x82>; }; video-phy@fe850000 { compatible = "rockchip,rk3568-video-phy"; reg = <0x00 0xfe850000 0x00 0x10000 0x00 0xfe060000 0x00 0x10000>; clocks = <0x2e 0x17 0x1f 0x17a 0x1f 0xe8>; clock-names = "ref\0pclk_phy\0pclk_host"; #clock-cells = <0x00>; resets = <0x1f 0x1bb>; reset-names = "rst"; power-domains = <0x21 0x09>; #phy-cells = <0x00>; status = "disabled"; phandle = <0x2b>; }; mipi-dphy@fe860000 { compatible = "rockchip,rk3568-mipi-dphy"; reg = <0x00 0xfe860000 0x00 0x10000>; clocks = <0x2e 0x19 0x1f 0x17b>; clock-names = "ref\0pclk"; clock-output-names = "mipi_dphy1_pll"; #clock-cells = <0x00>; resets = <0x1f 0x1bc>; reset-names = "apb"; power-domains = <0x21 0x09>; #phy-cells = <0x00>; rockchip,grf = <0x2f>; status = "okay"; phandle = <0x84>; }; csi2-dphy-hw@fe870000 { compatible = "rockchip,rk3568-csi2-dphy-hw"; reg = <0x00 0xfe870000 0x00 0x1000>; clocks = <0x1f 0x179>; clock-names = "pclk"; rockchip,grf = <0x2f>; status = "okay"; phandle = <0xe5>; }; csi2-dphy0 { compatible = "rockchip,rk3568-csi2-dphy"; rockchip,hw = <0xe5>; status = "okay"; phandle = <0x194>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; endpoint@1 { reg = <0x01>; remote-endpoint = <0xe6>; data-lanes = <0x01 0x02>; phandle = <0xb6>; }; endpoint@2 { reg = <0x02>; remote-endpoint = <0xe7>; data-lanes = <0x01 0x02 0x03 0x04>; phandle = <0xb5>; }; }; port@1 { reg = <0x01>; #address-cells = <0x01>; #size-cells = <0x00>; endpoint@1 { reg = <0x01>; remote-endpoint = <0xe8>; phandle = <0x69>; }; }; }; }; csi2-dphy1 { compatible = "rockchip,rk3568-csi2-dphy"; rockchip,hw = <0xe5>; status = "disabled"; phandle = <0x195>; }; csi2-dphy2 { compatible = "rockchip,rk3568-csi2-dphy"; rockchip,hw = <0xe5>; status = "disabled"; phandle = <0x196>; }; usb2-phy@fe8a0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x00 0xfe8a0000 0x00 0x10000>; interrupts = <0x00 0x87 0x04>; clocks = <0x2e 0x13>; clock-names = "phyclk"; #clock-cells = <0x00>; assigned-clocks = <0x1f 0x0b>; assigned-clock-parents = <0x24>; clock-output-names = "usb480m_phy"; rockchip,usbgrf = <0xe9>; status = "okay"; phandle = <0x24>; host-port { #phy-cells = <0x00>; status = "okay"; phy-supply = <0xea>; phandle = <0x25>; }; otg-port { #phy-cells = <0x00>; status = "okay"; vbus-supply = <0xeb>; phandle = <0x23>; }; }; usb2-phy@fe8b0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x00 0xfe8b0000 0x00 0x10000>; interrupts = <0x00 0x88 0x04>; clocks = <0x2e 0x15>; clock-names = "phyclk"; #clock-cells = <0x00>; rockchip,usbgrf = <0xec>; status = "disabled"; phandle = <0x26>; host-port { #phy-cells = <0x00>; status = "disabled"; phy-supply = <0xea>; phandle = <0x28>; }; otg-port { #phy-cells = <0x00>; status = "disabled"; phy-supply = <0xea>; phandle = <0x27>; }; }; pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <0x2f>; rockchip,pmu = <0x30>; #address-cells = <0x02>; #size-cells = <0x02>; ranges; phandle = <0xed>; gpio@fdd60000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfdd60000 0x00 0x100>; interrupts = <0x00 0x21 0x04>; clocks = <0x2e 0x2e 0x2e 0x0c>; gpio-controller; #gpio-cells = <0x02>; gpio-ranges = <0xed 0x00 0x00 0x20>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x100>; }; gpio@fe740000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe740000 0x00 0x100>; interrupts = <0x00 0x22 0x04>; clocks = <0x1f 0x163 0x1f 0x164>; gpio-controller; #gpio-cells = <0x02>; gpio-ranges = <0xed 0x00 0x20 0x20>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x10b>; }; gpio@fe750000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe750000 0x00 0x100>; interrupts = <0x00 0x23 0x04>; clocks = <0x1f 0x165 0x1f 0x166>; gpio-controller; #gpio-cells = <0x02>; gpio-ranges = <0xed 0x00 0x40 0x20>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x104>; }; gpio@fe760000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe760000 0x00 0x100>; interrupts = <0x00 0x24 0x04>; clocks = <0x1f 0x167 0x1f 0x168>; gpio-controller; #gpio-cells = <0x02>; gpio-ranges = <0xed 0x00 0x60 0x20>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0xb4>; }; gpio@fe770000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe770000 0x00 0x100>; interrupts = <0x00 0x25 0x04>; clocks = <0x1f 0x169 0x1f 0x16a>; gpio-controller; #gpio-cells = <0x02>; gpio-ranges = <0xed 0x00 0x80 0x20>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x6d>; }; pcfg-pull-up { bias-pull-up; phandle = <0xf0>; }; pcfg-pull-down { bias-pull-down; phandle = <0xf6>; }; pcfg-pull-none { bias-disable; phandle = <0xee>; }; pcfg-pull-none-drv-level-1 { bias-disable; drive-strength = <0x01>; phandle = <0xf2>; }; pcfg-pull-none-drv-level-2 { bias-disable; drive-strength = <0x02>; phandle = <0xf1>; }; pcfg-pull-none-drv-level-3 { bias-disable; drive-strength = <0x03>; phandle = <0xf5>; }; pcfg-pull-up-drv-level-1 { bias-pull-up; drive-strength = <0x01>; phandle = <0xf4>; }; pcfg-pull-up-drv-level-2 { bias-pull-up; drive-strength = <0x02>; phandle = <0xef>; }; pcfg-pull-none-smt { bias-disable; input-schmitt-enable; phandle = <0xf3>; }; acodec { acodec-pins { rockchip,pins = <0x01 0x09 0x05 0xee 0x01 0x01 0x05 0xee 0x01 0x00 0x05 0xee 0x01 0x07 0x05 0xee 0x01 0x08 0x05 0xee 0x01 0x03 0x05 0xee 0x01 0x05 0x05 0xee>; phandle = <0xaf>; }; }; cam { camera-pwr { rockchip,pins = <0x00 0x15 0x00 0xee>; phandle = <0x107>; }; }; cif { cif-clk { rockchip,pins = <0x04 0x10 0x01 0xee>; phandle = <0xb3>; }; }; clk32k { clk32k-out0 { rockchip,pins = <0x00 0x08 0x02 0xee>; phandle = <0x1e>; }; }; ebc { ebc-pins { rockchip,pins = <0x04 0x10 0x02 0xee 0x04 0x0b 0x02 0xee 0x04 0x0c 0x02 0xee 0x04 0x06 0x02 0xee 0x04 0x11 0x02 0xee 0x03 0x16 0x02 0xee 0x03 0x17 0x02 0xee 0x03 0x18 0x02 0xee 0x03 0x19 0x02 0xee 0x03 0x1a 0x02 0xee 0x03 0x1b 0x02 0xee 0x03 0x1c 0x02 0xee 0x03 0x1d 0x02 0xee 0x03 0x1e 0x02 0xee 0x03 0x1f 0x02 0xee 0x04 0x00 0x02 0xee 0x04 0x01 0x02 0xee 0x04 0x02 0x02 0xee 0x04 0x03 0x02 0xee 0x04 0x04 0x02 0xee 0x04 0x05 0x02 0xee 0x04 0x0e 0x02 0xee 0x04 0x0f 0x02 0xee>; phandle = <0x5b>; }; }; gmac1 { gmac1m1-miim { rockchip,pins = <0x04 0x0e 0x03 0xee 0x04 0x0f 0x03 0xee>; phandle = <0x6f>; }; gmac1m1-clkinout { rockchip,pins = <0x04 0x11 0x03 0xee>; phandle = <0x74>; }; gmac1m1-rx-bus2 { rockchip,pins = <0x04 0x07 0x03 0xee 0x04 0x08 0x03 0xee 0x04 0x09 0x03 0xee>; phandle = <0x71>; }; gmac1m1-tx-bus2 { rockchip,pins = <0x04 0x04 0x03 0xf1 0x04 0x05 0x03 0xf1 0x04 0x06 0x03 0xee>; phandle = <0x70>; }; gmac1m1-rgmii-clk { rockchip,pins = <0x04 0x03 0x03 0xee 0x04 0x00 0x03 0xf2>; phandle = <0x72>; }; gmac1m1-rgmii-bus { rockchip,pins = <0x04 0x01 0x03 0xee 0x04 0x02 0x03 0xee 0x03 0x1e 0x03 0xf1 0x03 0x1f 0x03 0xf1>; phandle = <0x73>; }; }; hdmitx { hdmitxm0-cec { rockchip,pins = <0x04 0x19 0x01 0xee>; phandle = <0x88>; }; hdmitx-scl { rockchip,pins = <0x04 0x17 0x01 0xee>; phandle = <0x86>; }; hdmitx-sda { rockchip,pins = <0x04 0x18 0x01 0xee>; phandle = <0x87>; }; }; i2c0 { i2c0-xfer { rockchip,pins = <0x00 0x09 0x01 0xf3 0x00 0x0a 0x01 0xf3>; phandle = <0x31>; }; }; i2c1 { i2c1-xfer { rockchip,pins = <0x00 0x0b 0x01 0xf3 0x00 0x0c 0x01 0xf3>; phandle = <0xb1>; }; }; i2c2 { i2c2m1-xfer { rockchip,pins = <0x04 0x0d 0x01 0xf3 0x04 0x0c 0x01 0xf3>; phandle = <0xb2>; }; }; i2c3 { i2c3m0-xfer { rockchip,pins = <0x01 0x01 0x01 0xf3 0x01 0x00 0x01 0xf3>; phandle = <0xb7>; }; }; i2c4 { i2c4m0-xfer { rockchip,pins = <0x04 0x0b 0x01 0xf3 0x04 0x0a 0x01 0xf3>; phandle = <0xb8>; }; }; i2c5 { i2c5m0-xfer { rockchip,pins = <0x03 0x0b 0x04 0xf3 0x03 0x0c 0x04 0xf3>; phandle = <0xb9>; }; }; i2s1 { i2s1m0-lrcktx { rockchip,pins = <0x01 0x05 0x01 0xee>; phandle = <0x9d>; }; i2s1m0-sclktx { rockchip,pins = <0x01 0x03 0x01 0xee>; phandle = <0x9c>; }; i2s1m0-sdi0 { rockchip,pins = <0x01 0x0b 0x01 0xee>; phandle = <0x9e>; }; i2s1m0-sdo0 { rockchip,pins = <0x01 0x07 0x01 0xee>; phandle = <0x9f>; }; }; i2s2 { i2s2m0-lrcktx { rockchip,pins = <0x02 0x13 0x01 0xee>; phandle = <0xa1>; }; i2s2m0-sclktx { rockchip,pins = <0x02 0x12 0x01 0xee>; phandle = <0xa0>; }; i2s2m0-sdi { rockchip,pins = <0x02 0x15 0x01 0xee>; phandle = <0xa2>; }; i2s2m0-sdo { rockchip,pins = <0x02 0x14 0x01 0xee>; phandle = <0xa3>; }; }; i2s3 { i2s3m0-lrck { rockchip,pins = <0x03 0x04 0x04 0xee>; phandle = <0xa5>; }; i2s3m0-sclk { rockchip,pins = <0x03 0x03 0x04 0xee>; phandle = <0xa4>; }; i2s3m0-sdi { rockchip,pins = <0x03 0x06 0x04 0xee>; phandle = <0xa6>; }; i2s3m0-sdo { rockchip,pins = <0x03 0x05 0x04 0xee>; phandle = <0xa7>; }; }; lcdc { lcdc-ctl { rockchip,pins = <0x03 0x00 0x01 0xee 0x02 0x18 0x01 0xee 0x02 0x19 0x01 0xee 0x02 0x1a 0x01 0xee 0x02 0x1b 0x01 0xee 0x02 0x1c 0x01 0xee 0x02 0x1d 0x01 0xee 0x02 0x1e 0x01 0xee 0x02 0x1f 0x01 0xee 0x03 0x01 0x01 0xee 0x03 0x02 0x01 0xee 0x03 0x03 0x01 0xee 0x03 0x04 0x01 0xee 0x03 0x05 0x01 0xee 0x03 0x06 0x01 0xee 0x03 0x07 0x01 0xee 0x03 0x08 0x01 0xee 0x03 0x09 0x01 0xee 0x03 0x0a 0x01 0xee 0x03 0x0b 0x01 0xee 0x03 0x0c 0x01 0xee 0x03 0x0d 0x01 0xee 0x03 0x0e 0x01 0xee 0x03 0x0f 0x01 0xee 0x03 0x10 0x01 0xee 0x03 0x13 0x01 0xee 0x03 0x11 0x01 0xee 0x03 0x12 0x01 0xee>; phandle = <0x2d>; }; }; pdm { pdmm0-clk { rockchip,pins = <0x01 0x06 0x03 0xee>; phandle = <0xa8>; }; pdmm0-clk1 { rockchip,pins = <0x01 0x04 0x03 0xee>; phandle = <0xa9>; }; pdmm0-sdi0 { rockchip,pins = <0x01 0x0b 0x02 0xee>; phandle = <0xaa>; }; pdmm0-sdi1 { rockchip,pins = <0x01 0x0a 0x03 0xee>; phandle = <0xab>; }; pdmm0-sdi2 { rockchip,pins = <0x01 0x09 0x03 0xee>; phandle = <0xac>; }; pdmm0-sdi3 { rockchip,pins = <0x01 0x08 0x03 0xee>; phandle = <0xad>; }; }; pwm0 { pwm0m0-pins { rockchip,pins = <0x00 0x0f 0x01 0xee>; phandle = <0x34>; }; }; pwm1 { pwm1m0-pins { rockchip,pins = <0x00 0x10 0x01 0xee>; phandle = <0x35>; }; }; pwm2 { pwm2m0-pins { rockchip,pins = <0x00 0x11 0x01 0xee>; phandle = <0x36>; }; }; pwm3 { pwm3-pins { rockchip,pins = <0x00 0x12 0x01 0xee>; phandle = <0x37>; }; }; pwm4 { pwm4-pins { rockchip,pins = <0x00 0x13 0x01 0xee>; phandle = <0xd4>; }; }; pwm5 { pwm5-pins { rockchip,pins = <0x00 0x14 0x01 0xee>; phandle = <0xd5>; }; }; pwm6 { pwm6-pins { rockchip,pins = <0x00 0x15 0x01 0xee>; phandle = <0xd6>; }; }; pwm7 { pwm7-pins { rockchip,pins = <0x00 0x16 0x01 0xee>; phandle = <0xd7>; }; }; pwm8 { pwm8m0-pins { rockchip,pins = <0x03 0x09 0x05 0xee>; phandle = <0xd8>; }; }; pwm9 { pwm9m0-pins { rockchip,pins = <0x03 0x0a 0x05 0xee>; phandle = <0xd9>; }; }; pwm10 { pwm10m0-pins { rockchip,pins = <0x03 0x0d 0x05 0xee>; phandle = <0xda>; }; }; pwm11 { pwm11m0-pins { rockchip,pins = <0x03 0x0e 0x05 0xee>; phandle = <0xdb>; }; }; pwm12 { pwm12m0-pins { rockchip,pins = <0x03 0x0f 0x02 0xee>; phandle = <0xdc>; }; }; pwm13 { pwm13m0-pins { rockchip,pins = <0x03 0x10 0x02 0xee>; phandle = <0xdd>; }; }; pwm14 { pwm14m0-pins { rockchip,pins = <0x03 0x14 0x01 0xee>; phandle = <0xde>; }; }; pwm15 { pwm15m0-pins { rockchip,pins = <0x03 0x15 0x01 0xee>; phandle = <0xdf>; }; }; scr { scr-pins { rockchip,pins = <0x01 0x02 0x03 0xee 0x01 0x07 0x03 0xf0 0x01 0x03 0x03 0xf0 0x01 0x05 0x03 0xee>; phandle = <0xb0>; }; }; sdmmc0 { sdmmc0-bus4 { rockchip,pins = <0x01 0x1d 0x01 0xef 0x01 0x1e 0x01 0xef 0x01 0x1f 0x01 0xef 0x02 0x00 0x01 0xef>; phandle = <0x93>; }; sdmmc0-clk { rockchip,pins = <0x02 0x02 0x01 0xef>; phandle = <0x94>; }; sdmmc0-cmd { rockchip,pins = <0x02 0x01 0x01 0xef>; phandle = <0x95>; }; sdmmc0-det { rockchip,pins = <0x00 0x04 0x01 0xf0>; phandle = <0x96>; }; }; sdmmc1 { sdmmc1-bus4 { rockchip,pins = <0x02 0x03 0x01 0xef 0x02 0x04 0x01 0xef 0x02 0x05 0x01 0xef 0x02 0x06 0x01 0xef>; phandle = <0x98>; }; sdmmc1-clk { rockchip,pins = <0x02 0x08 0x01 0xef>; phandle = <0x9a>; }; sdmmc1-cmd { rockchip,pins = <0x02 0x07 0x01 0xef>; phandle = <0x99>; }; }; spdif { spdifm0-tx { rockchip,pins = <0x01 0x04 0x04 0xee>; phandle = <0xae>; }; }; spi0 { spi0m0-pins { rockchip,pins = <0x00 0x0d 0x02 0xee 0x00 0x15 0x02 0xee 0x00 0x0e 0x02 0xee>; phandle = <0xbc>; }; spi0m0-cs0 { rockchip,pins = <0x00 0x16 0x02 0xee>; phandle = <0xba>; }; spi0m0-cs1 { rockchip,pins = <0x00 0x14 0x02 0xee>; phandle = <0xbb>; }; }; spi1 { spi1m0-pins { rockchip,pins = <0x02 0x0d 0x03 0xee 0x02 0x0e 0x03 0xee 0x02 0x0f 0x04 0xee>; phandle = <0xc0>; }; spi1m0-cs0 { rockchip,pins = <0x02 0x10 0x04 0xee>; phandle = <0xbe>; }; spi1m0-cs1 { rockchip,pins = <0x02 0x16 0x03 0xee>; phandle = <0xbf>; }; }; spi2 { spi2m0-pins { rockchip,pins = <0x02 0x11 0x04 0xee 0x02 0x12 0x04 0xee 0x02 0x13 0x04 0xee>; phandle = <0xc4>; }; spi2m0-cs0 { rockchip,pins = <0x02 0x14 0x04 0xee>; phandle = <0xc2>; }; spi2m0-cs1 { rockchip,pins = <0x02 0x15 0x04 0xee>; phandle = <0xc3>; }; }; spi3 { spi3m0-pins { rockchip,pins = <0x04 0x0b 0x04 0xee 0x04 0x08 0x04 0xee 0x04 0x0a 0x04 0xee>; phandle = <0xc8>; }; spi3m0-cs0 { rockchip,pins = <0x04 0x06 0x04 0xee>; phandle = <0xc6>; }; spi3m0-cs1 { rockchip,pins = <0x04 0x07 0x04 0xee>; phandle = <0xc7>; }; }; tsadc { tsadc-shutorg { rockchip,pins = <0x00 0x01 0x02 0xee>; phandle = <0xe1>; }; }; uart0 { uart0-xfer { rockchip,pins = <0x00 0x10 0x03 0xf0 0x00 0x11 0x03 0xf0>; phandle = <0x33>; }; }; uart1 { uart1m0-xfer { rockchip,pins = <0x02 0x0b 0x02 0xf0 0x02 0x0c 0x02 0xf0>; phandle = <0xca>; }; uart1m0-ctsn { rockchip,pins = <0x02 0x0e 0x02 0xee>; phandle = <0xcb>; }; uart1m0-rtsn { rockchip,pins = <0x02 0x0d 0x02 0xee>; phandle = <0x109>; }; }; uart2 { uart2m0-xfer { rockchip,pins = <0x00 0x18 0x01 0xf0 0x00 0x19 0x01 0xf0>; phandle = <0xcc>; }; }; uart3 { uart3m0-xfer { rockchip,pins = <0x01 0x00 0x02 0xf0 0x01 0x01 0x02 0xf0>; phandle = <0xcd>; }; }; uart4 { uart4m0-xfer { rockchip,pins = <0x01 0x04 0x02 0xf0 0x01 0x06 0x02 0xf0>; phandle = <0xce>; }; }; uart5 { uart5m0-xfer { rockchip,pins = <0x02 0x01 0x03 0xf0 0x02 0x02 0x03 0xf0>; phandle = <0xcf>; }; }; uart6 { uart6m0-xfer { rockchip,pins = <0x02 0x03 0x03 0xf0 0x02 0x04 0x03 0xf0>; phandle = <0xd0>; }; }; uart7 { uart7m0-xfer { rockchip,pins = <0x02 0x05 0x03 0xf0 0x02 0x06 0x03 0xf0>; phandle = <0xd1>; }; }; uart8 { uart8m0-xfer { rockchip,pins = <0x02 0x16 0x02 0xf0 0x02 0x15 0x03 0xf0>; phandle = <0xd2>; }; }; uart9 { uart9m0-xfer { rockchip,pins = <0x02 0x07 0x03 0xf0 0x02 0x08 0x03 0xf0>; phandle = <0xd3>; }; }; spi0-hs { spi0m0-pins { rockchip,pins = <0x00 0x0d 0x02 0xf4 0x00 0x15 0x02 0xf4 0x00 0x0e 0x02 0xf4>; phandle = <0xbd>; }; }; spi1-hs { spi1m0-pins { rockchip,pins = <0x02 0x0d 0x03 0xf4 0x02 0x0e 0x03 0xf4 0x02 0x0f 0x04 0xf4>; phandle = <0xc1>; }; }; spi2-hs { spi2m0-pins { rockchip,pins = <0x02 0x11 0x04 0xf4 0x02 0x12 0x04 0xf4 0x02 0x13 0x04 0xf4>; phandle = <0xc5>; }; }; spi3-hs { spi3m0-pins { rockchip,pins = <0x04 0x0b 0x04 0xf4 0x04 0x08 0x04 0xf4 0x04 0x0a 0x04 0xf4>; phandle = <0xc9>; }; }; gpio-func { tsadc-gpio-func { rockchip,pins = <0x00 0x01 0x00 0xee>; phandle = <0xe0>; }; }; sdio-pwrseq { wifi-enable-h { rockchip,pins = <0x02 0x09 0x00 0xee>; phandle = <0x102>; }; wifi-32k { rockchip,pins = <0x02 0x16 0x01 0xee>; phandle = <0x103>; }; }; usb { vcc5v0-host-en { rockchip,pins = <0x00 0x06 0x00 0xee>; phandle = <0x105>; }; vcc5v0-otg-en { rockchip,pins = <0x00 0x16 0x00 0xee>; phandle = <0x106>; }; }; wireless-wlan { wifi-host-wake-irq { rockchip,pins = <0x02 0x0a 0x00 0xf6>; phandle = <0x108>; }; }; wireless-bluetooth { uart1-gpios { rockchip,pins = <0x02 0x0d 0x00 0xee>; phandle = <0x10a>; }; }; }; adc-keys { compatible = "adc-keys"; io-channels = <0xf7 0x00>; io-channel-names = "buttons"; keyup-threshold-microvolt = <0x1b7740>; poll-interval = <0x64>; phandle = <0x197>; vol-up-key { label = "volume up"; linux,code = <0x73>; press-threshold-microvolt = <0x6d6>; }; vol-down-key { label = "volume down"; linux,code = <0x72>; press-threshold-microvolt = <0x48a1c>; }; }; dc-12v { compatible = "regulator-fixed"; regulator-name = "dc_12v"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0xb71b00>; regulator-max-microvolt = <0xb71b00>; phandle = <0xfc>; }; hdmi-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <0x100>; simple-audio-card,name = "hdmi-sound"; status = "okay"; phandle = <0x198>; simple-audio-card,cpu { sound-dai = <0xf8>; }; simple-audio-card,codec { sound-dai = <0xf9>; }; }; spdif-sound { status = "okay"; compatible = "simple-audio-card"; simple-audio-card,name = "ROCKCHIP,SPDIF"; simple-audio-card,cpu { sound-dai = <0xfa>; }; simple-audio-card,codec { sound-dai = <0xfb>; }; }; spdif-out { status = "okay"; compatible = "linux,spdif-dit"; #sound-dai-cells = <0x00>; phandle = <0xfb>; }; vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; vin-supply = <0xfc>; phandle = <0x101>; }; vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x4c4b40>; regulator-max-microvolt = <0x4c4b40>; vin-supply = <0xfc>; phandle = <0xfd>; }; vcc_1v8 { compatible = "regulator-fixed"; regulator-name = "vcc_1v8"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; vin-supply = <0xfd>; phandle = <0x2a>; }; vcc_3v3 { compatible = "regulator-fixed"; regulator-name = "vcc_3v3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; vin-supply = <0xfd>; phandle = <0x29>; }; vdd-fixed { compatible = "regulator-fixed"; regulator-name = "vdd_fixed"; regulator-min-microvolt = <0xe7ef0>; regulator-max-microvolt = <0xe7ef0>; regulator-always-on; regulator-boot-on; vin-supply = <0xfd>; phandle = <0x53>; }; vdd-cpu { compatible = "pwm-regulator"; pwms = <0xfe 0x00 0x1388 0x01>; regulator-name = "vdd_cpu"; regulator-min-microvolt = "\0\f5"; regulator-max-microvolt = <0x124f80>; regulator-init-microvolt = <0xe7ef0>; regulator-always-on; regulator-boot-on; regulator-settling-time-up-us = <0xfa>; pwm-supply = <0xfd>; status = "okay"; phandle = <0x05>; }; vdd-logic { compatible = "pwm-regulator"; pwms = <0xff 0x00 0x1388 0x01>; regulator-name = "vdd_logic"; regulator-min-microvolt = "\0\f5"; regulator-max-microvolt = <0x10c8e0>; regulator-init-microvolt = <0xe7ef0>; regulator-always-on; regulator-boot-on; regulator-settling-time-up-us = <0xfa>; pwm-supply = <0xfd>; status = "okay"; phandle = <0x56>; }; gpio-leds { compatible = "gpio-leds"; ir-led { gpios = <0x6d 0x15 0x00>; default-state = "off"; }; work-led { gpios = <0x100 0x13 0x00>; linux,default-trigger = "timer"; }; }; vcc2v5-ddr { compatible = "regulator-fixed"; regulator-name = "vcc2v5-sys"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x2625a0>; regulator-max-microvolt = <0x2625a0>; vin-supply = <0x101>; phandle = <0x199>; }; sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <0x2e 0x05>; clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <0x102 0x103>; reset-gpios = <0x104 0x09 0x01>; phandle = <0x97>; }; vcc3v3-sd-regulator { compatible = "regulator-gpio"; regulator-name = "vcc3v3_sd"; regulator-min-microvolt = <0x186a0>; regulator-max-microvolt = <0x325aa0>; gpios = <0x100 0x05 0x00>; gpios-states = <0x01>; states = <0x186a0 0x01 0x325aa0 0x00>; phandle = <0x92>; }; vccio-sd-regulator { compatible = "regulator-gpio"; regulator-name = "vccio_sd"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x325aa0>; gpios = <0x100 0x0e 0x00>; gpios-states = <0x01>; states = <0x1b7740 0x00 0x325aa0 0x01>; phandle = <0x19a>; }; vcc5v0-host-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <0x100 0x06 0x00>; pinctrl-names = "default"; pinctrl-0 = <0x105>; regulator-name = "vcc5v0_host"; regulator-always-on; phandle = <0xea>; }; vcc5v0-otg-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <0x100 0x16 0x00>; pinctrl-names = "default"; pinctrl-0 = <0x106>; regulator-name = "vcc5v0_otg"; phandle = <0xeb>; }; vcc-camera-regulator { compatible = "regulator-fixed"; gpio = <0x100 0x15 0x00>; pinctrl-names = "default"; pinctrl-0 = <0x107>; regulator-name = "vcc_camera"; enable-active-high; regulator-always-on; regulator-boot-on; phandle = <0x19b>; }; wireless-wlan { compatible = "wlan-platdata"; rockchip,grf = <0x2f>; wifi_chip_type = "ap6398s"; pinctrl-names = "default"; pinctrl-0 = <0x108>; WIFI,host_wake_irq = <0x104 0x0a 0x00>; status = "okay"; phandle = <0x19c>; }; wireless-bluetooth { compatible = "bluetooth-platdata"; clocks = <0x2e 0x05>; clock-names = "ext_clock"; uart_rts_gpios = <0x104 0x0d 0x01>; pinctrl-names = "default\0rts_gpio"; pinctrl-0 = <0x109>; pinctrl-1 = <0x10a>; BT,reset_gpio = <0x104 0x0f 0x00>; BT,wake_gpio = <0x104 0x11 0x00>; BT,wake_host_irq = <0x104 0x10 0x00>; status = "okay"; phandle = <0x19d>; }; fd655_dev { compatible = "rockchip,fd655_dev"; status = "okay"; clk_pin = <0x10b 0x01 0x00>; dat_pin = <0x10b 0x00 0x00>; }; fd6513_dev { compatible = "amlogic,FD6513"; status = "okay"; clk_pin = <0x10b 0x0a 0x00>; dat_pin = <0x10b 0x09 0x00>; }; chosen { bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0"; phandle = <0x19e>; }; fiq-debugger { compatible = "rockchip,fiq-debugger"; rockchip,serial-id = <0x02>; rockchip,wake-irq = <0x00>; rockchip,irq-mode-enable = <0x01>; rockchip,baudrate = <0x16e360>; interrupts = <0x00 0xfc 0x08>; pinctrl-names = "default"; pinctrl-0 = <0xcc>; status = "okay"; }; debug@fd904000 { compatible = "rockchip,debug"; reg = <0x00 0xfd904000 0x00 0x1000 0x00 0xfd905000 0x00 0x1000 0x00 0xfd906000 0x00 0x1000 0x00 0xfd907000 0x00 0x1000>; phandle = <0x19f>; }; cspmu@fd90c000 { compatible = "rockchip,cspmu"; reg = <0x00 0xfd90c000 0x00 0x1000 0x00 0xfd90d000 0x00 0x1000 0x00 0xfd90e000 0x00 0x1000 0x00 0xfd90f000 0x00 0x1000>; phandle = <0x1a0>; }; __symbols__ { ddr_timing = "/ddr_timing"; cpu0 = "/cpus/cpu@0"; cpu1 = "/cpus/cpu@100"; cpu2 = "/cpus/cpu@200"; cpu3 = "/cpus/cpu@300"; CPU_SLEEP = "/cpus/idle-states/cpu-sleep"; cpu0_opp_table = "/cpu0-opp-table"; display_subsystem = "/display-subsystem"; route_dsi0 = "/display-subsystem/route/route-dsi0"; route_dsi1 = "/display-subsystem/route/route-dsi1"; route_edp = "/display-subsystem/route/route-edp"; route_hdmi = "/display-subsystem/route/route-hdmi"; route_lvds = "/display-subsystem/route/route-lvds"; route_rgb = "/display-subsystem/route/route-rgb"; optee = "/firmware/optee"; scmi = "/firmware/scmi"; scmi_clk = "/firmware/scmi/protocol@14"; sdei = "/firmware/sdei"; mpp_srv = "/mpp-srv"; reserved_memory = "/reserved-memory"; drm_logo = "/reserved-memory/drm-logo@00000000"; drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000"; rknpu_reserved = "/reserved-memory/rknpu"; ramoops = "/reserved-memory/ramoops@110000"; rockchip_suspend = "/rockchip-suspend"; rockchip_system_monitor = "/rockchip-system-monitor"; thermal_zones = "/thermal-zones"; soc_thermal = "/thermal-zones/soc-thermal"; threshold = "/thermal-zones/soc-thermal/trips/trip-point-0"; target = "/thermal-zones/soc-thermal/trips/trip-point-1"; soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit"; gpu_thermal = "/thermal-zones/gpu-thermal"; gmac1_clkin = "/external-gmac1-clock"; gmac1_xpcsclk = "/xpcs-gmac1-clock"; i2s1_mclkin_rx = "/i2s1-mclkin-rx"; i2s1_mclkin_tx = "/i2s1-mclkin-tx"; i2s2_mclkin = "/i2s2-mclkin"; i2s3_mclkin = "/i2s3-mclkin"; mpll = "/mpll"; xin24m = "/xin24m"; xin32k = "/xin32k"; scmi_shmem = "/scmi-shmem@10f000"; sata1 = "/sata@fc400000"; sata2 = "/sata@fc800000"; usbdrd30 = "/usbdrd"; usbdrd_dwc3 = "/usbdrd/dwc3@fcc00000"; usbhost30 = "/usbhost"; usbhost_dwc3 = "/usbhost/dwc3@fd000000"; gic = "/interrupt-controller@fd400000"; its = "/interrupt-controller@fd400000/interrupt-controller@fd440000"; usb_host0_ehci = "/usb@fd800000"; usb_host0_ohci = "/usb@fd840000"; usb_host1_ehci = "/usb@fd880000"; usb_host1_ohci = "/usb@fd8c0000"; xpcs = "/syscon@fda00000"; pmugrf = "/syscon@fdc20000"; pmu_io_domains = "/syscon@fdc20000/io-domains"; reboot_mode = "/syscon@fdc20000/reboot-mode"; pipegrf = "/syscon@fdc50000"; grf = "/syscon@fdc60000"; io_domains = "/syscon@fdc60000/io-domains"; lvds = "/syscon@fdc60000/lvds"; lvds_in_vp1 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@1"; lvds_in_vp2 = "/syscon@fdc60000/lvds/ports/port@0/endpoint@2"; rgb = "/syscon@fdc60000/rgb"; rgb_in_vp2 = "/syscon@fdc60000/rgb/ports/port@0/endpoint@2"; pipe_phy_grf0 = "/syscon@fdc70000"; pipe_phy_grf1 = "/syscon@fdc80000"; pipe_phy_grf2 = "/syscon@fdc90000"; usb2phy0_grf = "/syscon@fdca0000"; usb2phy1_grf = "/syscon@fdca8000"; edp_phy = "/edp-phy@fdcb0000"; sram = "/sram@fdcc0000"; rkvdec_sram = "/sram@fdcc0000/rkvdec-sram@0"; pmucru = "/clock-controller@fdd00000"; cru = "/clock-controller@fdd20000"; i2c0 = "/i2c@fdd40000"; uart0 = "/serial@fdd50000"; pwm0 = "/pwm@fdd70000"; pwm1 = "/pwm@fdd70010"; pwm2 = "/pwm@fdd70020"; pwm3 = "/pwm@fdd70030"; pmu = "/power-management@fdd90000"; power = "/power-management@fdd90000/power-controller"; rknpu = "/npu@fde40000"; npu_opp_table = "/npu-opp-table"; bus_npu = "/bus-npu"; bus_npu_opp_table = "/bus-npu-opp-table"; rknpu_mmu = "/iommu@fde4b000"; gpu = "/gpu@fde60000"; gpu_power_model = "/gpu@fde60000/power-model"; gpu_opp_table = "/opp-table2"; vdpu = "/vdpu@fdea0400"; vdpu_mmu = "/iommu@fdea0800"; rk_rga = "/rk_rga@fdeb0000"; ebc = "/ebc@fdec0000"; jpegd = "/jpegd@fded0000"; jpegd_mmu = "/iommu@fded0480"; vepu = "/vepu@fdee0000"; vepu_mmu = "/iommu@fdee0800"; iep = "/iep@fdef0000"; iep_mmu = "/iommu@fdef0800"; eink = "/eink@fdf00000"; rkvenc = "/rkvenc@fdf40000"; rkvenc_opp_table = "/rkvenc-opp-table"; rkvenc_mmu = "/iommu@fdf40f00"; rkvdec = "/rkvdec@fdf80200"; rkvdec_mmu = "/iommu@fdf80800"; mipi_csi2 = "/mipi-csi2@fdfb0000"; rkcif = "/rkcif@fdfe0000"; rkcif_mmu = "/iommu@fdfe0800"; rkcif_dvp = "/rkcif_dvp"; rkcif_dvp_sditf = "/rkcif_dvp_sditf"; rkcif_mipi_lvds = "/rkcif_mipi_lvds"; rkcif_mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf"; rkisp = "/rkisp@fdff0000"; rkisp_mmu = "/iommu@fdff1a00"; rkisp_vir0 = "/rkisp-vir0"; isp0_in = "/rkisp-vir0/port/endpoint@0"; rkisp_vir1 = "/rkisp-vir1"; gmac1 = "/ethernet@fe010000"; mdio1 = "/ethernet@fe010000/mdio"; rgmii_phy1 = "/ethernet@fe010000/mdio/phy@0"; gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config"; gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config"; gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config"; vop = "/vop@fe040000"; vop_out = "/vop@fe040000/ports"; vp0 = "/vop@fe040000/ports/port@0"; vp0_out_dsi0 = "/vop@fe040000/ports/port@0/endpoint@0"; vp0_out_dsi1 = "/vop@fe040000/ports/port@0/endpoint@1"; vp0_out_edp = "/vop@fe040000/ports/port@0/endpoint@2"; vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@3"; vp1 = "/vop@fe040000/ports/port@1"; vp1_out_dsi0 = "/vop@fe040000/ports/port@1/endpoint@0"; vp1_out_dsi1 = "/vop@fe040000/ports/port@1/endpoint@1"; vp1_out_edp = "/vop@fe040000/ports/port@1/endpoint@2"; vp1_out_hdmi = "/vop@fe040000/ports/port@1/endpoint@3"; vp1_out_lvds = "/vop@fe040000/ports/port@1/endpoint@4"; vp2 = "/vop@fe040000/ports/port@2"; vp2_out_lvds = "/vop@fe040000/ports/port@2/endpoint@0"; vp2_out_rgb = "/vop@fe040000/ports/port@2/endpoint@1"; vop_mmu = "/iommu@fe043e00"; dsi0 = "/dsi@fe060000"; dsi0_in = "/dsi@fe060000/ports/port@0"; dsi0_in_vp0 = "/dsi@fe060000/ports/port@0/endpoint@0"; dsi0_in_vp1 = "/dsi@fe060000/ports/port@0/endpoint@1"; dsi1 = "/dsi@fe070000"; dsi1_in = "/dsi@fe070000/ports/port@0"; dsi1_in_vp0 = "/dsi@fe070000/ports/port@0/endpoint@0"; dsi1_in_vp1 = "/dsi@fe070000/ports/port@0/endpoint@1"; hdmi = "/hdmi@fe0a0000"; hdmi_in = "/hdmi@fe0a0000/ports/port"; hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port/endpoint@0"; hdmi_in_vp1 = "/hdmi@fe0a0000/ports/port/endpoint@1"; edp = "/edp@fe0c0000"; edp_in = "/edp@fe0c0000/ports/port@0"; edp_in_vp0 = "/edp@fe0c0000/ports/port@0/endpoint@0"; edp_in_vp1 = "/edp@fe0c0000/ports/port@0/endpoint@1"; qos_gpu = "/qos@fe128000"; qos_rkvenc_rd_m0 = "/qos@fe138080"; qos_rkvenc_rd_m1 = "/qos@fe138100"; qos_rkvenc_wr_m0 = "/qos@fe138180"; qos_isp = "/qos@fe148000"; qos_vicap0 = "/qos@fe148080"; qos_vicap1 = "/qos@fe148100"; qos_vpu = "/qos@fe150000"; qos_ebc = "/qos@fe158000"; qos_iep = "/qos@fe158100"; qos_jpeg_dec = "/qos@fe158180"; qos_jpeg_enc = "/qos@fe158200"; qos_rga_rd = "/qos@fe158280"; qos_rga_wr = "/qos@fe158300"; qos_npu = "/qos@fe180000"; qos_pcie2x1 = "/qos@fe190000"; qos_sata1 = "/qos@fe190280"; qos_sata2 = "/qos@fe190300"; qos_usb3_0 = "/qos@fe190380"; qos_usb3_1 = "/qos@fe190400"; qos_rkvdec = "/qos@fe198000"; qos_hdcp = "/qos@fe1a8000"; qos_vop_m0 = "/qos@fe1a8080"; qos_vop_m1 = "/qos@fe1a8100"; sdmmc2 = "/dwmmc@fe000000"; dfi = "/dfi@fe230000"; dmc = "/dmc"; dmc_opp_table = "/dmc-opp-table"; pcie2x1 = "/pcie@fe260000"; pcie2x1_intc = "/pcie@fe260000/legacy-interrupt-controller"; sdmmc0 = "/dwmmc@fe2b0000"; sdmmc1 = "/dwmmc@fe2c0000"; sfc = "/sfc@fe300000"; sdhci = "/sdhci@fe310000"; nandc0 = "/nandc@fe330000"; crypto = "/crypto@fe380000"; rng = "/rng@fe388000"; otp = "/otp@fe38c000"; cpu_code = "/otp@fe38c000/cpu-code@2"; otp_cpu_version = "/otp@fe38c000/cpu-version@8"; mbist_vmin = "/otp@fe38c000/mbist-vmin@9"; otp_id = "/otp@fe38c000/id@a"; cpu_leakage = "/otp@fe38c000/cpu-leakage@1a"; log_leakage = "/otp@fe38c000/log-leakage@1b"; npu_leakage = "/otp@fe38c000/npu-leakage@1c"; gpu_leakage = "/otp@fe38c000/gpu-leakage@1d"; core_pvtm = "/otp@fe38c000/core-pvtm@2a"; i2s0_8ch = "/i2s@fe400000"; i2s1_8ch = "/i2s@fe410000"; i2s2_2ch = "/i2s@fe420000"; i2s3_2ch = "/i2s@fe430000"; pdm = "/pdm@fe440000"; vad = "/vad@fe450000"; spdif_8ch = "/spdif@fe460000"; audpwm = "/audpwm@fe470000"; dig_acodec = "/codec-digital@fe478000"; dmac0 = "/dmac@fe530000"; dmac1 = "/dmac@fe550000"; scr = "/rkscr@fe560000"; can0 = "/can@fe570000"; can1 = "/can@fe580000"; can2 = "/can@fe590000"; i2c1 = "/i2c@fe5a0000"; i2c2 = "/i2c@fe5b0000"; gc8034 = "/i2c@fe5b0000/gc8034@37"; gc8034_out = "/i2c@fe5b0000/gc8034@37/port/endpoint"; gc4c33 = "/i2c@fe5b0000/gc4c33@29"; gc4c33_out = "/i2c@fe5b0000/gc4c33@29/port/endpoint"; i2c3 = "/i2c@fe5c0000"; i2c4 = "/i2c@fe5d0000"; i2c5 = "/i2c@fe5e0000"; rktimer = "/timer@fe5f0000"; wdt = "/watchdog@fe600000"; spi0 = "/spi@fe610000"; spi1 = "/spi@fe620000"; spi2 = "/spi@fe630000"; spi3 = "/spi@fe640000"; uart1 = "/serial@fe650000"; uart2 = "/serial@fe660000"; uart3 = "/serial@fe670000"; uart4 = "/serial@fe680000"; uart5 = "/serial@fe690000"; uart6 = "/serial@fe6a0000"; uart7 = "/serial@fe6b0000"; uart8 = "/serial@fe6c0000"; uart9 = "/serial@fe6d0000"; pwm4 = "/pwm@fe6e0000"; pwm5 = "/pwm@fe6e0010"; pwm6 = "/pwm@fe6e0020"; pwm7 = "/pwm@fe6e0030"; pwm8 = "/pwm@fe6f0000"; pwm9 = "/pwm@fe6f0010"; pwm10 = "/pwm@fe6f0020"; pwm11 = "/pwm@fe6f0030"; pwm12 = "/pwm@fe700000"; pwm13 = "/pwm@fe700010"; pwm14 = "/pwm@fe700020"; pwm15 = "/pwm@fe700030"; tsadc = "/tsadc@fe710000"; saradc = "/saradc@fe720000"; mailbox = "/mailbox@fe780000"; combphy1_usq = "/phy@fe830000"; combphy2_psq = "/phy@fe840000"; mipi_dphy0 = "/mipi-dphy@fe850000"; video_phy0 = "/video-phy@fe850000"; mipi_dphy1 = "/mipi-dphy@fe860000"; csi2_dphy_hw = "/csi2-dphy-hw@fe870000"; csi2_dphy0 = "/csi2-dphy0"; mipi_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1"; mipi_in_ucam1 = "/csi2-dphy0/ports/port@0/endpoint@2"; csidphy_out = "/csi2-dphy0/ports/port@1/endpoint@1"; csi2_dphy1 = "/csi2-dphy1"; csi2_dphy2 = "/csi2-dphy2"; usb2phy0 = "/usb2-phy@fe8a0000"; u2phy0_host = "/usb2-phy@fe8a0000/host-port"; u2phy0_otg = "/usb2-phy@fe8a0000/otg-port"; usb2phy1 = "/usb2-phy@fe8b0000"; u2phy1_host = "/usb2-phy@fe8b0000/host-port"; u2phy1_otg = "/usb2-phy@fe8b0000/otg-port"; pinctrl = "/pinctrl"; gpio0 = "/pinctrl/gpio@fdd60000"; gpio1 = "/pinctrl/gpio@fe740000"; gpio2 = "/pinctrl/gpio@fe750000"; gpio3 = "/pinctrl/gpio@fe760000"; gpio4 = "/pinctrl/gpio@fe770000"; pcfg_pull_up = "/pinctrl/pcfg-pull-up"; pcfg_pull_down = "/pinctrl/pcfg-pull-down"; pcfg_pull_none = "/pinctrl/pcfg-pull-none"; pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1"; pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2"; pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3"; pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1"; pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2"; pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt"; acodec_pins = "/pinctrl/acodec/acodec-pins"; camera_pwr = "/pinctrl/cam/camera-pwr"; cif_clk = "/pinctrl/cif/cif-clk"; clk32k_out0 = "/pinctrl/clk32k/clk32k-out0"; ebc_pins = "/pinctrl/ebc/ebc-pins"; gmac1m1_miim = "/pinctrl/gmac1/gmac1m1-miim"; gmac1m1_clkinout = "/pinctrl/gmac1/gmac1m1-clkinout"; gmac1m1_rx_bus2 = "/pinctrl/gmac1/gmac1m1-rx-bus2"; gmac1m1_tx_bus2 = "/pinctrl/gmac1/gmac1m1-tx-bus2"; gmac1m1_rgmii_clk = "/pinctrl/gmac1/gmac1m1-rgmii-clk"; gmac1m1_rgmii_bus = "/pinctrl/gmac1/gmac1m1-rgmii-bus"; hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec"; hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl"; hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda"; i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer"; i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer"; i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer"; i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer"; i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer"; i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer"; i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx"; i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx"; i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0"; i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0"; i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx"; i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx"; i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi"; i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo"; i2s3m0_lrck = "/pinctrl/i2s3/i2s3m0-lrck"; i2s3m0_sclk = "/pinctrl/i2s3/i2s3m0-sclk"; i2s3m0_sdi = "/pinctrl/i2s3/i2s3m0-sdi"; i2s3m0_sdo = "/pinctrl/i2s3/i2s3m0-sdo"; lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl"; pdmm0_clk = "/pinctrl/pdm/pdmm0-clk"; pdmm0_clk1 = "/pinctrl/pdm/pdmm0-clk1"; pdmm0_sdi0 = "/pinctrl/pdm/pdmm0-sdi0"; pdmm0_sdi1 = "/pinctrl/pdm/pdmm0-sdi1"; pdmm0_sdi2 = "/pinctrl/pdm/pdmm0-sdi2"; pdmm0_sdi3 = "/pinctrl/pdm/pdmm0-sdi3"; pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins"; pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins"; pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins"; pwm3_pins = "/pinctrl/pwm3/pwm3-pins"; pwm4_pins = "/pinctrl/pwm4/pwm4-pins"; pwm5_pins = "/pinctrl/pwm5/pwm5-pins"; pwm6_pins = "/pinctrl/pwm6/pwm6-pins"; pwm7_pins = "/pinctrl/pwm7/pwm7-pins"; pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins"; pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins"; pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins"; pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins"; pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins"; pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins"; pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins"; pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins"; scr_pins = "/pinctrl/scr/scr-pins"; sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4"; sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk"; sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd"; sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det"; sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4"; sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk"; sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd"; spdifm0_tx = "/pinctrl/spdif/spdifm0-tx"; spi0m0_pins = "/pinctrl/spi0/spi0m0-pins"; spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0"; spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1"; spi1m0_pins = "/pinctrl/spi1/spi1m0-pins"; spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0"; spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1"; spi2m0_pins = "/pinctrl/spi2/spi2m0-pins"; spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0"; spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1"; spi3m0_pins = "/pinctrl/spi3/spi3m0-pins"; spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0"; spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1"; tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg"; uart0_xfer = "/pinctrl/uart0/uart0-xfer"; uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer"; uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn"; uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn"; uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer"; uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer"; uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer"; uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer"; uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer"; uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer"; uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer"; uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer"; spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins"; spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins"; spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins"; spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins"; tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func"; wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h"; wifi_32k = "/pinctrl/sdio-pwrseq/wifi-32k"; vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en"; vcc5v0_otg_en = "/pinctrl/usb/vcc5v0-otg-en"; wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq"; uart1_gpios = "/pinctrl/wireless-bluetooth/uart1-gpios"; adc_keys = "/adc-keys"; dc_12v = "/dc-12v"; hdmi_sound = "/hdmi-sound"; spdif_out = "/spdif-out"; vcc3v3_sys = "/vcc3v3-sys"; vcc5v0_sys = "/vcc5v0-sys"; vcc_1v8 = "/vcc_1v8"; vcc_3v3 = "/vcc_3v3"; vdd_fixed = "/vdd-fixed"; vdd_cpu = "/vdd-cpu"; vdd_logic = "/vdd-logic"; vcc2v5_sys = "/vcc2v5-ddr"; sdio_pwrseq = "/sdio-pwrseq"; vcc3v3_sd = "/vcc3v3-sd-regulator"; vccio_sd = "/vccio-sd-regulator"; vcc5v0_host = "/vcc5v0-host-regulator"; vcc5v0_otg = "/vcc5v0-otg-regulator"; vcc_camera = "/vcc-camera-regulator"; wireless_wlan = "/wireless-wlan"; wireless_bluetooth = "/wireless-bluetooth"; chosen = "/chosen"; debug = "/debug@fd904000"; cspmu = "/cspmu@fd90c000"; }; }; 0 Quote
Hefti Posted October 4, 2022 Posted October 4, 2022 Broke my u-boot partition. i guess i bricked my device now. My goal is to boot an os with efi partition, the existing u-boot partition has no bootefi command. To do this, i decided to try building my own u-boot img. I found out that rockchip does not suport rk3566 , only rk3568. Thats why i followed a guide for rk356x chips. I booted armbian on the target device and build it natively using this guide: https://forum.pine64.org/showthread.php?tid=14507 the patch file is gone (404). I had to clone the repo and use git log --full-history -1 -- [file path] to the commit of the file and finally find it. I used the patch and fixed one broken entry, so i could start compiling. At the end i got a u-boot.img which i finally copied using dd to partiton2 (u-boot) of the emmc. This overwrites the current working u-boot. On my attached UART i get the following output. ▒zDDR Version V1.09 20210630 ln ddrconfig:7 LPDDR4X, 324MHz BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=8192MB tdqss: cs0 dqs0: 48ps, dqs1: -72ps, dqs2: -72ps, dqs3: -144ps, tdqss: cs1 dqs0: 48ps, dqs1: -72ps, dqs2: -72ps, dqs3: -120ps, change to: 324MHz PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:41% dram drv:40,odt:0 clk skew:0x61 change to: 528MHz PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:41% dram drv:40,odt:0 clk skew:0x58 change to: 780MHz PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:41% dram drv:40,odt:0 clk skew:0x58 change to: 920MHz(final freq) PHY drv:clk:36,ca:36,DQ:29,odt:60 vrefinner:16%, vrefout:22% dram drv:40,odt:80 vref_ca:00000071 clk skew:0x3b cs 0: the read training result: DQS0:0x46, DQS1:0x47, DQS2:0x4b, DQS3:0x43, min : 0xa 0xa 0xe 0xb 0x1 0x2 0x6 0x2 , 0x6 0x6 0x2 0x2 0xa 0xa 0xc 0x7 , 0xf 0xf 0xe 0xa 0x6 0x1 0x6 0x4 , 0xa 0x6 0x5 0x1 0xd 0xc 0x9 0xc , mid :0x2d 0x2e 0x31 0x2f 0x24 0x26 0x2a 0x26 ,0x28 0x28 0x25 0x23 0x2d 0x2a 0x2f 0x29 , 0x33 0x32 0x30 0x2d 0x29 0x24 0x26 0x28 ,0x2c 0x29 0x28 0x23 0x2f 0x2e 0x2b 0x2f , max :0x51 0x52 0x55 0x53 0x48 0x4b 0x4e 0x4a ,0x4b 0x4a 0x49 0x44 0x50 0x4b 0x52 0x4b , 0x58 0x56 0x52 0x50 0x4c 0x48 0x47 0x4c ,0x4e 0x4c 0x4b 0x46 0x52 0x50 0x4d 0x52 , range:0x47 0x48 0x47 0x48 0x47 0x49 0x48 0x48 ,0x45 0x44 0x47 0x42 0x46 0x41 0x46 0x44 , 0x49 0x47 0x44 0x46 0x46 0x47 0x41 0x48 ,0x44 0x46 0x46 0x45 0x45 0x44 0x44 0x46 , the write training result: DQS0:0x40, DQS1:0x33, DQS2:0x33, DQS3:0x2b, min :0x5e 0x61 0x63 0x5f 0x56 0x58 0x5a 0x5c 0x5a ,0x4d 0x4d 0x49 0x48 0x50 0x4f 0x54 0x51 0x4d , 0x51 0x50 0x4e 0x4e 0x48 0x48 0x4a 0x4f 0x4d ,0x49 0x48 0x46 0x43 0x4d 0x4d 0x4d 0x4e 0x48 , mid :0x7b 0x7d 0x7f 0x7c 0x73 0x75 0x77 0x77 0x76 ,0x6a 0x69 0x65 0x64 0x6d 0x6b 0x6d 0x6c 0x69 , 0x6e 0x6e 0x69 0x69 0x65 0x5d 0x5f 0x65 0x66 ,0x66 0x65 0x61 0x5e 0x69 0x6a 0x62 0x6b 0x60 , max :0x98 0x9a 0x9b 0x99 0x91 0x92 0x94 0x93 0x93 ,0x87 0x85 0x82 0x81 0x8a 0x87 0x87 0x88 0x85 , 0x8c 0x8c 0x85 0x85 0x82 0x73 0x74 0x7b 0x80 ,0x84 0x82 0x7d 0x7a 0x86 0x88 0x78 0x89 0x78 , range:0x3a 0x39 0x38 0x3a 0x3b 0x3a 0x3a 0x37 0x39 ,0x3a 0x38 0x39 0x39 0x3a 0x38 0x33 0x37 0x38 , 0x3b 0x3c 0x37 0x37 0x3a 0x2b 0x2a 0x2c 0x33 ,0x3b 0x3a 0x37 0x37 0x39 0x3b 0x2b 0x3b 0x30 , cs 1: the read training result: DQS0:0x44, DQS1:0x47, DQS2:0x4c, DQS3:0x43, min : 0x9 0x9 0xc 0x9 0x1 0x2 0x5 0x1 , 0x5 0x5 0x3 0x1 0xb 0x8 0xd 0x6 , 0x11 0x10 0xe 0xb 0x6 0x2 0x7 0x5 , 0xa 0x7 0x6 0x2 0xe 0xd 0xa 0xd , mid :0x2c 0x2c 0x2f 0x2c 0x23 0x25 0x27 0x24 ,0x28 0x28 0x26 0x23 0x2d 0x2a 0x30 0x29 , 0x34 0x34 0x30 0x2e 0x2a 0x25 0x28 0x29 ,0x2c 0x29 0x28 0x24 0x30 0x2e 0x2c 0x2f , max :0x4f 0x4f 0x53 0x50 0x46 0x48 0x4a 0x47 ,0x4c 0x4b 0x4a 0x45 0x50 0x4d 0x53 0x4c , 0x58 0x58 0x52 0x51 0x4e 0x49 0x49 0x4e ,0x4e 0x4c 0x4b 0x46 0x52 0x50 0x4e 0x51 , range:0x46 0x46 0x47 0x47 0x45 0x46 0x45 0x46 ,0x47 0x46 0x47 0x44 0x45 0x45 0x46 0x46 , 0x47 0x48 0x44 0x46 0x48 0x47 0x42 0x49 ,0x44 0x45 0x45 0x44 0x44 0x43 0x44 0x44 , the write training result: DQS0:0x40, DQS1:0x33, DQS2:0x33, DQS3:0x2b, min :0x5d 0x5f 0x62 0x60 0x56 0x58 0x5a 0x5c 0x5a ,0x4c 0x4c 0x49 0x48 0x4f 0x4f 0x53 0x51 0x4d , 0x52 0x52 0x4e 0x4e 0x48 0x48 0x4a 0x4f 0x4f ,0x4b 0x4a 0x49 0x46 0x4f 0x4e 0x4f 0x50 0x4b , mid :0x7a 0x7c 0x7e 0x7d 0x73 0x75 0x77 0x77 0x76 ,0x69 0x69 0x65 0x65 0x6c 0x6b 0x6d 0x6c 0x69 , 0x6f 0x6e 0x69 0x6a 0x65 0x5d 0x5f 0x65 0x68 ,0x69 0x66 0x65 0x61 0x6c 0x6c 0x64 0x6d 0x62 , max :0x98 0x9a 0x9b 0x9a 0x91 0x93 0x95 0x93 0x93 ,0x87 0x86 0x82 0x82 0x8a 0x87 0x87 0x88 0x85 , 0x8c 0x8b 0x84 0x87 0x82 0x73 0x74 0x7b 0x81 ,0x87 0x83 0x81 0x7d 0x89 0x8a 0x7a 0x8b 0x79 , range:0x3b 0x3b 0x39 0x3a 0x3b 0x3b 0x3b 0x37 0x39 ,0x3b 0x3a 0x39 0x3a 0x3b 0x38 0x34 0x37 0x38 , 0x3a 0x39 0x36 0x39 0x3a 0x2b 0x2a 0x2c 0x32 ,0x3c 0x39 0x38 0x37 0x3a 0x3c 0x2b 0x3b 0x2e , CA Training result: cs:0 min :0x47 0x49 0x41 0x40 0x41 0x3e 0x45 ,0x44 0x44 0x3d 0x3d 0x3f 0x3e 0x45 , cs:0 mid :0x86 0x87 0x81 0x7e 0x80 0x7c 0x76 ,0x83 0x82 0x7d 0x7c 0x7e 0x7c 0x75 , cs:0 max :0xc6 0xc6 0xc1 0xbd 0xbf 0xbb 0xa7 ,0xc3 0xc1 0xbd 0xbb 0xbd 0xba 0xa6 , cs:0 range:0x7f 0x7d 0x80 0x7d 0x7e 0x7d 0x62 ,0x7f 0x7d 0x80 0x7e 0x7e 0x7c 0x61 , cs:1 min :0x45 0x4c 0x3e 0x41 0x3c 0x41 0x44 ,0x43 0x46 0x3b 0x40 0x3c 0x40 0x41 , cs:1 mid :0x86 0x87 0x80 0x7e 0x7e 0x7d 0x77 ,0x84 0x82 0x7d 0x7c 0x7e 0x7c 0x74 , cs:1 max :0xc8 0xc3 0xc2 0xbb 0xc1 0xb9 0xaa ,0xc6 0xbf 0xbf 0xb9 0xc0 0xb9 0xa8 , cs:1 range:0x83 0x77 0x84 0x7a 0x85 0x78 0x66 ,0x83 0x79 0x84 0x79 0x84 0x79 0x67 , out U-Boot SPL board init U-Boot SPL 2017.09-ga1f6fc00a0-210413 #ldq (Apr 13 2021 - 11:35:00) unknown raw ID phN unrecognized JEDEC id bytes: 00, 00, 00 Trying to boot from MMC2 spl: partition error Trying to boot from MMC1 No misc partition ## Verified-boot: 0 ## Checking firmware@1 0x00a00000 ... OK ## Checking fdt@1 0x00b33108 ... OK At this point, the system hangs, and its not possible to CTRL-C stop the boot process etc. I tried flashing the Device with Android Tool or the RockChip Factory Tool, but it seems not to detect the usb device anymore. Thats very bad because i thought if i mess up with u-boot i could still reflash it using this tool. Maybe i am just doing something wrong with the factory Tool but as far as i see, i guess it requires the pre-installed u-boot? Any help would be appreciated. Thx! 0 Quote
Hefti Posted October 4, 2022 Posted October 4, 2022 My last hope is that it is possible to intercept unknown raw ID phN unrecognized JEDEC id bytes: 00, 00, 00 Trying to boot from MMC2 ---- HERE ---- spl: partition error Trying to boot from MMC1 ---- OR HERE ---- No misc partition ## Verified-boot: 0 ## Checking firmware@1 0x00a00000 ... OK ## Checking fdt@1 0x00b33108 ... OK To get it working again. But this would require some magically prepared sd card i guess? Any help would be welcome. 0 Quote
DigitalDaz Posted October 4, 2022 Author Posted October 4, 2022 U can always flash back the original android image 1 Quote
Hefti Posted October 4, 2022 Posted October 4, 2022 But how to? My Device is not detected by usb anymore. 0 Quote
Hefti Posted October 4, 2022 Posted October 4, 2022 When i follow this video guide, there is no sound popping up when i connect my device. 0 Quote
Hqnicolas Posted October 23, 2022 Posted October 23, 2022 Hefti, you need to short the EMMC CLK pin to GND on your board to connect the RK3566 on Desktop USB Maskrom Mode. TUTORIAL: https://roc-rk3328-cc.readthedocs.io/en/latest/flash_emmc.html 0 Quote
Hqnicolas Posted October 23, 2022 Posted October 23, 2022 i decide to compile entire Linux distro using my android rk3566DDR3.dtb files to a flash image.img https://wiki.t-firefly.com/en/ROC-RK3566-PC/prepare_compile_linux.html i'm working at the same processor as you, Please follow my posts l 0 Quote
Hefti Posted October 23, 2022 Posted October 23, 2022 @hotnikq Thx i will check it regularly. 0 Quote
Hqnicolas Posted November 6, 2022 Posted November 6, 2022 please have a look at the forum https://www.t95plus.com/ on this topic they have a bullseye_legacy_4.19 0 Quote
Energokom Posted November 19, 2022 Posted November 19, 2022 On 9/29/2022 at 9:27 PM, Hefti said: For the reference, here is the device tree source of t95plus.dtb How extract device tree dtb from android? 0 Quote
tmm1 Posted December 1, 2022 Posted December 1, 2022 On 10/22/2022 at 10:15 PM, hotnikq said: Hefti, you need to short the EMMC CLK pin to GND on your board to connect the RK3566 on Desktop USB Maskrom Mode. Can you advise which pins to short for https://www.t95plus.com/forums/index.php?threads/maskrom-mode-for-unbricking.7/ 0 Quote
Hqnicolas Posted December 2, 2022 Posted December 2, 2022 @tmm1 Usually these pins are close to the EMMC some manufacturers put a small "CLK" and "GND" writing next to the EMMC or on the other side of the board 0 Quote
tmm1 Posted December 10, 2022 Posted December 10, 2022 @Hefti Did you figure out how to restore your board? I just clobbered mine too (with `rkdeveloptool wl 0x40 idloader.bin` gone wrong). I think I will need to short the eMMC 0 Quote
Dougieee Posted May 21, 2023 Posted May 21, 2023 has anyone gotten a newer version to run with wifi on the t95 plus? i have an 8gb model and got klipper to run just fine off the sd card but would like to update to get wifi working and install to emmc ive tried the steps over at t95plus.com but issue is when i get to Replace the UUID in the line beginning with APPEND with the UUID obtained from the step above, it should end up like this: i have issues with the UI 0 Quote
BliteKnight Posted September 26, 2023 Posted September 26, 2023 @Dougieee - can you provide you DTB files that you are using to boot as I can't find one that works. 0 Quote
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