Hqnicolas Posted April 6 Author Posted April 6 (edited) 11 minutes ago, Werner said: https://www.sparkfun.com/datasheets/IC/cp2102.pdf TL2102 just handle 921600 with just 7 or 8 data bits only. absolutely the market is flooded with fake Chinese! i have tested: 2102 300bps ~ 1MBps and 2104 300 bps ~ 2Mbps But now Firefly and many customers have found in actual use that the actual baud rate of many CH340s on the market cannot reach 1.5Mbps, which causes a lot of trouble in the development process Edited April 6 by Hqnicolas 0 Quote
pocosparc Posted April 8 Posted April 8 I only use the original FTDI cables - currently C232HD which can go up to 12 Mbaud. I learned my share of these Chinese copycats - there was even a driver update, that bricked these devices as clones. On the other hand, there is also a possibility to use the ST-Link V3 JTAG expansion board as it reaches somewhere near 2.5 Mbaud (confirmed in one project of mine). Nevertheless, I installed the Armbian Bookworm v1.1 on the eMMC and I am still fiddling around it. What I can confirm that it works: 1000 MBit ethernet - speed nearly the same as on the physical PC Wifi 5 GHz Both USB ports HDMI@1440p Can`t say anything about SD-Card - still haven't received the SD card socket. I am also enclosing the whole hwinfo dump so that we will know what is on this H96 MAX v20 board. In the armbian-config I enabled the BT and IR, but still need to test them out. One thing that I saw in the dmesg is this one [ 1488.583390] of_dma_request_slave_channel: dma-names property of node '/serial@fe650000' missing or empty According to the dts file it should be the UART1 used by the Bluetooth if I am interpreting this one correctly (I need to check into the MCU datasheet but I must say that this datasheet is a disaster). Anyway, as soon as I find something new I'll keep you posted. hwinfo.txt 0 Quote
Hqnicolas Posted April 9 Author Posted April 9 (edited) On 4/8/2024 at 9:04 AM, pocosparc said: I installed the Armbian Bookworm v1.1 on the eMMC and I am still fiddling around it. Can you be the first to run video drivers on this device? https://developer.arm.com/downloads/-/mali-drivers/bifrost-kernel https://docs.mesa3d.org/download.html https://docs.mesa3d.org/drivers/panfrost.html I use it as a server without video render. But some users ask for video acceleration. Quote panfrost: /devices/platform/fde60000.gpu panfrost: module = panfrost Quote P: /devices/platform/fde60000.gpu/drm/card1 M: card1 R: 1 U: drm T: drm_minor D: c 226:1 N: dri/card1 L: 0 S: dri/by-path/platform-fde60000.gpu-card E: DEVPATH=/devices/platform/fde60000.gpu/drm/card1 E: SUBSYSTEM=drm E: DEVNAME=/dev/dri/card1 E: DEVTYPE=drm_minor E: MAJOR=226 E: MINOR=1 E: USEC_INITIALIZED=14388857 E: ID_PATH=platform-fde60000.gpu E: ID_PATH_TAG=platform-fde60000_gpu E: ID_FOR_SEAT=drm-platform-fde60000_gpu E: DEVLINKS=/dev/dri/by-path/platform-fde60000.gpu-card E: TAGS=:master-of-seat:uaccess:seat: E: CURRENT_TAGS=:master-of-seat:uaccess:seat: Quote P: /devices/platform/fde60000.gpu/drm/renderD128 M: renderD128 R: 128 U: drm T: drm_minor D: c 226:128 N: dri/renderD128 L: 0 S: dri/by-path/platform-fde60000.gpu-render E: DEVPATH=/devices/platform/fde60000.gpu/drm/renderD128 E: SUBSYSTEM=drm E: DEVNAME=/dev/dri/renderD128 E: DEVTYPE=drm_minor E: MAJOR=226 E: MINOR=128 E: USEC_INITIALIZED=14384474 E: ID_PATH=platform-fde60000.gpu E: ID_PATH_TAG=platform-fde60000_gpu E: ID_FOR_SEAT=drm-platform-fde60000_gpu E: DEVLINKS=/dev/dri/by-path/platform-fde60000.gpu-render E: TAGS=:uaccess:seat: E: CURRENT_TAGS=:uaccess:seat: Quote P: /devices/platform/fdea0000.video-codec M: fdea0000.video-codec U: platform V: hantro-vpu E: DEVPATH=/devices/platform/fdea0000.video-codec E: SUBSYSTEM=platform E: DRIVER=hantro-vpu E: OF_NAME=video-codec E: OF_FULLNAME=/video-codec@fdea0400 E: OF_COMPATIBLE_0=rockchip,rk3568-vpu E: OF_COMPATIBLE_N=1 E: MODALIAS=of:Nvideo-codecT(null)Crockchip,rk3568-vpu E: USEC_INITIALIZED=4867738 E: ID_PATH=platform-fdea0000.video-codec E: ID_PATH_TAG=platform-fdea0000_video-codec E: ID_DRIVE_FLOPPY=1 Edited April 9 by Hqnicolas 0 Quote
pocosparc Posted April 10 Posted April 10 Hi @Hqnicolas I am currently still doing some research as I found out that Bluetooth does not work and it has to do something with the UART1 line. I will first try to fetch the low-hanging fruits. Meanwhile, I replaced the debian with ubuntu image for now and I extracted all of the firmware drivers from my backup dump from the super.img file. I am attaching them to this post and they are coming from the vendor/firmware part. I currently do not know if they need to be statically or dynamically linked with the kernel. If they help in any way, we can include them in the armbian Linux. Link I have a few questions for you as well. Do we have some sort of PCBA schematics and the HW setup with the external hardware: direct pins connections, what goes via muxes, etc.? This would speed things up. I requested this from the buyer, but the chances are really low that he will send anything back. What is the latest dts version? Do we have it in the form of mnemonics and not as bare pointers in byte values (&gpio instead of some 0x8e value)? Now to the Bluetooth problem I found somewhere in this forum that someone fixed the Bluetooth by changing the TX and RX pins in the dts. Link to git commit Looking at what is currently in (I am using some rk3566-firefly-roc-pc.dts - there are multiple of them and changes are phandles for USB 2.0) and what is in the git and the version originally coming from this device show that there is a TX and RX swap in the file (maybe due to different PCB layouts and hoping that there is one bit that allows UART alternate function RX/TX swap - not sure as the datasheet for RK3566 is far from being useful). So the file should be at least changed to: bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <0x8d 0x01>; clock-names = "lpo"; device-wake-gpios = <0x8e 0x10 0x00>; host-wake-gpios = <0x8e 0x11 0x00>; shutdown-gpios = <0x8e 0x0f 0x00>; pinctrl-names = "default"; pinctrl-0 = <0x8f 0x90 0x91>; vbat-supply = <0x24>; vddio-supply = <0x92>; status = "disabled"; }; In the original dump file there is also UART8 messing around, but I am currently not sure what her role is. @Hqnicolas If you have everything setup on you side, can you quickly check this out? Or I will try to fiddle around with armbian-config and device tree entries and let's see where it gets me. 0 Quote
pocosparc Posted April 10 Posted April 10 @Hqnicolas For the graphical libraries. Where did you copy paste this commands from? I need a bit more context than that. 0 Quote
Hqnicolas Posted April 12 Author Posted April 12 (edited) On 4/10/2024 at 1:27 PM, pocosparc said: I need a bit more context than that. I have never succeded with any video or NPU drivers on this device, this is a dark spot that you can shine. On 4/10/2024 at 10:38 AM, pocosparc said: In the original dump file there is also UART8 messing around This is weird, looks like a backdoor or somebody enable all of them on kernel Quote uart8 { uart8m0-xfer { rockchip,pins = <0x02 0x16 0x02 0xb7 0x02 0x15 0x03 0xb7>; phandle = <0x99>; }; uart8m0-ctsn { rockchip,pins = <0x02 0x0a 0x03 0xb5>; phandle = <0x22d>; }; uart8m0-rtsn { rockchip,pins = <0x02 0x09 0x03 0xb5>; phandle = <0x22e>; }; uart8m1-xfer { rockchip,pins = <0x03 0x00 0x04 0xb7 0x02 0x1f 0x04 0xb7>; phandle = <0x22f>; }; }; Quote if you go ahead with UART8 You will find UART8 M0 at serial@fe6c0000 in my device is disabled, can you test it? serial@fe6c0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6c0000 0x00 0x100>; interrupts = <0x00 0x7c 0x04>; clocks = <0x0e 0x13b 0x0e 0x138>; clock-names = "baudclk\0apb_pclk"; dmas = <0x25 0x10 0x25 0x11>; pinctrl-0 = <0x99>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x10f>; }; On 4/10/2024 at 10:38 AM, pocosparc said: Or I will try to fiddle around with armbian-config and device tree entries and let's see where it gets me. We need to doit.... On 4/10/2024 at 10:38 AM, pocosparc said: but the chances are really low that he will send anything back. They don´t have it, this chinese factorys just copy and past PCB, they all use the same android software because they dont know how this device works. it´s weird what I have seen this factorys copying. https://www.instagram.com/reel/C5gRnT8P34b/?igsh=ZmkyMW54a3R2Nnpy On 4/10/2024 at 10:38 AM, pocosparc said: Do we have it in the form of mnemonics and not as bare pointers in byte values (&gpio instead of some 0x8e value)? rk3566-firefly-roc-pc.dtbrk3566-firefly-roc-pc.dts On 4/10/2024 at 10:38 AM, pocosparc said: Link to git commit This is the JianPian TV BOX You give me an idea, You can use the JianPian DTB as a base to take in byte values (&gpio) Take this as a basis: https://github.com/armbian/build/blob/main/config/boards/jp-tvbox-3566.tvb and take this as a basis: https://github.com/armbian/build/blob/main/patch/kernel/archive/rockchip64-6.6/dt/rk3566-jp-tvbox.dts @ning have tested our DTB file on JianPian device, you will just need to change the LAN, USB and bluetooth and wifi pins based on our DTB 0x8e as you can see here: https://forum.armbian.com/topic/31887-jianpian-rk3566-tv-box-8g32g-develop-log/?do=findComment&comment=176492 by this way you can enable this board on armbian repo. Edited April 12 by Hqnicolas 0 Quote
ning Posted April 13 Posted April 13 @Hqnicolas here is my tree https://github.com/zhangn1985/linux-stable/ 0 Quote
Hqnicolas Posted April 13 Author Posted April 13 (edited) On 4/6/2024 at 6:14 AM, Werner said: Press X for 'doubt'. The CP2102 cannot handle 1.5Mbaud @Werner I haven't gone crazy yet, my debug was done by Chinese CP2102 This is the driver that I'm Using and for Terminal I was using https://putty.org/ On 4/6/2024 at 12:12 AM, Hqnicolas said: Please Use a debug Tool TTL UART Baud rate: 1500000 Data bit: 8 Stop bit: 1 Parity check: none Flow control: none ☑️ CP2104 TTL Tested the original one! ☑️ CP2102 TTL Tested the chinese fake one! Edited April 13 by Hqnicolas 0 Quote
Hqnicolas Posted April 14 Author Posted April 14 (edited) ########################### EMMC: V1.2 & V1.3 Release Version ########################### @ning Thank you for your Job! I'm bring this H96MAX Board UP based on your BoardConfig! Board Bring UP! PR: https://github.com/armbian/build/pull/6494 Repo: https://github.com/hqnicolas/build/tree/main Wifi Driver: https://drive.google.com/file/d/1B1LmAylalETcnBEWiPiJHL0MjK5xlIV4/view?usp=sharing BootLoader: H96-MAX-8gb-MiniLoaderAll.bin H96-MAX-4gb-MiniLoaderAll.bin 8gb RAM SDCard = Tested 8gb RAM Emmc = Tested Kernel Versions: longterm: 6.6.27, 2024-04-13 longterm: 6.1.86, 2024-04-13 How to flash: Same as V1.1 Edited May 2 by Hqnicolas 0 Quote
pocosparc Posted April 15 Posted April 15 @Hqnicolas Nice Job! Sorry I was away for the weekend and I already see that I need to reflash the board. Well I needed to start again with the version 1.2 - I started with Bluetooth and made it work - Although still not sure what is physically written on the chip and how it behaves. I have hcy6335, which in turn should be AP6335 containing the BCM4335 and for Bluetooth BCM4339. Somehow the chip gets represented as hci0: BCM4335A0 (002.001.006) build 0000. I am attaching the hcd file to this post that needs to be copied to the /lib/firmware/brcm. I also changed the dtb for the uart1 as there is no UART1 DMA mode possible otherwise. One just needs to add the dma-names to serial@fe650000 node: serial@fe650000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe650000 0x00 0x100>; interrupts = <0x00 0x75 0x04>; clocks = <0x0e 0x11f 0x0e 0x11c>; clock-names = "baudclk\0apb_pclk"; dmas = <0x24 0x02 0x24 0x03>; dma-names = "tx\0rx"; pinctrl-0 = <0x91 0x92 0x93>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "okay"; phandle = <0x10a>; bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <0x94 0x01>; clock-names = "lpo"; device-wakeup-gpios = <0x95 0x11 0x00>; host-wakeup-gpios = <0x95 0x10 0x00>; shutdown-gpios = <0x95 0x0f 0x00>; max-speed = <0x16e360>; pinctrl-names = "default"; pinctrl-0 = <0x96 0x97 0x98>; vbat-supply = <0x23>; vddio-supply = <0x63>; }; }; These are now the dmesg logs that I am getting [ 16.268929] Bluetooth: hci0: BCM: chip id 82 [ 16.269548] Bluetooth: hci0: BCM: features 0x2f [ 16.272162] Bluetooth: hci0: BCM4335A0 [ 16.272173] Bluetooth: hci0: BCM4335A0 (002.001.006) build 0000 [ 16.274413] Bluetooth: hci0: BCM4335A0 'brcm/BCM4335A0.hcd' Patch [ 17.114840] systemd[1]: Finished Armbian memory supported logging. [ 17.152605] systemd[1]: Starting Journal Service... [ 17.299179] systemd[1]: Started Journal Service. [ 17.339995] systemd-journald[632]: Received client request to flush runtime journal. [ 17.369055] Bluetooth: hci0: BCM: features 0x2f [ 17.372008] Bluetooth: hci0: BCM4335B0 JF-LTE MurataXJ AFH_LimitPwr_EDR 2STOPBIT-0343 [ 17.372025] Bluetooth: hci0: BCM4335A0 (002.001.006) build 0353 [ 17.482709] RPC: Registered named UNIX socket transport module. [ 17.482729] RPC: Registered udp transport module. [ 17.482733] RPC: Registered tcp transport module. [ 17.482736] RPC: Registered tcp-with-tls transport module. [ 17.482740] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 18.604874] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 18.604896] Bluetooth: BNEP filters: protocol multicast [ 18.604914] Bluetooth: BNEP socket layer initialized [ 18.647499] Bluetooth: MGMT ver 1.22 ... [ 23.677339] Bluetooth: RFCOMM TTY layer initialized [ 23.677399] Bluetooth: RFCOMM socket layer initialized [ 23.677430] Bluetooth: RFCOMM ver 1.11 h96-tvbox-3566-wifi:~:% hciconfig -a hci0: Type: Primary Bus: UART BD Address: 43:35:B0:07:1F:AC ACL MTU: 1021:8 SCO MTU: 64:1 UP RUNNING RX bytes:4846 acl:0 sco:0 events:556 errors:0 TX bytes:71684 acl:0 sco:0 commands:556 errors:0 Features: 0xbf 0xfe 0xcf 0xff 0xdf 0xff 0x7b 0x87 Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3 Link policy: RSWITCH SNIFF Link mode: PERIPHERAL ACCEPT Name: 'h96-tvbox-3566-wifi' Class: 0x6c0000 Service Classes: Rendering, Capturing, Audio, Telephony Device Class: Miscellaneous, HCI Version: 4.0 (0x6) Revision: 0x161 LMP Version: 4.0 (0x6) Subversion: 0x4106 Manufacturer: Broadcom Corporation (15) h96-tvbox-3566-wifi:~:% bluetoothctl Agent registered [CHG] Controller 43:35:B0:07:1F:AC Pairable: yes [bluetooth]# show Controller 43:35:B0:07:1F:AC (public) Name: h96-tvbox-3566-wifi Alias: h96-tvbox-3566-wifi Class: 0x006c0000 Powered: yes Discoverable: no DiscoverableTimeout: 0x000000b4 Pairable: yes UUID: A/V Remote Control (0000110e-0000-1000-8000-00805f9b34fb) UUID: Handsfree Audio Gateway (0000111f-0000-1000-8000-00805f9b34fb) UUID: PnP Information (00001200-0000-1000-8000-00805f9b34fb) UUID: Audio Sink (0000110b-0000-1000-8000-00805f9b34fb) UUID: Headset (00001108-0000-1000-8000-00805f9b34fb) UUID: A/V Remote Control Target (0000110c-0000-1000-8000-00805f9b34fb) UUID: Generic Access Profile (00001800-0000-1000-8000-00805f9b34fb) UUID: Audio Source (0000110a-0000-1000-8000-00805f9b34fb) UUID: Generic Attribute Profile (00001801-0000-1000-8000-00805f9b34fb) UUID: Device Information (0000180a-0000-1000-8000-00805f9b34fb) Modalias: usb:v1D6Bp0246d0540 Discovering: no Roles: central Roles: peripheral Advertising Features: ActiveInstances: 0x00 (0) SupportedInstances: 0x05 (5) SupportedIncludes: tx-power SupportedIncludes: appearance SupportedIncludes: local-name [bluetooth]# scan on Discovery started [CHG] Controller 43:35:B0:07:1F:AC Discovering: yes [NEW] Device 4C:BA:D7:02:F5:B7 4C-BA-D7-02-F5-B7 @ning @Hqnicolas UART1 speed is set to max-speed = <1500000>; but according to the datasheet (still no clue if it is the right one) we can go up to 4 MBit/s. Another thing is the schematics that I found somewhere on the internet, but still they are using some AP6xxx wifi/BT chip. Need to dive into this, but hey, now we see the missing components needed for SD-Card slot. Heartbeat is a nice thing, but I will try to enable the backlight blue LEDs, WiFi runniung, and then try to get some HDMI audio out of this thing. BCM4335A0.hcd p562297-AP6335 datasheet_V1.3_02102014.pdf ROC-3566-PC-V10-20210419.pdf 0 Quote
Hqnicolas Posted April 15 Author Posted April 15 (edited) 1 hour ago, pocosparc said: Heartbeat is a nice thing, but I will try to enable the backlight blue LEDs This is how @ning enable the LED and InfraRed https://github.com/zhangn1985/linux-stable/commit/eb97929f95b1af3257b74528159a5d55a6409bba 1 hour ago, pocosparc said: Another thing is the schematics that I found somewhere on the internet Nice @pocosparc Now I know why this device has an battery controller enabled, that's a tablet project 1 hour ago, pocosparc said: I am attaching the hcd file to this post that needs to be copied to the /lib/firmware/brcm I don't want to add pré-compiled files to a linux repo, This way, Wifi fix will need to be an unnoficial patch. 1 hour ago, pocosparc said: dma-names = "tx\0rx"; I think this patch can be applyed by PR on armbian 1 hour ago, pocosparc said: now we see the missing components needed for SD-Card slot I just Soldered the SDCard Slot Edited April 15 by Hqnicolas 0 Quote
Hqnicolas Posted April 15 Author Posted April 15 (edited) On 4/15/2024 at 6:10 PM, pocosparc said: serial@fe650000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe650000 0x00 0x100>; interrupts = <0x00 0x75 0x04>; clocks = <0x0e 0x11f 0x0e 0x11c>; clock-names = "baudclk\0apb_pclk"; dmas = <0x24 0x02 0x24 0x03>; dma-names = "tx\0rx"; pinctrl-0 = <0x91 0x92 0x93>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "okay"; phandle = <0x10a>; Quote serial@fe650000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe650000 0x00 0x100>; interrupts = <0x00 0x75 0x04>; clocks = <0x0e 0x11f 0x0e 0x11c>; clock-names = "baudclk\0apb_pclk"; dmas = <0x25 0x02 0x25 0x03>; pinctrl-0 = <0x8a 0x8b 0x8c>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "okay"; uart-has-rtscts; phandle = <0x108>; I'm trying to figureout what you change on DTS to edit the Github PR in that way. Just add: dma-names = "tx\0rx"; as you can see: https://github.com/hqnicolas/build/blob/9d0d690fe33a022c302ac538c4ecdd3dcacb482d/patch/kernel/archive/rockchip64-6.6/overlay/rockchip-rk3568-hk-uart1.dts#L12 Other boards have the same patch and I copy it: https://github.com/hqnicolas/build/blob/main/patch/kernel/archive/rockchip64-6.6/dt/rk3566-h96-tvbox.dts about the file, I just add it to the wifi external patch: Wifi Driver: https://drive.google.com/file/d/1B1LmAylalETcnBEWiPiJHL0MjK5xlIV4/view?usp=sharing Edited April 22 by Hqnicolas 0 Quote
pocosparc Posted April 16 Posted April 16 vor 10 Stunden schrieb Hqnicolas: vor 10 Stunden schrieb pocosparc: Heartbeat is a nice thing, but I will try to enable the backlight blue LEDs This is how @ning enable the LED and InfraRed https://github.com/zhangn1985/linux-stable/commit/eb97929f95b1af3257b74528159a5d55a6409bba I will try it out. In his repo I have also seen that he implemented the right keystrokes for it. Will need to check this one. For the dts I edited it right on the machine - the file that Armbian in settingsEnv is pointing at. Can you try dmesg at your side if you see any errors that uart1 DMAs have no name and therefore it wont be active? I am not sure how this overlays work, but if I remember correctly - I read somewhere that Rockchip does not support overlays. Do you know how to turn them on? Do they need to be compiled against the "main" dtb file? Why these patches need to be external. There are already lots of dtb files in that brcm folder or in a worst case they can be setup in a special deb package, whereas the dependancies to it could be managable. I think this is the RPi way of working and if there is a driver update, you get a new "firmware" debian package. @Hqnicolas To start fiddling with the WiFi I need to recompile the whole kernel once again or is there a quicker route? 0 Quote
Hqnicolas Posted April 16 Author Posted April 16 (edited) On 4/16/2024 at 5:01 AM, pocosparc said: To start fiddling with the WiFi I need to recompile the whole kernel once again or is there a quicker route? I'm uploading all bluetooth updated images again sudo apt-get install device-tree-compiler you can: dtc -I dtb -O dts rk3566-h96-tvbox.dtb -o rk3566-h96-tvbox.dts edit the DTS file to work with wifi and reverse it: dtc -I dts -O dtb -o rk3566-h96-tvbox.dtb rk3566-h96-tvbox.dts apply it on device i think you will need to find the brcmfmac4335-sdio.firefly,rk3566-roc-pc.bin for kernel 6.6 it was working on 6.2 Edited April 19 by Hqnicolas 0 Quote
pocosparc Posted April 16 Posted April 16 vor 13 Minuten schrieb Hqnicolas: sudo apt-get install device-tree-compiler you can: dtc -I dtb -O dts h96-tv-box-3566.dtb -o h96-tv-box-3566.dts edit the DTS file to work with wifi and reverse it: dtc -I dts -O dtb -o H96-tvbox-3566-wifi.dtb H96-tvbox-3566-wifi.dts apply it on device What do you want to say with this? This is how I added the tx/rx DMA IRQ names, yes. I don't know why the overlay (if it already exists), was not active on my Rockshit device. 0 Quote
Hqnicolas Posted April 16 Author Posted April 16 2 hours ago, pocosparc said: Why these patches need to be external. There are already lots of dtb files in that brcm folder or in a worst case they can be setup in a special deb package I dont wanna take this risks with drivers, you can create a Github Pull Request to armbian too. 4 minutes ago, pocosparc said: What do you want to say with this? your wifi was working? dont need any fix? i think you wont need to change DTB anymore, just need the kernel 6 binary to brcm4335 0 Quote
pocosparc Posted April 16 Posted April 16 vor 2 Minuten schrieb Hqnicolas: your wifi was working? dont need any fix? i think you wont need to change DTB anymore, just need the kernel 6 binary to brcm4335 Yes it was working before as the kernel itself reported that the bin files are missing. Now I am not sure how the kernel was compiled. So it will automatically parse from the config and driver bin files and then create the wlan0 interface? 0 Quote
Hqnicolas Posted April 16 Author Posted April 16 (edited) 3 hours ago, pocosparc said: I read somewhere that Rockchip does not support overlays. Do you know how to turn them on? Do they need to be compiled against the "main" dtb file? I dont know about overlays I have uploaded new bluetooth images to drive @pocosparc https://forum.armbian.com/topic/28895-efforts-to-develop-firmware-for-h96-max-v56-rk3566-8g64g/?do=findComment&comment=187569 Edited April 16 by Hqnicolas 0 Quote
Hqnicolas Posted April 16 Author Posted April 16 (edited) 1 hour ago, pocosparc said: Yes it was working before as the kernel itself reported that the bin files are missing. Now I am not sure how the kernel was compiled. So it will automatically parse from the config and driver bin files and then create the wlan0 interface? at kernel 6.6 your wifi work? how? I think wifi was wrong.... thats the current DTS: Quote /dts-v1/; / { interrupt-parent = <0x01>; #address-cells = <0x02>; #size-cells = <0x02>; compatible = "anbernic,rg353p\0rockchip,rk3566"; model = "RG353P"; aliases { gpio0 = "/pinctrl/gpio@fdd60000"; gpio1 = "/pinctrl/gpio@fe740000"; gpio2 = "/pinctrl/gpio@fe750000"; gpio3 = "/pinctrl/gpio@fe760000"; gpio4 = "/pinctrl/gpio@fe770000"; i2c0 = "/i2c@fdd40000"; i2c1 = "/i2c@fe5a0000"; i2c2 = "/i2c@fe5b0000"; i2c3 = "/i2c@fe5c0000"; i2c4 = "/i2c@fe5d0000"; i2c5 = "/i2c@fe5e0000"; serial0 = "/serial@fdd50000"; serial1 = "/serial@fe650000"; serial2 = "/serial@fe660000"; serial3 = "/serial@fe670000"; serial4 = "/serial@fe680000"; serial5 = "/serial@fe690000"; serial6 = "/serial@fe6a0000"; serial7 = "/serial@fe6b0000"; serial8 = "/serial@fe6c0000"; serial9 = "/serial@fe6d0000"; spi0 = "/spi@fe610000"; spi1 = "/spi@fe620000"; spi2 = "/spi@fe630000"; spi3 = "/spi@fe640000"; mmc0 = "/mmc@fe310000"; mmc1 = "/mmc@fe2b0000"; mmc2 = "/mmc@fe2c0000"; mmc3 = "/mmc@fe000000"; }; cpus { #address-cells = <0x02>; #size-cells = <0x00>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x00>; clocks = <0x02 0x00>; #cooling-cells = <0x02>; enable-method = "psci"; operating-points-v2 = <0x03>; cpu-supply = <0x04>; phandle = <0x09>; }; cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x100>; #cooling-cells = <0x02>; enable-method = "psci"; operating-points-v2 = <0x03>; cpu-supply = <0x04>; phandle = <0x0a>; }; cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x200>; #cooling-cells = <0x02>; enable-method = "psci"; operating-points-v2 = <0x03>; cpu-supply = <0x04>; phandle = <0x0b>; }; cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x00 0x300>; #cooling-cells = <0x02>; enable-method = "psci"; operating-points-v2 = <0x03>; cpu-supply = <0x04>; phandle = <0x0c>; }; }; opp-table-0 { compatible = "operating-points-v2"; opp-shared; phandle = <0x03>; opp-408000000 { opp-hz = <0x00 0x18519600>; opp-microvolt = <0xdbba0 0xdbba0 0x118c30>; clock-latency-ns = <0x9c40>; }; opp-600000000 { opp-hz = <0x00 0x23c34600>; opp-microvolt = <0xdbba0 0xdbba0 0x118c30>; }; opp-816000000 { opp-hz = <0x00 0x30a32c00>; opp-microvolt = <0xdbba0 0xdbba0 0x118c30>; opp-suspend; }; opp-1104000000 { opp-hz = <0x00 0x41cdb400>; opp-microvolt = <0xdbba0 0xdbba0 0x118c30>; }; opp-1416000000 { opp-hz = <0x00 0x54667200>; opp-microvolt = <0xdbba0 0xdbba0 0x118c30>; }; opp-1608000000 { opp-hz = <0x00 0x5fd82200>; opp-microvolt = <0xee098 0xee098 0x118c30>; }; opp-1800000000 { opp-hz = <0x00 0x6b49d200>; opp-microvolt = <0x100590 0x100590 0x118c30>; }; }; display-subsystem { compatible = "rockchip,display-subsystem"; ports = <0x05>; phandle = <0xd3>; }; firmware { scmi { compatible = "arm,scmi-smc"; arm,smc-id = <0x82000010>; shmem = <0x06>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0xd4>; protocol@14 { reg = <0x14>; #clock-cells = <0x01>; phandle = <0x02>; }; }; }; opp-table-1 { compatible = "operating-points-v2"; phandle = <0x43>; opp-200000000 { opp-hz = <0x00 0xbebc200>; opp-microvolt = <0xc96a8>; }; opp-300000000 { opp-hz = <0x00 0x11e1a300>; opp-microvolt = <0xc96a8>; }; opp-400000000 { opp-hz = <0x00 0x17d78400>; opp-microvolt = <0xc96a8>; }; opp-600000000 { opp-hz = <0x00 0x23c34600>; opp-microvolt = <0xc96a8>; }; opp-700000000 { opp-hz = <0x00 0x29b92700>; opp-microvolt = <0xdbba0>; }; opp-800000000 { opp-hz = <0x00 0x2faf0800>; opp-microvolt = <0xf4240>; }; }; hdmi-sound { compatible = "simple-audio-card"; simple-audio-card,name = "HDMI"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <0x100>; status = "okay"; phandle = <0xd5>; simple-audio-card,codec { sound-dai = <0x07>; }; simple-audio-card,cpu { sound-dai = <0x08>; }; }; pmu { compatible = "arm,cortex-a55-pmu"; interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>; interrupt-affinity = <0x09 0x0a 0x0b 0x0c>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>; arm,no-tick-in-suspend; }; xin24m { compatible = "fixed-clock"; clock-frequency = <0x16e3600>; clock-output-names = "xin24m"; #clock-cells = <0x00>; phandle = <0x1c>; }; xin32k { compatible = "fixed-clock"; clock-frequency = <0x8000>; clock-output-names = "xin32k"; pinctrl-0 = <0x0d>; pinctrl-names = "default"; #clock-cells = <0x00>; phandle = <0xd6>; }; sram@10f000 { compatible = "mmio-sram"; reg = <0x00 0x10f000 0x00 0x100>; #address-cells = <0x01>; #size-cells = <0x01>; ranges = <0x00 0x00 0x10f000 0x100>; sram@0 { compatible = "arm,scmi-shmem"; reg = <0x00 0x100>; phandle = <0x06>; }; }; sata@fc400000 { compatible = "rockchip,rk3568-dwc-ahci\0snps,dwc-ahci"; reg = <0x00 0xfc400000 0x00 0x1000>; clocks = <0x0e 0x9b 0x0e 0x9c 0x0e 0x9d>; clock-names = "sata\0pmalive\0rxoob"; interrupts = <0x00 0x5f 0x04>; phys = <0x0f 0x01>; phy-names = "sata-phy"; ports-implemented = <0x01>; power-domains = <0x10 0x0f>; status = "disabled"; phandle = <0xd7>; }; sata@fc800000 { compatible = "rockchip,rk3568-dwc-ahci\0snps,dwc-ahci"; reg = <0x00 0xfc800000 0x00 0x1000>; clocks = <0x0e 0xa0 0x0e 0xa1 0x0e 0xa2>; clock-names = "sata\0pmalive\0rxoob"; interrupts = <0x00 0x60 0x04>; phys = <0x11 0x01>; phy-names = "sata-phy"; ports-implemented = <0x01>; power-domains = <0x10 0x0f>; status = "disabled"; phandle = <0xd8>; }; usb@fcc00000 { compatible = "rockchip,rk3568-dwc3\0snps,dwc3"; reg = <0x00 0xfcc00000 0x00 0x400000>; interrupts = <0x00 0xa9 0x04>; clocks = <0x0e 0xa6 0x0e 0xa7 0x0e 0xa5>; clock-names = "ref_clk\0suspend_clk\0bus_clk"; dr_mode = "peripheral"; phy_type = "utmi_wide"; power-domains = <0x10 0x0f>; resets = <0x0e 0x94>; snps,dis_u2_susphy_quirk; status = "okay"; phys = <0x12>; phy-names = "usb2-phy"; extcon = <0x13>; maximum-speed = "high-speed"; phandle = <0xd9>; }; usb@fd000000 { compatible = "rockchip,rk3568-dwc3\0snps,dwc3"; reg = <0x00 0xfd000000 0x00 0x400000>; interrupts = <0x00 0xaa 0x04>; clocks = <0x0e 0xa9 0x0e 0xaa 0x0e 0xa8>; clock-names = "ref_clk\0suspend_clk\0bus_clk"; dr_mode = "host"; phys = <0x14 0x0f 0x04>; phy-names = "usb2-phy\0usb3-phy"; phy_type = "utmi_wide"; power-domains = <0x10 0x0f>; resets = <0x0e 0x95>; snps,dis_u2_susphy_quirk; status = "okay"; phandle = <0xda>; }; interrupt-controller@fd400000 { compatible = "arm,gic-v3"; reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0x80000>; interrupts = <0x01 0x09 0x04>; interrupt-controller; #interrupt-cells = <0x03>; mbi-alias = <0x00 0xfd410000>; mbi-ranges = <0x128 0x18>; msi-controller; phandle = <0x01>; }; usb@fd800000 { compatible = "generic-ehci"; reg = <0x00 0xfd800000 0x00 0x40000>; interrupts = <0x00 0x82 0x04>; clocks = <0x0e 0xbd 0x0e 0xbe 0x0e 0xbc>; phys = <0x15>; phy-names = "usb"; status = "disabled"; phandle = <0xdb>; }; usb@fd840000 { compatible = "generic-ohci"; reg = <0x00 0xfd840000 0x00 0x40000>; interrupts = <0x00 0x83 0x04>; clocks = <0x0e 0xbd 0x0e 0xbe 0x0e 0xbc>; phys = <0x15>; phy-names = "usb"; status = "disabled"; phandle = <0xdc>; }; usb@fd880000 { compatible = "generic-ehci"; reg = <0x00 0xfd880000 0x00 0x40000>; interrupts = <0x00 0x85 0x04>; clocks = <0x0e 0xbf 0x0e 0xc0 0x0e 0xbc>; phys = <0x14>; phy-names = "usb"; status = "okay"; phandle = <0xdd>; }; usb@fd8c0000 { compatible = "generic-ohci"; reg = <0x00 0xfd8c0000 0x00 0x40000>; interrupts = <0x00 0x86 0x04>; clocks = <0x0e 0xbf 0x0e 0xc0 0x0e 0xbc>; phys = <0x14>; phy-names = "usb"; status = "okay"; phandle = <0xde>; }; syscon@fdc20000 { compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; reg = <0x00 0xfdc20000 0x00 0x10000>; phandle = <0xb4>; io-domains { compatible = "rockchip,rk3568-pmu-io-voltage-domain"; status = "okay"; pmuio1-supply = <0x16>; pmuio2-supply = <0x16>; vccio1-supply = <0x17>; vccio3-supply = <0x18>; vccio4-supply = <0x19>; vccio5-supply = <0x1a>; vccio6-supply = <0x1b>; vccio7-supply = <0x1a>; phandle = <0xdf>; }; }; syscon@fdc50000 { reg = <0x00 0xfdc50000 0x00 0x1000>; compatible = "rockchip,rk3566-pipe-grf\0syscon"; phandle = <0xaf>; }; syscon@fdc60000 { compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; reg = <0x00 0xfdc60000 0x00 0x10000>; phandle = <0x1e>; }; syscon@fdc80000 { compatible = "rockchip,rk3568-pipe-phy-grf\0syscon"; reg = <0x00 0xfdc80000 0x00 0x1000>; phandle = <0xb0>; }; syscon@fdc90000 { compatible = "rockchip,rk3568-pipe-phy-grf\0syscon"; reg = <0x00 0xfdc90000 0x00 0x1000>; phandle = <0xb1>; }; syscon@fdca0000 { compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; reg = <0x00 0xfdca0000 0x00 0x8000>; phandle = <0xb2>; }; syscon@fdca8000 { compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; reg = <0x00 0xfdca8000 0x00 0x8000>; phandle = <0xb3>; }; clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x00 0xfdd00000 0x00 0x1000>; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x1d>; }; clock-controller@fdd20000 { compatible = "rockchip,rk3568-cru"; reg = <0x00 0xfdd20000 0x00 0x1000>; clocks = <0x1c>; clock-names = "xin24m"; #clock-cells = <0x01>; #reset-cells = <0x01>; assigned-clocks = <0x1d 0x05 0x0e 0x04 0x1d 0x01 0x0e 0x05>; assigned-clock-rates = <0x8000 0x47868c00 0xbebc200 0xe64ff60>; assigned-clock-parents = <0x1d 0x08>; rockchip,grf = <0x1e>; phandle = <0x0e>; }; i2c@fdd40000 { compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; reg = <0x00 0xfdd40000 0x00 0x1000>; interrupts = <0x00 0x2e 0x04>; clocks = <0x1d 0x07 0x1d 0x2d>; clock-names = "i2c\0pclk"; pinctrl-0 = <0x1f>; pinctrl-names = "default"; #address-cells = <0x01>; #size-cells = <0x00>; status = "okay"; phandle = <0xe0>; pmic@20 { compatible = "rockchip,rk817"; reg = <0x20>; interrupt-parent = <0x20>; interrupts = <0x03 0x08>; clock-output-names = "rk808-clkout1\0rk808-clkout2"; clock-names = "mclk"; clocks = <0x0e 0x48>; assigned-clocks = <0x0e 0x48>; assigned-clock-parents = <0x0e 0x196>; #clock-cells = <0x01>; #sound-dai-cells = <0x00>; pinctrl-names = "default"; pinctrl-0 = <0x21 0x22>; wakeup-source; vcc1-supply = <0x23>; vcc2-supply = <0x23>; vcc3-supply = <0x23>; vcc4-supply = <0x23>; vcc5-supply = <0x23>; vcc6-supply = <0x23>; vcc7-supply = <0x23>; vcc8-supply = <0x23>; vcc9-supply = <0x24>; phandle = <0xca>; regulators { DCDC_REG1 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x7a120>; regulator-max-microvolt = <0x149970>; regulator-ramp-delay = <0x1771>; regulator-initial-mode = <0x02>; regulator-name = "vdd_logic"; phandle = <0xe1>; regulator-state-mem { regulator-off-in-suspend; regulator-suspend-microvolt = <0xdbba0>; }; }; DCDC_REG2 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x7a120>; regulator-max-microvolt = <0x149970>; regulator-ramp-delay = <0x1771>; regulator-initial-mode = <0x02>; regulator-name = "vdd_gpu"; phandle = <0x44>; regulator-state-mem { regulator-off-in-suspend; }; }; DCDC_REG3 { regulator-always-on; regulator-boot-on; regulator-initial-mode = <0x02>; regulator-name = "vcc_ddr"; phandle = <0xe2>; regulator-state-mem { regulator-on-in-suspend; }; }; DCDC_REG4 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-initial-mode = <0x02>; regulator-name = "vcc_3v3"; phandle = <0x1a>; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <0x325aa0>; }; }; LDO_REG1 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-name = "vcca1v8_pmu"; phandle = <0x4c>; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <0x1b7740>; }; }; LDO_REG2 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0xdbba0>; regulator-max-microvolt = <0xdbba0>; regulator-name = "vdda_0v9"; phandle = <0xe3>; regulator-state-mem { regulator-off-in-suspend; }; }; LDO_REG3 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0xdbba0>; regulator-max-microvolt = <0xdbba0>; regulator-name = "vdda0v9_pmu"; phandle = <0xe4>; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <0xdbba0>; }; }; LDO_REG4 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-name = "vccio_acodec"; phandle = <0x17>; regulator-state-mem { regulator-off-in-suspend; }; }; LDO_REG5 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x325aa0>; regulator-name = "vccio_sd"; phandle = <0x18>; regulator-state-mem { regulator-off-in-suspend; }; }; LDO_REG6 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-name = "vcc3v3_pmu"; phandle = <0x16>; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <0x325aa0>; }; }; LDO_REG7 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-name = "vcc_1v8"; phandle = <0x19>; regulator-state-mem { regulator-off-in-suspend; }; }; LDO_REG8 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x325aa0>; regulator-name = "vcc1v8_dvp"; phandle = <0x1b>; regulator-state-mem { regulator-off-in-suspend; }; }; LDO_REG9 { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; regulator-name = "vcc2v8_dvp"; phandle = <0xe5>; regulator-state-mem { regulator-off-in-suspend; }; }; BOOST { regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x47b760>; regulator-max-microvolt = <0x5265c0>; regulator-name = "boost"; phandle = <0x24>; regulator-state-mem { regulator-off-in-suspend; }; }; OTG_SWITCH { regulator-name = "otg_switch"; phandle = <0xe6>; regulator-state-mem { regulator-off-in-suspend; }; }; }; charger { monitored-battery = <0x25>; rockchip,resistor-sense-micro-ohms = <0x2710>; rockchip,sleep-enter-current-microamp = <0x493e0>; rockchip,sleep-filter-current-microamp = <0x186a0>; phandle = <0xe7>; }; }; regulator@40 { compatible = "fcs,fan53555"; reg = <0x40>; fcs,suspend-voltage-selector = <0x01>; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0xadf34>; regulator-max-microvolt = <0x1535b0>; regulator-name = "vdd_cpu"; regulator-ramp-delay = <0x8fc>; vin-supply = <0x23>; phandle = <0x04>; regulator-state-mem { regulator-off-in-suspend; }; }; power-monitor@62 { compatible = "cellwise,cw2015"; reg = <0x62>; status = "disabled"; }; }; serial@fdd50000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfdd50000 0x00 0x100>; interrupts = <0x00 0x74 0x04>; clocks = <0x1d 0x0b 0x1d 0x2c>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x00 0x26 0x01>; pinctrl-0 = <0x27>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0xe8>; }; pwm@fdd70000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfdd70000 0x00 0x10>; clocks = <0x1d 0x0d 0x1d 0x30>; clock-names = "pwm\0pclk"; pinctrl-0 = <0x28>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "okay"; phandle = <0xc9>; }; pwm@fdd70010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfdd70010 0x00 0x10>; clocks = <0x1d 0x0d 0x1d 0x30>; clock-names = "pwm\0pclk"; pinctrl-0 = <0x29>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0xe9>; }; pwm@fdd70020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfdd70020 0x00 0x10>; clocks = <0x1d 0x0d 0x1d 0x30>; clock-names = "pwm\0pclk"; pinctrl-0 = <0x2a>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0xea>; }; pwm@fdd70030 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfdd70030 0x00 0x10>; clocks = <0x1d 0x0d 0x1d 0x30>; clock-names = "pwm\0pclk"; pinctrl-0 = <0x2b>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0xeb>; }; power-management@fdd90000 { compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd"; reg = <0x00 0xfdd90000 0x00 0x1000>; phandle = <0xec>; power-controller { compatible = "rockchip,rk3568-power-controller"; #power-domain-cells = <0x01>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x10>; power-domain@7 { reg = <0x07>; clocks = <0x0e 0x19 0x0e 0x1a>; pm_qos = <0x2c>; #power-domain-cells = <0x00>; }; power-domain@8 { reg = <0x08>; clocks = <0x0e 0xcc 0x0e 0xcd>; pm_qos = <0x2d 0x2e 0x2f>; #power-domain-cells = <0x00>; }; power-domain@9 { reg = <0x09>; clocks = <0x0e 0xda 0x0e 0xdb 0x0e 0xdc>; pm_qos = <0x30 0x31 0x32>; #power-domain-cells = <0x00>; }; power-domain@10 { reg = <0x0a>; clocks = <0x0e 0xf1 0x0e 0xf2>; pm_qos = <0x33 0x34 0x35 0x36 0x37 0x38>; #power-domain-cells = <0x00>; }; power-domain@11 { reg = <0x0b>; clocks = <0x0e 0xed>; pm_qos = <0x39>; #power-domain-cells = <0x00>; }; power-domain@13 { clocks = <0x0e 0x107>; reg = <0x0d>; pm_qos = <0x3a>; #power-domain-cells = <0x00>; }; power-domain@14 { reg = <0x0e>; clocks = <0x0e 0x102>; pm_qos = <0x3b 0x3c 0x3d>; #power-domain-cells = <0x00>; }; power-domain@15 { reg = <0x0f>; clocks = <0x0e 0x7f>; pm_qos = <0x3e 0x3f 0x40 0x41 0x42>; #power-domain-cells = <0x00>; }; }; }; gpu@fde60000 { compatible = "rockchip,rk3568-mali\0arm,mali-bifrost"; reg = <0x00 0xfde60000 0x00 0x4000>; interrupts = <0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x27 0x04>; interrupt-names = "job\0mmu\0gpu"; clocks = <0x02 0x01 0x0e 0x1b>; clock-names = "gpu\0bus"; #cooling-cells = <0x02>; operating-points-v2 = <0x43>; power-domains = <0x10 0x07>; status = "okay"; mali-supply = <0x44>; phandle = <0xa0>; }; video-codec@fdea0400 { compatible = "rockchip,rk3568-vpu"; reg = <0x00 0xfdea0000 0x00 0x800>; interrupts = <0x00 0x8b 0x04>; interrupt-names = "vdpu"; clocks = <0x0e 0xee 0x0e 0xef>; clock-names = "aclk\0hclk"; iommus = <0x45>; power-domains = <0x10 0x0b>; phandle = <0xed>; }; iommu@fdea0800 { compatible = "rockchip,rk3568-iommu"; reg = <0x00 0xfdea0800 0x00 0x40>; interrupts = <0x00 0x8a 0x04>; clock-names = "aclk\0iface"; clocks = <0x0e 0xee 0x0e 0xef>; power-domains = <0x10 0x0b>; #iommu-cells = <0x00>; phandle = <0x45>; }; rga@fdeb0000 { compatible = "rockchip,rk3568-rga\0rockchip,rk3288-rga"; reg = <0x00 0xfdeb0000 0x00 0x180>; interrupts = <0x00 0x5a 0x04>; clocks = <0x0e 0xf3 0x0e 0xf4 0x0e 0xf5>; clock-names = "aclk\0hclk\0sclk"; resets = <0x0e 0x126 0x0e 0x124 0x0e 0x125>; reset-names = "core\0axi\0ahb"; power-domains = <0x10 0x0a>; phandle = <0xee>; }; video-codec@fdee0000 { compatible = "rockchip,rk3568-vepu"; reg = <0x00 0xfdee0000 0x00 0x800>; interrupts = <0x00 0x40 0x04>; clocks = <0x0e 0xfd 0x0e 0xfe>; clock-names = "aclk\0hclk"; iommus = <0x46>; power-domains = <0x10 0x0a>; phandle = <0xef>; }; iommu@fdee0800 { compatible = "rockchip,rk3568-iommu"; reg = <0x00 0xfdee0800 0x00 0x40>; interrupts = <0x00 0x3f 0x04>; clocks = <0x0e 0xfd 0x0e 0xfe>; clock-names = "aclk\0iface"; power-domains = <0x10 0x0a>; #iommu-cells = <0x00>; phandle = <0x46>; }; mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; reg = <0x00 0xfe000000 0x00 0x4000>; interrupts = <0x00 0x64 0x04>; clocks = <0x0e 0xc1 0x0e 0xc2 0x0e 0x18e 0x0e 0x18f>; clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; fifo-depth = <0x100>; max-frequency = <0x8f0d180>; resets = <0x0e 0xeb>; reset-names = "reset"; status = "okay"; bus-width = <0x04>; cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; mmc-pwrseq = <0x47>; non-removable; pinctrl-0 = <0x48 0x49 0x4a>; pinctrl-names = "default"; vmmc-supply = <0x4b>; vqmmc-supply = <0x4c>; phandle = <0xf0>; }; ethernet@fe010000 { compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; reg = <0x00 0xfe010000 0x00 0x10000>; interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>; interrupt-names = "macirq\0eth_wake_irq"; clocks = <0x0e 0x186 0x0e 0x189 0x0e 0x189 0x0e 0xc7 0x0e 0xc3 0x0e 0xc4 0x0e 0x189 0x0e 0xc8>; clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref"; resets = <0x0e 0xec>; reset-names = "stmmaceth"; rockchip,grf = <0x1e>; snps,axi-config = <0x4d>; snps,mixed-burst; snps,mtl-rx-config = <0x4e>; snps,mtl-tx-config = <0x4f>; snps,tso; status = "disabled"; phandle = <0xf1>; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0xf2>; }; stmmac-axi-config { snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; snps,rd_osr_lmt = <0x08>; snps,wr_osr_lmt = <0x04>; phandle = <0x4d>; }; rx-queues-config { snps,rx-queues-to-use = <0x01>; phandle = <0x4e>; queue0 { }; }; tx-queues-config { snps,tx-queues-to-use = <0x01>; phandle = <0x4f>; queue0 { }; }; }; vop@fe040000 { reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>; reg-names = "vop\0gamma-lut"; interrupts = <0x00 0x94 0x04>; clocks = <0x0e 0xdd 0x0e 0xde 0x0e 0xdf 0x0e 0xe0 0x0e 0xe1>; clock-names = "aclk\0hclk\0dclk_vp0\0dclk_vp1\0dclk_vp2"; iommus = <0x50>; power-domains = <0x10 0x09>; rockchip,grf = <0x1e>; status = "okay"; compatible = "rockchip,rk3566-vop"; assigned-clocks = <0x0e 0xdf 0x0e 0xe0>; assigned-clock-parents = <0x1d 0x02 0x0e 0x05>; phandle = <0xf3>; ports { #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0x05>; port@0 { reg = <0x00>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0xf4>; endpoint@2 { reg = <0x02>; remote-endpoint = <0x51>; phandle = <0x5e>; }; }; port@1 { reg = <0x01>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0xf5>; endpoint@4 { reg = <0x04>; remote-endpoint = <0x52>; phandle = <0x54>; }; }; port@2 { reg = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0xf6>; }; }; }; iommu@fe043e00 { compatible = "rockchip,rk3568-iommu"; reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>; interrupts = <0x00 0x94 0x04>; clocks = <0x0e 0xdd 0x0e 0xde>; clock-names = "aclk\0iface"; #iommu-cells = <0x00>; status = "okay"; phandle = <0x50>; }; dsi@fe060000 { compatible = "rockchip,rk3568-mipi-dsi\0snps,dw-mipi-dsi"; reg = <0x00 0xfe060000 0x00 0x10000>; interrupts = <0x00 0x44 0x04>; clock-names = "pclk"; clocks = <0x0e 0xe8>; phy-names = "dphy"; phys = <0x53>; power-domains = <0x10 0x09>; reset-names = "apb"; resets = <0x0e 0x110>; rockchip,grf = <0x1e>; status = "okay"; #address-cells = <0x01>; #size-cells = <0x00>; phandle = <0xf7>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; phandle = <0xf8>; endpoint { remote-endpoint = <0x54>; phandle = <0x52>; }; }; port@1 { reg = <0x01>; phandle = <0xf9>; endpoint { remote-endpoint = <0x55>; phandle = <0x5a>; }; }; }; panel@0 { compatible = "anbernic,rg353p-panel\0newvision,nv3051d"; reg = <0x00>; backlight = <0x56>; pinctrl-names = "default"; pinctrl-0 = <0x57>; reset-gpios = <0x58 0x00 0x01>; vdd-supply = <0x59>; phandle = <0xfa>; port { endpoint { remote-endpoint = <0x5a>; phandle = <0x55>; }; }; }; }; dsi@fe070000 { compatible = "rockchip,rk3568-mipi-dsi\0snps,dw-mipi-dsi"; reg = <0x00 0xfe070000 0x00 0x10000>; interrupts = <0x00 0x45 0x04>; clock-names = "pclk"; clocks = <0x0e 0xe9>; phy-names = "dphy"; phys = <0x5b>; power-domains = <0x10 0x09>; reset-names = "apb"; resets = <0x0e 0x111>; rockchip,grf = <0x1e>; status = "disabled"; phandle = <0xfb>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; phandle = <0xfc>; }; port@1 { reg = <0x01>; phandle = <0xfd>; }; }; }; hdmi@fe0a0000 { compatible = "rockchip,rk3568-dw-hdmi"; reg = <0x00 0xfe0a0000 0x00 0x20000>; interrupts = <0x00 0x2d 0x04>; clocks = <0x0e 0xe6 0x0e 0xe7 0x0e 0x193 0x1d 0x28 0x0e 0xda>; clock-names = "iahb\0isfr\0cec\0ref"; pinctrl-names = "default"; pinctrl-0 = <0x5c>; power-domains = <0x10 0x09>; reg-io-width = <0x04>; rockchip,grf = <0x1e>; #sound-dai-cells = <0x00>; status = "okay"; ddc-i2c-bus = <0x5d>; phandle = <0x07>; ports { #address-cells = <0x01>; #size-cells = <0x00>; port@0 { reg = <0x00>; phandle = <0xfe>; endpoint { remote-endpoint = <0x5e>; phandle = <0x51>; }; }; port@1 { reg = <0x01>; phandle = <0xff>; endpoint { remote-endpoint = <0x5f>; phandle = <0xc6>; }; }; }; }; qos@fe128000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe128000 0x00 0x20>; phandle = <0x2c>; }; qos@fe138080 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe138080 0x00 0x20>; phandle = <0x3b>; }; qos@fe138100 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe138100 0x00 0x20>; phandle = <0x3c>; }; qos@fe138180 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe138180 0x00 0x20>; phandle = <0x3d>; }; qos@fe148000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe148000 0x00 0x20>; phandle = <0x2d>; }; qos@fe148080 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe148080 0x00 0x20>; phandle = <0x2e>; }; qos@fe148100 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe148100 0x00 0x20>; phandle = <0x2f>; }; qos@fe150000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe150000 0x00 0x20>; phandle = <0x39>; }; qos@fe158000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe158000 0x00 0x20>; phandle = <0x33>; }; qos@fe158100 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe158100 0x00 0x20>; phandle = <0x34>; }; qos@fe158180 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe158180 0x00 0x20>; phandle = <0x35>; }; qos@fe158200 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe158200 0x00 0x20>; phandle = <0x36>; }; qos@fe158280 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe158280 0x00 0x20>; phandle = <0x37>; }; qos@fe158300 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe158300 0x00 0x20>; phandle = <0x38>; }; qos@fe180000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe180000 0x00 0x20>; phandle = <0x100>; }; qos@fe190000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe190000 0x00 0x20>; phandle = <0x3e>; }; qos@fe190280 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe190280 0x00 0x20>; phandle = <0x3f>; }; qos@fe190300 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe190300 0x00 0x20>; phandle = <0x40>; }; qos@fe190380 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe190380 0x00 0x20>; phandle = <0x41>; }; qos@fe190400 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe190400 0x00 0x20>; phandle = <0x42>; }; qos@fe198000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe198000 0x00 0x20>; phandle = <0x3a>; }; qos@fe1a8000 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe1a8000 0x00 0x20>; phandle = <0x30>; }; qos@fe1a8080 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe1a8080 0x00 0x20>; phandle = <0x31>; }; qos@fe1a8100 { compatible = "rockchip,rk3568-qos\0syscon"; reg = <0x00 0xfe1a8100 0x00 0x20>; phandle = <0x32>; }; pcie@fe260000 { compatible = "rockchip,rk3568-pcie"; reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000 0x00 0xf4000000 0x00 0x100000>; reg-names = "dbi\0apb\0config"; interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>; interrupt-names = "sys\0pmc\0msg\0legacy\0err"; bus-range = <0x00 0x0f>; clocks = <0x0e 0x81 0x0e 0x82 0x0e 0x83 0x0e 0x84 0x0e 0x85>; clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; device_type = "pci"; #interrupt-cells = <0x01>; interrupt-map-mask = <0x00 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x60 0x00 0x00 0x00 0x00 0x02 0x60 0x01 0x00 0x00 0x00 0x03 0x60 0x02 0x00 0x00 0x00 0x04 0x60 0x03>; linux,pci-domain = <0x00>; num-ib-windows = <0x06>; num-ob-windows = <0x02>; max-link-speed = <0x02>; msi-map = <0x00 0x01 0x00 0x1000>; num-lanes = <0x01>; phys = <0x11 0x02>; phy-names = "pcie-phy"; power-domains = <0x10 0x0f>; ranges = <0x1000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x2000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0x1e00000 0x3000000 0x00 0x40000000 0x03 0x00 0x00 0x40000000>; resets = <0x0e 0xa1>; reset-names = "pipe"; #address-cells = <0x03>; #size-cells = <0x02>; status = "disabled"; phandle = <0x101>; legacy-interrupt-controller { #address-cells = <0x00>; #interrupt-cells = <0x01>; interrupt-controller; interrupt-parent = <0x01>; interrupts = <0x00 0x48 0x01>; phandle = <0x60>; }; }; mmc@fe2b0000 { compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; reg = <0x00 0xfe2b0000 0x00 0x4000>; interrupts = <0x00 0x62 0x04>; clocks = <0x0e 0xb0 0x0e 0xb1 0x0e 0x18a 0x0e 0x18b>; clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; fifo-depth = <0x100>; max-frequency = <0x8f0d180>; resets = <0x0e 0xd4>; reset-names = "reset"; status = "okay"; bus-width = <0x04>; cap-sd-highspeed; cd-gpios = <0x20 0x04 0x01>; disable-wp; pinctrl-0 = <0x61 0x62 0x63 0x64>; pinctrl-names = "default"; sd-uhs-sdr104; vmmc-supply = <0x1a>; vqmmc-supply = <0x18>; phandle = <0x102>; }; mmc@fe2c0000 { compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; reg = <0x00 0xfe2c0000 0x00 0x4000>; interrupts = <0x00 0x63 0x04>; clocks = <0x0e 0xb2 0x0e 0xb3 0x0e 0x18c 0x0e 0x18d>; clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; fifo-depth = <0x100>; max-frequency = <0x8f0d180>; resets = <0x0e 0xd6>; reset-names = "reset"; status = "okay"; bus-width = <0x04>; cap-sd-highspeed; cd-gpios = <0x65 0x0a 0x01>; disable-wp; pinctrl-0 = <0x66 0x67 0x68 0x69>; pinctrl-names = "default"; sd-uhs-sdr104; vmmc-supply = <0x1a>; vqmmc-supply = <0x1b>; phandle = <0x103>; }; spi@fe300000 { compatible = "rockchip,sfc"; reg = <0x00 0xfe300000 0x00 0x4000>; interrupts = <0x00 0x65 0x04>; clocks = <0x0e 0x78 0x0e 0x76>; clock-names = "clk_sfc\0hclk_sfc"; pinctrl-0 = <0x6a>; pinctrl-names = "default"; status = "disabled"; phandle = <0x104>; }; mmc@fe310000 { compatible = "rockchip,rk3568-dwcmshc"; reg = <0x00 0xfe310000 0x00 0x10000>; interrupts = <0x00 0x13 0x04>; assigned-clocks = <0x0e 0x7b 0x0e 0x7d>; assigned-clock-rates = <0xbebc200 0x16e3600>; clocks = <0x0e 0x7c 0x0e 0x7a 0x0e 0x79 0x0e 0x7b 0x0e 0x7d>; clock-names = "core\0bus\0axi\0block\0timer"; status = "okay"; pinctrl-0 = <0x6b 0x6c 0x6d 0x6e 0x6f>; pinctrl-names = "default"; bus-width = <0x08>; mmc-hs200-1_8v; non-removable; vmmc-supply = <0x1a>; vqmmc-supply = <0x19>; phandle = <0x105>; }; crypto@fe380000 { compatible = "rockchip,rk3568-crypto"; reg = <0x00 0xfe380000 0x00 0x2000>; interrupts = <0x00 0x04 0x04>; clocks = <0x0e 0x6a 0x0e 0x6b 0x0e 0x6c>; clock-names = "aclk\0hclk\0core"; resets = <0x0e 0x69>; reset-names = "core"; status = "okay"; phandle = <0x106>; }; i2s@fe400000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe400000 0x00 0x1000>; interrupts = <0x00 0x34 0x04>; assigned-clocks = <0x0e 0x3d 0x0e 0x41>; assigned-clock-rates = <0x46cf7100 0x46cf7100>; clocks = <0x0e 0x3f 0x0e 0x43 0x0e 0x39>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x70 0x00>; dma-names = "tx"; resets = <0x0e 0x50 0x0e 0x51>; reset-names = "tx-m\0rx-m"; rockchip,grf = <0x1e>; #sound-dai-cells = <0x00>; status = "okay"; phandle = <0x08>; }; i2s@fe410000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe410000 0x00 0x1000>; interrupts = <0x00 0x35 0x04>; assigned-clocks = <0x0e 0x45 0x0e 0x49>; assigned-clock-rates = <0x46cf7100 0x46cf7100>; clocks = <0x0e 0x47 0x0e 0x4b 0x0e 0x3a>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x70 0x03 0x70 0x02>; dma-names = "rx\0tx"; resets = <0x0e 0x52 0x0e 0x53>; reset-names = "tx-m\0rx-m"; rockchip,grf = <0x1e>; pinctrl-names = "default"; pinctrl-0 = <0x71 0x72 0x73 0x74>; #sound-dai-cells = <0x00>; status = "okay"; rockchip,trcm-sync-tx-only; phandle = <0xd1>; }; i2s@fe420000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe420000 0x00 0x1000>; interrupts = <0x00 0x36 0x04>; assigned-clocks = <0x0e 0x4d>; assigned-clock-rates = <0x46cf7100>; clocks = <0x0e 0x4f 0x0e 0x4f 0x0e 0x3b>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x70 0x04 0x70 0x05>; dma-names = "tx\0rx"; resets = <0x0e 0x54>; reset-names = "tx-m"; rockchip,grf = <0x1e>; pinctrl-names = "default"; pinctrl-0 = <0x75 0x76 0x77 0x78>; #sound-dai-cells = <0x00>; status = "disabled"; phandle = <0x107>; }; i2s@fe430000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x00 0xfe430000 0x00 0x1000>; interrupts = <0x00 0x37 0x04>; clocks = <0x0e 0x53 0x0e 0x57 0x0e 0x3c>; clock-names = "mclk_tx\0mclk_rx\0hclk"; dmas = <0x70 0x06 0x70 0x07>; dma-names = "tx\0rx"; resets = <0x0e 0x55 0x0e 0x56>; reset-names = "tx-m\0rx-m"; rockchip,grf = <0x1e>; #sound-dai-cells = <0x00>; status = "disabled"; phandle = <0x108>; }; pdm@fe440000 { compatible = "rockchip,rk3568-pdm"; reg = <0x00 0xfe440000 0x00 0x1000>; interrupts = <0x00 0x4c 0x04>; clocks = <0x0e 0x5a 0x0e 0x59>; clock-names = "pdm_clk\0pdm_hclk"; dmas = <0x70 0x09>; dma-names = "rx"; pinctrl-0 = <0x79 0x7a 0x7b 0x7c 0x7d 0x7e>; pinctrl-names = "default"; resets = <0x0e 0x58>; reset-names = "pdm-m"; #sound-dai-cells = <0x00>; status = "disabled"; phandle = <0x109>; }; spdif@fe460000 { compatible = "rockchip,rk3568-spdif"; reg = <0x00 0xfe460000 0x00 0x1000>; interrupts = <0x00 0x66 0x04>; clock-names = "mclk\0hclk"; clocks = <0x0e 0x5f 0x0e 0x5c>; dmas = <0x70 0x01>; dma-names = "tx"; pinctrl-names = "default"; pinctrl-0 = <0x7f>; #sound-dai-cells = <0x00>; status = "disabled"; phandle = <0x10a>; }; dma-controller@fe530000 { compatible = "arm,pl330\0arm,primecell"; reg = <0x00 0xfe530000 0x00 0x4000>; interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04>; arm,pl330-periph-burst; clocks = <0x0e 0x10d>; clock-names = "apb_pclk"; #dma-cells = <0x01>; phandle = <0x26>; }; dma-controller@fe550000 { compatible = "arm,pl330\0arm,primecell"; reg = <0x00 0xfe550000 0x00 0x4000>; interrupts = <0x00 0x10 0x04 0x00 0x0f 0x04>; arm,pl330-periph-burst; clocks = <0x0e 0x10d>; clock-names = "apb_pclk"; #dma-cells = <0x01>; phandle = <0x70>; }; i2c@fe5a0000 { compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; reg = <0x00 0xfe5a0000 0x00 0x1000>; interrupts = <0x00 0x2f 0x04>; clocks = <0x0e 0x148 0x0e 0x147>; clock-names = "i2c\0pclk"; pinctrl-0 = <0x80>; pinctrl-names = "default"; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x10b>; }; i2c@fe5b0000 { compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; reg = <0x00 0xfe5b0000 0x00 0x1000>; interrupts = <0x00 0x30 0x04>; clocks = <0x0e 0x14a 0x0e 0x149>; clock-names = "i2c\0pclk"; pinctrl-0 = <0x81>; pinctrl-names = "default"; #address-cells = <0x01>; #size-cells = <0x00>; status = "okay"; pintctrl-names = "default"; phandle = <0x10c>; touch@1a { compatible = "hynitron,cst340"; reg = <0x1a>; interrupt-parent = <0x58>; interrupts = <0x09 0x02>; pinctrl-0 = <0x82>; pinctrl-names = "default"; reset-gpios = <0x58 0x06 0x01>; touchscreen-size-x = <0x280>; touchscreen-size-y = <0x1e0>; }; }; i2c@fe5c0000 { compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; reg = <0x00 0xfe5c0000 0x00 0x1000>; interrupts = <0x00 0x31 0x04>; clocks = <0x0e 0x14c 0x0e 0x14b>; clock-names = "i2c\0pclk"; pinctrl-0 = <0x83>; pinctrl-names = "default"; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x10d>; }; i2c@fe5d0000 { compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; reg = <0x00 0xfe5d0000 0x00 0x1000>; interrupts = <0x00 0x32 0x04>; clocks = <0x0e 0x14e 0x0e 0x14d>; clock-names = "i2c\0pclk"; pinctrl-0 = <0x84>; pinctrl-names = "default"; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x10e>; }; i2c@fe5e0000 { compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; reg = <0x00 0xfe5e0000 0x00 0x1000>; interrupts = <0x00 0x33 0x04>; clocks = <0x0e 0x150 0x0e 0x14f>; clock-names = "i2c\0pclk"; pinctrl-0 = <0x85>; pinctrl-names = "default"; #address-cells = <0x01>; #size-cells = <0x00>; status = "okay"; phandle = <0x5d>; }; watchdog@fe600000 { compatible = "rockchip,rk3568-wdt\0snps,dw-wdt"; reg = <0x00 0xfe600000 0x00 0x100>; interrupts = <0x00 0x95 0x04>; clocks = <0x0e 0x116 0x0e 0x115>; clock-names = "tclk\0pclk"; phandle = <0x10f>; }; spi@fe610000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe610000 0x00 0x1000>; interrupts = <0x00 0x67 0x04>; clocks = <0x0e 0x152 0x0e 0x151>; clock-names = "spiclk\0apb_pclk"; dmas = <0x26 0x14 0x26 0x15>; dma-names = "tx\0rx"; pinctrl-names = "default"; pinctrl-0 = <0x86 0x87 0x88>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x110>; }; spi@fe620000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe620000 0x00 0x1000>; interrupts = <0x00 0x68 0x04>; clocks = <0x0e 0x154 0x0e 0x153>; clock-names = "spiclk\0apb_pclk"; dmas = <0x26 0x16 0x26 0x17>; dma-names = "tx\0rx"; pinctrl-names = "default"; pinctrl-0 = <0x89 0x8a 0x8b>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x111>; }; spi@fe630000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe630000 0x00 0x1000>; interrupts = <0x00 0x69 0x04>; clocks = <0x0e 0x156 0x0e 0x155>; clock-names = "spiclk\0apb_pclk"; dmas = <0x26 0x18 0x26 0x19>; dma-names = "tx\0rx"; pinctrl-names = "default"; pinctrl-0 = <0x8c 0x8d 0x8e>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x112>; }; spi@fe640000 { compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; reg = <0x00 0xfe640000 0x00 0x1000>; interrupts = <0x00 0x6a 0x04>; clocks = <0x0e 0x158 0x0e 0x157>; clock-names = "spiclk\0apb_pclk"; dmas = <0x26 0x1a 0x26 0x1b>; dma-names = "tx\0rx"; pinctrl-names = "default"; pinctrl-0 = <0x8f 0x90 0x91>; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; phandle = <0x113>; }; serial@fe650000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe650000 0x00 0x100>; interrupts = <0x00 0x75 0x04>; clocks = <0x0e 0x11f 0x0e 0x11c>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x02 0x26 0x03>; pinctrl-0 = <0x92 0x93 0x94>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "okay"; uart-has-rtscts; phandle = <0x114>; bluetooth { compatible = "realtek,rtl8821cs-bt\0realtek,rtl8723bs-bt"; device-wake-gpios = <0x58 0x04 0x00>; enable-gpios = <0x58 0x03 0x00>; host-wake-gpios = <0x58 0x05 0x00>; }; }; serial@fe660000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe660000 0x00 0x100>; interrupts = <0x00 0x76 0x04>; clocks = <0x0e 0x123 0x0e 0x120>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x04 0x26 0x05>; pinctrl-0 = <0x95>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "okay"; phandle = <0x115>; }; serial@fe670000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe670000 0x00 0x100>; interrupts = <0x00 0x77 0x04>; clocks = <0x0e 0x127 0x0e 0x124>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x06 0x26 0x07>; pinctrl-0 = <0x96>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x116>; }; serial@fe680000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe680000 0x00 0x100>; interrupts = <0x00 0x78 0x04>; clocks = <0x0e 0x12b 0x0e 0x128>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x08 0x26 0x09>; pinctrl-0 = <0x97>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x117>; }; serial@fe690000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe690000 0x00 0x100>; interrupts = <0x00 0x79 0x04>; clocks = <0x0e 0x12f 0x0e 0x12c>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x0a 0x26 0x0b>; pinctrl-0 = <0x98>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x118>; }; serial@fe6a0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6a0000 0x00 0x100>; interrupts = <0x00 0x7a 0x04>; clocks = <0x0e 0x133 0x0e 0x130>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x0c 0x26 0x0d>; pinctrl-0 = <0x99>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x119>; }; serial@fe6b0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6b0000 0x00 0x100>; interrupts = <0x00 0x7b 0x04>; clocks = <0x0e 0x137 0x0e 0x134>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x0e 0x26 0x0f>; pinctrl-0 = <0x9a>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x11a>; }; serial@fe6c0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6c0000 0x00 0x100>; interrupts = <0x00 0x7c 0x04>; clocks = <0x0e 0x13b 0x0e 0x138>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x10 0x26 0x11>; pinctrl-0 = <0x9b>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x11b>; }; serial@fe6d0000 { compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; reg = <0x00 0xfe6d0000 0x00 0x100>; interrupts = <0x00 0x7d 0x04>; clocks = <0x0e 0x13f 0x0e 0x13c>; clock-names = "baudclk\0apb_pclk"; dmas = <0x26 0x12 0x26 0x13>; pinctrl-0 = <0x9c>; pinctrl-names = "default"; reg-io-width = <0x04>; reg-shift = <0x02>; status = "disabled"; phandle = <0x11c>; }; thermal-zones { phandle = <0x11d>; cpu-thermal { polling-delay-passive = <0x64>; polling-delay = <0x3e8>; thermal-sensors = <0x9d 0x00>; phandle = <0x11e>; trips { cpu_alert0 { temperature = <0x11170>; hysteresis = <0x7d0>; type = "passive"; phandle = <0x9e>; }; cpu_alert1 { temperature = <0x124f8>; hysteresis = <0x7d0>; type = "passive"; phandle = <0x11f>; }; cpu_crit { temperature = <0x17318>; hysteresis = <0x7d0>; type = "critical"; phandle = <0x120>; }; }; cooling-maps { map0 { trip = <0x9e>; cooling-device = <0x09 0xffffffff 0xffffffff 0x0a 0xffffffff 0xffffffff 0x0b 0xffffffff 0xffffffff 0x0c 0xffffffff 0xffffffff>; }; }; }; gpu-thermal { polling-delay-passive = <0x14>; polling-delay = <0x3e8>; thermal-sensors = <0x9d 0x01>; phandle = <0x121>; trips { gpu-threshold { temperature = <0x11170>; hysteresis = <0x7d0>; type = "passive"; phandle = <0x122>; }; gpu-target { temperature = <0x124f8>; hysteresis = <0x7d0>; type = "passive"; phandle = <0x9f>; }; gpu-crit { temperature = <0x17318>; hysteresis = <0x7d0>; type = "critical"; phandle = <0x123>; }; }; cooling-maps { map0 { trip = <0x9f>; cooling-device = <0xa0 0xffffffff 0xffffffff>; }; }; }; }; tsadc@fe710000 { compatible = "rockchip,rk3568-tsadc"; reg = <0x00 0xfe710000 0x00 0x100>; interrupts = <0x00 0x73 0x04>; assigned-clocks = <0x0e 0x110 0x0e 0x111>; assigned-clock-rates = <0x1036640 0xaae60>; clocks = <0x0e 0x111 0x0e 0x10f>; clock-names = "tsadc\0apb_pclk"; resets = <0x0e 0x181 0x0e 0x182 0x0e 0x1d7>; rockchip,grf = <0x1e>; rockchip,hw-tshut-temp = <0x17318>; pinctrl-names = "init\0default\0sleep"; pinctrl-0 = <0xa1>; pinctrl-1 = <0xa2>; pinctrl-2 = <0xa1>; #thermal-sensor-cells = <0x01>; status = "okay"; rockchip,hw-tshut-mode = <0x01>; rockchip,hw-tshut-polarity = <0x00>; phandle = <0x9d>; }; saradc@fe720000 { compatible = "rockchip,rk3568-saradc\0rockchip,rk3399-saradc"; reg = <0x00 0xfe720000 0x00 0x100>; interrupts = <0x00 0x5d 0x04>; clocks = <0x0e 0x113 0x0e 0x112>; clock-names = "saradc\0apb_pclk"; resets = <0x0e 0x180>; reset-names = "saradc-apb"; #io-channel-cells = <0x01>; status = "okay"; vref-supply = <0x19>; phandle = <0xc1>; }; pwm@fe6e0000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0000 0x00 0x10>; clocks = <0x0e 0x15a 0x0e 0x159>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xa3>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "okay"; phandle = <0xcf>; }; pwm@fe6e0010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0010 0x00 0x10>; clocks = <0x0e 0x15a 0x0e 0x159>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xa4>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "okay"; phandle = <0xce>; }; pwm@fe6e0020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0020 0x00 0x10>; clocks = <0x0e 0x15a 0x0e 0x159>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xa5>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "okay"; phandle = <0xc7>; }; pwm@fe6e0030 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6e0030 0x00 0x10>; clocks = <0x0e 0x15a 0x0e 0x159>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xa6>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "okay"; phandle = <0xc8>; }; pwm@fe6f0000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0000 0x00 0x10>; clocks = <0x0e 0x15d 0x0e 0x15c>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xa7>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x124>; }; pwm@fe6f0010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0010 0x00 0x10>; clocks = <0x0e 0x15d 0x0e 0x15c>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xa8>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x125>; }; pwm@fe6f0020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0020 0x00 0x10>; clocks = <0x0e 0x15d 0x0e 0x15c>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xa9>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x126>; }; pwm@fe6f0030 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe6f0030 0x00 0x10>; clocks = <0x0e 0x15d 0x0e 0x15c>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xaa>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x127>; }; pwm@fe700000 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700000 0x00 0x10>; clocks = <0x0e 0x160 0x0e 0x15f>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xab>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x128>; }; pwm@fe700010 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700010 0x00 0x10>; clocks = <0x0e 0x160 0x0e 0x15f>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xac>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x129>; }; pwm@fe700020 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700020 0x00 0x10>; clocks = <0x0e 0x160 0x0e 0x15f>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xad>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x12a>; }; pwm@fe700030 { compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; reg = <0x00 0xfe700030 0x00 0x10>; clocks = <0x0e 0x160 0x0e 0x15f>; clock-names = "pwm\0pclk"; pinctrl-0 = <0xae>; pinctrl-names = "default"; #pwm-cells = <0x03>; status = "disabled"; phandle = <0x12b>; }; phy@fe830000 { compatible = "rockchip,rk3568-naneng-combphy"; reg = <0x00 0xfe830000 0x00 0x100>; clocks = <0x1d 0x22 0x0e 0x17d 0x0e 0x7f>; clock-names = "ref\0apb\0pipe"; assigned-clocks = <0x1d 0x22>; assigned-clock-rates = <0x5f5e100>; resets = <0x0e 0x1c7>; rockchip,pipe-grf = <0xaf>; rockchip,pipe-phy-grf = <0xb0>; #phy-cells = <0x01>; status = "okay"; phandle = <0x0f>; }; phy@fe840000 { compatible = "rockchip,rk3568-naneng-combphy"; reg = <0x00 0xfe840000 0x00 0x100>; clocks = <0x1d 0x25 0x0e 0x17e 0x0e 0x7f>; clock-names = "ref\0apb\0pipe"; assigned-clocks = <0x1d 0x25>; assigned-clock-rates = <0x5f5e100>; resets = <0x0e 0x1c9>; rockchip,pipe-grf = <0xaf>; rockchip,pipe-phy-grf = <0xb1>; #phy-cells = <0x01>; status = "disabled"; phandle = <0x11>; }; phy@fe870000 { compatible = "rockchip,rk3568-csi-dphy"; reg = <0x00 0xfe870000 0x00 0x10000>; clocks = <0x0e 0x179>; clock-names = "pclk"; #phy-cells = <0x00>; resets = <0x0e 0x1ba>; reset-names = "apb"; rockchip,grf = <0x1e>; status = "disabled"; phandle = <0x12c>; }; mipi-dphy@fe850000 { compatible = "rockchip,rk3568-dsi-dphy"; reg = <0x00 0xfe850000 0x00 0x10000>; clock-names = "ref\0pclk"; clocks = <0x1d 0x17 0x0e 0x17a>; #phy-cells = <0x00>; power-domains = <0x10 0x09>; reset-names = "apb"; resets = <0x0e 0x1bb>; status = "okay"; phandle = <0x53>; }; mipi-dphy@fe860000 { compatible = "rockchip,rk3568-dsi-dphy"; reg = <0x00 0xfe860000 0x00 0x10000>; clock-names = "ref\0pclk"; clocks = <0x1d 0x19 0x0e 0x17b>; #phy-cells = <0x00>; power-domains = <0x10 0x09>; reset-names = "apb"; resets = <0x0e 0x1bc>; status = "disabled"; phandle = <0x5b>; }; usb2phy@fe8a0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x00 0xfe8a0000 0x00 0x10000>; clocks = <0x1d 0x13>; clock-names = "phyclk"; clock-output-names = "clk_usbphy0_480m"; interrupts = <0x00 0x87 0x04>; rockchip,usbgrf = <0xb2>; #clock-cells = <0x00>; status = "okay"; phandle = <0x13>; host-port { #phy-cells = <0x00>; status = "disabled"; phandle = <0x12d>; }; otg-port { #phy-cells = <0x00>; status = "okay"; phandle = <0x12>; }; }; usb2phy@fe8b0000 { compatible = "rockchip,rk3568-usb2phy"; reg = <0x00 0xfe8b0000 0x00 0x10000>; clocks = <0x1d 0x15>; clock-names = "phyclk"; clock-output-names = "clk_usbphy1_480m"; interrupts = <0x00 0x88 0x04>; rockchip,usbgrf = <0xb3>; #clock-cells = <0x00>; status = "okay"; phandle = <0x12e>; host-port { #phy-cells = <0x00>; status = "okay"; phandle = <0x14>; }; otg-port { #phy-cells = <0x00>; status = "disabled"; phandle = <0x15>; }; }; pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <0x1e>; rockchip,pmu = <0xb4>; #address-cells = <0x02>; #size-cells = <0x02>; ranges; phandle = <0xb5>; gpio@fdd60000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfdd60000 0x00 0x100>; interrupts = <0x00 0x21 0x04>; clocks = <0x1d 0x2e 0x1d 0x0c>; gpio-controller; gpio-ranges = <0xb5 0x00 0x00 0x20>; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x20>; }; gpio@fe740000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe740000 0x00 0x100>; interrupts = <0x00 0x22 0x04>; clocks = <0x0e 0x163 0x0e 0x164>; gpio-controller; gpio-ranges = <0xb5 0x00 0x20 0x20>; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x12f>; }; gpio@fe750000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe750000 0x00 0x100>; interrupts = <0x00 0x23 0x04>; clocks = <0x0e 0x165 0x0e 0x166>; gpio-controller; gpio-ranges = <0xb5 0x00 0x40 0x20>; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x65>; }; gpio@fe760000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe760000 0x00 0x100>; interrupts = <0x00 0x24 0x04>; clocks = <0x0e 0x167 0x0e 0x168>; gpio-controller; gpio-ranges = <0xb5 0x00 0x60 0x20>; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0xc4>; }; gpio@fe770000 { compatible = "rockchip,gpio-bank"; reg = <0x00 0xfe770000 0x00 0x100>; interrupts = <0x00 0x25 0x04>; clocks = <0x0e 0x169 0x0e 0x16a>; gpio-controller; gpio-ranges = <0xb5 0x00 0x80 0x20>; #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; phandle = <0x58>; }; pcfg-pull-up { bias-pull-up; phandle = <0xb8>; }; pcfg-pull-down { bias-pull-down; phandle = <0x130>; }; pcfg-pull-none { bias-disable; phandle = <0xb6>; }; pcfg-pull-none-drv-level-0 { bias-disable; drive-strength = <0x00>; phandle = <0x131>; }; pcfg-pull-none-drv-level-1 { bias-disable; drive-strength = <0x01>; phandle = <0xba>; }; pcfg-pull-none-drv-level-2 { bias-disable; drive-strength = <0x02>; phandle = <0xb9>; }; pcfg-pull-none-drv-level-3 { bias-disable; drive-strength = <0x03>; phandle = <0xbd>; }; pcfg-pull-none-drv-level-4 { bias-disable; drive-strength = <0x04>; phandle = <0x132>; }; pcfg-pull-none-drv-level-5 { bias-disable; drive-strength = <0x05>; phandle = <0x133>; }; pcfg-pull-none-drv-level-6 { bias-disable; drive-strength = <0x06>; phandle = <0x134>; }; pcfg-pull-none-drv-level-7 { bias-disable; drive-strength = <0x07>; phandle = <0x135>; }; pcfg-pull-none-drv-level-8 { bias-disable; drive-strength = <0x08>; phandle = <0x136>; }; pcfg-pull-none-drv-level-9 { bias-disable; drive-strength = <0x09>; phandle = <0x137>; }; pcfg-pull-none-drv-level-10 { bias-disable; drive-strength = <0x0a>; phandle = <0x138>; }; pcfg-pull-none-drv-level-11 { bias-disable; drive-strength = <0x0b>; phandle = <0x139>; }; pcfg-pull-none-drv-level-12 { bias-disable; drive-strength = <0x0c>; phandle = <0x13a>; }; pcfg-pull-none-drv-level-13 { bias-disable; drive-strength = <0x0d>; phandle = <0x13b>; }; pcfg-pull-none-drv-level-14 { bias-disable; drive-strength = <0x0e>; phandle = <0x13c>; }; pcfg-pull-none-drv-level-15 { bias-disable; drive-strength = <0x0f>; phandle = <0x13d>; }; pcfg-pull-up-drv-level-0 { bias-pull-up; drive-strength = <0x00>; phandle = <0x13e>; }; pcfg-pull-up-drv-level-1 { bias-pull-up; drive-strength = <0x01>; phandle = <0xbc>; }; pcfg-pull-up-drv-level-2 { bias-pull-up; drive-strength = <0x02>; phandle = <0xb7>; }; pcfg-pull-up-drv-level-3 { bias-pull-up; drive-strength = <0x03>; phandle = <0x13f>; }; pcfg-pull-up-drv-level-4 { bias-pull-up; drive-strength = <0x04>; phandle = <0x140>; }; pcfg-pull-up-drv-level-5 { bias-pull-up; drive-strength = <0x05>; phandle = <0x141>; }; pcfg-pull-up-drv-level-6 { bias-pull-up; drive-strength = <0x06>; phandle = <0x142>; }; pcfg-pull-up-drv-level-7 { bias-pull-up; drive-strength = <0x07>; phandle = <0x143>; }; pcfg-pull-up-drv-level-8 { bias-pull-up; drive-strength = <0x08>; phandle = <0x144>; }; pcfg-pull-up-drv-level-9 { bias-pull-up; drive-strength = <0x09>; phandle = <0x145>; }; pcfg-pull-up-drv-level-10 { bias-pull-up; drive-strength = <0x0a>; phandle = <0x146>; }; pcfg-pull-up-drv-level-11 { bias-pull-up; drive-strength = <0x0b>; phandle = <0x147>; }; pcfg-pull-up-drv-level-12 { bias-pull-up; drive-strength = <0x0c>; phandle = <0x148>; }; pcfg-pull-up-drv-level-13 { bias-pull-up; drive-strength = <0x0d>; phandle = <0x149>; }; pcfg-pull-up-drv-level-14 { bias-pull-up; drive-strength = <0x0e>; phandle = <0x14a>; }; pcfg-pull-up-drv-level-15 { bias-pull-up; drive-strength = <0x0f>; phandle = <0x14b>; }; pcfg-pull-down-drv-level-0 { bias-pull-down; drive-strength = <0x00>; phandle = <0x14c>; }; pcfg-pull-down-drv-level-1 { bias-pull-down; drive-strength = <0x01>; phandle = <0x14d>; }; pcfg-pull-down-drv-level-2 { bias-pull-down; drive-strength = <0x02>; phandle = <0x14e>; }; pcfg-pull-down-drv-level-3 { bias-pull-down; drive-strength = <0x03>; phandle = <0x14f>; }; pcfg-pull-down-drv-level-4 { bias-pull-down; drive-strength = <0x04>; phandle = <0x150>; }; pcfg-pull-down-drv-level-5 { bias-pull-down; drive-strength = <0x05>; phandle = <0x151>; }; pcfg-pull-down-drv-level-6 { bias-pull-down; drive-strength = <0x06>; phandle = <0x152>; }; pcfg-pull-down-drv-level-7 { bias-pull-down; drive-strength = <0x07>; phandle = <0x153>; }; pcfg-pull-down-drv-level-8 { bias-pull-down; drive-strength = <0x08>; phandle = <0x154>; }; pcfg-pull-down-drv-level-9 { bias-pull-down; drive-strength = <0x09>; phandle = <0x155>; }; pcfg-pull-down-drv-level-10 { bias-pull-down; drive-strength = <0x0a>; phandle = <0x156>; }; pcfg-pull-down-drv-level-11 { bias-pull-down; drive-strength = <0x0b>; phandle = <0x157>; }; pcfg-pull-down-drv-level-12 { bias-pull-down; drive-strength = <0x0c>; phandle = <0x158>; }; pcfg-pull-down-drv-level-13 { bias-pull-down; drive-strength = <0x0d>; phandle = <0x159>; }; pcfg-pull-down-drv-level-14 { bias-pull-down; drive-strength = <0x0e>; phandle = <0x15a>; }; pcfg-pull-down-drv-level-15 { bias-pull-down; drive-strength = <0x0f>; phandle = <0x15b>; }; pcfg-pull-up-smt { bias-pull-up; input-schmitt-enable; phandle = <0x15c>; }; pcfg-pull-down-smt { bias-pull-down; input-schmitt-enable; phandle = <0x15d>; }; pcfg-pull-none-smt { bias-disable; input-schmitt-enable; phandle = <0xbb>; }; pcfg-pull-none-drv-level-0-smt { bias-disable; drive-strength = <0x00>; input-schmitt-enable; phandle = <0x15e>; }; pcfg-output-high { output-high; phandle = <0x15f>; }; pcfg-output-low { output-low; phandle = <0xbe>; }; acodec { acodec-pins { rockchip,pins = <0x01 0x09 0x05 0xb6 0x01 0x01 0x05 0xb6 0x01 0x00 0x05 0xb6 0x01 0x07 0x05 0xb6 0x01 0x08 0x05 0xb6 0x01 0x03 0x05 0xb6 0x01 0x05 0x05 0xb6>; phandle = <0x160>; }; }; audiopwm { audiopwm-lout { rockchip,pins = <0x01 0x00 0x04 0xb6>; phandle = <0x161>; }; audiopwm-loutn { rockchip,pins = <0x01 0x01 0x06 0xb6>; phandle = <0x162>; }; audiopwm-loutp { rockchip,pins = <0x01 0x00 0x06 0xb6>; phandle = <0x163>; }; audiopwm-rout { rockchip,pins = <0x01 0x01 0x04 0xb6>; phandle = <0x164>; }; audiopwm-routn { rockchip,pins = <0x01 0x07 0x04 0xb6>; phandle = <0x165>; }; audiopwm-routp { rockchip,pins = <0x01 0x06 0x04 0xb6>; phandle = <0x166>; }; }; bt656 { bt656m0-pins { rockchip,pins = <0x03 0x00 0x02 0xb6 0x02 0x18 0x02 0xb6 0x02 0x19 0x02 0xb6 0x02 0x1a 0x02 0xb6 0x02 0x1b 0x02 0xb6 0x02 0x1c 0x02 0xb6 0x02 0x1d 0x02 0xb6 0x02 0x1e 0x02 0xb6 0x02 0x1f 0x02 0xb6>; phandle = <0x167>; }; bt656m1-pins { rockchip,pins = <0x04 0x0c 0x05 0xb6 0x03 0x16 0x05 0xb6 0x03 0x17 0x05 0xb6 0x03 0x18 0x05 0xb6 0x03 0x19 0x05 0xb6 0x03 0x1a 0x05 0xb6 0x03 0x1b 0x05 0xb6 0x03 0x1c 0x05 0xb6 0x03 0x1d 0x05 0xb6>; phandle = <0x168>; }; }; bt1120 { bt1120-pins { rockchip,pins = <0x03 0x06 0x02 0xb6 0x03 0x01 0x02 0xb6 0x03 0x02 0x02 0xb6 0x03 0x03 0x02 0xb6 0x03 0x04 0x02 0xb6 0x03 0x05 0x02 0xb6 0x03 0x07 0x02 0xb6 0x03 0x08 0x02 0xb6 0x03 0x09 0x02 0xb6 0x03 0x0a 0x02 0xb6 0x03 0x0b 0x02 0xb6 0x03 0x0c 0x02 0xb6 0x03 0x0d 0x02 0xb6 0x03 0x0e 0x02 0xb6 0x03 0x11 0x02 0xb6 0x03 0x12 0x02 0xb6 0x03 0x13 0x02 0xb6>; phandle = <0x169>; }; }; cam { cam-clkout0 { rockchip,pins = <0x04 0x07 0x01 0xb6>; phandle = <0x16a>; }; cam-clkout1 { rockchip,pins = <0x04 0x08 0x01 0xb6>; phandle = <0x16b>; }; }; can0 { can0m0-pins { rockchip,pins = <0x00 0x0c 0x02 0xb6 0x00 0x0b 0x02 0xb6>; phandle = <0x16c>; }; can0m1-pins { rockchip,pins = <0x02 0x02 0x04 0xb6 0x02 0x01 0x04 0xb6>; phandle = <0x16d>; }; }; can1 { can1m0-pins { rockchip,pins = <0x01 0x00 0x03 0xb6 0x01 0x01 0x03 0xb6>; phandle = <0x16e>; }; can1m1-pins { rockchip,pins = <0x04 0x12 0x03 0xb6 0x04 0x13 0x03 0xb6>; phandle = <0x16f>; }; }; can2 { can2m0-pins { rockchip,pins = <0x04 0x0c 0x03 0xb6 0x04 0x0d 0x03 0xb6>; phandle = <0x170>; }; can2m1-pins { rockchip,pins = <0x02 0x09 0x04 0xb6 0x02 0x0a 0x04 0xb6>; phandle = <0x171>; }; }; cif { cif-clk { rockchip,pins = <0x04 0x10 0x01 0xb6>; phandle = <0x172>; }; cif-dvp-clk { rockchip,pins = <0x04 0x11 0x01 0xb6 0x04 0x0e 0x01 0xb6 0x04 0x0f 0x01 0xb6>; phandle = <0x173>; }; cif-dvp-bus16 { rockchip,pins = <0x03 0x1e 0x01 0xb6 0x03 0x1f 0x01 0xb6 0x04 0x00 0x01 0xb6 0x04 0x01 0x01 0xb6 0x04 0x02 0x01 0xb6 0x04 0x03 0x01 0xb6 0x04 0x04 0x01 0xb6 0x04 0x05 0x01 0xb6>; phandle = <0x174>; }; cif-dvp-bus8 { rockchip,pins = <0x03 0x16 0x01 0xb6 0x03 0x17 0x01 0xb6 0x03 0x18 0x01 0xb6 0x03 0x19 0x01 0xb6 0x03 0x1a 0x01 0xb6 0x03 0x1b 0x01 0xb6 0x03 0x1c 0x01 0xb6 0x03 0x1d 0x01 0xb6>; phandle = <0x175>; }; }; clk32k { clk32k-in { rockchip,pins = <0x00 0x08 0x01 0xb6>; phandle = <0x176>; }; clk32k-out0 { rockchip,pins = <0x00 0x08 0x02 0xb6>; phandle = <0x0d>; }; clk32k-out1 { rockchip,pins = <0x02 0x16 0x01 0xb6>; phandle = <0x177>; }; }; cpu { cpu-pins { rockchip,pins = <0x00 0x0f 0x02 0xb6>; phandle = <0x178>; }; }; ebc { ebc-extern { rockchip,pins = <0x04 0x07 0x02 0xb6 0x04 0x08 0x02 0xb6 0x04 0x09 0x02 0xb6 0x04 0x0d 0x02 0xb6 0x04 0x0a 0x02 0xb6>; phandle = <0x179>; }; ebc-pins { rockchip,pins = <0x04 0x10 0x02 0xb6 0x04 0x0b 0x02 0xb6 0x04 0x0c 0x02 0xb6 0x04 0x06 0x02 0xb6 0x04 0x11 0x02 0xb6 0x03 0x16 0x02 0xb6 0x03 0x17 0x02 0xb6 0x03 0x18 0x02 0xb6 0x03 0x19 0x02 0xb6 0x03 0x1a 0x02 0xb6 0x03 0x1b 0x02 0xb6 0x03 0x1c 0x02 0xb6 0x03 0x1d 0x02 0xb6 0x03 0x1e 0x02 0xb6 0x03 0x1f 0x02 0xb6 0x04 0x00 0x02 0xb6 0x04 0x01 0x02 0xb6 0x04 0x02 0x02 0xb6 0x04 0x03 0x02 0xb6 0x04 0x04 0x02 0xb6 0x04 0x05 0x02 0xb6 0x04 0x0e 0x02 0xb6 0x04 0x0f 0x02 0xb6>; phandle = <0x17a>; }; }; edpdp { edpdpm0-pins { rockchip,pins = <0x04 0x14 0x01 0xb6>; phandle = <0x17b>; }; edpdpm1-pins { rockchip,pins = <0x00 0x12 0x02 0xb6>; phandle = <0x17c>; }; }; emmc { emmc-rstnout { rockchip,pins = <0x01 0x17 0x01 0xb6>; phandle = <0x6f>; }; emmc-bus8 { rockchip,pins = <0x01 0x0c 0x01 0xb7 0x01 0x0d 0x01 0xb7 0x01 0x0e 0x01 0xb7 0x01 0x0f 0x01 0xb7 0x01 0x10 0x01 0xb7 0x01 0x11 0x01 0xb7 0x01 0x12 0x01 0xb7 0x01 0x13 0x01 0xb7>; phandle = <0x6b>; }; emmc-clk { rockchip,pins = <0x01 0x15 0x01 0xb7>; phandle = <0x6c>; }; emmc-cmd { rockchip,pins = <0x01 0x14 0x01 0xb7>; phandle = <0x6d>; }; emmc-datastrobe { rockchip,pins = <0x01 0x16 0x01 0xb6>; phandle = <0x6e>; }; }; eth0 { eth0-pins { rockchip,pins = <0x02 0x11 0x02 0xb6>; phandle = <0x17d>; }; }; eth1 { eth1m0-pins { rockchip,pins = <0x03 0x08 0x03 0xb6>; phandle = <0x17e>; }; eth1m1-pins { rockchip,pins = <0x04 0x0b 0x03 0xb6>; phandle = <0x17f>; }; }; flash { flash-pins { rockchip,pins = <0x01 0x18 0x02 0xb6 0x01 0x16 0x03 0xb6 0x01 0x1b 0x02 0xb6 0x01 0x1c 0x02 0xb6 0x01 0x0c 0x02 0xb6 0x01 0x0d 0x02 0xb6 0x01 0x0e 0x02 0xb6 0x01 0x0f 0x02 0xb6 0x01 0x10 0x02 0xb6 0x01 0x11 0x02 0xb6 0x01 0x12 0x02 0xb6 0x01 0x13 0x02 0xb6 0x01 0x15 0x02 0xb6 0x01 0x1a 0x02 0xb6 0x01 0x19 0x02 0xb6 0x00 0x07 0x01 0xb6 0x01 0x17 0x03 0xb6 0x01 0x14 0x02 0xb6>; phandle = <0x180>; }; }; fspi { fspi-pins { rockchip,pins = <0x01 0x18 0x01 0xb6 0x01 0x1b 0x01 0xb6 0x01 0x19 0x01 0xb6 0x01 0x1a 0x01 0xb6 0x01 0x17 0x02 0xb6 0x01 0x1c 0x01 0xb6>; phandle = <0x6a>; }; fspi-cs1 { rockchip,pins = <0x01 0x16 0x02 0xb8>; phandle = <0x181>; }; }; gmac0 { gmac0-miim { rockchip,pins = <0x02 0x13 0x02 0xb6 0x02 0x14 0x02 0xb6>; phandle = <0x182>; }; gmac0-clkinout { rockchip,pins = <0x02 0x12 0x02 0xb6>; phandle = <0x183>; }; gmac0-rx-er { rockchip,pins = <0x02 0x15 0x02 0xb6>; phandle = <0x184>; }; gmac0-rx-bus2 { rockchip,pins = <0x02 0x0e 0x01 0xb6 0x02 0x0f 0x02 0xb6 0x02 0x10 0x02 0xb6>; phandle = <0x185>; }; gmac0-tx-bus2 { rockchip,pins = <0x02 0x0b 0x01 0xb9 0x02 0x0c 0x01 0xb9 0x02 0x0d 0x01 0xb6>; phandle = <0x186>; }; gmac0-rgmii-clk { rockchip,pins = <0x02 0x05 0x02 0xb6 0x02 0x08 0x02 0xba>; phandle = <0x187>; }; gmac0-rgmii-bus { rockchip,pins = <0x02 0x03 0x02 0xb6 0x02 0x04 0x02 0xb6 0x02 0x06 0x02 0xb9 0x02 0x07 0x02 0xb9>; phandle = <0x188>; }; }; gmac1 { gmac1m0-miim { rockchip,pins = <0x03 0x14 0x03 0xb6 0x03 0x15 0x03 0xb6>; phandle = <0x189>; }; gmac1m0-clkinout { rockchip,pins = <0x03 0x10 0x03 0xb6>; phandle = <0x18a>; }; gmac1m0-rx-er { rockchip,pins = <0x03 0x0c 0x03 0xb6>; phandle = <0x18b>; }; gmac1m0-rx-bus2 { rockchip,pins = <0x03 0x09 0x03 0xb6 0x03 0x0a 0x03 0xb6 0x03 0x0b 0x03 0xb6>; phandle = <0x18c>; }; gmac1m0-tx-bus2 { rockchip,pins = <0x03 0x0d 0x03 0xb9 0x03 0x0e 0x03 0xb9 0x03 0x0f 0x03 0xb6>; phandle = <0x18d>; }; gmac1m0-rgmii-clk { rockchip,pins = <0x03 0x07 0x03 0xb6 0x03 0x06 0x03 0xba>; phandle = <0x18e>; }; gmac1m0-rgmii-bus { rockchip,pins = <0x03 0x04 0x03 0xb6 0x03 0x05 0x03 0xb6 0x03 0x02 0x03 0xb9 0x03 0x03 0x03 0xb9>; phandle = <0x18f>; }; gmac1m1-miim { rockchip,pins = <0x04 0x0e 0x03 0xb6 0x04 0x0f 0x03 0xb6>; phandle = <0x190>; }; gmac1m1-clkinout { rockchip,pins = <0x04 0x11 0x03 0xb6>; phandle = <0x191>; }; gmac1m1-rx-er { rockchip,pins = <0x04 0x0a 0x03 0xb6>; phandle = <0x192>; }; gmac1m1-rx-bus2 { rockchip,pins = <0x04 0x07 0x03 0xb6 0x04 0x08 0x03 0xb6 0x04 0x09 0x03 0xb6>; phandle = <0x193>; }; gmac1m1-tx-bus2 { rockchip,pins = <0x04 0x04 0x03 0xb9 0x04 0x05 0x03 0xb9 0x04 0x06 0x03 0xb6>; phandle = <0x194>; }; gmac1m1-rgmii-clk { rockchip,pins = <0x04 0x03 0x03 0xb6 0x04 0x00 0x03 0xba>; phandle = <0x195>; }; gmac1m1-rgmii-bus { rockchip,pins = <0x04 0x01 0x03 0xb6 0x04 0x02 0x03 0xb6 0x03 0x1e 0x03 0xb9 0x03 0x1f 0x03 0xb9>; phandle = <0x196>; }; }; gpu { gpu-pins { rockchip,pins = <0x00 0x10 0x02 0xb6 0x00 0x06 0x04 0xb6>; phandle = <0x197>; }; }; hdmitx { hdmitxm0-cec { rockchip,pins = <0x04 0x19 0x01 0xb6>; phandle = <0x5c>; }; hdmitxm1-cec { rockchip,pins = <0x00 0x17 0x01 0xb6>; phandle = <0x198>; }; hdmitx-scl { rockchip,pins = <0x04 0x17 0x01 0xb6>; phandle = <0x199>; }; hdmitx-sda { rockchip,pins = <0x04 0x18 0x01 0xb6>; phandle = <0x19a>; }; }; i2c0 { i2c0-xfer { rockchip,pins = <0x00 0x09 0x01 0xbb 0x00 0x0a 0x01 0xbb>; phandle = <0x1f>; }; }; i2c1 { i2c1-xfer { rockchip,pins = <0x00 0x0b 0x01 0xbb 0x00 0x0c 0x01 0xbb>; phandle = <0x80>; }; }; i2c2 { i2c2m0-xfer { rockchip,pins = <0x00 0x0d 0x01 0xbb 0x00 0x0e 0x01 0xbb>; phandle = <0x19b>; }; i2c2m1-xfer { rockchip,pins = <0x04 0x0d 0x01 0xbb 0x04 0x0c 0x01 0xbb>; phandle = <0x81>; }; }; i2c3 { i2c3m0-xfer { rockchip,pins = <0x01 0x01 0x01 0xbb 0x01 0x00 0x01 0xbb>; phandle = <0x83>; }; i2c3m1-xfer { rockchip,pins = <0x03 0x0d 0x04 0xbb 0x03 0x0e 0x04 0xbb>; phandle = <0x19c>; }; }; i2c4 { i2c4m0-xfer { rockchip,pins = <0x04 0x0b 0x01 0xbb 0x04 0x0a 0x01 0xbb>; phandle = <0x84>; }; i2c4m1-xfer { rockchip,pins = <0x02 0x0a 0x02 0xbb 0x02 0x09 0x02 0xbb>; phandle = <0x19d>; }; }; i2c5 { i2c5m0-xfer { rockchip,pins = <0x03 0x0b 0x04 0xbb 0x03 0x0c 0x04 0xbb>; phandle = <0x19e>; }; i2c5m1-xfer { rockchip,pins = <0x04 0x17 0x02 0xbb 0x04 0x18 0x02 0xbb>; phandle = <0x85>; }; }; i2s1 { i2s1m0-lrckrx { rockchip,pins = <0x01 0x06 0x01 0xb6>; phandle = <0x19f>; }; i2s1m0-lrcktx { rockchip,pins = <0x01 0x05 0x01 0xb6>; phandle = <0x72>; }; i2s1m0-mclk { rockchip,pins = <0x01 0x02 0x01 0xb6>; phandle = <0x21>; }; i2s1m0-sclkrx { rockchip,pins = <0x01 0x04 0x01 0xb6>; phandle = <0x1a0>; }; i2s1m0-sclktx { rockchip,pins = <0x01 0x03 0x01 0xb6>; phandle = <0x71>; }; i2s1m0-sdi0 { rockchip,pins = <0x01 0x0b 0x01 0xb6>; phandle = <0x73>; }; i2s1m0-sdi1 { rockchip,pins = <0x01 0x0a 0x02 0xb6>; phandle = <0x1a1>; }; i2s1m0-sdi2 { rockchip,pins = <0x01 0x09 0x02 0xb6>; phandle = <0x1a2>; }; i2s1m0-sdi3 { rockchip,pins = <0x01 0x08 0x02 0xb6>; phandle = <0x1a3>; }; i2s1m0-sdo0 { rockchip,pins = <0x01 0x07 0x01 0xb6>; phandle = <0x74>; }; i2s1m0-sdo1 { rockchip,pins = <0x01 0x08 0x01 0xb6>; phandle = <0x1a4>; }; i2s1m0-sdo2 { rockchip,pins = <0x01 0x09 0x01 0xb6>; phandle = <0x1a5>; }; i2s1m0-sdo3 { rockchip,pins = <0x01 0x0a 0x01 0xb6>; phandle = <0x1a6>; }; i2s1m1-lrckrx { rockchip,pins = <0x04 0x07 0x05 0xb6>; phandle = <0x1a7>; }; i2s1m1-lrcktx { rockchip,pins = <0x03 0x18 0x04 0xb6>; phandle = <0x1a8>; }; i2s1m1-mclk { rockchip,pins = <0x03 0x16 0x04 0xb6>; phandle = <0x1a9>; }; i2s1m1-sclkrx { rockchip,pins = <0x04 0x06 0x05 0xb6>; phandle = <0x1aa>; }; i2s1m1-sclktx { rockchip,pins = <0x03 0x17 0x04 0xb6>; phandle = <0x1ab>; }; i2s1m1-sdi0 { rockchip,pins = <0x03 0x1a 0x04 0xb6>; phandle = <0x1ac>; }; i2s1m1-sdi1 { rockchip,pins = <0x03 0x1b 0x04 0xb6>; phandle = <0x1ad>; }; i2s1m1-sdi2 { rockchip,pins = <0x03 0x1c 0x04 0xb6>; phandle = <0x1ae>; }; i2s1m1-sdi3 { rockchip,pins = <0x03 0x1d 0x04 0xb6>; phandle = <0x1af>; }; i2s1m1-sdo0 { rockchip,pins = <0x03 0x19 0x04 0xb6>; phandle = <0x1b0>; }; i2s1m1-sdo1 { rockchip,pins = <0x04 0x08 0x05 0xb6>; phandle = <0x1b1>; }; i2s1m1-sdo2 { rockchip,pins = <0x04 0x09 0x04 0xb6>; phandle = <0x1b2>; }; i2s1m1-sdo3 { rockchip,pins = <0x04 0x0d 0x04 0xb6>; phandle = <0x1b3>; }; i2s1m2-lrckrx { rockchip,pins = <0x03 0x15 0x05 0xb6>; phandle = <0x1b4>; }; i2s1m2-lrcktx { rockchip,pins = <0x02 0x1a 0x05 0xb6>; phandle = <0x1b5>; }; i2s1m2-mclk { rockchip,pins = <0x02 0x18 0x05 0xb6>; phandle = <0x1b6>; }; i2s1m2-sclkrx { rockchip,pins = <0x03 0x13 0x05 0xb6>; phandle = <0x1b7>; }; i2s1m2-sclktx { rockchip,pins = <0x02 0x19 0x05 0xb6>; phandle = <0x1b8>; }; i2s1m2-sdi0 { rockchip,pins = <0x02 0x1b 0x05 0xb6>; phandle = <0x1b9>; }; i2s1m2-sdi1 { rockchip,pins = <0x02 0x1c 0x05 0xb6>; phandle = <0x1ba>; }; i2s1m2-sdi2 { rockchip,pins = <0x02 0x1d 0x05 0xb6>; phandle = <0x1bb>; }; i2s1m2-sdi3 { rockchip,pins = <0x02 0x1e 0x05 0xb6>; phandle = <0x1bc>; }; i2s1m2-sdo0 { rockchip,pins = <0x02 0x1f 0x05 0xb6>; phandle = <0x1bd>; }; i2s1m2-sdo1 { rockchip,pins = <0x03 0x00 0x05 0xb6>; phandle = <0x1be>; }; i2s1m2-sdo2 { rockchip,pins = <0x03 0x11 0x05 0xb6>; phandle = <0x1bf>; }; i2s1m2-sdo3 { rockchip,pins = <0x03 0x12 0x05 0xb6>; phandle = <0x1c0>; }; }; i2s2 { i2s2m0-lrckrx { rockchip,pins = <0x02 0x10 0x01 0xb6>; phandle = <0x1c1>; }; i2s2m0-lrcktx { rockchip,pins = <0x02 0x13 0x01 0xb6>; phandle = <0x76>; }; i2s2m0-mclk { rockchip,pins = <0x02 0x11 0x01 0xb6>; phandle = <0x1c2>; }; i2s2m0-sclkrx { rockchip,pins = <0x02 0x0f 0x01 0xb6>; phandle = <0x1c3>; }; i2s2m0-sclktx { rockchip,pins = <0x02 0x12 0x01 0xb6>; phandle = <0x75>; }; i2s2m0-sdi { rockchip,pins = <0x02 0x15 0x01 0xb6>; phandle = <0x77>; }; i2s2m0-sdo { rockchip,pins = <0x02 0x14 0x01 0xb6>; phandle = <0x78>; }; i2s2m1-lrckrx { rockchip,pins = <0x04 0x05 0x05 0xb6>; phandle = <0x1c4>; }; i2s2m1-lrcktx { rockchip,pins = <0x04 0x04 0x05 0xb6>; phandle = <0x1c5>; }; i2s2m1-mclk { rockchip,pins = <0x04 0x0e 0x05 0xb6>; phandle = <0x1c6>; }; i2s2m1-sclkrx { rockchip,pins = <0x04 0x11 0x05 0xb6>; phandle = <0x1c7>; }; i2s2m1-sclktx { rockchip,pins = <0x04 0x0f 0x04 0xb6>; phandle = <0x1c8>; }; i2s2m1-sdi { rockchip,pins = <0x04 0x0a 0x05 0xb6>; phandle = <0x1c9>; }; i2s2m1-sdo { rockchip,pins = <0x04 0x0b 0x05 0xb6>; phandle = <0x1ca>; }; }; i2s3 { i2s3m0-lrck { rockchip,pins = <0x03 0x04 0x04 0xb6>; phandle = <0x1cb>; }; i2s3m0-mclk { rockchip,pins = <0x03 0x02 0x04 0xb6>; phandle = <0x1cc>; }; i2s3m0-sclk { rockchip,pins = <0x03 0x03 0x04 0xb6>; phandle = <0x1cd>; }; i2s3m0-sdi { rockchip,pins = <0x03 0x06 0x04 0xb6>; phandle = <0x1ce>; }; i2s3m0-sdo { rockchip,pins = <0x03 0x05 0x04 0xb6>; phandle = <0x1cf>; }; i2s3m1-lrck { rockchip,pins = <0x04 0x14 0x05 0xb6>; phandle = <0x1d0>; }; i2s3m1-mclk { rockchip,pins = <0x04 0x12 0x05 0xb6>; phandle = <0x1d1>; }; i2s3m1-sclk { rockchip,pins = <0x04 0x13 0x05 0xb6>; phandle = <0x1d2>; }; i2s3m1-sdi { rockchip,pins = <0x04 0x16 0x05 0xb6>; phandle = <0x1d3>; }; i2s3m1-sdo { rockchip,pins = <0x04 0x15 0x05 0xb6>; phandle = <0x1d4>; }; }; isp { isp-pins { rockchip,pins = <0x04 0x0c 0x04 0xb6 0x04 0x06 0x01 0xb6 0x04 0x09 0x01 0xb6>; phandle = <0x1d5>; }; }; jtag { jtag-pins { rockchip,pins = <0x01 0x1f 0x02 0xb6 0x02 0x00 0x02 0xb6>; phandle = <0x1d6>; }; }; lcdc { lcdc-ctl { rockchip,pins = <0x03 0x00 0x01 0xb6 0x02 0x18 0x01 0xb6 0x02 0x19 0x01 0xb6 0x02 0x1a 0x01 0xb6 0x02 0x1b 0x01 0xb6 0x02 0x1c 0x01 0xb6 0x02 0x1d 0x01 0xb6 0x02 0x1e 0x01 0xb6 0x02 0x1f 0x01 0xb6 0x03 0x01 0x01 0xb6 0x03 0x02 0x01 0xb6 0x03 0x03 0x01 0xb6 0x03 0x04 0x01 0xb6 0x03 0x05 0x01 0xb6 0x03 0x06 0x01 0xb6 0x03 0x07 0x01 0xb6 0x03 0x08 0x01 0xb6 0x03 0x09 0x01 0xb6 0x03 0x0a 0x01 0xb6 0x03 0x0b 0x01 0xb6 0x03 0x0c 0x01 0xb6 0x03 0x0d 0x01 0xb6 0x03 0x0e 0x01 0xb6 0x03 0x0f 0x01 0xb6 0x03 0x10 0x01 0xb6 0x03 0x13 0x01 0xb6 0x03 0x11 0x01 0xb6 0x03 0x12 0x01 0xb6>; phandle = <0x1d7>; }; lcdc-clock { rockchip,pins = <0x03 0x00 0x01 0xb6 0x03 0x13 0x01 0xb6 0x03 0x11 0x01 0xb6 0x03 0x12 0x01 0xb6>; phandle = <0x1d8>; }; lcdc-data16 { rockchip,pins = <0x02 0x1b 0x01 0xb6 0x02 0x1c 0x01 0xb6 0x02 0x1d 0x01 0xb6 0x02 0x1e 0x01 0xb6 0x02 0x1f 0x01 0xb6 0x03 0x03 0x01 0xb6 0x03 0x04 0x01 0xb6 0x03 0x05 0x01 0xb6 0x03 0x06 0x01 0xb6 0x03 0x07 0x01 0xb6 0x03 0x08 0x01 0xb6 0x03 0x0c 0x01 0xb6 0x03 0x0d 0x01 0xb6 0x03 0x0e 0x01 0xb6 0x03 0x0f 0x01 0xb6 0x03 0x10 0x01 0xb6>; phandle = <0x1d9>; }; lcdc-data18 { rockchip,pins = <0x02 0x1a 0x01 0xb6 0x02 0x1b 0x01 0xb6 0x02 0x1c 0x01 0xb6 0x02 0x1d 0x01 0xb6 0x02 0x1e 0x01 0xb6 0x02 0x1f 0x01 0xb6 0x03 0x03 0x01 0xb6 0x03 0x04 0x01 0xb6 0x03 0x05 0x01 0xb6 0x03 0x06 0x01 0xb6 0x03 0x07 0x01 0xb6 0x03 0x08 0x01 0xb6 0x03 0x0b 0x01 0xb6 0x03 0x0c 0x01 0xb6 0x03 0x0d 0x01 0xb6 0x03 0x0e 0x01 0xb6 0x03 0x0f 0x01 0xb6 0x03 0x10 0x01 0xb6>; phandle = <0x1da>; }; }; mcu { mcu-pins { rockchip,pins = <0x00 0x0c 0x04 0xb6 0x00 0x11 0x04 0xb6 0x00 0x0b 0x04 0xb6 0x00 0x12 0x04 0xb6 0x00 0x13 0x04 0xb6>; phandle = <0x1db>; }; }; npu { npu-pins { rockchip,pins = <0x00 0x11 0x02 0xb6>; phandle = <0x1dc>; }; }; pcie20 { pcie20m0-pins { rockchip,pins = <0x00 0x05 0x03 0xb6 0x00 0x0e 0x03 0xb6 0x00 0x0d 0x03 0xb6>; phandle = <0x1dd>; }; pcie20m1-pins { rockchip,pins = <0x02 0x18 0x04 0xb6 0x03 0x11 0x04 0xb6 0x02 0x19 0x04 0xb6>; phandle = <0x1de>; }; pcie20m2-pins { rockchip,pins = <0x01 0x08 0x04 0xb6 0x01 0x0a 0x04 0xb6 0x01 0x09 0x04 0xb6>; phandle = <0x1df>; }; pcie20-buttonrstn { rockchip,pins = <0x00 0x0c 0x03 0xb6>; phandle = <0x1e0>; }; }; pcie30x1 { pcie30x1m0-pins { rockchip,pins = <0x00 0x04 0x03 0xb6 0x00 0x13 0x03 0xb6 0x00 0x12 0x03 0xb6>; phandle = <0x1e1>; }; pcie30x1m1-pins { rockchip,pins = <0x02 0x1a 0x04 0xb6 0x03 0x01 0x04 0xb6 0x02 0x1b 0x04 0xb6>; phandle = <0x1e2>; }; pcie30x1m2-pins { rockchip,pins = <0x01 0x05 0x04 0xb6 0x01 0x02 0x04 0xb6 0x01 0x03 0x04 0xb6>; phandle = <0x1e3>; }; pcie30x1-buttonrstn { rockchip,pins = <0x00 0x0b 0x03 0xb6>; phandle = <0x1e4>; }; }; pcie30x2 { pcie30x2m0-pins { rockchip,pins = <0x00 0x06 0x02 0xb6 0x00 0x16 0x03 0xb6 0x00 0x15 0x03 0xb6>; phandle = <0x1e5>; }; pcie30x2m1-pins { rockchip,pins = <0x02 0x1c 0x04 0xb6 0x02 0x1e 0x04 0xb6 0x02 0x1d 0x04 0xb6>; phandle = <0x1e6>; }; pcie30x2m2-pins { rockchip,pins = <0x04 0x12 0x04 0xb6 0x04 0x14 0x04 0xb6 0x04 0x13 0x04 0xb6>; phandle = <0x1e7>; }; pcie30x2-buttonrstn { rockchip,pins = <0x00 0x08 0x03 0xb6>; phandle = <0x1e8>; }; }; pdm { pdmm0-clk { rockchip,pins = <0x01 0x06 0x03 0xb6>; phandle = <0x79>; }; pdmm0-clk1 { rockchip,pins = <0x01 0x04 0x03 0xb6>; phandle = <0x7a>; }; pdmm0-sdi0 { rockchip,pins = <0x01 0x0b 0x02 0xb6>; phandle = <0x7b>; }; pdmm0-sdi1 { rockchip,pins = <0x01 0x0a 0x03 0xb6>; phandle = <0x7c>; }; pdmm0-sdi2 { rockchip,pins = <0x01 0x09 0x03 0xb6>; phandle = <0x7d>; }; pdmm0-sdi3 { rockchip,pins = <0x01 0x08 0x03 0xb6>; phandle = <0x7e>; }; pdmm1-clk { rockchip,pins = <0x03 0x1e 0x05 0xb6>; phandle = <0x1e9>; }; pdmm1-clk1 { rockchip,pins = <0x04 0x00 0x04 0xb6>; phandle = <0x1ea>; }; pdmm1-sdi0 { rockchip,pins = <0x03 0x1f 0x05 0xb6>; phandle = <0x1eb>; }; pdmm1-sdi1 { rockchip,pins = <0x04 0x01 0x04 0xb6>; phandle = <0x1ec>; }; pdmm1-sdi2 { rockchip,pins = <0x04 0x02 0x05 0xb6>; phandle = <0x1ed>; }; pdmm1-sdi3 { rockchip,pins = <0x04 0x03 0x05 0xb6>; phandle = <0x1ee>; }; pdmm2-clk1 { rockchip,pins = <0x03 0x14 0x05 0xb6>; phandle = <0x1ef>; }; pdmm2-sdi0 { rockchip,pins = <0x03 0x0b 0x05 0xb6>; phandle = <0x1f0>; }; pdmm2-sdi1 { rockchip,pins = <0x03 0x0c 0x05 0xb6>; phandle = <0x1f1>; }; pdmm2-sdi2 { rockchip,pins = <0x03 0x0f 0x05 0xb6>; phandle = <0x1f2>; }; pdmm2-sdi3 { rockchip,pins = <0x03 0x10 0x05 0xb6>; phandle = <0x1f3>; }; }; pmic { pmic-pins { rockchip,pins = <0x00 0x02 0x01 0xb6>; phandle = <0x1f4>; }; pmic-int-l { rockchip,pins = <0x00 0x03 0x00 0xb8>; phandle = <0x22>; }; }; pmu { pmu-pins { rockchip,pins = <0x00 0x05 0x04 0xb6 0x00 0x06 0x03 0xb6 0x00 0x14 0x04 0xb6 0x00 0x15 0x04 0xb6 0x00 0x16 0x04 0xb6 0x00 0x17 0x04 0xb6>; phandle = <0x1f5>; }; }; pwm0 { pwm0m0-pins { rockchip,pins = <0x00 0x0f 0x01 0xb6>; phandle = <0x1f6>; }; pwm0m1-pins { rockchip,pins = <0x00 0x17 0x02 0xb6>; phandle = <0x28>; }; }; pwm1 { pwm1m0-pins { rockchip,pins = <0x00 0x10 0x01 0xb6>; phandle = <0x29>; }; pwm1m1-pins { rockchip,pins = <0x00 0x0d 0x04 0xb6>; phandle = <0x1f7>; }; }; pwm2 { pwm2m0-pins { rockchip,pins = <0x00 0x11 0x01 0xb6>; phandle = <0x2a>; }; pwm2m1-pins { rockchip,pins = <0x00 0x0e 0x04 0xb6>; phandle = <0x1f8>; }; }; pwm3 { pwm3-pins { rockchip,pins = <0x00 0x12 0x01 0xb6>; phandle = <0x2b>; }; }; pwm4 { pwm4-pins { rockchip,pins = <0x00 0x13 0x01 0xb6>; phandle = <0xa3>; }; }; pwm5 { pwm5-pins { rockchip,pins = <0x00 0x14 0x01 0xb6>; phandle = <0xa4>; }; }; pwm6 { pwm6-pins { rockchip,pins = <0x00 0x15 0x01 0xb6>; phandle = <0xa5>; }; }; pwm7 { pwm7-pins { rockchip,pins = <0x00 0x16 0x01 0xb6>; phandle = <0xa6>; }; }; pwm8 { pwm8m0-pins { rockchip,pins = <0x03 0x09 0x05 0xb6>; phandle = <0xa7>; }; pwm8m1-pins { rockchip,pins = <0x01 0x1d 0x04 0xb6>; phandle = <0x1f9>; }; }; pwm9 { pwm9m0-pins { rockchip,pins = <0x03 0x0a 0x05 0xb6>; phandle = <0xa8>; }; pwm9m1-pins { rockchip,pins = <0x01 0x1e 0x04 0xb6>; phandle = <0x1fa>; }; }; pwm10 { pwm10m0-pins { rockchip,pins = <0x03 0x0d 0x05 0xb6>; phandle = <0xa9>; }; pwm10m1-pins { rockchip,pins = <0x02 0x01 0x02 0xb6>; phandle = <0x1fb>; }; }; pwm11 { pwm11m0-pins { rockchip,pins = <0x03 0x0e 0x05 0xb6>; phandle = <0xaa>; }; pwm11m1-pins { rockchip,pins = <0x04 0x10 0x03 0xb6>; phandle = <0x1fc>; }; }; pwm12 { pwm12m0-pins { rockchip,pins = <0x03 0x0f 0x02 0xb6>; phandle = <0xab>; }; pwm12m1-pins { rockchip,pins = <0x04 0x15 0x01 0xb6>; phandle = <0x1fd>; }; }; pwm13 { pwm13m0-pins { rockchip,pins = <0x03 0x10 0x02 0xb6>; phandle = <0xac>; }; pwm13m1-pins { rockchip,pins = <0x04 0x16 0x01 0xb6>; phandle = <0x1fe>; }; }; pwm14 { pwm14m0-pins { rockchip,pins = <0x03 0x14 0x01 0xb6>; phandle = <0xad>; }; pwm14m1-pins { rockchip,pins = <0x04 0x12 0x01 0xb6>; phandle = <0x1ff>; }; }; pwm15 { pwm15m0-pins { rockchip,pins = <0x03 0x15 0x01 0xb6>; phandle = <0xae>; }; pwm15m1-pins { rockchip,pins = <0x04 0x13 0x01 0xb6>; phandle = <0x200>; }; }; refclk { refclk-pins { rockchip,pins = <0x00 0x00 0x01 0xb6>; phandle = <0x201>; }; }; sata { sata-pins { rockchip,pins = <0x00 0x04 0x02 0xb6 0x00 0x06 0x01 0xb6 0x00 0x05 0x02 0xb6>; phandle = <0x202>; }; }; sata0 { sata0-pins { rockchip,pins = <0x04 0x16 0x03 0xb6>; phandle = <0x203>; }; }; sata1 { sata1-pins { rockchip,pins = <0x04 0x15 0x03 0xb6>; phandle = <0x204>; }; }; sata2 { sata2-pins { rockchip,pins = <0x04 0x14 0x03 0xb6>; phandle = <0x205>; }; }; scr { scr-pins { rockchip,pins = <0x01 0x02 0x03 0xb6 0x01 0x07 0x03 0xb8 0x01 0x03 0x03 0xb8 0x01 0x05 0x03 0xb6>; phandle = <0x206>; }; }; sdmmc0 { sdmmc0-bus4 { rockchip,pins = <0x01 0x1d 0x01 0xb7 0x01 0x1e 0x01 0xb7 0x01 0x1f 0x01 0xb7 0x02 0x00 0x01 0xb7>; phandle = <0x61>; }; sdmmc0-clk { rockchip,pins = <0x02 0x02 0x01 0xb7>; phandle = <0x62>; }; sdmmc0-cmd { rockchip,pins = <0x02 0x01 0x01 0xb7>; phandle = <0x63>; }; sdmmc0-det { rockchip,pins = <0x00 0x04 0x01 0xb8>; phandle = <0x64>; }; sdmmc0-pwren { rockchip,pins = <0x00 0x05 0x01 0xb6>; phandle = <0x207>; }; }; sdmmc1 { sdmmc1-bus4 { rockchip,pins = <0x02 0x03 0x01 0xb7 0x02 0x04 0x01 0xb7 0x02 0x05 0x01 0xb7 0x02 0x06 0x01 0xb7>; phandle = <0x66>; }; sdmmc1-clk { rockchip,pins = <0x02 0x08 0x01 0xb7>; phandle = <0x68>; }; sdmmc1-cmd { rockchip,pins = <0x02 0x07 0x01 0xb7>; phandle = <0x67>; }; sdmmc1-det { rockchip,pins = <0x02 0x0a 0x01 0xb8>; phandle = <0x69>; }; sdmmc1-pwren { rockchip,pins = <0x02 0x09 0x01 0xb6>; phandle = <0x208>; }; }; sdmmc2 { sdmmc2m0-bus4 { rockchip,pins = <0x03 0x16 0x03 0xb7 0x03 0x17 0x03 0xb7 0x03 0x18 0x03 0xb7 0x03 0x19 0x03 0xb7>; phandle = <0x48>; }; sdmmc2m0-clk { rockchip,pins = <0x03 0x1b 0x03 0xb7>; phandle = <0x4a>; }; sdmmc2m0-cmd { rockchip,pins = <0x03 0x1a 0x03 0xb7>; phandle = <0x49>; }; sdmmc2m0-det { rockchip,pins = <0x03 0x1c 0x03 0xb8>; phandle = <0x209>; }; sdmmc2m0-pwren { rockchip,pins = <0x03 0x1d 0x03 0xb6>; phandle = <0x20a>; }; sdmmc2m1-bus4 { rockchip,pins = <0x03 0x01 0x05 0xb7 0x03 0x02 0x05 0xb7 0x03 0x03 0x05 0xb7 0x03 0x04 0x05 0xb7>; phandle = <0x20b>; }; sdmmc2m1-clk { rockchip,pins = <0x03 0x06 0x05 0xb7>; phandle = <0x20c>; }; sdmmc2m1-cmd { rockchip,pins = <0x03 0x05 0x05 0xb7>; phandle = <0x20d>; }; sdmmc2m1-det { rockchip,pins = <0x03 0x07 0x04 0xb8>; phandle = <0x20e>; }; sdmmc2m1-pwren { rockchip,pins = <0x03 0x08 0x04 0xb6>; phandle = <0x20f>; }; }; spdif { spdifm0-tx { rockchip,pins = <0x01 0x04 0x04 0xb6>; phandle = <0x7f>; }; spdifm1-tx { rockchip,pins = <0x03 0x15 0x02 0xb6>; phandle = <0x210>; }; spdifm2-tx { rockchip,pins = <0x04 0x14 0x02 0xb6>; phandle = <0x211>; }; }; spi0 { spi0m0-pins { rockchip,pins = <0x00 0x0d 0x02 0xb6 0x00 0x15 0x02 0xb6 0x00 0x0e 0x02 0xb6>; phandle = <0x88>; }; spi0m0-cs0 { rockchip,pins = <0x00 0x16 0x02 0xb6>; phandle = <0x86>; }; spi0m0-cs1 { rockchip,pins = <0x00 0x14 0x02 0xb6>; phandle = <0x87>; }; spi0m1-pins { rockchip,pins = <0x02 0x1b 0x03 0xb6 0x02 0x18 0x03 0xb6 0x02 0x19 0x03 0xb6>; phandle = <0x212>; }; spi0m1-cs0 { rockchip,pins = <0x02 0x1a 0x03 0xb6>; phandle = <0x213>; }; }; spi1 { spi1m0-pins { rockchip,pins = <0x02 0x0d 0x03 0xb6 0x02 0x0e 0x03 0xb6 0x02 0x0f 0x04 0xb6>; phandle = <0x8b>; }; spi1m0-cs0 { rockchip,pins = <0x02 0x10 0x04 0xb6>; phandle = <0x89>; }; spi1m0-cs1 { rockchip,pins = <0x02 0x16 0x03 0xb6>; phandle = <0x8a>; }; spi1m1-pins { rockchip,pins = <0x03 0x13 0x03 0xb6 0x03 0x12 0x03 0xb6 0x03 0x11 0x03 0xb6>; phandle = <0x214>; }; spi1m1-cs0 { rockchip,pins = <0x03 0x01 0x03 0xb6>; phandle = <0x215>; }; }; spi2 { spi2m0-pins { rockchip,pins = <0x02 0x11 0x04 0xb6 0x02 0x12 0x04 0xb6 0x02 0x13 0x04 0xb6>; phandle = <0x8e>; }; spi2m0-cs0 { rockchip,pins = <0x02 0x14 0x04 0xb6>; phandle = <0x8c>; }; spi2m0-cs1 { rockchip,pins = <0x02 0x15 0x04 0xb6>; phandle = <0x8d>; }; spi2m1-pins { rockchip,pins = <0x03 0x00 0x03 0xb6 0x02 0x1f 0x03 0xb6 0x02 0x1e 0x03 0xb6>; phandle = <0x216>; }; spi2m1-cs0 { rockchip,pins = <0x02 0x1d 0x03 0xb6>; phandle = <0x217>; }; spi2m1-cs1 { rockchip,pins = <0x02 0x1c 0x03 0xb6>; phandle = <0x218>; }; }; spi3 { spi3m0-pins { rockchip,pins = <0x04 0x0b 0x04 0xb6 0x04 0x08 0x04 0xb6 0x04 0x0a 0x04 0xb6>; phandle = <0x91>; }; spi3m0-cs0 { rockchip,pins = <0x04 0x06 0x04 0xb6>; phandle = <0x8f>; }; spi3m0-cs1 { rockchip,pins = <0x04 0x07 0x04 0xb6>; phandle = <0x90>; }; spi3m1-pins { rockchip,pins = <0x04 0x12 0x02 0xb6 0x04 0x15 0x02 0xb6 0x04 0x13 0x02 0xb6>; phandle = <0x219>; }; spi3m1-cs0 { rockchip,pins = <0x04 0x16 0x02 0xb6>; phandle = <0x21a>; }; spi3m1-cs1 { rockchip,pins = <0x04 0x19 0x02 0xb6>; phandle = <0x21b>; }; }; tsadc { tsadcm0-shut { rockchip,pins = <0x00 0x01 0x01 0xb6>; phandle = <0x21c>; }; tsadcm1-shut { rockchip,pins = <0x00 0x02 0x02 0xb6>; phandle = <0x21d>; }; tsadc-shutorg { rockchip,pins = <0x00 0x01 0x02 0xb6>; phandle = <0xa2>; }; tsadc-pin { rockchip,pins = <0x00 0x01 0x00 0xb6>; phandle = <0xa1>; }; }; uart0 { uart0-xfer { rockchip,pins = <0x00 0x10 0x03 0xb8 0x00 0x11 0x03 0xb8>; phandle = <0x27>; }; uart0-ctsn { rockchip,pins = <0x00 0x17 0x03 0xb6>; phandle = <0x21e>; }; uart0-rtsn { rockchip,pins = <0x00 0x14 0x03 0xb6>; phandle = <0x21f>; }; }; uart1 { uart1m0-xfer { rockchip,pins = <0x02 0x0b 0x02 0xb8 0x02 0x0c 0x02 0xb8>; phandle = <0x220>; }; uart1m0-ctsn { rockchip,pins = <0x02 0x0e 0x02 0xb6>; phandle = <0x221>; }; uart1m0-rtsn { rockchip,pins = <0x02 0x0d 0x02 0xb6>; phandle = <0x222>; }; uart1m1-xfer { rockchip,pins = <0x03 0x1f 0x04 0xb8 0x03 0x1e 0x04 0xb8>; phandle = <0x92>; }; uart1m1-ctsn { rockchip,pins = <0x04 0x11 0x04 0xb6>; phandle = <0x93>; }; uart1m1-rtsn { rockchip,pins = <0x04 0x0e 0x04 0xb6>; phandle = <0x94>; }; }; uart2 { uart2m0-xfer { rockchip,pins = <0x00 0x18 0x01 0xb8 0x00 0x19 0x01 0xb8>; phandle = <0x95>; }; uart2m1-xfer { rockchip,pins = <0x01 0x1e 0x02 0xb8 0x01 0x1d 0x02 0xb8>; phandle = <0x223>; }; }; uart3 { uart3m0-xfer { rockchip,pins = <0x01 0x00 0x02 0xb8 0x01 0x01 0x02 0xb8>; phandle = <0x96>; }; uart3m0-ctsn { rockchip,pins = <0x01 0x03 0x02 0xb6>; phandle = <0x224>; }; uart3m0-rtsn { rockchip,pins = <0x01 0x02 0x02 0xb6>; phandle = <0x225>; }; uart3m1-xfer { rockchip,pins = <0x03 0x10 0x04 0xb8 0x03 0x0f 0x04 0xb8>; phandle = <0x226>; }; }; uart4 { uart4m0-xfer { rockchip,pins = <0x01 0x04 0x02 0xb8 0x01 0x06 0x02 0xb8>; phandle = <0x97>; }; uart4m0-ctsn { rockchip,pins = <0x01 0x07 0x02 0xb6>; phandle = <0x227>; }; uart4m0-rtsn { rockchip,pins = <0x01 0x05 0x02 0xb6>; phandle = <0x228>; }; uart4m1-xfer { rockchip,pins = <0x03 0x09 0x04 0xb8 0x03 0x0a 0x04 0xb8>; phandle = <0x229>; }; }; uart5 { uart5m0-xfer { rockchip,pins = <0x02 0x01 0x03 0xb8 0x02 0x02 0x03 0xb8>; phandle = <0x98>; }; uart5m0-ctsn { rockchip,pins = <0x01 0x1f 0x03 0xb6>; phandle = <0x22a>; }; uart5m0-rtsn { rockchip,pins = <0x02 0x00 0x03 0xb6>; phandle = <0x22b>; }; uart5m1-xfer { rockchip,pins = <0x03 0x13 0x04 0xb8 0x03 0x12 0x04 0xb8>; phandle = <0x22c>; }; }; uart6 { uart6m0-xfer { rockchip,pins = <0x02 0x03 0x03 0xb8 0x02 0x04 0x03 0xb8>; phandle = <0x99>; }; uart6m0-ctsn { rockchip,pins = <0x02 0x10 0x03 0xb6>; phandle = <0x22d>; }; uart6m0-rtsn { rockchip,pins = <0x02 0x0f 0x03 0xb6>; phandle = <0x22e>; }; uart6m1-xfer { rockchip,pins = <0x01 0x1e 0x03 0xb8 0x01 0x1d 0x03 0xb8>; phandle = <0x22f>; }; }; uart7 { uart7m0-xfer { rockchip,pins = <0x02 0x05 0x03 0xb8 0x02 0x06 0x03 0xb8>; phandle = <0x9a>; }; uart7m0-ctsn { rockchip,pins = <0x02 0x12 0x03 0xb6>; phandle = <0x230>; }; uart7m0-rtsn { rockchip,pins = <0x02 0x11 0x03 0xb6>; phandle = <0x231>; }; uart7m1-xfer { rockchip,pins = <0x03 0x15 0x04 0xb8 0x03 0x14 0x04 0xb8>; phandle = <0x232>; }; uart7m2-xfer { rockchip,pins = <0x04 0x03 0x04 0xb8 0x04 0x02 0x04 0xb8>; phandle = <0x233>; }; }; uart8 { uart8m0-xfer { rockchip,pins = <0x02 0x16 0x02 0xb8 0x02 0x15 0x03 0xb8>; phandle = <0x9b>; }; uart8m0-ctsn { rockchip,pins = <0x02 0x0a 0x03 0xb6>; phandle = <0x234>; }; uart8m0-rtsn { rockchip,pins = <0x02 0x09 0x03 0xb6>; phandle = <0x235>; }; uart8m1-xfer { rockchip,pins = <0x03 0x00 0x04 0xb8 0x02 0x1f 0x04 0xb8>; phandle = <0x236>; }; }; uart9 { uart9m0-xfer { rockchip,pins = <0x02 0x07 0x03 0xb8 0x02 0x08 0x03 0xb8>; phandle = <0x9c>; }; uart9m0-ctsn { rockchip,pins = <0x02 0x14 0x03 0xb6>; phandle = <0x237>; }; uart9m0-rtsn { rockchip,pins = <0x02 0x13 0x03 0xb6>; phandle = <0x238>; }; uart9m1-xfer { rockchip,pins = <0x04 0x16 0x04 0xb8 0x04 0x15 0x04 0xb8>; phandle = <0x239>; }; uart9m2-xfer { rockchip,pins = <0x04 0x05 0x04 0xb8 0x04 0x04 0x04 0xb8>; phandle = <0x23a>; }; }; vop { vopm0-pins { rockchip,pins = <0x00 0x13 0x02 0xb6>; phandle = <0x23b>; }; vopm1-pins { rockchip,pins = <0x03 0x14 0x02 0xb6>; phandle = <0x23c>; }; }; spi0-hs { spi0m0-pins { rockchip,pins = <0x00 0x0d 0x02 0xbc 0x00 0x15 0x02 0xbc 0x00 0x0e 0x02 0xbc>; phandle = <0x23d>; }; spi0m0-cs0 { rockchip,pins = <0x00 0x16 0x02 0xbc>; phandle = <0x23e>; }; spi0m0-cs1 { rockchip,pins = <0x00 0x14 0x02 0xbc>; phandle = <0x23f>; }; spi0m1-pins { rockchip,pins = <0x02 0x1b 0x03 0xbc 0x02 0x18 0x03 0xbc 0x02 0x19 0x03 0xbc>; phandle = <0x240>; }; spi0m1-cs0 { rockchip,pins = <0x02 0x1a 0x03 0xbc>; phandle = <0x241>; }; }; spi1-hs { spi1m0-pins { rockchip,pins = <0x02 0x0d 0x03 0xbc 0x02 0x0e 0x03 0xbc 0x02 0x0f 0x04 0xbc>; phandle = <0x242>; }; spi1m0-cs0 { rockchip,pins = <0x02 0x10 0x04 0xbc>; phandle = <0x243>; }; spi1m0-cs1 { rockchip,pins = <0x02 0x16 0x03 0xbc>; phandle = <0x244>; }; spi1m1-pins { rockchip,pins = <0x03 0x13 0x03 0xbc 0x03 0x12 0x03 0xbc 0x03 0x11 0x03 0xbc>; phandle = <0x245>; }; spi1m1-cs0 { rockchip,pins = <0x03 0x01 0x03 0xbc>; phandle = <0x246>; }; }; spi2-hs { spi2m0-pins { rockchip,pins = <0x02 0x11 0x04 0xbc 0x02 0x12 0x04 0xbc 0x02 0x13 0x04 0xbc>; phandle = <0x247>; }; spi2m0-cs0 { rockchip,pins = <0x02 0x14 0x04 0xbc>; phandle = <0x248>; }; spi2m0-cs1 { rockchip,pins = <0x02 0x15 0x04 0xbc>; phandle = <0x249>; }; spi2m1-pins { rockchip,pins = <0x03 0x00 0x03 0xbc 0x02 0x1f 0x03 0xbc 0x02 0x1e 0x03 0xbc>; phandle = <0x24a>; }; spi2m1-cs0 { rockchip,pins = <0x02 0x1d 0x03 0xbc>; phandle = <0x24b>; }; spi2m1-cs1 { rockchip,pins = <0x02 0x1c 0x03 0xbc>; phandle = <0x24c>; }; }; spi3-hs { spi3m0-pins { rockchip,pins = <0x04 0x0b 0x04 0xbc 0x04 0x08 0x04 0xbc 0x04 0x0a 0x04 0xbc>; phandle = <0x24d>; }; spi3m0-cs0 { rockchip,pins = <0x04 0x06 0x04 0xbc>; phandle = <0x24e>; }; spi3m0-cs1 { rockchip,pins = <0x04 0x07 0x04 0xbc>; phandle = <0x24f>; }; spi3m1-pins { rockchip,pins = <0x04 0x12 0x02 0xbc 0x04 0x15 0x02 0xbc 0x04 0x13 0x02 0xbc>; phandle = <0x250>; }; spi3m1-cs0 { rockchip,pins = <0x04 0x16 0x02 0xbc>; phandle = <0x251>; }; spi3m1-cs1 { rockchip,pins = <0x04 0x19 0x02 0xbc>; phandle = <0x252>; }; }; gmac-txd-level3 { gmac0-tx-bus2-level3 { rockchip,pins = <0x02 0x0b 0x01 0xbd 0x02 0x0c 0x01 0xbd 0x02 0x0d 0x01 0xb6>; phandle = <0x253>; }; gmac0-rgmii-bus-level3 { rockchip,pins = <0x02 0x03 0x02 0xb6 0x02 0x04 0x02 0xb6 0x02 0x06 0x02 0xbd 0x02 0x07 0x02 0xbd>; phandle = <0x254>; }; gmac1m0-tx-bus2-level3 { rockchip,pins = <0x03 0x0d 0x03 0xbd 0x03 0x0e 0x03 0xbd 0x03 0x0f 0x03 0xb6>; phandle = <0x255>; }; gmac1m0-rgmii-bus-level3 { rockchip,pins = <0x03 0x04 0x03 0xb6 0x03 0x05 0x03 0xb6 0x03 0x02 0x03 0xbd 0x03 0x03 0x03 0xbd>; phandle = <0x256>; }; gmac1m1-tx-bus2-level3 { rockchip,pins = <0x04 0x04 0x03 0xbd 0x04 0x05 0x03 0xbd 0x04 0x06 0x03 0xb6>; phandle = <0x257>; }; gmac1m1-rgmii-bus-level3 { rockchip,pins = <0x04 0x01 0x03 0xb6 0x04 0x02 0x03 0xb6 0x03 0x1e 0x03 0xbd 0x03 0x1f 0x03 0xbd>; phandle = <0x258>; }; }; gmac-txc-level2 { gmac0-rgmii-clk-level2 { rockchip,pins = <0x02 0x05 0x02 0xb6 0x02 0x08 0x02 0xb9>; phandle = <0x259>; }; gmac1m0-rgmii-clk-level2 { rockchip,pins = <0x03 0x07 0x03 0xb6 0x03 0x06 0x03 0xb9>; phandle = <0x25a>; }; gmac1m1-rgmii-clk-level2 { rockchip,pins = <0x04 0x03 0x03 0xb6 0x04 0x00 0x03 0xb9>; phandle = <0x25b>; }; }; gpio-btns { btn-pins-ctrl { rockchip,pins = <0x03 0x01 0x00 0xb8 0x03 0x02 0x00 0xb8 0x03 0x03 0x00 0xb8 0x03 0x04 0x00 0xb8 0x03 0x05 0x00 0xb8 0x03 0x06 0x00 0xb8 0x03 0x09 0x00 0xb8 0x03 0x0a 0x00 0xb8 0x03 0x0b 0x00 0xb8 0x03 0x0c 0x00 0xb8 0x03 0x0d 0x00 0xb8 0x03 0x0e 0x00 0xb8 0x03 0x10 0x00 0xb8 0x03 0x11 0x00 0xb8 0x03 0x12 0x00 0xb8 0x03 0x13 0x00 0xb8>; phandle = <0xc3>; }; btn-pins-vol { rockchip,pins = <0x03 0x07 0x00 0xb8 0x03 0x08 0x00 0xb8>; phandle = <0xc5>; }; }; joy-mux { joy-mux-en { rockchip,pins = <0x00 0x0d 0x00 0xbe>; phandle = <0xc0>; }; }; sdio-pwrseq { wifi-enable-h { rockchip,pins = <0x04 0x02 0x00 0xb6>; phandle = <0xcb>; }; }; vcc3v3-lcd { vcc-lcd-h { rockchip,pins = <0x00 0x12 0x00 0xb6>; phandle = <0xcc>; }; }; vcc-wifi { vcc-wifi-h { rockchip,pins = <0x00 0x00 0x00 0xb6>; phandle = <0xcd>; }; }; gpio-lcd { lcd-rst { rockchip,pins = <0x04 0x00 0x00 0xb6>; phandle = <0x57>; }; }; audio-amplifier { spk-amp-enable-h { rockchip,pins = <0x04 0x12 0x00 0xb6>; phandle = <0xd2>; }; }; touch { touch-rst { rockchip,pins = <0x04 0x06 0x00 0xb8>; phandle = <0x82>; }; }; }; chosen { stdout-path = "serial2:1500000n8"; phandle = <0x25c>; }; adc-joystick { compatible = "adc-joystick"; io-channels = <0xbf 0x00 0xbf 0x01 0xbf 0x02 0xbf 0x03>; pinctrl-0 = <0xc0>; pinctrl-names = "default"; poll-interval = <0x3c>; #address-cells = <0x01>; #size-cells = <0x00>; axis@0 { reg = <0x00>; abs-flat = <0x20>; abs-fuzz = <0x20>; abs-range = <0x3ff 0x0f>; linux,code = <0x00>; }; axis@1 { reg = <0x01>; abs-flat = <0x20>; abs-fuzz = <0x20>; abs-range = <0x0f 0x3ff>; linux,code = <0x03>; }; axis@2 { reg = <0x02>; abs-flat = <0x20>; abs-fuzz = <0x20>; abs-range = <0x0f 0x3ff>; linux,code = <0x01>; }; axis@3 { reg = <0x03>; abs-flat = <0x20>; abs-fuzz = <0x20>; abs-range = <0x3ff 0x0f>; linux,code = <0x04>; }; }; adc-keys { compatible = "adc-keys"; io-channels = <0xc1 0x00>; io-channel-names = "buttons"; keyup-threshold-microvolt = <0x1b7740>; poll-interval = <0x3c>; phandle = <0x25d>; button-mode { label = "MODE"; linux,code = <0x13c>; press-threshold-microvolt = <0x6d6>; }; }; adc-mux { compatible = "io-channel-mux"; channels = "left_x\0right_x\0left_y\0right_y"; #io-channel-cells = <0x01>; io-channels = <0xc1 0x03>; io-channel-names = "parent"; mux-controls = <0xc2>; settle-time-us = <0x64>; phandle = <0xbf>; }; gpio-keys-control { compatible = "gpio-keys"; pinctrl-0 = <0xc3>; pinctrl-names = "default"; phandle = <0x25e>; button-b { gpios = <0xc4 0x13 0x01>; label = "SOUTH"; linux,code = <0x130>; }; button-down { gpios = <0xc4 0x04 0x01>; label = "DPAD-DOWN"; linux,code = <0x221>; }; button-l1 { gpios = <0xc4 0x09 0x01>; label = "TL"; linux,code = <0x136>; }; button-l2 { gpios = <0xc4 0x0a 0x01>; label = "TL2"; linux,code = <0x138>; }; button-select { gpios = <0xc4 0x0e 0x01>; label = "SELECT"; linux,code = <0x13a>; }; button-start { gpios = <0xc4 0x0d 0x01>; label = "START"; linux,code = <0x13b>; }; button-thumbl { gpios = <0xc4 0x01 0x01>; label = "THUMBL"; linux,code = <0x13d>; }; button-thumbr { gpios = <0xc4 0x02 0x01>; label = "THUMBR"; linux,code = <0x13e>; }; button-up { gpios = <0xc4 0x03 0x01>; label = "DPAD-UP"; linux,code = <0x220>; }; button-x { gpios = <0xc4 0x10 0x01>; label = "NORTH"; linux,code = <0x133>; }; button-a { gpios = <0xc4 0x12 0x01>; label = "EAST"; linux,code = <0x131>; }; button-left { gpios = <0xc4 0x06 0x01>; label = "DPAD-LEFT"; linux,code = <0x222>; }; button-right { gpios = <0xc4 0x05 0x01>; label = "DPAD-RIGHT"; linux,code = <0x223>; }; button-y { gpios = <0xc4 0x11 0x01>; label = "WEST"; linux,code = <0x134>; }; button-r1 { gpios = <0xc4 0x0c 0x01>; label = "TR"; linux,code = <0x137>; }; button-r2 { gpios = <0xc4 0x0b 0x01>; label = "TR2"; linux,code = <0x139>; }; }; gpio-keys-vol { compatible = "gpio-keys"; autorepeat; pinctrl-0 = <0xc5>; pinctrl-names = "default"; phandle = <0x25f>; button-vol-down { gpios = <0xc4 0x08 0x01>; label = "VOLUMEDOWN"; linux,code = <0x72>; }; button-vol-up { gpios = <0xc4 0x07 0x01>; label = "VOLUMEUP"; linux,code = <0x73>; }; }; mux-controller { compatible = "gpio-mux"; mux-gpios = <0x20 0x0e 0x01 0x20 0x0f 0x01>; #mux-control-cells = <0x00>; phandle = <0xc2>; }; hdmi-con { compatible = "hdmi-connector"; ddc-i2c-bus = <0x5d>; type = "c"; port { endpoint { remote-endpoint = <0xc6>; phandle = <0x5f>; }; }; }; pwm-leds { compatible = "pwm-leds"; phandle = <0x260>; led-0 { color = <0x02>; default-state = "on"; function = "power"; max-brightness = <0xff>; pwms = <0xc7 0x00 0x61a8 0x00>; phandle = <0x261>; }; led-1 { color = <0x04>; function = "charging"; max-brightness = <0xff>; pwms = <0xc8 0x00 0x61a8 0x00>; phandle = <0x262>; }; led-2 { color = <0x01>; default-state = "off"; function = "status"; max-brightness = <0xff>; pwms = <0xc9 0x00 0x61a8 0x00>; phandle = <0x263>; }; }; sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <0xca 0x01>; clock-names = "ext_clock"; pinctrl-0 = <0xcb>; pinctrl-names = "default"; post-power-on-delay-ms = <0xc8>; reset-gpios = <0x58 0x02 0x01>; phandle = <0x47>; }; regulator-vcc3v3-lcd0 { compatible = "regulator-fixed"; gpio = <0x20 0x12 0x00>; enable-active-high; pinctrl-0 = <0xcc>; pinctrl-names = "default"; regulator-boot-on; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-name = "vcc3v3_lcd0_n"; vin-supply = <0x1a>; phandle = <0x59>; regulator-state-mem { regulator-off-in-suspend; }; }; regulator-vcc-sys { compatible = "regulator-fixed"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x39fbc0>; regulator-max-microvolt = <0x39fbc0>; regulator-name = "vcc_sys"; phandle = <0x23>; }; regulator-vcc-wifi { compatible = "regulator-fixed"; enable-active-high; gpio = <0x20 0x00 0x00>; pinctrl-0 = <0xcd>; pinctrl-names = "default"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-name = "vcc_wifi"; phandle = <0x4b>; }; pwm-vibrator { compatible = "pwm-vibrator"; pwm-names = "enable"; pwms = <0xce 0x00 0x3b9aca00 0x00>; phandle = <0x264>; }; backlight { compatible = "pwm-backlight"; power-supply = <0x23>; pwms = <0xcf 0x00 0x61a8 0x00>; phandle = <0x56>; }; battery { compatible = "simple-battery"; charge-full-design-microamp-hours = <0x34fa80>; charge-term-current-microamp = <0x493e0>; constant-charge-current-max-microamp = <0x1e8480>; constant-charge-voltage-max-microvolt = <0x401640>; factory-internal-resistance-micro-ohms = <0x1c908>; voltage-max-design-microvolt = <0x3fa8e0>; voltage-min-design-microvolt = <0x33e140>; ocv-capacity-celsius = <0x14>; ocv-capacity-table-0 = <0x3fa8e0 0x64 0x3ddbf0 0x5f 0x3cca80 0x5a 0x3be7f0 0x55 0x3b1cd0 0x50 0x3a6150 0x4b 0x39b958 0x46 0x3928d0 0x41 0x38abd0 0x3c 0x3832b8 0x37 0x37b1d0 0x32 0x375be0 0x2d 0x371d60 0x28 0x36ee80 0x23 0x36bbb8 0x1e 0x367d38 0x19 0x363300 0x14 0x35c988 0x0f 0x3548a0 0x0a 0x3494f0 0x05 0x33e140 0x00>; phandle = <0x25>; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "rk817_ext"; simple-audio-card,aux-devs = <0xd0>; simple-audio-card,format = "i2s"; simple-audio-card,hp-det-gpio = <0x58 0x16 0x00>; simple-audio-card,mclk-fs = <0x100>; simple-audio-card,widgets = "Microphone\0Mic Jack\0Headphone\0Headphones\0Speaker\0Internal Speakers"; simple-audio-card,routing = "MICL\0Mic Jack\0Headphones\0HPOL\0Headphones\0HPOR\0Internal Speakers\0Speaker Amp OUTL\0Internal Speakers\0Speaker Amp OUTR\0Speaker Amp INL\0HPOL\0Speaker Amp INR\0HPOR"; simple-audio-card,pin-switches = "Internal Speakers"; simple-audio-card,codec { sound-dai = <0xca>; }; simple-audio-card,cpu { sound-dai = <0xd1>; }; }; audio-amplifier { compatible = "simple-audio-amplifier"; enable-gpios = <0x58 0x12 0x00>; pinctrl-0 = <0xd2>; pinctrl-names = "default"; sound-name-prefix = "Speaker Amp"; phandle = <0xd0>; }; __symbols__ { cpu0 = "/cpus/cpu@0"; cpu1 = "/cpus/cpu@100"; cpu2 = "/cpus/cpu@200"; cpu3 = "/cpus/cpu@300"; cpu0_opp_table = "/opp-table-0"; display_subsystem = "/display-subsystem"; scmi = "/firmware/scmi"; scmi_clk = "/firmware/scmi/protocol@14"; gpu_opp_table = "/opp-table-1"; hdmi_sound = "/hdmi-sound"; xin24m = "/xin24m"; xin32k = "/xin32k"; scmi_shmem = "/sram@10f000/sram@0"; sata1 = "/sata@fc400000"; sata2 = "/sata@fc800000"; usb_host0_xhci = "/usb@fcc00000"; usb_host1_xhci = "/usb@fd000000"; gic = "/interrupt-controller@fd400000"; usb_host0_ehci = "/usb@fd800000"; usb_host0_ohci = "/usb@fd840000"; usb_host1_ehci = "/usb@fd880000"; usb_host1_ohci = "/usb@fd8c0000"; pmugrf = "/syscon@fdc20000"; pmu_io_domains = "/syscon@fdc20000/io-domains"; pipegrf = "/syscon@fdc50000"; grf = "/syscon@fdc60000"; pipe_phy_grf1 = "/syscon@fdc80000"; pipe_phy_grf2 = "/syscon@fdc90000"; usb2phy0_grf = "/syscon@fdca0000"; usb2phy1_grf = "/syscon@fdca8000"; pmucru = "/clock-controller@fdd00000"; cru = "/clock-controller@fdd20000"; i2c0 = "/i2c@fdd40000"; rk817 = "/i2c@fdd40000/pmic@20"; vdd_logic = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG1"; vdd_gpu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG2"; vcc_ddr = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG3"; vcc_3v3 = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG4"; vcca1v8_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG1"; vdda_0v9 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG2"; vdda0v9_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG3"; vccio_acodec = "/i2c@fdd40000/pmic@20/regulators/LDO_REG4"; vccio_sd = "/i2c@fdd40000/pmic@20/regulators/LDO_REG5"; vcc3v3_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG6"; vcc_1v8 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG7"; vcc1v8_dvp = "/i2c@fdd40000/pmic@20/regulators/LDO_REG8"; vcc2v8_dvp = "/i2c@fdd40000/pmic@20/regulators/LDO_REG9"; dcdc_boost = "/i2c@fdd40000/pmic@20/regulators/BOOST"; otg_switch = "/i2c@fdd40000/pmic@20/regulators/OTG_SWITCH"; rk817_charger = "/i2c@fdd40000/pmic@20/charger"; vdd_cpu = "/i2c@fdd40000/regulator@40"; uart0 = "/serial@fdd50000"; pwm0 = "/pwm@fdd70000"; pwm1 = "/pwm@fdd70010"; pwm2 = "/pwm@fdd70020"; pwm3 = "/pwm@fdd70030"; pmu = "/power-management@fdd90000"; power = "/power-management@fdd90000/power-controller"; gpu = "/gpu@fde60000"; vpu = "/video-codec@fdea0400"; vdpu_mmu = "/iommu@fdea0800"; rga = "/rga@fdeb0000"; vepu = "/video-codec@fdee0000"; vepu_mmu = "/iommu@fdee0800"; sdmmc2 = "/mmc@fe000000"; gmac1 = "/ethernet@fe010000"; mdio1 = "/ethernet@fe010000/mdio"; gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config"; gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config"; gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config"; vop = "/vop@fe040000"; vop_out = "/vop@fe040000/ports"; vp0 = "/vop@fe040000/ports/port@0"; vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@2"; vp1 = "/vop@fe040000/ports/port@1"; vp1_out_dsi0 = "/vop@fe040000/ports/port@1/endpoint@4"; vp2 = "/vop@fe040000/ports/port@2"; vop_mmu = "/iommu@fe043e00"; dsi0 = "/dsi@fe060000"; dsi0_in = "/dsi@fe060000/ports/port@0"; dsi0_in_vp1 = "/dsi@fe060000/ports/port@0/endpoint"; dsi0_out = "/dsi@fe060000/ports/port@1"; mipi_out_panel = "/dsi@fe060000/ports/port@1/endpoint"; panel = "/dsi@fe060000/panel@0"; mipi_in_panel = "/dsi@fe060000/panel@0/port/endpoint"; dsi1 = "/dsi@fe070000"; dsi1_in = "/dsi@fe070000/ports/port@0"; dsi1_out = "/dsi@fe070000/ports/port@1"; hdmi = "/hdmi@fe0a0000"; hdmi_in = "/hdmi@fe0a0000/ports/port@0"; hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port@0/endpoint"; hdmi_out = "/hdmi@fe0a0000/ports/port@1"; hdmi_out_con = "/hdmi@fe0a0000/ports/port@1/endpoint"; qos_gpu = "/qos@fe128000"; qos_rkvenc_rd_m0 = "/qos@fe138080"; qos_rkvenc_rd_m1 = "/qos@fe138100"; qos_rkvenc_wr_m0 = "/qos@fe138180"; qos_isp = "/qos@fe148000"; qos_vicap0 = "/qos@fe148080"; qos_vicap1 = "/qos@fe148100"; qos_vpu = "/qos@fe150000"; qos_ebc = "/qos@fe158000"; qos_iep = "/qos@fe158100"; qos_jpeg_dec = "/qos@fe158180"; qos_jpeg_enc = "/qos@fe158200"; qos_rga_rd = "/qos@fe158280"; qos_rga_wr = "/qos@fe158300"; qos_npu = "/qos@fe180000"; qos_pcie2x1 = "/qos@fe190000"; qos_sata1 = "/qos@fe190280"; qos_sata2 = "/qos@fe190300"; qos_usb3_0 = "/qos@fe190380"; qos_usb3_1 = "/qos@fe190400"; qos_rkvdec = "/qos@fe198000"; qos_hdcp = "/qos@fe1a8000"; qos_vop_m0 = "/qos@fe1a8080"; qos_vop_m1 = "/qos@fe1a8100"; pcie2x1 = "/pcie@fe260000"; pcie_intc = "/pcie@fe260000/legacy-interrupt-controller"; sdmmc0 = "/mmc@fe2b0000"; sdmmc1 = "/mmc@fe2c0000"; sfc = "/spi@fe300000"; sdhci = "/mmc@fe310000"; crypto = "/crypto@fe380000"; i2s0_8ch = "/i2s@fe400000"; i2s1_8ch = "/i2s@fe410000"; i2s2_2ch = "/i2s@fe420000"; i2s3_2ch = "/i2s@fe430000"; pdm = "/pdm@fe440000"; spdif = "/spdif@fe460000"; dmac0 = "/dma-controller@fe530000"; dmac1 = "/dma-controller@fe550000"; i2c1 = "/i2c@fe5a0000"; i2c2 = "/i2c@fe5b0000"; i2c3 = "/i2c@fe5c0000"; i2c4 = "/i2c@fe5d0000"; i2c5 = "/i2c@fe5e0000"; wdt = "/watchdog@fe600000"; spi0 = "/spi@fe610000"; spi1 = "/spi@fe620000"; spi2 = "/spi@fe630000"; spi3 = "/spi@fe640000"; uart1 = "/serial@fe650000"; uart2 = "/serial@fe660000"; uart3 = "/serial@fe670000"; uart4 = "/serial@fe680000"; uart5 = "/serial@fe690000"; uart6 = "/serial@fe6a0000"; uart7 = "/serial@fe6b0000"; uart8 = "/serial@fe6c0000"; uart9 = "/serial@fe6d0000"; thermal_zones = "/thermal-zones"; cpu_thermal = "/thermal-zones/cpu-thermal"; cpu_alert0 = "/thermal-zones/cpu-thermal/trips/cpu_alert0"; cpu_alert1 = "/thermal-zones/cpu-thermal/trips/cpu_alert1"; cpu_crit = "/thermal-zones/cpu-thermal/trips/cpu_crit"; gpu_thermal = "/thermal-zones/gpu-thermal"; gpu_threshold = "/thermal-zones/gpu-thermal/trips/gpu-threshold"; gpu_target = "/thermal-zones/gpu-thermal/trips/gpu-target"; gpu_crit = "/thermal-zones/gpu-thermal/trips/gpu-crit"; tsadc = "/tsadc@fe710000"; saradc = "/saradc@fe720000"; pwm4 = "/pwm@fe6e0000"; pwm5 = "/pwm@fe6e0010"; pwm6 = "/pwm@fe6e0020"; pwm7 = "/pwm@fe6e0030"; pwm8 = "/pwm@fe6f0000"; pwm9 = "/pwm@fe6f0010"; pwm10 = "/pwm@fe6f0020"; pwm11 = "/pwm@fe6f0030"; pwm12 = "/pwm@fe700000"; pwm13 = "/pwm@fe700010"; pwm14 = "/pwm@fe700020"; pwm15 = "/pwm@fe700030"; combphy1 = "/phy@fe830000"; combphy2 = "/phy@fe840000"; csi_dphy = "/phy@fe870000"; dsi_dphy0 = "/mipi-dphy@fe850000"; dsi_dphy1 = "/mipi-dphy@fe860000"; usb2phy0 = "/usb2phy@fe8a0000"; usb2phy0_host = "/usb2phy@fe8a0000/host-port"; usb2phy0_otg = "/usb2phy@fe8a0000/otg-port"; usb2phy1 = "/usb2phy@fe8b0000"; usb2phy1_host = "/usb2phy@fe8b0000/host-port"; usb2phy1_otg = "/usb2phy@fe8b0000/otg-port"; pinctrl = "/pinctrl"; gpio0 = "/pinctrl/gpio@fdd60000"; gpio1 = "/pinctrl/gpio@fe740000"; gpio2 = "/pinctrl/gpio@fe750000"; gpio3 = "/pinctrl/gpio@fe760000"; gpio4 = "/pinctrl/gpio@fe770000"; pcfg_pull_up = "/pinctrl/pcfg-pull-up"; pcfg_pull_down = "/pinctrl/pcfg-pull-down"; pcfg_pull_none = "/pinctrl/pcfg-pull-none"; pcfg_pull_none_drv_level_0 = "/pinctrl/pcfg-pull-none-drv-level-0"; pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1"; pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2"; pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3"; pcfg_pull_none_drv_level_4 = "/pinctrl/pcfg-pull-none-drv-level-4"; pcfg_pull_none_drv_level_5 = "/pinctrl/pcfg-pull-none-drv-level-5"; pcfg_pull_none_drv_level_6 = "/pinctrl/pcfg-pull-none-drv-level-6"; pcfg_pull_none_drv_level_7 = "/pinctrl/pcfg-pull-none-drv-level-7"; pcfg_pull_none_drv_level_8 = "/pinctrl/pcfg-pull-none-drv-level-8"; pcfg_pull_none_drv_level_9 = "/pinctrl/pcfg-pull-none-drv-level-9"; pcfg_pull_none_drv_level_10 = "/pinctrl/pcfg-pull-none-drv-level-10"; pcfg_pull_none_drv_level_11 = "/pinctrl/pcfg-pull-none-drv-level-11"; pcfg_pull_none_drv_level_12 = "/pinctrl/pcfg-pull-none-drv-level-12"; pcfg_pull_none_drv_level_13 = "/pinctrl/pcfg-pull-none-drv-level-13"; pcfg_pull_none_drv_level_14 = "/pinctrl/pcfg-pull-none-drv-level-14"; pcfg_pull_none_drv_level_15 = "/pinctrl/pcfg-pull-none-drv-level-15"; pcfg_pull_up_drv_level_0 = "/pinctrl/pcfg-pull-up-drv-level-0"; pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1"; pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2"; pcfg_pull_up_drv_level_3 = "/pinctrl/pcfg-pull-up-drv-level-3"; pcfg_pull_up_drv_level_4 = "/pinctrl/pcfg-pull-up-drv-level-4"; pcfg_pull_up_drv_level_5 = "/pinctrl/pcfg-pull-up-drv-level-5"; pcfg_pull_up_drv_level_6 = "/pinctrl/pcfg-pull-up-drv-level-6"; pcfg_pull_up_drv_level_7 = "/pinctrl/pcfg-pull-up-drv-level-7"; pcfg_pull_up_drv_level_8 = "/pinctrl/pcfg-pull-up-drv-level-8"; pcfg_pull_up_drv_level_9 = "/pinctrl/pcfg-pull-up-drv-level-9"; pcfg_pull_up_drv_level_10 = "/pinctrl/pcfg-pull-up-drv-level-10"; pcfg_pull_up_drv_level_11 = "/pinctrl/pcfg-pull-up-drv-level-11"; pcfg_pull_up_drv_level_12 = "/pinctrl/pcfg-pull-up-drv-level-12"; pcfg_pull_up_drv_level_13 = "/pinctrl/pcfg-pull-up-drv-level-13"; pcfg_pull_up_drv_level_14 = "/pinctrl/pcfg-pull-up-drv-level-14"; pcfg_pull_up_drv_level_15 = "/pinctrl/pcfg-pull-up-drv-level-15"; pcfg_pull_down_drv_level_0 = "/pinctrl/pcfg-pull-down-drv-level-0"; pcfg_pull_down_drv_level_1 = "/pinctrl/pcfg-pull-down-drv-level-1"; pcfg_pull_down_drv_level_2 = "/pinctrl/pcfg-pull-down-drv-level-2"; pcfg_pull_down_drv_level_3 = "/pinctrl/pcfg-pull-down-drv-level-3"; pcfg_pull_down_drv_level_4 = "/pinctrl/pcfg-pull-down-drv-level-4"; pcfg_pull_down_drv_level_5 = "/pinctrl/pcfg-pull-down-drv-level-5"; pcfg_pull_down_drv_level_6 = "/pinctrl/pcfg-pull-down-drv-level-6"; pcfg_pull_down_drv_level_7 = "/pinctrl/pcfg-pull-down-drv-level-7"; pcfg_pull_down_drv_level_8 = "/pinctrl/pcfg-pull-down-drv-level-8"; pcfg_pull_down_drv_level_9 = "/pinctrl/pcfg-pull-down-drv-level-9"; pcfg_pull_down_drv_level_10 = "/pinctrl/pcfg-pull-down-drv-level-10"; pcfg_pull_down_drv_level_11 = "/pinctrl/pcfg-pull-down-drv-level-11"; pcfg_pull_down_drv_level_12 = "/pinctrl/pcfg-pull-down-drv-level-12"; pcfg_pull_down_drv_level_13 = "/pinctrl/pcfg-pull-down-drv-level-13"; pcfg_pull_down_drv_level_14 = "/pinctrl/pcfg-pull-down-drv-level-14"; pcfg_pull_down_drv_level_15 = "/pinctrl/pcfg-pull-down-drv-level-15"; pcfg_pull_up_smt = "/pinctrl/pcfg-pull-up-smt"; pcfg_pull_down_smt = "/pinctrl/pcfg-pull-down-smt"; pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt"; pcfg_pull_none_drv_level_0_smt = "/pinctrl/pcfg-pull-none-drv-level-0-smt"; pcfg_output_high = "/pinctrl/pcfg-output-high"; pcfg_output_low = "/pinctrl/pcfg-output-low"; acodec_pins = "/pinctrl/acodec/acodec-pins"; audiopwm_lout = "/pinctrl/audiopwm/audiopwm-lout"; audiopwm_loutn = "/pinctrl/audiopwm/audiopwm-loutn"; audiopwm_loutp = "/pinctrl/audiopwm/audiopwm-loutp"; audiopwm_rout = "/pinctrl/audiopwm/audiopwm-rout"; audiopwm_routn = "/pinctrl/audiopwm/audiopwm-routn"; audiopwm_routp = "/pinctrl/audiopwm/audiopwm-routp"; bt656m0_pins = "/pinctrl/bt656/bt656m0-pins"; bt656m1_pins = "/pinctrl/bt656/bt656m1-pins"; bt1120_pins = "/pinctrl/bt1120/bt1120-pins"; cam_clkout0 = "/pinctrl/cam/cam-clkout0"; cam_clkout1 = "/pinctrl/cam/cam-clkout1"; can0m0_pins = "/pinctrl/can0/can0m0-pins"; can0m1_pins = "/pinctrl/can0/can0m1-pins"; can1m0_pins = "/pinctrl/can1/can1m0-pins"; can1m1_pins = "/pinctrl/can1/can1m1-pins"; can2m0_pins = "/pinctrl/can2/can2m0-pins"; can2m1_pins = "/pinctrl/can2/can2m1-pins"; cif_clk = "/pinctrl/cif/cif-clk"; cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk"; cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16"; cif_dvp_bus8 = "/pinctrl/cif/cif-dvp-bus8"; clk32k_in = "/pinctrl/clk32k/clk32k-in"; clk32k_out0 = "/pinctrl/clk32k/clk32k-out0"; clk32k_out1 = "/pinctrl/clk32k/clk32k-out1"; cpu_pins = "/pinctrl/cpu/cpu-pins"; ebc_extern = "/pinctrl/ebc/ebc-extern"; ebc_pins = "/pinctrl/ebc/ebc-pins"; edpdpm0_pins = "/pinctrl/edpdp/edpdpm0-pins"; edpdpm1_pins = "/pinctrl/edpdp/edpdpm1-pins"; emmc_rstnout = "/pinctrl/emmc/emmc-rstnout"; emmc_bus8 = "/pinctrl/emmc/emmc-bus8"; emmc_clk = "/pinctrl/emmc/emmc-clk"; emmc_cmd = "/pinctrl/emmc/emmc-cmd"; emmc_datastrobe = "/pinctrl/emmc/emmc-datastrobe"; eth0_pins = "/pinctrl/eth0/eth0-pins"; eth1m0_pins = "/pinctrl/eth1/eth1m0-pins"; eth1m1_pins = "/pinctrl/eth1/eth1m1-pins"; flash_pins = "/pinctrl/flash/flash-pins"; fspi_pins = "/pinctrl/fspi/fspi-pins"; fspi_cs1 = "/pinctrl/fspi/fspi-cs1"; gmac0_miim = "/pinctrl/gmac0/gmac0-miim"; gmac0_clkinout = "/pinctrl/gmac0/gmac0-clkinout"; gmac0_rx_er = "/pinctrl/gmac0/gmac0-rx-er"; gmac0_rx_bus2 = "/pinctrl/gmac0/gmac0-rx-bus2"; gmac0_tx_bus2 = "/pinctrl/gmac0/gmac0-tx-bus2"; gmac0_rgmii_clk = "/pinctrl/gmac0/gmac0-rgmii-clk"; gmac0_rgmii_bus = "/pinctrl/gmac0/gmac0-rgmii-bus"; gmac1m0_miim = "/pinctrl/gmac1/gmac1m0-miim"; gmac1m0_clkinout = "/pinctrl/gmac1/gmac1m0-clkinout"; gmac1m0_rx_er = "/pinctrl/gmac1/gmac1m0-rx-er"; gmac1m0_rx_bus2 = "/pinctrl/gmac1/gmac1m0-rx-bus2"; gmac1m0_tx_bus2 = "/pinctrl/gmac1/gmac1m0-tx-bus2"; gmac1m0_rgmii_clk = "/pinctrl/gmac1/gmac1m0-rgmii-clk"; gmac1m0_rgmii_bus = "/pinctrl/gmac1/gmac1m0-rgmii-bus"; gmac1m1_miim = "/pinctrl/gmac1/gmac1m1-miim"; gmac1m1_clkinout = "/pinctrl/gmac1/gmac1m1-clkinout"; gmac1m1_rx_er = "/pinctrl/gmac1/gmac1m1-rx-er"; gmac1m1_rx_bus2 = "/pinctrl/gmac1/gmac1m1-rx-bus2"; gmac1m1_tx_bus2 = "/pinctrl/gmac1/gmac1m1-tx-bus2"; gmac1m1_rgmii_clk = "/pinctrl/gmac1/gmac1m1-rgmii-clk"; gmac1m1_rgmii_bus = "/pinctrl/gmac1/gmac1m1-rgmii-bus"; gpu_pins = "/pinctrl/gpu/gpu-pins"; hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec"; hdmitxm1_cec = "/pinctrl/hdmitx/hdmitxm1-cec"; hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl"; hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda"; i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer"; i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer"; i2c2m0_xfer = "/pinctrl/i2c2/i2c2m0-xfer"; i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer"; i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer"; i2c3m1_xfer = "/pinctrl/i2c3/i2c3m1-xfer"; i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer"; i2c4m1_xfer = "/pinctrl/i2c4/i2c4m1-xfer"; i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer"; i2c5m1_xfer = "/pinctrl/i2c5/i2c5m1-xfer"; i2s1m0_lrckrx = "/pinctrl/i2s1/i2s1m0-lrckrx"; i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx"; i2s1m0_mclk = "/pinctrl/i2s1/i2s1m0-mclk"; i2s1m0_sclkrx = "/pinctrl/i2s1/i2s1m0-sclkrx"; i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx"; i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0"; i2s1m0_sdi1 = "/pinctrl/i2s1/i2s1m0-sdi1"; i2s1m0_sdi2 = "/pinctrl/i2s1/i2s1m0-sdi2"; i2s1m0_sdi3 = "/pinctrl/i2s1/i2s1m0-sdi3"; i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0"; i2s1m0_sdo1 = "/pinctrl/i2s1/i2s1m0-sdo1"; i2s1m0_sdo2 = "/pinctrl/i2s1/i2s1m0-sdo2"; i2s1m0_sdo3 = "/pinctrl/i2s1/i2s1m0-sdo3"; i2s1m1_lrckrx = "/pinctrl/i2s1/i2s1m1-lrckrx"; i2s1m1_lrcktx = "/pinctrl/i2s1/i2s1m1-lrcktx"; i2s1m1_mclk = "/pinctrl/i2s1/i2s1m1-mclk"; i2s1m1_sclkrx = "/pinctrl/i2s1/i2s1m1-sclkrx"; i2s1m1_sclktx = "/pinctrl/i2s1/i2s1m1-sclktx"; i2s1m1_sdi0 = "/pinctrl/i2s1/i2s1m1-sdi0"; i2s1m1_sdi1 = "/pinctrl/i2s1/i2s1m1-sdi1"; i2s1m1_sdi2 = "/pinctrl/i2s1/i2s1m1-sdi2"; i2s1m1_sdi3 = "/pinctrl/i2s1/i2s1m1-sdi3"; i2s1m1_sdo0 = "/pinctrl/i2s1/i2s1m1-sdo0"; i2s1m1_sdo1 = "/pinctrl/i2s1/i2s1m1-sdo1"; i2s1m1_sdo2 = "/pinctrl/i2s1/i2s1m1-sdo2"; i2s1m1_sdo3 = "/pinctrl/i2s1/i2s1m1-sdo3"; i2s1m2_lrckrx = "/pinctrl/i2s1/i2s1m2-lrckrx"; i2s1m2_lrcktx = "/pinctrl/i2s1/i2s1m2-lrcktx"; i2s1m2_mclk = "/pinctrl/i2s1/i2s1m2-mclk"; i2s1m2_sclkrx = "/pinctrl/i2s1/i2s1m2-sclkrx"; i2s1m2_sclktx = "/pinctrl/i2s1/i2s1m2-sclktx"; i2s1m2_sdi0 = "/pinctrl/i2s1/i2s1m2-sdi0"; i2s1m2_sdi1 = "/pinctrl/i2s1/i2s1m2-sdi1"; i2s1m2_sdi2 = "/pinctrl/i2s1/i2s1m2-sdi2"; i2s1m2_sdi3 = "/pinctrl/i2s1/i2s1m2-sdi3"; i2s1m2_sdo0 = "/pinctrl/i2s1/i2s1m2-sdo0"; i2s1m2_sdo1 = "/pinctrl/i2s1/i2s1m2-sdo1"; i2s1m2_sdo2 = "/pinctrl/i2s1/i2s1m2-sdo2"; i2s1m2_sdo3 = "/pinctrl/i2s1/i2s1m2-sdo3"; i2s2m0_lrckrx = "/pinctrl/i2s2/i2s2m0-lrckrx"; i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx"; i2s2m0_mclk = "/pinctrl/i2s2/i2s2m0-mclk"; i2s2m0_sclkrx = "/pinctrl/i2s2/i2s2m0-sclkrx"; i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx"; i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi"; i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo"; i2s2m1_lrckrx = "/pinctrl/i2s2/i2s2m1-lrckrx"; i2s2m1_lrcktx = "/pinctrl/i2s2/i2s2m1-lrcktx"; i2s2m1_mclk = "/pinctrl/i2s2/i2s2m1-mclk"; i2s2m1_sclkrx = "/pinctrl/i2s2/i2s2m1-sclkrx"; i2s2m1_sclktx = "/pinctrl/i2s2/i2s2m1-sclktx"; i2s2m1_sdi = "/pinctrl/i2s2/i2s2m1-sdi"; i2s2m1_sdo = "/pinctrl/i2s2/i2s2m1-sdo"; i2s3m0_lrck = "/pinctrl/i2s3/i2s3m0-lrck"; i2s3m0_mclk = "/pinctrl/i2s3/i2s3m0-mclk"; i2s3m0_sclk = "/pinctrl/i2s3/i2s3m0-sclk"; i2s3m0_sdi = "/pinctrl/i2s3/i2s3m0-sdi"; i2s3m0_sdo = "/pinctrl/i2s3/i2s3m0-sdo"; i2s3m1_lrck = "/pinctrl/i2s3/i2s3m1-lrck"; i2s3m1_mclk = "/pinctrl/i2s3/i2s3m1-mclk"; i2s3m1_sclk = "/pinctrl/i2s3/i2s3m1-sclk"; i2s3m1_sdi = "/pinctrl/i2s3/i2s3m1-sdi"; i2s3m1_sdo = "/pinctrl/i2s3/i2s3m1-sdo"; isp_pins = "/pinctrl/isp/isp-pins"; jtag_pins = "/pinctrl/jtag/jtag-pins"; lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl"; lcdc_clock = "/pinctrl/lcdc/lcdc-clock"; lcdc_data16 = "/pinctrl/lcdc/lcdc-data16"; lcdc_data18 = "/pinctrl/lcdc/lcdc-data18"; mcu_pins = "/pinctrl/mcu/mcu-pins"; npu_pins = "/pinctrl/npu/npu-pins"; pcie20m0_pins = "/pinctrl/pcie20/pcie20m0-pins"; pcie20m1_pins = "/pinctrl/pcie20/pcie20m1-pins"; pcie20m2_pins = "/pinctrl/pcie20/pcie20m2-pins"; pcie20_buttonrstn = "/pinctrl/pcie20/pcie20-buttonrstn"; pcie30x1m0_pins = "/pinctrl/pcie30x1/pcie30x1m0-pins"; pcie30x1m1_pins = "/pinctrl/pcie30x1/pcie30x1m1-pins"; pcie30x1m2_pins = "/pinctrl/pcie30x1/pcie30x1m2-pins"; pcie30x1_buttonrstn = "/pinctrl/pcie30x1/pcie30x1-buttonrstn"; pcie30x2m0_pins = "/pinctrl/pcie30x2/pcie30x2m0-pins"; pcie30x2m1_pins = "/pinctrl/pcie30x2/pcie30x2m1-pins"; pcie30x2m2_pins = "/pinctrl/pcie30x2/pcie30x2m2-pins"; pcie30x2_buttonrstn = "/pinctrl/pcie30x2/pcie30x2-buttonrstn"; pdmm0_clk = "/pinctrl/pdm/pdmm0-clk"; pdmm0_clk1 = "/pinctrl/pdm/pdmm0-clk1"; pdmm0_sdi0 = "/pinctrl/pdm/pdmm0-sdi0"; pdmm0_sdi1 = "/pinctrl/pdm/pdmm0-sdi1"; pdmm0_sdi2 = "/pinctrl/pdm/pdmm0-sdi2"; pdmm0_sdi3 = "/pinctrl/pdm/pdmm0-sdi3"; pdmm1_clk = "/pinctrl/pdm/pdmm1-clk"; pdmm1_clk1 = "/pinctrl/pdm/pdmm1-clk1"; pdmm1_sdi0 = "/pinctrl/pdm/pdmm1-sdi0"; pdmm1_sdi1 = "/pinctrl/pdm/pdmm1-sdi1"; pdmm1_sdi2 = "/pinctrl/pdm/pdmm1-sdi2"; pdmm1_sdi3 = "/pinctrl/pdm/pdmm1-sdi3"; pdmm2_clk1 = "/pinctrl/pdm/pdmm2-clk1"; pdmm2_sdi0 = "/pinctrl/pdm/pdmm2-sdi0"; pdmm2_sdi1 = "/pinctrl/pdm/pdmm2-sdi1"; pdmm2_sdi2 = "/pinctrl/pdm/pdmm2-sdi2"; pdmm2_sdi3 = "/pinctrl/pdm/pdmm2-sdi3"; pmic_pins = "/pinctrl/pmic/pmic-pins"; pmic_int_l = "/pinctrl/pmic/pmic-int-l"; pmu_pins = "/pinctrl/pmu/pmu-pins"; pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins"; pwm0m1_pins = "/pinctrl/pwm0/pwm0m1-pins"; pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins"; pwm1m1_pins = "/pinctrl/pwm1/pwm1m1-pins"; pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins"; pwm2m1_pins = "/pinctrl/pwm2/pwm2m1-pins"; pwm3_pins = "/pinctrl/pwm3/pwm3-pins"; pwm4_pins = "/pinctrl/pwm4/pwm4-pins"; pwm5_pins = "/pinctrl/pwm5/pwm5-pins"; pwm6_pins = "/pinctrl/pwm6/pwm6-pins"; pwm7_pins = "/pinctrl/pwm7/pwm7-pins"; pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins"; pwm8m1_pins = "/pinctrl/pwm8/pwm8m1-pins"; pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins"; pwm9m1_pins = "/pinctrl/pwm9/pwm9m1-pins"; pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins"; pwm10m1_pins = "/pinctrl/pwm10/pwm10m1-pins"; pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins"; pwm11m1_pins = "/pinctrl/pwm11/pwm11m1-pins"; pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins"; pwm12m1_pins = "/pinctrl/pwm12/pwm12m1-pins"; pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins"; pwm13m1_pins = "/pinctrl/pwm13/pwm13m1-pins"; pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins"; pwm14m1_pins = "/pinctrl/pwm14/pwm14m1-pins"; pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins"; pwm15m1_pins = "/pinctrl/pwm15/pwm15m1-pins"; refclk_pins = "/pinctrl/refclk/refclk-pins"; sata_pins = "/pinctrl/sata/sata-pins"; sata0_pins = "/pinctrl/sata0/sata0-pins"; sata1_pins = "/pinctrl/sata1/sata1-pins"; sata2_pins = "/pinctrl/sata2/sata2-pins"; scr_pins = "/pinctrl/scr/scr-pins"; sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4"; sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk"; sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd"; sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det"; sdmmc0_pwren = "/pinctrl/sdmmc0/sdmmc0-pwren"; sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4"; sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk"; sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd"; sdmmc1_det = "/pinctrl/sdmmc1/sdmmc1-det"; sdmmc1_pwren = "/pinctrl/sdmmc1/sdmmc1-pwren"; sdmmc2m0_bus4 = "/pinctrl/sdmmc2/sdmmc2m0-bus4"; sdmmc2m0_clk = "/pinctrl/sdmmc2/sdmmc2m0-clk"; sdmmc2m0_cmd = "/pinctrl/sdmmc2/sdmmc2m0-cmd"; sdmmc2m0_det = "/pinctrl/sdmmc2/sdmmc2m0-det"; sdmmc2m0_pwren = "/pinctrl/sdmmc2/sdmmc2m0-pwren"; sdmmc2m1_bus4 = "/pinctrl/sdmmc2/sdmmc2m1-bus4"; sdmmc2m1_clk = "/pinctrl/sdmmc2/sdmmc2m1-clk"; sdmmc2m1_cmd = "/pinctrl/sdmmc2/sdmmc2m1-cmd"; sdmmc2m1_det = "/pinctrl/sdmmc2/sdmmc2m1-det"; sdmmc2m1_pwren = "/pinctrl/sdmmc2/sdmmc2m1-pwren"; spdifm0_tx = "/pinctrl/spdif/spdifm0-tx"; spdifm1_tx = "/pinctrl/spdif/spdifm1-tx"; spdifm2_tx = "/pinctrl/spdif/spdifm2-tx"; spi0m0_pins = "/pinctrl/spi0/spi0m0-pins"; spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0"; spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1"; spi0m1_pins = "/pinctrl/spi0/spi0m1-pins"; spi0m1_cs0 = "/pinctrl/spi0/spi0m1-cs0"; spi1m0_pins = "/pinctrl/spi1/spi1m0-pins"; spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0"; spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1"; spi1m1_pins = "/pinctrl/spi1/spi1m1-pins"; spi1m1_cs0 = "/pinctrl/spi1/spi1m1-cs0"; spi2m0_pins = "/pinctrl/spi2/spi2m0-pins"; spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0"; spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1"; spi2m1_pins = "/pinctrl/spi2/spi2m1-pins"; spi2m1_cs0 = "/pinctrl/spi2/spi2m1-cs0"; spi2m1_cs1 = "/pinctrl/spi2/spi2m1-cs1"; spi3m0_pins = "/pinctrl/spi3/spi3m0-pins"; spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0"; spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1"; spi3m1_pins = "/pinctrl/spi3/spi3m1-pins"; spi3m1_cs0 = "/pinctrl/spi3/spi3m1-cs0"; spi3m1_cs1 = "/pinctrl/spi3/spi3m1-cs1"; tsadcm0_shut = "/pinctrl/tsadc/tsadcm0-shut"; tsadcm1_shut = "/pinctrl/tsadc/tsadcm1-shut"; tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg"; tsadc_pin = "/pinctrl/tsadc/tsadc-pin"; uart0_xfer = "/pinctrl/uart0/uart0-xfer"; uart0_ctsn = "/pinctrl/uart0/uart0-ctsn"; uart0_rtsn = "/pinctrl/uart0/uart0-rtsn"; uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer"; uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn"; uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn"; uart1m1_xfer = "/pinctrl/uart1/uart1m1-xfer"; uart1m1_ctsn = "/pinctrl/uart1/uart1m1-ctsn"; uart1m1_rtsn = "/pinctrl/uart1/uart1m1-rtsn"; uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer"; uart2m1_xfer = "/pinctrl/uart2/uart2m1-xfer"; uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer"; uart3m0_ctsn = "/pinctrl/uart3/uart3m0-ctsn"; uart3m0_rtsn = "/pinctrl/uart3/uart3m0-rtsn"; uart3m1_xfer = "/pinctrl/uart3/uart3m1-xfer"; uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer"; uart4m0_ctsn = "/pinctrl/uart4/uart4m0-ctsn"; uart4m0_rtsn = "/pinctrl/uart4/uart4m0-rtsn"; uart4m1_xfer = "/pinctrl/uart4/uart4m1-xfer"; uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer"; uart5m0_ctsn = "/pinctrl/uart5/uart5m0-ctsn"; uart5m0_rtsn = "/pinctrl/uart5/uart5m0-rtsn"; uart5m1_xfer = "/pinctrl/uart5/uart5m1-xfer"; uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer"; uart6m0_ctsn = "/pinctrl/uart6/uart6m0-ctsn"; uart6m0_rtsn = "/pinctrl/uart6/uart6m0-rtsn"; uart6m1_xfer = "/pinctrl/uart6/uart6m1-xfer"; uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer"; uart7m0_ctsn = "/pinctrl/uart7/uart7m0-ctsn"; uart7m0_rtsn = "/pinctrl/uart7/uart7m0-rtsn"; uart7m1_xfer = "/pinctrl/uart7/uart7m1-xfer"; uart7m2_xfer = "/pinctrl/uart7/uart7m2-xfer"; uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer"; uart8m0_ctsn = "/pinctrl/uart8/uart8m0-ctsn"; uart8m0_rtsn = "/pinctrl/uart8/uart8m0-rtsn"; uart8m1_xfer = "/pinctrl/uart8/uart8m1-xfer"; uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer"; uart9m0_ctsn = "/pinctrl/uart9/uart9m0-ctsn"; uart9m0_rtsn = "/pinctrl/uart9/uart9m0-rtsn"; uart9m1_xfer = "/pinctrl/uart9/uart9m1-xfer"; uart9m2_xfer = "/pinctrl/uart9/uart9m2-xfer"; vopm0_pins = "/pinctrl/vop/vopm0-pins"; vopm1_pins = "/pinctrl/vop/vopm1-pins"; spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins"; spi0m0_cs0_hs = "/pinctrl/spi0-hs/spi0m0-cs0"; spi0m0_cs1_hs = "/pinctrl/spi0-hs/spi0m0-cs1"; spi0m1_pins_hs = "/pinctrl/spi0-hs/spi0m1-pins"; spi0m1_cs0_hs = "/pinctrl/spi0-hs/spi0m1-cs0"; spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins"; spi1m0_cs0_hs = "/pinctrl/spi1-hs/spi1m0-cs0"; spi1m0_cs1_hs = "/pinctrl/spi1-hs/spi1m0-cs1"; spi1m1_pins_hs = "/pinctrl/spi1-hs/spi1m1-pins"; spi1m1_cs0_hs = "/pinctrl/spi1-hs/spi1m1-cs0"; spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins"; spi2m0_cs0_hs = "/pinctrl/spi2-hs/spi2m0-cs0"; spi2m0_cs1_hs = "/pinctrl/spi2-hs/spi2m0-cs1"; spi2m1_pins_hs = "/pinctrl/spi2-hs/spi2m1-pins"; spi2m1_cs0_hs = "/pinctrl/spi2-hs/spi2m1-cs0"; spi2m1_cs1_hs = "/pinctrl/spi2-hs/spi2m1-cs1"; spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins"; spi3m0_cs0_hs = "/pinctrl/spi3-hs/spi3m0-cs0"; spi3m0_cs1_hs = "/pinctrl/spi3-hs/spi3m0-cs1"; spi3m1_pins_hs = "/pinctrl/spi3-hs/spi3m1-pins"; spi3m1_cs0_hs = "/pinctrl/spi3-hs/spi3m1-cs0"; spi3m1_cs1_hs = "/pinctrl/spi3-hs/spi3m1-cs1"; gmac0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac0-tx-bus2-level3"; gmac0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac0-rgmii-bus-level3"; gmac1m0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-tx-bus2-level3"; gmac1m0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-rgmii-bus-level3"; gmac1m1_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m1-tx-bus2-level3"; gmac1m1_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m1-rgmii-bus-level3"; gmac0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac0-rgmii-clk-level2"; gmac1m0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m0-rgmii-clk-level2"; gmac1m1_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m1-rgmii-clk-level2"; btn_pins_ctrl = "/pinctrl/gpio-btns/btn-pins-ctrl"; btn_pins_vol = "/pinctrl/gpio-btns/btn-pins-vol"; joy_mux_en = "/pinctrl/joy-mux/joy-mux-en"; wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h"; vcc_lcd_h = "/pinctrl/vcc3v3-lcd/vcc-lcd-h"; vcc_wifi_h = "/pinctrl/vcc-wifi/vcc-wifi-h"; lcd_rst = "/pinctrl/gpio-lcd/lcd-rst"; spk_amp_enable_h = "/pinctrl/audio-amplifier/spk-amp-enable-h"; touch_rst = "/pinctrl/touch/touch-rst"; chosen = "/chosen"; adc_keys = "/adc-keys"; adc_mux = "/adc-mux"; gpio_keys_control = "/gpio-keys-control"; gpio_keys_vol = "/gpio-keys-vol"; gpio_mux = "/mux-controller"; hdmi_con_in = "/hdmi-con/port/endpoint"; leds = "/pwm-leds"; green_led = "/pwm-leds/led-0"; amber_led = "/pwm-leds/led-1"; red_led = "/pwm-leds/led-2"; sdio_pwrseq = "/sdio-pwrseq"; vcc3v3_lcd0_n = "/regulator-vcc3v3-lcd0"; vcc_sys = "/regulator-vcc-sys"; vcc_wifi = "/regulator-vcc-wifi"; vibrator = "/pwm-vibrator"; backlight = "/backlight"; battery = "/battery"; spk_amp = "/audio-amplifier"; }; }; You can Use it to compare with the original DTB -> DTS file and figure out any error on This DTS file that bring board UP Edited April 16 by Hqnicolas 0 Quote
pocosparc Posted April 16 Posted April 16 vor einer Stunde schrieb Hqnicolas: at kernel 6.6 your wifi work? how? I think wifi was wrong.... Yes you are right. It was working on the previous 1.1 image. There was the 6.1 kernel being active. 0 Quote
Hqnicolas Posted April 16 Author Posted April 16 (edited) On 4/16/2024 at 9:05 AM, pocosparc said: Yes you are right. It was working on the previous 1.1 image. There was the 6.1 kernel being active. I don't have time to test wifi, if you be the wifi guy, please use this method to fix the wifi power management or communication: On 4/16/2024 at 8:00 AM, Hqnicolas said: You can Use it to compare with the original DTB -> DTS file and figure out any error on This DTS file that bring board UP the process will be: compare two decompiled DTS. The old that wifi work and the new 6.6 without wifi and use it to fix the Board bring UP file RK3566-firefly-roc-pc = DTS Kernel 6.2 RK3566-h96max = DTS Kernel 6.6 rk3566-firefly-roc-pc.dtsrk3566-h96max.dts Edited April 18 by Hqnicolas 0 Quote
pocosparc Posted April 17 Posted April 17 Thx right on the spot. I made me a coffee to start to crack this wifi stuff 1 Quote
Hqnicolas Posted April 17 Author Posted April 17 (edited) Pull Request was approved today on Github we can now clone from main. git clone https://github.com/armbian/build.git The H96-max Files can be fount at https://github.com/hqnicolas/ArmBoardBringUp Edited April 17 by Hqnicolas 0 Quote
SteeMan Posted April 17 Posted April 17 1 hour ago, Hqnicolas said: Pull Request was approved today on Github we can now clone from main. git clone https://github.com/armbian/build.git With weekly image builds located here: https://github.com/armbian/community And daily rolling release apt packages (kernel and other armbian packages) located at: beta.armbian.com 0 Quote
Hqnicolas Posted April 17 Author Posted April 17 (edited) 3 hours ago, SteeMan said: With weekly image builds located here: https://github.com/armbian/community And daily rolling release apt packages (kernel and other armbian packages) located at: beta.armbian.com WOW! huge thanks! I didn't know about image generation, I believe that now everything will flow better here. Edited April 17 by Hqnicolas 0 Quote
Hqnicolas Posted April 18 Author Posted April 18 (edited) 20 hours ago, pocosparc said: I made me a coffee to start to crack this wifi stuff I'm working here too, I reflash my device with the official github armbian compiled and extracted again the DTB to DTS rk3566-h96max.dtsrk3566-firefly-roc-pc.dts RK3566-firefly-roc-pc = DTS Kernel 6.2 RK3566-h96max = DTS Kernel 6.6 On 4/5/2024 at 6:38 PM, pocosparc said: the I2C frequency of the bulk converter seems to be the right one for tcs4525 (also to format is correct, but the numbers are so small that I can't read them). The regulator is TCS4525 and i'ts the same as the Armbian Repo! Quote Edited April 18 by Hqnicolas 0 Quote
Hqnicolas Posted April 18 Author Posted April 18 (edited) analysing DTS File From H96_MAX Kernel 6.6 Using this method Quote pcfg-pull-none { bias-disable; phandle = <0xbb>; #### level 0 }; sdio-pwrseq { wifi-enable-h { rockchip,pins = <0x02 0x09 0x00 0xbb>; ####### GPiO2 ### RK_PB1 #### level 0 phandle = <0xc7>; }; }; wireless-wlan { wifi-host-wake-irq { rockchip,pins = <0x02 0x0a 0x00 0xc3>; ####### GPiO2 ### RK_PB2 #### level 0 phandle = <0xc8>; }; }; wireless-wlan { compatible = "wlan-platdata"; rockchip,grf = <0x1e>; wifi_chip_type = "ap6398s"; pinctrl-names = "default"; pinctrl-0 = <0xc8>; WIFI,host_wake_irq = <0x95 0x0a 0x00>; ####### GPiO2 ### RK_PB2 #### level 0 status = "okay"; phandle = <0x253>; }; bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <0x94 0x01>; clock-names = "lpo"; device-wakeup-gpios = <0x95 0x11 0x00>; ####### GPiO2 ### RK_PC1 ##### level 0 host-wakeup-gpios = <0x95 0x10 0x00>; ####### GPiO2 ### RK_PC0 ##### level 0 shutdown-gpios = <0x95 0x0f 0x00>; ####### GPiO2 ### RK_PB7 ##### level 0 max-speed = <0x16e360>; pinctrl-names = "default"; pinctrl-0 = <0x96 0x97 0x98>; vbat-supply = <0x23>; vddio-supply = <0x63>; }; }; From Kernel 6.6: Quote root@h96-tvbox-3566-wifi:~# sudo gpioinfo gpiochip0 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed "interrupt" input active-high [used] line 4: unnamed "cd" input active-low [used] line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed "led-status" output active-high [used] line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip1 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip2 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed "reset" output active-low [used] line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed "shutdown" output active-high [used] line 16: unnamed "host-wakeup" input active-high [used] line 17: unnamed "device-wakeup" output active-high [used] line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip3 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed "snps,reset" output active-low [used] line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip4 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high It's the same as Firefly board I have tested the pin12 from HCY6335 with kernel 6.2 it receives 1.8v with kernel 6.6 it receives 0.0v From Kernel 6.2: Quote pcfg-pull-none { bias-disable; phandle = <0xb5>; #### level 0 }; sdio-pwrseq { wifi-enable-h { rockchip,pins = <0x02 0x09 0x00 0xb5>; ####### GPiO2 ### RK_PB1 #### level 0 phandle = <0xc5>; }; }; bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <0x8d 0x01>; clock-names = "lpo"; device-wake-gpios = <0x8e 0x11 0x00>; ####### GPiO2 ### RK_PC1 ##### level 0 host-wake-gpios = <0x8e 0x10 0x00>; ####### GPiO2 ### RK_PC0 ##### level 0 shutdown-gpios = <0x8e 0x0f 0x00>; ####### GPiO2 ### RK_PB7 ##### level 0 pinctrl-names = "default"; pinctrl-0 = <0x8f 0x90 0x91>; vbat-supply = <0x24>; vddio-supply = <0x92>; status = "disabled"; }; From Kernel 6.2: Quote root@h96-max-v56:~# sudo gpioinfo gpiochip0 - 32 lines: line 0: unnamed unused output active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed "interrupt" input active-high [used] line 4: unnamed "cd" input active-low [used] line 5: unnamed "vcc5v0-otg-regulator" output active-high [used] line 6: unnamed "vcc5v0-host-regulator" output active-high [used] line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed "snps,reset" output active-low [used] line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused output active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed "firefly:blue:power" output active-high [used] line 28: unnamed "firefly:yellow:user" output active-high [used] line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip1 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip2 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed "reset" output active-low [used] line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip3 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused output active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high gpiochip4 - 32 lines: line 0: unnamed unused input active-high line 1: unnamed unused input active-high line 2: unnamed unused input active-high line 3: unnamed unused input active-high line 4: unnamed unused input active-high line 5: unnamed unused input active-high line 6: unnamed unused input active-high line 7: unnamed unused input active-high line 8: unnamed unused input active-high line 9: unnamed unused input active-high line 10: unnamed unused input active-high line 11: unnamed unused input active-high line 12: unnamed unused input active-high line 13: unnamed unused input active-high line 14: unnamed unused input active-high line 15: unnamed unused input active-high line 16: unnamed unused input active-high line 17: unnamed unused input active-high line 18: unnamed unused input active-high line 19: unnamed unused input active-high line 20: unnamed unused input active-high line 21: unnamed unused input active-high line 22: unnamed unused input active-high line 23: unnamed unused input active-high line 24: unnamed unused input active-high line 25: unnamed unused input active-high line 26: unnamed unused input active-high line 27: unnamed unused input active-high line 28: unnamed unused input active-high line 29: unnamed unused input active-high line 30: unnamed unused input active-high line 31: unnamed unused input active-high GPIO Definition: Quote #define RK_PA0 0 #define RK_PA1 1 #define RK_PA2 2 #define RK_PA3 3 #define RK_PA4 4 #define RK_PA5 5 #define RK_PA6 6 #define RK_PA7 7 #define RK_PB0 8 #define RK_PB1 9 #define RK_PB2 10 #define RK_PB3 11 #define RK_PB4 12 #define RK_PB5 13 #define RK_PB6 14 #define RK_PB7 15 #define RK_PC0 16 #define RK_PC1 17 #define RK_PC2 18 #define RK_PC3 19 #define RK_PC4 20 #define RK_PC5 21 #define RK_PC6 22 #define RK_PC7 23 #define RK_PD0 24 #define RK_PD1 25 #define RK_PD2 26 #define RK_PD3 27 #define RK_PD4 28 #define RK_PD5 29 #define RK_PD6 30 #define RK_PD7 31 Applyed changes here: https://github.com/hqnicolas/ArmBoardBringUp/blob/main/patch/kernel/archive/rockchip64-6.6/dt/rk3566-h96-tvbox.dts Testing.............. Edited April 18 by Hqnicolas 0 Quote
pocosparc Posted April 18 Posted April 18 Hi, yes this was also my conclusion. The pins were defined OK, but there was no voltage on that VCCIO4 domain - so the whole GPIOx was kept inactive or in a reset. It was confusing me, why BT is running, but there is no WiFi - the chip has to be powered somehow. I also see that you already defined the backlights on this PCBA. vor 5 Stunden schrieb Hqnicolas: shutdown-gpios = <0x8e 0x0f 0x00>; ####### GPiO2 ### RK_PD7 ##### level 0 This one is also confusing me - how is this one PD7? It should normally be PB7 on the GPIO2. Maybe can you share your current dtb file and I will also test it out? 0 Quote
pocosparc Posted April 18 Posted April 18 https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts This one looks promising. Maybe we only need to change some pins. 0 Quote
Hqnicolas Posted April 18 Author Posted April 18 (edited) 4 hours ago, pocosparc said: This one is also confusing me - how is this one PD7? It should normally be PB7 on the GPIO2. Maybe can you share your current dtb file and I will also test it out? I translated it wrong 0x0f 15 PB7 https://github.com/hqnicolas/ArmBoardBringUp/blob/main/patch/kernel/archive/rockchip64-6.6/dt/rk3566-h96-tvbox.dts Testing..... Edited April 18 by Hqnicolas 0 Quote
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