Armbian doesnt seem to see sata harddrives.

[ypopovych]

From what I see it could be backported even to 6.1. It's pretty small change. One new driver into clk-gpio.c, which should work on 6.1 too and couple of changes in the DT file.

[Igor]

22 minutes ago, ypopovych said:

could be backported even to 6.1

You mean this problem is present also on Rockchip vendor kernel? Well, then this is also helpful, while for mainline based kernels, 6.6 and 6.12.y are only target. Besides EDGE, where this will emerge automatically. 
Thanks.

[sdyspb]

10 hours ago, ypopovych said:

When we remove a resistor it simply avoids this bug and SATA controller works in a different mode (which could be slower)

It sounds wrong. There is no degradation in speed. Also, your assumption about SSC of the clock generator is wrong as well. According to datasheet of AU5426, it does not support SSC

Edited Thursday at 07:04 PM by sdyspb

[ypopovych]

8 hours ago, Igor said:

You mean this problem is present also on Rockchip vendor kernel?

yes. We have this problem on Armbian with 6.1 vendor kernel. And also ubuntu builds from Joshua Riek have the same problem (they use vendor 6.1 too)

 

=====

 

@sdyspb but if it's a hardware bug it shouldn't work properly on old 5.10 kernel too. But it works. And also shouldn't work randomly on 6.1 kernel. It's interesting why SRIS disabling fixes it. And why it works on old kernel with SRIS. And we have a kernel patch accepted in the 6.13 mainline kernel with fix for our problem.

 

Edited Thursday at 09:17 PM by ypopovych

[sdyspb]

Just look at this from datasheet and schematic perspective - ASM1164 needs SSC if SRIS is enabled, but according to datasheet of clock generator there is no SSC, so the original schem is not correct. There are three solutions:

 

1) place somehow clock with SSC or the best one is adding the independent clock for ASM1164

2) unsolder R29 to disable SRIS

3) disable SRIS by software

 

At this moment I choose number two, but if you find the third one I will stand on your side 

 

Actually, SRIS means that RC and EP are clocked by different sources (I think it is like SSC where some jitter always exists), but in Radxa 5 ITX all the clocks are produced by one oscillator, so, SRIS is not right mode for this board. According to PCIe architecture the board uses Common REFCLK, not SRIS. Due to Common Clock the PLL of ASM1164 can't sync in SRIS mode because it needs a little deviation to be locked

Edited Thursday at 11:13 PM by sdyspb

[ypopovych]

@sdyspb Should we also bother guys on Radxa forum? I think their forum is a better place to ask about hardware. Meantime software fix from latest kernel could be backported to enable oscillator without depending on the initialization order

[sdyspb]

I've already sent them my fix in WeChat (Tom Cubie and his team). They promised to take a look at my point. Of course, asking them on forum is a great idea

Edited Thursday at 11:08 PM by sdyspb

[prahal]

I will try this 6.13 patchset but it looks like SATA drives are already stable with 6.12 (iè without this patchset) or at least more stable than vendor 6.1.
Could be another fix between 6.1 and 6.12 helps.

Envoyé de mon CPH2089 en utilisant Tapatalk

[prahal]

Still building 6.1 vendor with the gated clock patch set. Though I noticed the mainline kernel has default pinctrl settings for pcie but not the vendor one. If one want to try testing these dts pinctrl pcie definition from mainline to vendor.