Armbian doesnt seem to see sata harddrives.

[prahal]

@Popolon indeed this issue rot for a long time. I cleaned up my backlog to have more time for armbian. Also I still have quite a few processes to learn about armbian board maintenance still to this day. 

 

But you confirm that with mainline 6.12 all is fine ? But, indeed no HDMI out and no audio. I still have a patch for mainline 6.12 in the pipe about a race condition between SATA chip and nvme as far as I remind. I will prioritize data vendor kernel debugging if this mainline patch is not required (and indeed mainline still lacks any multimedia capability, this might be a showstopper for most users) even though I am close to complete testing and send PR for this one.

 

As of now I have confirmed that this mainline patch set does not help vendor as the vendor branch has a hack that workaround the issue that mainline faces about this SATA/nvme race.

 

[prahal]

On 2/20/2025 at 11:24 PM, sdyspb said:

Just look at this from datasheet and schematic perspective - ASM1164 needs SSC if SRIS is enabled, but according to datasheet of clock generator there is no SSC, so the original schem is not correct. There are three solutions:

 

1) place somehow clock with SSC or the best one is adding the independent clock for ASM1164

2) unsolder R29 to disable SRIS

3) disable SRIS by software

 

At this moment I choose number two, but if you find the third one I will stand on your side 

 

Actually, SRIS means that RC and EP are clocked by different sources (I think it is like SSC where some jitter always exists), but in Radxa 5 ITX all the clocks are produced by one oscillator, so, SRIS is not right mode for this board. According to PCIe architecture the board uses Common REFCLK, not SRIS. Due to Common Clock the PLL of ASM1164 can't sync in SRIS mode because it needs a little deviation to be locked

 

Commit a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 in upstream tells that 

"rxX_cmn_refclk_mode"
RX common reference clock mode for lane X. This mode should be enabled
only when the far-end and near-end devices are running with a common
reference clock.

 

The link training either fails or is highly unstable (link state will jump
continuously between L0 and recovery) when this mode is enabled while
using an endpoint running in Separate Reference Clock with No SSC (SRNS)
mode or Separate Reference Clock with SSC (SRIS) mode.

 

I applied this patch and set `rockchip,rx-common-refclk-mode = <0 0 0 0>;` for `&pcie30phy` in rk3588-rock-5-itx.dtb as upstream does and SATA detection is stable now.

 

 

To all:

I still have that patch for upstream 6.12 to avoid having the ASM Sata PCIe controller hang when the M.2 PCIe controller is initialized first, pending. However, there were no reports of Armbian sata detection failure with 6.12 in this thread. Please report if I should bring it sooner.