Not be to a downer - but RISC-V, while interesting, is out of scope, much like X86/AMD64
RISC-V in particular - the ISA is under active development, and we have a wide array of chipset/SoC vendors that perhaps need improvement on their docs...
SImilar - I do a lot of work on older MIPS K24c chipset - but I don't bring specific back to the community here, as it's not relevant...
until