4 SPI

Marko Buršič


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On 12/16/2019 at 6:27 PM, Marko Buršič said:

And it was working OK. IMO, the good candidate for CS1 is GPIO4_D5 to get SPI1.1 device. So please, don't mess things that are already working properly. I don't understand why user messed up with renumbering the SPI channels and it gets /dev/spidev0.0 , SPI0 is already shared with ETH-PHY on RockPi 4.


I don't mess something up,  the DTBO which is provided in this post brings up spidev0.1, I just try to help @martinayotte to get the cs-gpio kernel patch to work to help testing the patch with real hardware, that's all.  With this you can have a SPI Bus and multiple GPIOs as chipselect so in other words use more than SPI Device on a single bus. As SPI Devices are common in the industrial field this would enhance the rockchip a lot.


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2 hours ago, said:

I just try to help @martinayotte to get the cs-gpio kernel patch to work to help testing the patch with real hardware

I'm still working on that ! I've just doing a new build with more traces since I got the following error which is a complete "non-sense" since /cpus/cpu@1 is NOT a gpio-controler, and all gpio-controlers have their #gpio-cells property :

[77657.634284] OF: /spi@ff1d0000: could not get #gpio-cells for /cpus/cpu@1
[77657.634295] rockchip-spi ff1d0000.spi: Failed to register master
[77657.634389] rockchip-spi: probe of ff1d0000.spi failed with error -22

EDIT: I think I figured it out : argument os "cs-gpio" is not <gpiobank_number pin_number active_low> but <gpioctl_phandle pin_number active_low> !

So, when I was passing gpiobank_number as 3, 3 was the phandle of /cpus/cpu@1, so, of course, not related ...

Since gpioctl_phandle could vary from one image to another, I can't hard coded in an overlay, I need to figure out a nice way to have such overlay.

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Got it working. I have changed the main .dtb file, but who knows it could be stripped to .dtbo as plugin, since I have manually added phandles, so not best suitable if the software gets updated.


The main added nodes are as follows:


1. In the pinctrl/spi1 node is added a subnode of definition of GPIO pin spi1/spi1-cs1 0x04 means GPIO4 conteller, 0x1a means pin D2 (therefore GPIO4_D2),  0x00 means a common GPIO (not linked to special functions), 0xb0 means no pull-up/down configured.  A phandle of 0x302 is added by myself manually, I guess a dtbo overlay could do it symbolically.

spi1 {

            spi1-clk {
                rockchip,pins = < 0x01 0x09 0x02 0xb3 >;
                phandle = < 0x4e >;

            spi1-cs0 {
                rockchip,pins = < 0x01 0x0a 0x02 0xb3 >;
                phandle = < 0x51 >;

            spi1-rx {
                rockchip,pins = < 0x01 0x07 0x02 0xb3 >;
                phandle = < 0x50 >;

            spi1-tx {
                rockchip,pins = < 0x01 0x08 0x02 0xb3 >;
                phandle = < 0x4f >;
            spi1-cs1 {
                rockchip,pins = < 0x04 0x1a 0x00 0xb0 >;
                phandle = < 0x302 >;


2.  In spi1 controller node (spi@ff1d0000) is added a reference to new CS pin : cs-gpios = <0>, <0x16 0x1a 0x00>; Where <0> is found working experimental, I have no idea what's its meaning, but changing this to <1> throws exception of IRQ, probably links the pin to IRQ controller.  0x16 is a handle to GPIO4 controller, 0x1a is a pin number D2 (so, GPIO4_D2) , 0x00 means ACTIVE_HIGH.


Spidev@0 works on hardware CS0 which is GPIO1_B2 (reg=<0>) , meanwhile the spidev@1 works with cs-gpios, GPIO4_D2 (reg=<1>). If enabled flash it would work with CS0, my LCD is still in research phase.


I got spidev1.0 and spidev1.1, traced the functionality with DSO, they both seems to work. It has to have newer kernel (mine 5.4.38) and kernel patched with add-csgpio-to-rockchip-spi.patch, the one provided by @martinayotte published in this post.

spi@ff1d0000 {
        compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
        reg = < 0x00 0xff1d0000 0x00 0x1000 >;
        clocks = < 0x08 0x48 0x08 0x15c >;
        clock-names = "spiclk\0apb_pclk";
        interrupts = < 0x00 0x35 0x04 0x00 >;
        dmas = < 0x49 0x0c 0x49 0x0d >;
        dma-names = "tx\0rx";
        pinctrl-names = "default";
        pinctrl-0 = < 0x4e 0x4f 0x50 0x51 0x302>;
        #address-cells = < 0x01 >;
        #size-cells = < 0x00 >;
        status = "okay";
        phandle = < 0xda >;
        cs-gpios = <0>, <0x16 0x1a 0x00>;

        spidev@0 {
            compatible = "rockchip,spidev";
            reg = <0>;
            status = "okay";
            spi-max-frequency = < 0x989680 >;

        spidev@1 {
            compatible = "rockchip,spidev";
            reg = <1>;
            status = "okay";
            spi-max-frequency = < 0x989680 >;

        spiflash@0 {
            compatible = "jedec,spi-nor";
            reg = < 0x00 >;
            spi-max-frequency = < 0x989680 >;
            status = "disabled";
            compatible = "solomon,ssd1322";
            reg = <1>;
            pinctrl-names = "default";
            pinctrl-0 = <0x300 0x301>;
            spi-max-frequency = <1000000>;
            buswidth = <8>;
                    rotate = <0>;
                    bgr = <0>;
                    fps = <20>;
            dc-gpios = <0x16 0x1c 0x00>; // phandle to gpio4=0x16 , pin Nr = D4=0x1c, GPIO_ACTIVE_HIGH = 0x00 
            reset-gpios = <0x16 0x1d 0x00>;    // phandle to gpio4=0x16 , pin Nr = D5=0x1d, GPIO_ACTIVE_HIGH = 0x00 
            debug = <0>;
            status = "disabled";




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