5kft

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  1. Like
    5kft got a reaction from guidol in Orange PI Zero Plus CPU frequency problem   
    I'm just catching up on this topic...  I don't have access to my Zero Plus at the moment but from the picture on Xunlong's site (and my previous experience) it looks like this board has the same HW limitation as the Plus2 - the missing Q5 MOSFET (see red oval highlight in this picture):

    This problem/limitation is described in this thread:
     
    @Darkyere, if it in fact is the case that this part is not included on this board, then unfortunately your board will be limited to a maximum of 1008MHz (for reliable operation).  According to the schematic (https://linux-sunxi.org/images/6/67/ORANGE_PI-ZERO-PLUS_V1_0_Schematic.pdf, page 7), the power circuit does include the switching regulator, so it should be capable of providing 1.3v if this part were installed.  (Again, refer to the thread I mentioned previously for all details about this.)
     
    Igor's guidance of specifying the 1.3v regulator overlay alone is a workaround that will enable the higher clockrate to 1.0GHz.  However, without the Q5 MOSFET installed, do not specify the 1.3GHz overclock overlay, as then your board will certainly crash (as you noticed) 
     
     
  2. Like
    5kft got a reaction from guidol in H5 board without voltage-switching only up to 816Mhz?   
    Hi @guidol, I've pushed the change to sunxi-dev:  https://github.com/armbian/build/commit/f1cdca27530ed401ff3f5f301aae46155704c85d
     
    Enjoy!  
  3. Like
    5kft got a reaction from guidol in H5 board without voltage-switching only up to 816Mhz?   
    Makes sense; I'll merge this new overlay patch in with the existing 1.3GHz patch and should be able to push it tonight.  Thanks for testing it!
  4. Like
    5kft got a reaction from guidol in NanoPi NEO2 Voltage Regulator Update   
    Indeed, I took a quick look at the schematic (http://wiki.friendlyarm.com/wiki/images/5/57/NanoPi-NEO2-Black_1907_Schematic.pdf) and noticed a few things (if the schematic is accurate):
    If the VCC regulator is really a SY8106A (first page notes it is a MP2143DJ, which I'm guessing is a mistake), then the power circuit looks like the same as the NEO Core2, which means that the board may be able to drive the core voltage to 1.4v, meaning it can run up to 1.4GHz (like on the Core2).  This is nice! The board "version" GPIO (PL3) is wired the same as the NEO2 v1.1, so for the NEO2 build target this won't allow full speed of the board as this would load the NEO2 v1.1 default DT which actually uses the far more limited MP2143DJ regulator.   In fact, with the Black they wired PC4, PC6, and PC7 the same as well as the NEO2 v1.1, which means that we can't do runtime board identification.  This likely means that we'll have to do a different board target...
  5. Like
    5kft reacted to guidol in NanoPi NEO2 Voltage Regulator Update   
    @Neko May armbian has support  for 1.3V
     
    Use armbian-config ==> system ==> hardware
    and enable
    cpu-clock-1.3GHz-1.3v
    and
    gpio-regulator-1.3v
     
    save/reboot
     
    and now set cpu-governor and speeds in armbian-config ==> system ==> CPU
    (I think with these new setting you will get all speeds)
     
    PS: I ediited  my DTB for the OPi Zero Plus2 H5 to allow up to 1008Mhz with the 1.1v setting
    (like I had it on older armbian-builds):

  6. Like
    5kft reacted to guidol in Start looking at 5.3.y   
    @5kft I edited my table a bit less conservative - setting also 960 and 1008Mhz to 1.1V.
     
    and the OPi Zero Plus2 H5 "does work" - i dont know how good, but for testing reasons it seems to be OK for me
      hardware limits: 480 MHz - 1.01 GHz
      available frequency steps: 480 MHz, 648 MHz, 816 MHz, 960 MHz, 1.01 GHz
    idle:
      cpufreq stats: 480 MHz:95.51%, 648 MHz:0.15%, 816 MHz:0.70%, 960 MHz:0.01%, 1.01 GHz:3.63%  (142)
     
  7. Like
    5kft got a reaction from guidol in Start looking at 5.3.y   
    Hi @guidol, my guess is that you are seeing the crash at boot on your board because of the default hardware limitation in the Plus2.  Using the default opp table you can run an Plus2 at higher clock rates than 816MHz only if you've added the missing MOSFET part (see thread at https://forum.armbian.com/topic/6866-orange-pi-zero-plus2-h5-hardware-oddity-in-vdd_cpux-power-circuit/).
     
    The default opp table is requiring 1.2v for operation at 960MHz+, and the regulator output for an unmodified OPi Plus2 is 1.1v.  It might be possible to reliably push the H5 to 1008MHz at 1.1v, but the default table is more conservative (not sure why).  FWIW I run all my boards at higher speeds, (including my NEO Core2s at 1.4GHz - see https://github.com/5kft/nanopi-misc/blob/master/nanopi-neo-core2-1.4GHz/nanopi-neo-core2-1.4GHz.dts).
     
  8. Like
    5kft reacted to Igor in armbianmonitor cpu-temperature broken? -ge: unary operator expected   
    https://github.com/armbian/build/commit/76ac54aae381714cee7bf1b03d4bce097b1630de
    root@orangepizeroplus2:~# uname -a Linux orangepizeroplus2 5.1.15-sunxi64 #5.90 SMP Thu Jul 4 21:07:22 CEST 2019 aarch64 GNU/Linux root@orangepizeroplus2:~# cat /sys/class/thermal/thermal_zone0/temp 58191  
  9. Like
    5kft got a reaction from chwe in armbianmonitor cpu-temperature broken? -ge: unary operator expected   
    Hi @Igor, @guidol - in case it is helpful, I took a quick look at this and the fix is pretty straightforward.  Essentially all that needs to be done is to remove the existing "patch/kernel/sunxi-dev/ths-29-sun4i-gpadc-iio-add-h5-thermal-zone.patch" for 5.1, and to port over the 4.19 "patch/kernel/sunxi-next/ths-29-add-correct-h5-thermal-zone.patch" to 5.1 (i.e., bring into "patch/kernel/sunxi-dev/").  The problem is the currently the thermal-zone is defined in the wrong DT location, and the zone definition and tips  and cooling maps are incorrect/incomplete for the 5.1 version.
     
    I did a quick test of fixing it this way and the result works:
    root@nanopineo2:~# cat /proc/version Linux version 5.1.15-sunxi64 (root@elrond) (gcc version 7.4.1 20181213 [linaro-7.4-2019.02 revision 56ec6f6b99cc167ff0c2f8e1a2eed33b1edc85d4] (Linaro GCC 7.4-2019.02)) #5.90.190705 SMP Thu Jul 4 14:05:17 UTC 2019 root@nanopineo2:~# cat /sys/class/thermal/thermal_zone0/temp 40936 root@nanopineo2:~# I'd fix this and submit the change myself, but unfortunately I don't have time to be thorough about testing it right now (e.g., verify on some H3 boards and other H5 boards as well), and likely won't be able to until next week...I'm happy to do this then if you don't have time to look into this.
  10. Like
    5kft got a reaction from guidol in armbianmonitor cpu-temperature broken? -ge: unary operator expected   
    Hi @Igor, @guidol - in case it is helpful, I took a quick look at this and the fix is pretty straightforward.  Essentially all that needs to be done is to remove the existing "patch/kernel/sunxi-dev/ths-29-sun4i-gpadc-iio-add-h5-thermal-zone.patch" for 5.1, and to port over the 4.19 "patch/kernel/sunxi-next/ths-29-add-correct-h5-thermal-zone.patch" to 5.1 (i.e., bring into "patch/kernel/sunxi-dev/").  The problem is the currently the thermal-zone is defined in the wrong DT location, and the zone definition and tips  and cooling maps are incorrect/incomplete for the 5.1 version.
     
    I did a quick test of fixing it this way and the result works:
    root@nanopineo2:~# cat /proc/version Linux version 5.1.15-sunxi64 (root@elrond) (gcc version 7.4.1 20181213 [linaro-7.4-2019.02 revision 56ec6f6b99cc167ff0c2f8e1a2eed33b1edc85d4] (Linaro GCC 7.4-2019.02)) #5.90.190705 SMP Thu Jul 4 14:05:17 UTC 2019 root@nanopineo2:~# cat /sys/class/thermal/thermal_zone0/temp 40936 root@nanopineo2:~# I'd fix this and submit the change myself, but unfortunately I don't have time to be thorough about testing it right now (e.g., verify on some H3 boards and other H5 boards as well), and likely won't be able to until next week...I'm happy to do this then if you don't have time to look into this.
  11. Like
    5kft got a reaction from LJB in Problem with Wifi on NanoPi Neo Plus2   
    The problem with AP6212 appears to be a regression caused by this commit:  https://github.com/armbian/build/commit/52d82c921d02366f5fe7fa5e6a754227ce9e6913.  I added a comment to the commit regarding this...
     
  12. Like
    5kft got a reaction from Igor in Problem with Wifi on NanoPi Neo Plus2   
    The problem with AP6212 appears to be a regression caused by this commit:  https://github.com/armbian/build/commit/52d82c921d02366f5fe7fa5e6a754227ce9e6913.  I added a comment to the commit regarding this...
     
  13. Like
    5kft got a reaction from Dwyt in Nanopi NEO2 CPU frequency issue   
    Per request, here are updated instructions for overclocking the NEO2 v1.1 LTS board to 1.3GHz, for the latest builds of Armbian (kernel 4.19+, build 5.70+):
     
    1.  Please note that this will not work on a NEO2 v1.0 board - the first version of the board doesn't include a regulator nor circuit that supports voltage switching.  Only follow these instructions if you are using a v1.1 board!
     
     
    2.  Edit /boot/armbianEnv.txt, and add these lines:
    overlay_prefix=sun50i-h5 overlays=cpu-clock-1.3GHz-1.3v If you have other overlays specified in your /boot/armbianEnv.txt, simply append these two new ones following them, for example:
    overlay_prefix=sun50i-h5 overlays=spi-spidev usbhost1 usbhost2 cpu-clock-1.3GHz-1.3v  
    3.  Edit /etc/default/cpufrequtils, and set the MAX_SPEED definition to 1300000, e.g.:
    # WARNING: this file will be replaced on board support package (linux-root-...) upgrade ENABLE=true MIN_SPEED=408000 MAX_SPEED=1300000 GOVERNOR=ondemand  
    4.  Configure APT so that /etc/default/cpufrequtils will not be reverted to the system default when the package is upgraded (e.g., via "apt upgrade"):
    dpkg-divert --add /etc/default/cpufrequtils  
    5.  Reboot the board.
     
    That should be it!  Following reboot, you can verify proper operation at the higher CPU clock speeds using "cpufreq-info" (for example).
  14. Like
    5kft got a reaction from Dwyt in Nanopi NEO2 CPU frequency issue   
    Given the number of boards that can support higher CPU clocks (e.g., Nano Pi Neo 2, Plus2, Core2, OPi Zero Plus, OPi Zero Plus2 w/H/W MOSFET fix, etc.) it'd be great to be able to do this with overlays, rather than introduce a combinatorial explosion of board DTBs (i.e., per-board 1.1GHz max, 1.3GHz max, 1.4GHz max).
     
    I have made some test override overlays to add the regulator and extend the CPU operating table (e.g., adding additional CPU core clock frequencies).  This works fine - one can just add the desired overlays in armbianEnv.txt and the new clock speeds appear and work:
    ... overlay_prefix=sun50i-h5 overlays=spi-spidev usbhost2 usbhost3 gpio-regulator-1.3v cpu-clock-1.3GHz param_spidev_spi_bus=1 ... However the problem is that one can't reliably run these boards at the higher clock rates without adjusting the thermal-zone cooling-map for the higher speeds.  Unfortunately device tree overlays don't appear to support thermal zones (at least I can't get them to compile with these present ).
     
    I'm interested if anyone might have any ideas to to manage this.  Just brainstorming here, but perhaps we could make the default cooling-map for the H5 a bit more conservative, and then it could cover the introduction of the higher possible clock rates?  Or perhaps we could remove some slower entries from the H5 default clock operating table to allow for the addition of the optional higher clock rates (to better correspond to the default H5 cooling-map)?
     
    Again, the nice thing about the overlay route is that we wouldn't have to change the 1.1GHz Armbian H5 default, so operation will be reliable.  But if users want to try speeding up their boards (whatever brand, VDD regulator, etc.), then they can just add an overlay or two and voila the higher speeds will be enabled.
     
  15. Like
    5kft got a reaction from Frank F. in NanoPi NEO2 or NEO Plus2 - Shopping advice needed   
    Hi @Frank F., interesting...I'm not sure why the Plus2 is still WIP, as IMHO it essentially is at the same level of functionality as the other FriendlyElec H5 boards (e.g., NEO2).  I actually use both boards for several different purposes and they work really well.
     
    I use both GPIOs and SPI on the NEO2 and they work great (multiple LED control as well as interfacing to an nRF24l01-based wireless radio).  I have tried a subset of the I/Os on the NEO Plus2 some time back (e.g., testing interfacing with SPI flash), but haven't used the I/Os on that board since.  I don't know why it all wouldn't work the same on the Plus2 given that the base platforms are essentially the same.
     
    Wi-Fi works nicely on the Plus2 (I use the FE metal case with the included antenna).  I haven't tried BT.  The USB ports work fine on both.  The eMMC on the Plus2 is fairly fast as well (I use btrfs to save space as it is only 8GB in size).  They both overclock nicely to 1.3GHz.
     
    Here's a quick dump of some stuff from the Plus2:
    root@nano:~# cat /proc/version Linux version 4.19.20-sunxi64 (root@armbian.com) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 10:29:25 CET 2019 root@nano:~# uptime 14:20:35 up 49 days, 22:46, 2 users, load average: 0.04, 0.03, 0.00 root@nano:~# dpkg --list | grep plus2 ii linux-stretch-root-next-nanopineoplus2 5.73 arm64 Armbian tweaks for stretch on nanopineoplus2 (next branch) ii linux-u-boot-nanopineoplus2-next 5.75 arm64 Uboot loader 2018.11 root@nano:~# hdparm -tT /dev/mmcblk2 /dev/mmcblk2: Timing cached reads: 1078 MB in 2.00 seconds = 538.66 MB/sec Timing buffered disk reads: 132 MB in 3.04 seconds = 43.41 MB/sec root@nano:~# root@nano:~# sysbench --test=cpu --cpu-max-prime=20000 --num-threads=4 run sysbench 0.4.12: multi-threaded system evaluation benchmark Running the test with following options: Number of threads: 4 Doing CPU performance benchmark Threads started! Done. Maximum prime number checked in CPU test: 20000 Test execution summary: total time: 7.0618s total number of events: 10000 total time taken by event execution: 28.2335 per-request statistics: min: 2.79ms avg: 2.82ms max: 8.84ms approx. 95 percentile: 2.79ms Threads fairness: events (avg/stddev): 2500.0000/0.71 execution time (avg/stddev): 7.0584/0.00 root@nano:~#  
    As to which one to get, a lot depends on your desired use...  The NEO2 is really nice because of its tiny size; however there is no included eMMC, nor Wi-Fi, and it includes just one USB port.  The Plus2 is a bit larger, but the two USB ports and gigE port are nice (I use one of the boards as a local router), as is the built-in Wi-Fi and eMMC (so no additional uSD card is needed).  The metal case for the Plus2 is really great as well (https://www.friendlyarm.com/index.php?route=product/product&path=93&product_id=203).
     
    I hope that this feedback helps a bit!
     
     
  16. Like
    5kft reacted to guidol in Orange Pi Zero Plus2 H5: Install to eMMC bricked device   
    little "dumb" idea:
    if the part outside the linuxfilesystem is damaged, the non-armbian-image will work because of the vfat partition which is "covering" the error.
    years ago I had a old hdd which has bad sectors in the first 1GB.
    after adding a 1GB partition ad the start of the hdd and using the rest as the second partition the os could be installed and used from the second partition.
    Maybe @rmoriz could use the other partition style for armbian when tranfering armbian manually to emmc.
  17. Like
    5kft got a reaction from guidol in Nanopi Neo 2 LEDs (green at least) - just curious   
    Hi @dispo, nice catch!  I just enabled the CPU activity LED trigger in the kernel (https://github.com/armbian/build/commit/fd3b83136b9baa62326feea28d14d44736b6f448).  With this change you can set the LED trigger to "activity" and the LED will flash based upon instant CPU load (across all cores).
  18. Like
    5kft reacted to Igor in Next LTS kernel 4.19.y Allwinner A10, A20, A64, H2+, H3, H5, H6 debugging party   
    Images are building and uploading at this moment. A few more tests and repository will also be updated, so you will be able to upgrade your current build to 4.19.y
  19. Like
    5kft reacted to Igor in Next LTS kernel 4.19.y Allwinner A10, A20, A64, H2+, H3, H5, H6 debugging party   
    You already helped a LOT! 
     

    Indeed! Let's fix this Pinebook's troubles and we might slowly switch 4.19.y to nightly NEXT building ...
  20. Like
    5kft got a reaction from Igor in Next LTS kernel 4.19.y Allwinner A10, A20, A64, H2+, H3, H5, H6 debugging party   
    Hi @Igor, I just tested both I2C and SPI on the Plus2 H5 and both appear to work.  Both tests were to devices connected to the pin header.  The SPI test was using a 4MB SPI flash part, and the I2C test was just to detect an SH1106 OLED display connected to TWI0-SDA/SCK (display is configured at I2C address 0x3c):
    root@orangepizeroplus2:~/tmp# dd if=/dev/random of=test.dat bs=1024 count=4096 iflag=fullblock 4096+0 records in 4096+0 records out 4194304 bytes (4.2 MB, 4.0 MiB) copied, 8.29973 s, 505 kB/s root@orangepizeroplus2:~/tmp# root@orangepizeroplus2:~/tmp# flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -w test.dat flashrom v0.9.9-r1954 on Linux 4.19.4-sunxi64 (aarch64) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25Q32.V" (4096 kB, SPI) on linux_spi. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. root@orangepizeroplus2:~/tmp# flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -r test2.dat flashrom v0.9.9-r1954 on Linux 4.19.4-sunxi64 (aarch64) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25Q32.V" (4096 kB, SPI) on linux_spi. Reading flash... done. root@orangepizeroplus2:~/tmp# md5sum test*.dat 979776e45a0b9fd7caf154f4f1bbbbf4 test2.dat 979776e45a0b9fd7caf154f4f1bbbbf4 test.dat root@orangepizeroplus2:~/tmp# root@orangepizeroplus2:~/tmp# i2cdetect -y 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- 3c -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- root@orangepizeroplus2:~/tmp# root@orangepizeroplus2:~/tmp# cat /boot/armbianEnv.txt verbosity=1 console=both overlay_prefix=sun50i-h5 overlays=usbhost2 usbhost3 spi-spidev i2c0 param_spidev_spi_bus=1 rootdev=UUID=2b29fd0a-3553-4999-be20-f3175d84e624 rootfstype=ext4 usbstoragequirks=0x2537:0x1066:u,0x2537:0x1068:u root@orangepizeroplus2:~/tmp# Very nice how well it all is working!
     
  21. Like
    5kft got a reaction from guidol in Next LTS kernel 4.19.y Allwinner A10, A20, A64, H2+, H3, H5, H6 debugging party   
    Hi, this should now be fixed with https://github.com/armbian/build/commit/e0f27fff66220e56b6419879957af28fa46ff84f.  I tested this on an unmodified Plus2 H5 (i.e., missing MOSFET in the regulator switching circuit).  Without this change the boot would fail as @guidol noted (heartbeat, then stops, and the board hangs); with this change it boots and runs just fine, and the maximum CPU clock rate is properly limited.
  22. Like
    5kft got a reaction from Igor in Next LTS kernel 4.19.y Allwinner A10, A20, A64, H2+, H3, H5, H6 debugging party   
    Hi, this should now be fixed with https://github.com/armbian/build/commit/e0f27fff66220e56b6419879957af28fa46ff84f.  I tested this on an unmodified Plus2 H5 (i.e., missing MOSFET in the regulator switching circuit).  Without this change the boot would fail as @guidol noted (heartbeat, then stops, and the board hangs); with this change it boots and runs just fine, and the maximum CPU clock rate is properly limited.
  23. Like
    5kft reacted to guidol in Next LTS kernel 4.19.y Allwinner A10, A20, A64, H2+, H3, H5, H6 debugging party   
    I did also compile for the OPi R1 - I could also successfully test the USB via the OPi NAS AddOn.
    A report has been created (dont know if @5kft did this also)
    I do have some lacking at the SSH-connection via eth0  like on a "bad" WiFi-Connection because of:
     
    [ 1439.605021] ==> rtl8188e_iol_efuse_patch [ 1501.258078] dwmac-sun8i 1c30000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx [ 1523.785870] dwmac-sun8i 1c30000.ethernet eth0: Link is Down [ 1524.810021] dwmac-sun8i 1c30000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx [ 1528.905843] dwmac-sun8i 1c30000.ethernet eth0: Link is Down [ 1529.930016] dwmac-sun8i 1c30000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx [ 1538.121820] dwmac-sun8i 1c30000.ethernet eth0: Link is Down [ 1539.146029] dwmac-sun8i 1c30000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx [ 1628.389288] ==> rtl8188e_iol_efuse_patch [ 1691.429555] ==> rtl8188e_iol_efuse_patch [ 1754.554618] ==> rtl8188e_iol_efuse_patch the second ethernet-port enxc0742bffxxxx didnt seem to have this lacking
  24. Like
    5kft got a reaction from shaun27 in Quick review of NanoPi Fire3   
    Hi @shaun27, I just implemented support for this for the Fire3 and have pushed the changes into Armbian (see https://github.com/armbian/build/commit/1301f9f8c254d8408b9136948c786dffa5007acd).  The power button/PWRKEY now works for both powering up the board as well as powering it down 
     
  25. Like
    5kft got a reaction from Igor in Next LTS kernel 4.19.y Allwinner A10, A20, A64, H2+, H3, H5, H6 debugging party   
    Hi @Igor, just a quick note - I had to make a small fix for Orange Pi Zero Plus (https://github.com/armbian/build/commit/b0f92ee58c6cbefbbcd52dcb93e1128c7528cb54); with this change this board seems to work fine now as well with the new 4.19.y kernel.