balbes150 Posted January 8, 2019 Posted January 8, 2019 On 12/30/2018 at 12:56 AM, NicoD said: I tried downloading your LibreElec image for the Edge. Got this message 'Произошла ошибка'. I don't have an Edge, but still wanted to let you know. What dtb was used ? Have you tried the "combined" startup option (write the same image to the SD card and USB flash drive, connect the SD and USB media at the same time, and turn on the power) ?
NicoD Posted January 8, 2019 Posted January 8, 2019 7 hours ago, balbes150 said: What dtb was used ? Have you tried the "combined" startup option (write the same image to the SD card and USB flash drive, connect the SD and USB media at the same time, and turn on the power) ? I can not download the image from Yandjeks. The .img.gz file gives "Ой, что-то сломалось…" when I click on it. And I can't login to yandjeks either for the other file. I just downloaded the LibreElec from the Khadas Edge download page. I thought it's also yours they're using. It didn't have the other .dtb files. I had an older Armbian image of you for the RK3399, I installed that on an sd, copied all the .dtb files. There's none for the NanoPi M4, so I choose RockPro64. Seems to work great. Sound ok, 4K plays well. So great job. Thank you.
balbes150 Posted January 9, 2019 Posted January 9, 2019 13 hours ago, NicoD said: I just downloaded the LibreElec from the Khadas Edge download page. I thought it's also yours they're using. It didn't have the other .dtb files. I had an older Armbian image of you for the RK3399, I installed that on an sd, copied all the .dtb files. There's none for the NanoPi M4, so I choose RockPro64. On the download page Khadas version of arm, I build aarch64, so this is a different version. Perhaps it is built from the official git Libreelec or GIT Kwiboo.
Arinze Izukanne Posted January 17, 2019 Posted January 17, 2019 Hi @martinayotte, I am considering using this Orange Pi RK3399 for a project. Your feedback on a few issues will be appreciated. Were you able to load armbian and boot from eMMC? Do the onboard sensors Hall, Gyro, Compass etc work with the NanoPC-T4 4.19.y image? How stable is the board? Thanks
martinayotte Posted January 17, 2019 Posted January 17, 2019 4 hours ago, Arinze Izukanne said: Were you able to load armbian and boot from eMMC? Yes ! 4 hours ago, Arinze Izukanne said: Do the onboard sensors Hall, Gyro, Compass etc work with the NanoPC-T4 4.19.y image? No needs of NanoPC-T4, since I've created an OrangePi-RK3399 template, so you can build an image for that. Sensors are appearing on /dev/i2c-4, so you simply need to get proper software/library to use them. 4 hours ago, Arinze Izukanne said: How stable is the board? Pretty stable !
Arinze Izukanne Posted January 17, 2019 Posted January 17, 2019 2 hours ago, martinayotte said: No needs of NanoPC-T4, since I've created an OrangePi-RK3399 template, so you can build an image for that. Splendid. Please how can I access the template?
martinayotte Posted January 17, 2019 Posted January 17, 2019 Using Armbian build process with the EXPERT mode, it will be in the WIP boards list : sudo ./compile.sh EXPERT=yes PROGRESS_DISPLAY=plain PROGRESS_LOG_TO_FILE=yes | tee build.log
Igor Posted January 25, 2019 Posted January 25, 2019 Which recipe is working for Orange RK3399? Legacy kernel. I tried to build from what we have. It stops here: Spoiler DDR Version 1.07 20161103 In Channel 0: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Channel 1: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB 256B stride ch 0 ddrconfig = 0x101, ddrsize = 0x20 ch 1 ddrconfig = 0x101, ddrsize = 0x20 pmugrf_os_reg[2] = 0x32817281, stride = 0x9 OUT Boot1: 2016-07-29, version: 1.05 CPUId = 0x0 ChipType = 10 1842 SdmmcInit=2 0 BootCapSize=100000 UserCapSize=14910MB FwPartOffset=2000 , 100000 SdmmcInit=0 0 BootCapSize=0 UserCapSize=30528MB FwPartOffset=2000 , 0 StorageInit ok = 242066 LoadTrustBL No find bl30.bin No find bl32.bin theLoader 200000 315112 LoaderFlag2: 0x0 Unhandled Exception in EL3. x30 = 0x0000000000034804 x0 = 0x0f1e2d3c4b5a6978 x1 = 0x0000000000030080 x2 = 0x0000000000000018 x3 = 0x0000000000000018 x4 = 0x0000000000000018 x5 = 0x0000000000000000 x6 = 0x0000000000000000 x7 = 0x0000000000000000 x8 = 0x0000000003011908 x9 = 0x0000000000010080 x10 = 0x000000000001ffa8 x11 = 0x0000000000000000 x12 = 0x000000000000000a x13 = 0x0000000000000001 x14 = 0x0000000000000002 x15 = 0x0000000000000004 x16 = 0x0000000000000000 x17 = 0x0000000000000000 x18 = 0x0000000000800000 x19 = 0x0f1e2d3c4b5a6978 x20 = 0x0000000000038210 x21 = 0x0f1e2d3c4b5a6978 x22 = 0x000000000003168d x23 = 0x0000000000038220 x24 = 0x0000000000012000 x25 = 0x0000000000000001 x26 = 0x00000000ff8c2000 x27 = 0x0000000000000110 x28 = 0x0000000000000110 x29 = 0x00000000000358c0 scr_el3 = 0x0000000000000238 sctlr_el3 = 0x0000000000c5383a cptr_el3 = 0x0000000000000000 tcr_el3 = 0x0000000000000000 daif = 0x00000000000003c0 mair_el3 = 0x44e048e000098aa4 spsr_el3 = 0x00000000600002cc elr_el3 = 0x0000000000011724 ttbr0_el3 = 0x00128104060c2001 esr_el3 = 0x0000000096000000 far_el3 = 0x0f1e2d3c4b5a6978 spsr_el1 = 0x00000000080404fc elr_el1 = 0x00407d2944003000 spsr_abt = 0x0000000022110518 spsr_und = 0x0000000086142804 spsr_irq = 0x0000000008095000 spsr_fiq = 0x0000000000180001 sctlr_el1 = 0x0000000000c52838 actlr_el1 = 0x0000000000000000 cpacr_el1 = 0x0000000000000000 csselr_el1 = 0x0000000000000000 sp_el1 = 0x91224080010c1b00 esr_el1 = 0x0000000021d209c8 ttbr0_el1 = 0x2004d00809072318 ttbr1_el1 = 0x5448180880450400 mair_el1 = 0x44e048e000098aa4 amair_el1 = 0x0000000000000000 tcr_el1 = 0x0000000000000000 tpidr_el1 = 0x1109000030000208 tpidr_el0 = 0x3080101260800100 tpidrro_el0 = 0x0002801251008161 dacr32_el2 = 0x0000000080020472 ifsr32_el2 = 0x0000000000000020 par_el1 = 0xd600000040c01004 mpidr_el1 = 0x0000000080000000 afsr0_el1 = 0x0000000000000000 afsr1_el1 = 0x0000000000000000 contextidr_el1 = 0x0000000000000000 vbar_el1 = 0x0000000000000000 cntp_ctl_el0 = 0x0000000000000000 cntp_cval_el0 = 0x0109000800001221 cntv_ctl_el0 = 0x0000000000000000 cntv_cval_el0 = 0x0188004440051000 cntkctl_el1 = 0x0000000000000000 fpexc32_el2 = 0x0000000000000700 sp_el0 = 0x00000000000358c0 isr_el1 = 0x0000000000000000 cpuectlr_el1 = 0x0000000000000040 cpumerrsr_el1 = 0x0000000000000000 l2merrsr_el1 = 0x0000000000000000 gicc_hppir = 0x0000000000000000 gicc_ahppir = 0x0000000000000000 gicc_ctlr = 0x0000000014000082 gicd_ispendr regs (Offsets 0x200 - 0x278) 0000000000000200: 0x0000001800000000 0000000000000208: 0x0000000000000000 0000000000000210: 0x0000000000000010 0000000000000218: 0x0000000000000000 0000000000000220: 0x0000000000000000 0000000000000228: 0x0000000000000000 0000000000000230: 0x0000000000000000 0000000000000238: 0x0000000000000000 0000000000000240: 0x0000000000000000 0000000000000248: 0x0000000000000000 0000000000000250: 0x0000000000000000 0000000000000258: 0x0000000000000000 0000000000000260: 0x0000000000000000 0000000000000268: 0x0000000000000000 0000000000000270: 0x0000000000000000 0000000000000278: 0x0000000000000000 cci_snoop_ctrl_cluster0 = 0x00000000c0000000 cci_snoop_ctrl_cluster1 = 0x00000000c0000000 Do I need to
martinayotte Posted January 25, 2019 Posted January 25, 2019 2 hours ago, Igor said: Which recipe is working for Orange RK3399? Legacy kernel. I tried to build from what we have. It stops here: Did you have shorted the TP50265 test point to GND ?
Igor Posted January 25, 2019 Posted January 25, 2019 5 minutes ago, martinayotte said: Did you have shorted the TP50265 test point to GND ? Yes. Then it stops here: Spoiler DDR Version 1.07 20161103 In Channel 0: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Channel 1: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB 256B stride ch 0 ddrconfig = 0x101, ddrsize = 0x20 ch 1 ddrconfig = 0x101, ddrsize = 0x20 pmugrf_os_reg[2] = 0x32817281, stride = 0x9 OUT Boot1: 2016-07-29, version: 1.05 CPUId = 0x0 ChipType = 10 1846
Igor Posted January 25, 2019 Posted January 25, 2019 And continue this way: Spoiler mmc: ERROR: SDHCI:Transfer data timeout mmc: ERROR: SDHCI ERR:cmd:0x153a,stat:0x0 mmc: ERROR: Tuning procedure failed, falling back to fixed sampling clock mmc: ERROR: tuning execution failed emmc reinit SdmmcInit=2 0 BootCapSize=100000 UserCapSize=14910MB FwPartOffset=2000 , 100000 SdmmcInit=0 0 BootCapSize=0 UserCapSize=30528MB FwPartOffset=2000 , 0 StorageInit ok = 12825500 LoadTrustBL No find bl30.bin No find bl32.bin theLoader 200000 12898540 LoaderFlag2: 0x0 Unhandled Exception in EL3. when I remove shorting.
martinayotte Posted January 25, 2019 Posted January 25, 2019 13 minutes ago, Igor said: Yes. Then it stops here: Strange ... did you kept the short long enough to see u-boot stage #2, the one that will display Armbian U-Boot ? Here is what I'm getting on fresh boot, as you can see, stage #1 DDR doesn't match with your : DDR Version 1.14 20180803 In Channel 0: DDR3, 800MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Channel 1: DDR3, 800MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB 256B stride ch 0 ddrconfig = 0x101, ddrsize = 0x20 ch 1 ddrconfig = 0x101, ddrsize = 0x20 pmugrf_os_reg[2] = 0x32817281, stride = 0x9 OUT Boot1: 2018-08-06, version: 1.15 CPUId = 0x0 ChipType = 0x10, 214 SdmmcInit=2 0 BootCapSize=100000 UserCapSize=14910MB FwPartOffset=2000 , 100000 mmc0:cmd8,20 mmc0:cmd5,20 mmc0:cmd55,20 mmc0:cmd1,20 mmc0:cmd8,20 mmc0:cmd5,20 mmc0:cmd55,20 mmc0:cmd1,20 mmc0:cmd8,20 mmc0:cmd5,20 mmc0:cmd55,20 mmc0:cmd1,20 SdmmcInit=0 1 StorageInit ok = 67017 SecureMode = 0 SecureInit read PBA: 0x4 SecureInit read PBA: 0x404 SecureInit read PBA: 0x804 SecureInit read PBA: 0xc04 SecureInit read PBA: 0x1004 SecureInit read PBA: 0x1404 SecureInit read PBA: 0x1804 SecureInit read PBA: 0x1c04 SecureInit ret = 0, SecureMode = 0 GPT 0x3190d20 signature is wrong LoadTrust Addr:0x4000 No find bl30.bin No find bl32.bin Load uboot, ReadLba = 2000 Load OK, addr=0x200000, size=0x99bc0 RunBL31 0x10000 NOTICE: BL31: v1.3(debug):f947c7e NOTICE: BL31: Built : 16:24:02, Aug 26 2018 NOTICE: BL31: Rockchip release version: v1.1 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1089): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 U-Boot 2018.11-armbian (Jan 17 2019 - 12:07:21 -0500) Model: OrangePi boards based on Rockchip RK3399 DRAM: 2 GiB MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0 Loading Environment from EXT4... ** File not found /boot/boot.env ** ** Unable to read "/boot/boot.env" from mmc0:1 ** In: serial@ff1a0000 Out: serial@ff1a0000 Err: serial@ff1a0000 Model: OrangePi boards based on Rockchip RK3399 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: Error: ethernet@fe300000 address not set. eth-1: ethernet@fe300000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found U-Boot script /boot/boot.scr 2958 bytes read in 6 ms (481.4 KiB/s) ## Executing script at 00500000 Boot script loaded from mmc 0 203 bytes read in 3 ms (65.4 KiB/s) 5033491 bytes read in 536 ms (9 MiB/s) 13437440 bytes read in 1410 ms (9.1 MiB/s) 74945 bytes read in 25 ms (2.9 MiB/s) 232 bytes read in 7 ms (32.2 KiB/s) Applying kernel provided DT fixup script (rockchip-fixup.scr) ## Executing script at 39000000 ## Loading init Ramdisk from Legacy Image at 04000000 ... Image Name: uInitrd Image Type: AArch64 Linux RAMDisk Image (gzip compressed) Data Size: 5033427 Bytes = 4.8 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 01f00000 Booting using the fdt blob at 0x1f00000 Loading Ramdisk to 7da51000, end 7df1ddd3 ... OK reserving fdt memory region: addr=1f00000 size=78000 Loading Device Tree to 000000007d9d6000, end 000000007da50fff ... OK Starting kernel ...
martinayotte Posted January 25, 2019 Posted January 25, 2019 24 minutes ago, Igor said: DDR Version 1.07 20161103 I've looked at the original backup of the factory android image I did, it is the same version as your output ! So, maybe your shortening wasn't good enough and was still booting from eMMC ...
martinayotte Posted January 25, 2019 Posted January 25, 2019 7 minutes ago, Igor said: No, I don't get there. Which image do you use? A image built with Armbian script using this config : https://github.com/armbian/build/blob/master/config/boards/orangepi-rk3399.wip
Igor Posted January 25, 2019 Posted January 25, 2019 It works. My shorting procedure was not good enough
martinayotte Posted January 25, 2019 Posted January 25, 2019 12 minutes ago, Igor said: It works. My shorting procedure was not good enough Right ! I've used a tweezers between the 2 pads, but I had to press hard on it to avoid moving it while doing the power recycling with my other hand ! At some point, I though even to add solder blob to make it easier, but I finally succeeded without ...
chwe Posted January 25, 2019 Posted January 25, 2019 let's hope you guys don't have to repeat this often otherwise the pad might be gone..
martinayotte Posted January 25, 2019 Posted January 25, 2019 3 minutes ago, chwe said: let's hope you guys don't have to repeat this often otherwise the pad might be gone.. No worries : it is only when the board is "virgin from factory" with their Android u-boot. So, I did it only once ... After that, the workaround is to stop at u-boot prompt and use "setenv devnum X" followed by "run mmc_boot" ...
R2fan Posted January 28, 2019 Posted January 28, 2019 Hi @martinayotte, Nice work on your builds. I am following the progress! I built a 16GB A1 Sandisk SD card with Armbian_5.73.190127_Orangepi-rk3399_Debian_stretch_dev_4.20.0.img. "Of course, to be able to boot from SDCard, we need to short the eMMC clock using the test point TP50265 :" I have tried this for a couple of seconds on powerup, and released, but dont see any new DHCP address assigned by my other router. I only have HDMI, Ethernet, and 12v power connected to the OPI RK3399. Did you have to do something else to get his board working with SD card? Thank you, and well done on your work so far.
Igor Posted January 28, 2019 Posted January 28, 2019 1 hour ago, R2fan said: I have tried this for a couple of seconds on powerup, and released I had many troubles (check few posts back) to properly close this test point, before I could boot the board. Use image from the download section. That one almost certainly works. Serial console would be recommended at this stage. You see at once if booting goes from SD card ... and for the future if you want to boot from a SD card. You need to get into u-boot.
martinayotte Posted January 28, 2019 Posted January 28, 2019 1 hour ago, R2fan said: Did you have to do something else to get his board working with SD card? No ! As @Igor said, you should get some USB-TTL Serial dongle to do some serious debugging. Maybe you didn't short TP50265 properly during u-boot phase.
R2fan Posted January 28, 2019 Posted January 28, 2019 OK, thanks both. FYI, raspberry PI3b+ UART never displayed serial comms correctly. The closest I got was with "sudo minicom -D /dev/ttyS0 -b 1500000" , then selecting Ctrl+A, Z , P - select Space parity (P), but this is unusable: 130|s(%ll@2+3399_mi$_or!.gep):/ $ 130|s(ell2k3399_m)$_o2!nge0):/ $ 130<sh%,,@rk3399-id_/ran'%pi:/ $ However, FTDI232 USB->UART from a windows laptop and putty (baud 1500000, 8, none) does show serial comms OK. I tried both Ubuntu and Debian images from the download section, and with the SD card now inserted, I get not identical, but very similar results if I short TP50265 (held for 1, 5,or 20 seconds), or not, and there is no user interaction at the end.. I tried both shorting to the GND pin next to it, and also with your trick Igor, by connecting to a GND on the GPIO header. with shorting: DDR Version 1.07 20161103 In Channel 0: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Channel 1: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB 256B stride ch 0 ddrconfig = 0x101, ddrsize = 0x20 ch 1 ddrconfig = 0x101, ddrsize = 0x20 pmugrf_os_reg[2] = 0x32817281, stride = 0x9 OUT Boot1: 2016-07-29, version: 1.05 CPUId = 0x0 ChipType = 10 1844 mmc: ERROR: SDHCI:Transfer data timeout mmc: ERROR: SDHCI ERR:cmd:0x153a,stat:0x0 mmc: ERROR: Tuning procedure failed, falling back to fixed sampling clock mmc: ERROR: tuning execution failed emmc reinit SdmmcInit=2 0 BootCapSize=100000 UserCapSize=14910MB FwPartOffset=2000 , 100000 SdmmcInit=0 0 BootCapSize=0 UserCapSize=15193MB FwPartOffset=2000 , 0 StorageInit ok = 12938472 LoadTrustBL No find bl30.bin No find bl32.bin theLoader 200000 13011111 LoaderFlag2: 0x0 Unhandled Exception in EL3. x30 = 0x0000000000034804 x0 = 0x0f1e2d3c4b5a6978 x1 = 0x0000000000030080 x2 = 0x0000000000000018 x3 = 0x0000000000000018 x4 = 0x0000000000000018 x5 = 0x0000000000000000 x6 = 0x0000000000000000 x7 = 0x0000000000000000 x8 = 0x0000000003011908 x9 = 0x0000000000010080 x10 = 0x000000000001ffa8 x11 = 0x0000000000000000 x12 = 0x000000000000000a x13 = 0x0000000000000001 x14 = 0x0000000000000002 x15 = 0x0000000000000004 x16 = 0x0000000000000000 x17 = 0x0000000000000000 x18 = 0x0000000000800000 x19 = 0x0f1e2d3c4b5a6978 x20 = 0x0000000000038210 x21 = 0x0f1e2d3c4b5a6978 x22 = 0x000000000003168d x23 = 0x0000000000038220 x24 = 0x0000000000012000 x25 = 0x0000000000000001 x26 = 0x00000000ff8c2000 x27 = 0x0000000000000110 x28 = 0x0000000000000110 x29 = 0x00000000000358c0 scr_el3 = 0x0000000000000238 sctlr_el3 = 0x0000000000c5383a cptr_el3 = 0x0000000000000000 tcr_el3 = 0x0000000000000000 daif = 0x00000000000003c0 mair_el3 = 0x44e048e000098aa4 spsr_el3 = 0x00000000600002cc elr_el3 = 0x0000000000011724 ttbr0_el3 = 0x0010011920043020 esr_el3 = 0x0000000096000000 far_el3 = 0x0f1e2d3c4b5a6978 spsr_el1 = 0x00000000300c0088 elr_el1 = 0x2a14c6406338102d spsr_abt = 0x000000000000000a spsr_und = 0x0000000000030056 spsr_irq = 0x0000000036002060 spsr_fiq = 0x0000000018011018 sctlr_el1 = 0x0000000000c52838 actlr_el1 = 0x0000000000000000 cpacr_el1 = 0x0000000000000000 csselr_el1 = 0x0000000000000000 sp_el1 = 0x06038283c2208000 esr_el1 = 0x00000000e2ca20f1 ttbr0_el1 = 0x000e20d65110a020 ttbr1_el1 = 0x00a2046712000511 mair_el1 = 0x44e048e000098aa4 amair_el1 = 0x0000000000000000 tcr_el1 = 0x0000000000000000 tpidr_el1 = 0x8024080400110900 tpidr_el0 = 0x80001908a6a00050 tpidrro_el0 = 0x40020200d8002029 dacr32_el2 = 0x000000008088c024 ifsr32_el2 = 0x0000000000000020 par_el1 = 0x0500000070620d60 mpidr_el1 = 0x0000000080000000 afsr0_el1 = 0x0000000000000000 afsr1_el1 = 0x0000000000000000 contextidr_el1 = 0x0000000000000000 vbar_el1 = 0x0000000000000000 cntp_ctl_el0 = 0x0000000000000002 cntp_cval_el0 = 0x2ff648404721a82d cntv_ctl_el0 = 0x0000000000000000 cntv_cval_el0 = 0x00000020c2700238 cntkctl_el1 = 0x0000000000000000 fpexc32_el2 = 0x0000000000000700 sp_el0 = 0x00000000000358c0 isr_el1 = 0x0000000000000000 cpuectlr_el1 = 0x0000000000000040 cpumerrsr_el1 = 0x0000000000000000 l2merrsr_el1 = 0x0000000000000000 gicc_hppir = 0x0000000000000000 gicc_ahppir = 0x0000000000000000 gicc_ctlr = 0x0000000014000082 gicd_ispendr regs (Offsets 0x200 - 0x278) 0000000000000200: 0x0000001800000000 0000000000000208: 0x0000000000000000 0000000000000210: 0x0000000000000010 0000000000000218: 0x0000000000000000 0000000000000220: 0x0000000000000000 0000000000000228: 0x0000000000000000 0000000000000230: 0x0000000000000000 0000000000000238: 0x0000000000000000 0000000000000240: 0x0000000000000000 0000000000000248: 0x0000000000000000 0000000000000250: 0x0000000000000000 0000000000000258: 0x0000000000000000 0000000000000260: 0x0000000000000000 0000000000000268: 0x0000000000000000 0000000000000270: 0x0000000000000000 0000000000000278: 0x0000000000000000 cci_snoop_ctrl_cluster0 = 0x00000000c0000000 cci_snoop_ctrl_cluster1 = 0x00000000c0000000 without shorting: DDR Version 1.07 20161103 In Channel 0: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Channel 1: DDR3, 666MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB 256B stride ch 0 ddrconfig = 0x101, ddrsize = 0x20 ch 1 ddrconfig = 0x101, ddrsize = 0x20 pmugrf_os_reg[2] = 0x32817281, stride = 0x9 OUT Boot1: 2016-07-29, version: 1.05 CPUId = 0x0 ChipType = 10 1844 SdmmcInit=2 0 BootCapSize=100000 UserCapSize=14910MB FwPartOffset=2000 , 100000 SdmmcInit=0 0 BootCapSize=0 UserCapSize=15193MB FwPartOffset=2000 , 0 StorageInit ok = 182057 LoadTrustBL No find bl30.bin No find bl32.bin theLoader 200000 254667 LoaderFlag2: 0x0 Unhandled Exception in EL3. x30 = 0x0000000000034804 x0 = 0x0f1e2d3c4b5a6978 x1 = 0x0000000000030080 x2 = 0x0000000000000018 x3 = 0x0000000000000018 x4 = 0x0000000000000018 x5 = 0x0000000000000000 x6 = 0x0000000000000000 x7 = 0x0000000000000000 x8 = 0x0000000003011908 x9 = 0x0000000000010080 x10 = 0x000000000001ffa8 x11 = 0x0000000000000000 x12 = 0x000000000000000a x13 = 0x0000000000000001 x14 = 0x0000000000000002 x15 = 0x0000000000000004 x16 = 0x0000000000000000 x17 = 0x0000000000000000 x18 = 0x0000000000800000 x19 = 0x0f1e2d3c4b5a6978 x20 = 0x0000000000038210 x21 = 0x0f1e2d3c4b5a6978 x22 = 0x000000000003168d x23 = 0x0000000000038220 x24 = 0x0000000000012000 x25 = 0x0000000000000001 x26 = 0x00000000ff8c2000 x27 = 0x0000000000000110 x28 = 0x0000000000000110 x29 = 0x00000000000358c0 scr_el3 = 0x0000000000000238 sctlr_el3 = 0x0000000000c5383a cptr_el3 = 0x0000000000000000 tcr_el3 = 0x0000000000000000 daif = 0x00000000000003c0 mair_el3 = 0x44e048e000098aa4 spsr_el3 = 0x00000000600002cc elr_el3 = 0x0000000000011724 ttbr0_el3 = 0x0050011900043060 esr_el3 = 0x0000000096000000 far_el3 = 0x0f1e2d3c4b5a6978 spsr_el1 = 0x00000000300c0088 elr_el1 = 0x2a14c6406b38102d spsr_abt = 0x000000000000000a spsr_und = 0x0000000000030056 spsr_irq = 0x0000000034000060 spsr_fiq = 0x000000001801111a sctlr_el1 = 0x0000000000c52838 actlr_el1 = 0x0000000000000000 cpacr_el1 = 0x0000000000000000 csselr_el1 = 0x0000000000000000 sp_el1 = 0x0e038203c0008000 esr_el1 = 0x00000000428820f1 ttbr0_el1 = 0x000820d65111a020 ttbr1_el1 = 0x00a2006592000711 mair_el1 = 0x44e048e000098aa4 amair_el1 = 0x0000000000000000 tcr_el1 = 0x0000000000000000 tpidr_el1 = 0x0024080400110900 tpidr_el0 = 0x80000908a6a00050 tpidrro_el0 = 0x4002020098002029 dacr32_el2 = 0x000000008080c024 ifsr32_el2 = 0x0000000000000020 par_el1 = 0x0500000070620860 mpidr_el1 = 0x0000000080000000 afsr0_el1 = 0x0000000000000000 afsr1_el1 = 0x0000000000000000 contextidr_el1 = 0x0000000000000000 vbar_el1 = 0x0000000000000000 cntp_ctl_el0 = 0x0000000000000002 cntp_cval_el0 = 0x2ff44841c721a82d cntv_ctl_el0 = 0x0000000000000000 cntv_cval_el0 = 0x00002020c2720238 cntkctl_el1 = 0x0000000000000000 fpexc32_el2 = 0x0000000000000700 sp_el0 = 0x00000000000358c0 isr_el1 = 0x0000000000000000 cpuectlr_el1 = 0x0000000000000040 cpumerrsr_el1 = 0x0000000000000000 l2merrsr_el1 = 0x0000000000000000 gicc_hppir = 0x0000000000000000 gicc_ahppir = 0x0000000000000000 gicc_ctlr = 0x0000000014000082 gicd_ispendr regs (Offsets 0x200 - 0x278) 0000000000000200: 0x0000001800000000 0000000000000208: 0x0000000000000000 0000000000000210: 0x0000000000000010 0000000000000218: 0x0000000000000000 0000000000000220: 0x0000000000000000 0000000000000228: 0x0000000000000000 0000000000000230: 0x0000000000000000 0000000000000238: 0x0000000000000000 0000000000000240: 0x0000000000000000 0000000000000248: 0x0000000000000000 0000000000000250: 0x0000000000000000 0000000000000258: 0x0000000000000000 0000000000000260: 0x0000000000000000 0000000000000268: 0x0000000000000000 0000000000000270: 0x0000000000000000 0000000000000278: 0x0000000000000000 cci_snoop_ctrl_cluster0 = 0x00000000c0000000 cci_snoop_ctrl_cluster1 = 0x00000000c0000000
martinayotte Posted January 28, 2019 Posted January 28, 2019 1 hour ago, R2fan said: with shorting: DDR Version 1.07 20161103 As I said to @Igor last Friday, this DDR Version signature is the one found in the factory android image ! So, maybe your shortening wasn't good enough and for sure was still booting from eMMC the old Android which then stop seeing that SDCard is inserted but not compatible ... With the current build, or at least the one I did 2 weeks ago, you should get this DDR signature : DDR Version 1.14 20180803 In soft reset SRX Channel 0: DDR3, 800MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Channel 1: DDR3, 800MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
R2fan Posted January 28, 2019 Posted January 28, 2019 How long did you short the pins for? This person here: https://www.youtube.com/watch?v=R0qsW1zBdEg does it quite quickly, but I notice this may be an older v1.4 version of the board, since TP50265 in this video is on the bottom side, and mine and Igors (and I guess yours) is on the top. Thanks
martinayotte Posted January 28, 2019 Posted January 28, 2019 1 hour ago, R2fan said: How long did you short the pins for? It is only require 2 or 3 secs been shorted while pressing the "reset" push button SW2103 near the eMMC. As I said to @Igor , those small pads, TP50265 and GND nearby are so small (yes, located on the top side), I took a tweezers and press hard to make sure contact was good, and then gently press "reset". EDIT : I've tried to learn what those other pads on the bottom side are doing, I can't really tell, and the youtube clip is in chinese, which I'm not fluent with it (I don't know a single word) ...
woodfe Posted January 29, 2019 Posted January 29, 2019 5 hours ago, martinayotte said: It is only require 2 or 3 secs been shorted while pressing the "reset" push button SW2103 near the eMMC. As I said to @Igor , those small pads, TP50265 and GND nearby are so small (yes, located on the top side), I took a tweezers and press hard to make sure contact was good, and then gently press "reset". EDIT : I've tried to learn what those other pads on the bottom side are doing, I can't really tell, and the youtube clip is in chinese, which I'm not fluent with it (I don't know a single word) ... in youtube clip, he said: "short the emmc clk pin and ground".
Igor Posted January 29, 2019 Posted January 29, 2019 49 minutes ago, woodfe said: short the emmc clk pin and ground You could do that as well, but I guess it is even more tricky than by using test point. I wonder why they didn't simply install a switch? Or a jumper. 1
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